CN101989406A - Display control circuit with extremely low power consumption and related method thereof - Google Patents

Abstract

The invention discloses a display control circuit with extremely low power consumption and a related method, which can effectively save power consumption of a display in a standby state and achieve low cost. The ultra-low power consumption display control circuit includes a transformer with a primary side and a secondary side, a capacitor coupled to the secondary side of the transformer, a voltage stabilizer, a display controller, and a voltage proportional unit; the transformer is used to receive high-voltage direct current on the primary side The voltage is converted into a DC voltage on the secondary side; the capacitor is used to stabilize the DC voltage; the regulator is coupled to the capacitor to receive the DC voltage and generate a DC regulated output; the display controller is coupled to the regulator for It operates by receiving a DC regulated output; the voltage ratio unit is coupled to the display controller and the secondary side of the transformer to receive a reference voltage and provide a voltage ratio on the secondary side; so that the display controller can be used in power saving mode by The general-purpose input and output pins change the voltage ratio.

Description

Display control circuit with extremely low power consumption and related method

technical field

The present invention relates to the power consumption of a display control circuit, in particular to an ultra-low power display control circuit and a related method.

Background technique

FIG. 1 is a block diagram 100 of a display circuit inside a display in the prior art, including a power supply circuit 110, a zoom controller 120, and a backlight module 130. The power supply circuit 110 is converted into appropriate voltages 114 and 116 via an AC power supply 112, and respectively supplies power to Operation of the backlight module 130 and the zoom controller 120 . The display circuit block diagram 100 can be applied to a computer monitor, an analog television or a digital television. In the world trend of energy saving and carbon reduction, many manufacturers are committed to saving the power consumption of the display in the standby state. The prior art utilizes an AC/DC conversion power supply circuit 110 to save power.

Therefore, it is very urgent to develop a display circuit and a related method that can be realized at low cost with extremely low power consumption.

Contents of the invention

The technical problem to be solved by the present invention is to provide a display control circuit and related method with extremely low power consumption, which can effectively save power consumption of the display in the standby state and realize low cost.

In order to solve the above technical problems, the present invention provides the following technical solutions:

The invention provides a very low power consumption power conversion controller, which includes a transformer with a primary side and a secondary side, a capacitor coupled to the transformer, a voltage stabilizer, a display controller and a voltage proportional unit; the transformer is used for the primary side Receive high-voltage DC voltage to convert to DC voltage on the secondary side; the capacitor is used to stabilize the DC voltage; the voltage regulator is coupled to the capacitor to receive the DC voltage and generate a DC regulated output; the display controller is coupled to the voltage regulator , used to receive DC regulated output and operate; the voltage ratio unit is coupled to the display controller and the secondary side of the transformer to receive the reference voltage and provide a voltage ratio on the secondary side; so that the display controller can save power The mode changes the voltage ratio through the general-purpose input and output pins.

The present invention further proposes a control method for an extremely low power consumption power supply, including: the display controller enters the power saving mode; the display controller changes the voltage ratio to reduce the output voltage level of the secondary side of the transformer; and the secondary side of the secondary side The output voltage is regulated by a voltage regulator to generate a regulated output for displaying the operation of the controller in the power-saving mode.

The display control circuit with extremely low power consumption and the related method adopted in the present invention can effectively save power consumption of the display in the standby state, and at the same time realize a display circuit with low cost and extremely low power consumption by using the AC/DC conversion power supply circuit and related method implementations.

Description of drawings

FIG. 1 is a block diagram of a display circuit inside a prior art display.

FIG. 2 is a very low power consumption display control circuit according to a specific embodiment of the present invention.

FIG. 3 is a main waveform diagram related to the embodiment shown in FIG. 2 .

FIG. 4 is a very low power consumption display control circuit according to another embodiment of the present invention.

FIG. 5 is a very low power consumption display control circuit according to another embodiment of the present invention.

FIG. 6 is a very low power consumption display control circuit according to another embodiment of the present invention.

FIG. 7 is a flow chart of a method for controlling an ultra-low power consumption display according to a specific embodiment of the present invention.

FIG. 8 is a very low power consumption power conversion controller according to an embodiment of the present invention.

FIG. 9 is a waveform diagram of main signals of the ultra-low power consumption power conversion control operation in FIG. 8 .

FIG. 10 is a flowchart of a power conversion method with extremely low power consumption according to an embodiment of the present invention.

FIG. 11 is a power conversion controller according to a specific embodiment of the present invention.

FIG. 12 is a waveform diagram of main signals in the operation of the power conversion controller in FIG. 11 .

FIG. 13 is a very low power consumption display control circuit according to another embodiment of the present invention.

FIG. 14 is a signal waveform diagram of the output voltage signal VCC5V' in FIG. 13 .

FIG. 15 is a flow chart of a method for controlling an ultra-low power consumption display according to a specific embodiment of the present invention.

The main component symbols are explained as follows:

100 Display Circuit Block Diagram

112 AC power supply

110 Power circuit

114, 116 Voltage signal

120 Zoom Controller

130 Backlight Module

300, 400, 500, 1300 Display control circuit

302 AC power supply

310 rectifier

320, 420 Bias circuit

330, 530, 1330 Transformer

340, 540, 800, 1100, 1340 power conversion controller

342, 542, 842, 1142 Current Source

350, 550, 1350 voltage regulator

360 Zoom Controller

370, 570 Optical coupling components

560, 1360 Display Controller

810, 820, 1110, 1120 comparators

830, 1130 Hysteresis Comparator

812, 822 Signal

811 gain amplifier

840, 1140 oscillator

850, 1150 voltage regulator

860, 1160 flip-flop

870, 872, 1170 AND gates

880, 1180 buffer

890 control circuit

892 OR gate

894, 896 Inverter

1370 Voltage proportional unit

F1 fuse

A, B node

NTC resistor

SW' switch

VDDP, VDDP’, VCC14V, VCC14V’, VDD3V3, VDD3V3’ Signals

COMP, COMP’, HV, HV’, VCC5Vsense, AC_OFF signal

DRV, DRV’, VCC5V, VCC5V’ Signal

R11, R12, R13, R2, R4, R5, R6, R72, R80, R82, R1’, R2’ Resistors

D1, D21, D22, D3, D4, D5, D80 Diodes

Q1, Q2, Q3, Q4, Q8 Transistors

C1, C2, C3, C4, C1’, C2’ Capacitance

Z’ shunt regulation

device

Detailed ways

2 is an extremely low power consumption display control circuit 300 according to a specific embodiment of the present invention. The AC power supply 302 supplies an AC voltage to the rectifier 310, for example, an AC voltage of 80 to 220 volts; the rectifier 310 rectifies and outputs a DC voltage to the bias circuit 320. A transformer (transformer) 330, such as 120 to 375 volts DC, and a rectifier 310, such as a full-bridge rectifier; biased by the bias circuit 320, the DC voltage signal VDDP is supplied to the power conversion controller 340 for operation, and the DC voltage signal VDDP For example, if the DC voltage is 20V, the power conversion controller 340 is an analog circuit chip, usually packaged with eight pins, and the number of pins is limited due to cost considerations. The transformer 330 uses coil induction to convert the high-voltage DC voltage on its primary side into other appropriate DC voltages for output on the secondary side for the operation of other circuits. For example, the output DC voltage signals VCC14V and VCC5V provide 14 volts and 5 volts of DC voltage respectively. The 14V DC voltage can supply the operation of the backlight module, such as the operation of the cold cathode lamp or the backlight module of the LED. The DC voltage signal VCC 5V passes through the voltage regulator 350 , such as a low drop-out regulator (LDO) 350 , and outputs a DC voltage signal 3V3 to supply power to the operation of the scaling controller 360 . The scaling controller 360 controls the operation of the power conversion controller 340 according to the voltage status of the DC voltage signal VCC5V output by the transformer 330, for example, the voltage division signal VCC5Vsense of the DC voltage signal VCC5V through the resistors R5 and R6 is sent to the scaling controller 360's successive approximation register analog-to-digital converter (successive approximation ADC, referred to as SAR ADC) detects the voltage condition on the DC voltage signal VCC5V, and those who are familiar with this technology can understand that the progressive approximation register analog-to-digital converter is low-cost and achievable The low-speed analog-to-digital converter, or, sends the divided voltage signal VCC5Vsense to a comparator (not shown) and a reference voltage, such as 4 volts, of the scaling controller 360 to detect the voltage condition on the DC voltage signal VCC5V; then, The scaling controller 360 can use the general purpose I/O (GPIO) pin to control the compensation pin COMP of the power conversion controller 340 through the opto-coupler (or called photocoupler) 370, and feedback control The power conversion controller 340 is turned on to achieve the purpose of extremely low power consumption. It should be noted that those skilled in the art can understand that the power conversion controller 340 is an analog circuit chip, usually packaged into eight pins, wherein the compensation pin COMP provides a current source 342 inside the power conversion controller 340, for example, a 200 micron Current source in amperes (µA). The bias circuit 320 includes resistors R11, R12, R13, diodes D21, D22, transistors Q1, Q2, Q3. The bias circuit 320 utilizes the path of the resistors R11, R12 and the transistor Q1 to bias the high-voltage DC voltage into a DC voltage signal VDDP to supply power to the power conversion controller 340 for operation.

The power conversion controller 340 utilizes the charge stored in the capacitor C1 to temporarily supply the operation of the power conversion controller 340 when the transistor Q1 is turned off and the power supply stops. It takes time to actually start supplying normal DC voltage, so the capacitor C1 should not be too large, for example, 22 microfarads (μF). The scaling controller 360 can use the capacitor C2 to temporarily supply the operation of the scaling controller 360 when the power is cut off. Typically, the capacitor C2 is quite large, such as 2000 microfarads (μF). It should be noted that the capacitor C2 can provide The stored power is much larger than that of the capacitor C1.

The ultra-low power consumption display control circuit 300 shown in FIG. 2 uses the capacitor C2 to temporarily supply power to the operation of the scaling controller 360 after the system power is turned off, and outputs a DC voltage signal 3V3 through the regulator 350 to supply power to the scaling control The operation of the controller 360, as long as the DC voltage signal VCC5V is stabilized by the voltage regulator 350 and the output DC voltage signal 3V3 is higher than the working voltage of the scaling controller 360, the scaling controller 360 can be operated, and the power consumption of the voltage regulator 350 The power is extremely low, and the voltage drop LDODrop between the DC voltage signal VCC5V and the DC voltage signal 3V3 is extremely small. Assuming that the working voltage of the scaling controller 360 is 3.3V, through the gradual discharge of the capacitor C2, as long as the DC voltage signal VCC5V exceeds (3.3V+LDODrop), the scaling controller 360 can operate.

After the system power is turned off, the scaling controller 360 uses the GPIO pin to send the signal AC_OFF to reflect the voltage state of the scaling controller 360 to the power conversion controller 340 through the resistor R4 and the optical coupling component 370 to draw current, and the power conversion controller 340 uses the compensation pin COMP to make the current source 342 supply the current through the resistor R13, the diodes D21, D22 and the transistor Q3. For example, the current transfer ratio (current transfer ratio, referred to as CTR) of the photocoupler 370 is 1:1 , the current drawn by both sides of the optical coupling element 370 is 1:1, and the assertion period of the signal AC_OFF is related to the level of the DC voltage signal VCC5V. When the power conversion controller 340 senses that the voltage of the scaling controller 360 at the compensation pin COMP is lower than a predetermined level, it briefly drives the signal DRV to turn on the transistor Q4, and briefly starts the primary side of the transformer 330 to draw external power to the capacitor. C1 charges and charges the bulk capacitor C2 on the secondary side of the transformer 330 for the operation of the scaling controller 360 during the next cycle. The directions of the arrows in FIG. 2 indicate the main current flows in several circuit analyzes so that those skilled in the art can better understand the operation of this embodiment.

For the power conversion controller 340, when the signal AC_OFF is asserted, for example, at a high level, the optical coupling component 370 generates a coupling current, and draws the required coupling current through the node A, diodes D21, D22 and the optical coupling component 370, so that the transistor Q3 The base voltage drops, and the transistor Q3 and diodes D21 and D22 are turned on, so that the voltage on the compensation pin COMP drops, and the transistor Q2 is turned off, so that the base potential of the transistor Q1 drops and the transistor Q1 is turned off; the transistor Q3 has the function of current amplification and can The discharge speed of the current source 342 is accelerated. If the current capability of the current source 342 in the power conversion controller 340 is low, the transistor Q3 can be omitted, and the diode D22 can be directly used for discharging. On the other hand, when the signal AC_OFF is released, for example, it is at a low level, no induction current is generated, the transistor Q1 is turned on to charge the capacitor C1, and then the voltage on the compensation pin COMP gradually rises, and the transistor Q2 is turned on, so that the transistor Q1 The base is grounded and the transistor Q1 is turned off, so that the power conversion controller 340 uses the power stored in the capacitor C1 to discharge the capacitor C1; therefore, whether the power conversion controller 340 operates or not is controlled by the assertion of the signal AC_OFF to control the capacitor C1 charge and discharge cycle operation.

FIG. 3 is a main waveform diagram of the ultra-low power consumption display control circuit 300 in FIG. 2 , including a waveform relationship diagram among the signal AC_OFF, the voltage signal VDDP, the signal DRV, the voltage signal VCC5V, and the sensing signal VCC5Vsense. In this embodiment, after the signal AC_OFF is pulled high, the current source in the power conversion controller 340 is quickly forced through the diodes D21, D22 and the optical coupling device 370. The 342 discharge pulls down the potential and turns off the transistor Q1, forcibly cutting off the power supply from the external power supply to the power conversion controller 340, and the voltage signal VDDP is quickly pulled down and kept at 0 volts for a long time to achieve the purpose of power saving. After the signal AC_OFF is pulled low, the transistor Q1 is turned on to charge the capacitor C1, so that the voltage signal VDDP rises rapidly. After reaching the highest voltage, such as 20 volts, the voltage on the compensation pin COMP rises to a predetermined level, and the power conversion controller 340 briefly The asserted signal DRV is, for example, temporarily generated by a pulse width modulation (PWM) controller in the power conversion controller 340 to temporarily generate a high-low level width-modulated signal DRV, or by pulse frequency modulation ( The pulse frequency modulation (PFM) controller generates signals DRV with different frequencies, and briefly turns on the transistor Q4, so that the primary side of the transformer 330 is temporarily turned on to charge the capacitor C1 and the large capacitor C2 on the secondary side, for example, the voltage The signal VCC5V is quickly pulled up to 5 volts, which can be achieved by comparing with a comparator and a reference voltage, or, for example, charging the large capacitor C2 on the secondary side for a predetermined period; as long as the voltage signal VCC5V is discharged to the predetermined voltage before , the zoom controller 360 can operate normally and monitor the change of the sensing signal VCC5Vsense, and thus continue to operate in a cycle. For example, as long as the voltage signal VCC5V is greater than (3.3 volts + voltage drop LDODrop) during the entire process, it can operate normally. The sensing signal VCC5Vsense displays the charging and discharging changes of the corresponding voltage signal VCC5V. It should be noted that the voltage signal VDDP is maintained at 0 volts for a long period of time, so that the driving period of the signal DRV is far apart, which can completely isolate the consumption of the external power supply and achieve the purpose of extremely low power consumption. After circuit simulation, the total power The consumption can be less than 150 milliwatts (mW), and the actual additional cost is very low, taking into account both cost and performance. The operation of other auxiliary components in this embodiment, such as the fuse F1, the negative temperature coefficient resistor NTC, the resistor R2, the capacitor C4, etc., can be understood by those skilled in the art and will not be repeated here.

FIG. 4 is an extremely low power consumption display control circuit 400 according to another specific embodiment of the present invention. Compared with the embodiment in FIG. 2 , the difference is that the bias voltage circuit 420 uses the resistor R18 to provide bias voltage control, and the transistor Q3 is omitted. , and the far right shows that the 5-volt signal PC5V from the personal computer can be coupled to the voltage signal VCC5V through the diode D6 to charge the capacitor C2; and the zoom controller 360 can also be widely integrated in the display controller (display controller), Application to analog TV and digital TV does not escape the scope of the present invention.

FIG. 5 is an ultra-low power consumption display control circuit 500 according to another embodiment of the present invention, which is mainly derived from the concept of the embodiment in FIG. 2 . Similar signals also use the labels of the previous signals, which is helpful for understanding the operation of this embodiment. The main difference is that the power conversion controller 540 integrates similar components of the bias circuit 320 in FIG. 2 , and the display controller 560 directly detects the side voltage signal VDD3V3, saving the pins of the analog-to-digital converter or the comparator of the progressive approximation register; As disclosed in the previous embodiments, the display controller 560 detects the change of the voltage signal VDD3V3 , for example, ensures that the voltage signal VDD3V3 is higher than 3.3 volts. For example, before the voltage signal VDD3V3 is higher than 3.3 volts, the display controller 560 can use the GPIO pin to assert the signal AC_OFF to stop the power conversion controller 540 from drawing external power through the optocoupler 570 and the compensation pin COMP; Before the signal VDD3V3 drops to 3.3 volts, the display controller 560 asserts the signal AC_OFF, and the power conversion controller 540 briefly draws the external power from the node B through the high-voltage power supply pin HV by turning on the internal switch (not shown), so that The controlled current source 542 inside the power conversion controller 540 charges the capacitor C1 through the voltage signal VDDp', and briefly drives the signal DRV to start the primary side of the transformer 530, so that the transformer 530 charges the capacitor C1 and the secondary side large The capacitor C2 is charged to a predetermined voltage or for a predetermined period of time. The power conversion controller 540 cuts off the external power supply for a long time, which can greatly reduce the power consumption. The directions of the arrows indicate the main current flow directions in several circuit analyzes so that those skilled in the art can better understand the operation of this embodiment.

According to the above disclosure of many embodiments, those skilled in the art can make many possible changes without departing from the scope of the present invention. For example, the display controller 560 uses the GPIO pin control signal AC_OFF to feedback control the compensation pin COMP through the resistor R4 and the optical coupling component 570 to control whether the power conversion controller 540 draws external power, and there may be other changes. Possibly, for example, the circuit near the optocoupler 570 can be modified so that the high and low levels of the signal AC_OFF are opposite to the operation of the power conversion controller 540; The operation of the current; or, in the above embodiments, the level of the control signal AC_OFF is output by the GPIO pin. By modifying the circuit near the optical coupling component 570, the GPIO pin can be operated as an input. As shown in Figure 6, the optical The coupling component 570 is coupled to the GPIO pin of the display controller 560 through the resistor R72, and controls whether to turn on the discharge through the transistor Q8. When the control signal CTRL is asserted, the transistor Q8 is turned on, and the signal COMP triggers the power conversion controller 540 similar to the above. Operation of the embodiment.

FIG. 7 is a flow chart of a method for controlling an ultra-low power consumption display according to a specific embodiment of the present invention. In step 702, the DC voltage level of the secondary side of the transformer is sensed. For example, the change of the signal VCC5V in FIG. 2 can be sensed, or the change of the signal VDD3V3 can be directly sensed. 3.3 volts; in step 704, the display controller controls the compensation pin of the power conversion controller by turning on the optocoupler through the GPIO pin, and turns off the operation of the power conversion controller. For example, as shown in FIG. 5, The display controller 560 can increase the magnitude of the coupling current of the optical coupling element 570 through the assertion signal AC_OFF of the GPIO pin, and shut down the operation of the power conversion controller 540, or, as shown in FIG. 6 , the optical coupling element 570 is coupled to the display The GPIO pin of the controller 560 forms a discharge path through the transistor Q8 to shut down the operation of the power conversion controller 540; in step 706, when the DC voltage level drops to a predetermined level, the optocoupler is lowered through the GPIO pin The size of the coupling current, control the compensation pin of the power conversion controller, and start the operation of the power conversion controller; in step 708, briefly turn on the primary side of the transformer, and briefly charge the first capacitor and the second capacitor, for example In other words, as shown in FIG. 5 , the gate of the transistor Q4 is controlled by pulse width modulation or pulse frequency modulation, so that the transformer 530 charges the first capacitor C1 and the second capacitor C2 on the secondary side.

FIG. 8 is an extremely low power consumption power conversion controller 800 according to a specific embodiment of the present invention, which has pins such as HV, VDDp, DRV, CS, COMP, and GND. When applied to the operation of the embodiment of FIG. 5, FIG. 8 The operation of the external circuit of each pin is as described in the foregoing embodiments. The very low power consumption power conversion controller 800 includes comparators 810, 820, hysteresis comparator 830, oscillator 840, current source 842, voltage regulator 850, flip-flop 860, AND gates 870, 872, buffer 880, control Circuit 890, resistors R80, R82, all-sodium diode D80.

FIG. 9 shows the main signal waveform diagram of the operation of the ultra-low power consumption power conversion controller 800 in FIG. Represents the voltage signal of the VDDp pin, the voltage signal of the COMP pin, the current magnitude of the HV pin, the current magnitude of the VDDp pin, the voltage signal of the DRV pin, and the 5V voltage signal. When the power conversion controller 800 is first started, the HV pin charges the capacitor (not shown) outside the VDDp pin via the current source 842, and when the potential gradually rises to the point where the input voltage of the positive terminal of the hysteresis comparator 830 is higher than the first hysteresis The reference voltage VDDH, the output level of the hysteresis comparator 830 is high, so that the output of the AND gate 870 is high, enabling the voltage regulator 850 to output the operating voltage in the signal 852 to supply the internal operation of the power conversion controller 800; and, the hysteresis comparator The output high level of the device 830 passes through the OR gate 892 and the inverter 894, the current source 842 is turned off, and the HV pin stops drawing current from the outside. The control path of the OR gate 892 and the inverter 894 ensures that the output of the hysteresis comparator 830 is high. will turn off the current source 842 to block the external power consumption. The oscillator 840 generates a square wave signal and outputs it to the S input terminal of the SR flip-flop 860, and the R input terminal of the SR flip-flop 860 is at a low level at first, and the Q output terminal turns to a high level, when the DRV pin is pulled High level, the externally connected transistor (not shown) will be turned on, and the current sense (CS) pin will be pulled high accordingly. After the comparator 810, the R input terminal of the SR flip-flop 860 will change is a high level, when the SR flip-flop 860 receives a trigger next time, the S input terminal and the R input terminal of the R flip-flop 860 are at a low level and a high level respectively, and after the trigger, the Q output terminal turns to a low level, that is, In other words, the operation of this circuit, the input of the S input terminal and the R input terminal are exactly inverting when the trigger is triggered, so as to generate a pulse width modulation signal on the DRV pin. For example, the square wave signal is a 1MHz square wave signal to reduce the power consumption of the ultra-low power consumption power conversion controller 800 in standby mode, and the square wave signal is placed on the DRV pin through the AND gate 872 and the buffer 880 output. Next, the capacitor (not shown) outside the VDDp pin slowly releases the stored power until the positive terminal input voltage of the hysteresis comparator 830 reaches the second hysteresis reference voltage VDDL, so that the output level of the hysteresis comparator 830 is changed by High to low, so that the output of the AND gate 870 is low, the output of the AND gate 872 is low, the output of the DRV pin is low, and the external transistor (not shown) connected to it is turned off and the external transformer (not shown) is turned off. ), as shown in Figure 9, the I(HV) signal starts to draw the charging current Icharge, and when V(VDDP) changes from the voltage VDDH to the voltage VDDL, the I(HV) signal (from the external power supply) consumes a sudden drop in current to Ihv_off. The current released by I(VDDp) is Istartup and Iop, and the current Iop is supplied to the power conversion controller 800 to drive the square wave signal on the DRV pin.

Then, after the primary side of the external transformer is turned on, the display controller (not shown) on the secondary side can obtain power to operate, and can control the V(COMP) signal. Through the control of the COMP pin disclosed in the above-mentioned embodiments, by controlling the compensation signal on the COMP pin, the time interval for generating the PWM signal can be lengthened and the real time length of the generation can be shortened, but the power supply is still The conversion controller 800 operates in a fully monitored manner, so that the entire system will not go out of control and fail to wake up.

When the voltage of the V(COMP) signal is pulled low, the operation of the oscillator 840 is forcibly turned off, or the output frequency of the oscillator 840 is adjusted in response to the potential level of the V(COMP) signal. For example, V(COMP ) signal high, the output frequency becomes high, and the V(COMP) signal low, the output frequency becomes low, or reverse operation, so the V(COMP) signal potential can affect the power consumption of the power conversion controller 800 and the control comparator 820 compares the positive terminal voltage with the feedback reference voltage Voff, and outputs a low level to the feedback control signal 822, so that the output of the AND gate 870 is at a low level, disabling the operation of the voltage regulator 850, and turning off The internal power supply of the power conversion controller 800 makes the power conversion controller 800 enter the extremely low power consumption mode, and the current I(VDDp) is instantly reduced to Ioff, preferably the current Ioff is less than the current 0.1*Iop, or lower, V( The falling speed of the VDDP) potential becomes very slow, that is, the falling slope of the V(VDDP) potential becomes smaller, and by controlling the V(COMP) signal, the time to start charging the external capacitor next time can be greatly lengthened, reducing the overall system Power consumption; it should be noted that pulling down the V(COMP) signal can make the low level output in the feedback control signal 822 pass through the inverter 896 and the OR gate 892 to forcibly turn off the current source 842, and stop the HV pin from drawing current from the outside, because At this time, the output of the hysteresis comparator 830 is at a high level, and the operation of the current source 842 has been turned off. That is to say, the simple control circuit 890 including the OR gate 892 and the inverters 894 and 896 can timely control the timing of turning on and off the current source 842 .

Returning to Figure 8, when the action of pulling down the V(COMP) signal is stopped, that is, when the voltage on the COMP pin is controlled to be higher than the feedback reference voltage Voff, the level of the feedback control signal 822 is high, and the current I (VDDp) returns to Iop, and the external large capacitor (not shown) restores the operating power of the power conversion controller 800 again, and the power conversion controller 800 operates normally until the V(VDDP) voltage is VDDL. At this time, the hysteresis comparator 830 When the positive input voltage of the positive terminal reaches the second hysteresis reference voltage VDDL, the output level of the hysteresis comparator 830 changes from high to low, so that the output of the AND gate 870 is low, the output of the AND gate 872 is low, and the output of the DRV pin to low level.

Then, after the HV pin temporarily charges the capacitor (not shown) outside the pin VDDp via the current source 842 , the potential of V(VDDP) is charged from VDDL to VDDH, and the current I(VDDp) starts to discharge so that the loop operates. The COMP pin can first pass through the gain amplifier 811, such as a gain adjustment of 1/2. This gain adjustment can be adjusted according to the actual circuit design. After entering the comparison of the comparator 810, the R input terminal of the SR flip-flop 860 is controlled. 1 volt (V) is just an example of the range in which the comparator 810 compares voltages. In this embodiment, the comparator 810 compares the CS pin voltage with the COMP voltage and the 1V voltage within two level ranges. People familiar with this technology possible circuit changes may be made.

FIG. 10 is a flow chart of a power conversion method with extremely low power consumption according to a specific embodiment of the present invention. In step 1020, a current source is turned on for a first predetermined period, such as charging to a voltage VDDH; A voltage regulator in the power conversion controller reaches a second predetermined period, and generates a driving signal during the second predetermined period, such as a pulse width modulation signal or a pulse frequency modulation signal; in step 1040, assert (assert) The feedback control signal, such as the feedback control signal 822 in FIG. 8 , disables the voltage regulator so that the power conversion controller enters a very low power consumption mode, preferably, the current consumed in the very low power consumption mode One-tenth of the current size lower than normal operation, or lower, preferably, asserting the feedback control signal can also force the current source to be turned off; in step 1060, then asserting the feedback control signal to restore the power conversion controller to normal When the operation reaches the discharge of the external capacitor to the voltage VDDL, that is, the operation reaches the third predetermined period, the external capacitor is controlled to be charged from the voltage VDDL to the voltage VDDH.

11 is a power conversion controller 1100 according to a specific embodiment of the present invention, which has pins such as HV', VDDp', DRV', CS', COMP' and GND'. The power conversion controller 1100 includes a comparator 1110, 1120, hysteresis comparator 1130, oscillator 1140, current source 1142, voltage regulator 1150, flip-flop 1160, AND gates 1170, 1172, buffer 1180, control circuit 1190 and so on.

FIG. 12 is a waveform diagram of main signals in the operation of the power conversion controller 1100 in FIG. 11. The VDDP', DRV', and VCC5V' signals respectively represent the voltage signal of the VDDp' pin, the voltage signal of the DRV pin, and the 5V voltage signal. When the power conversion controller 1100 starts up, the HV pin charges the capacitor (not shown) outside the VDDp pin via the current source 1142. When the potential gradually rises to the point where the input voltage of the positive terminal of the hysteresis comparator 1130 is higher than the first hysteresis The reference voltage VDDH', the output level of the hysteresis comparator 1130 is high, so that the output of the AND gate 1170 is high, enabling the voltage regulator 1150 to output the operating voltage in the signal 1152 to supply the internal operation of the power conversion controller 1100; and, the hysteresis The high level output of the comparator 1130 passes through the inverter 1190 to turn off the current source 1142 and stop the HV' pin from drawing current from the outside. The oscillator 1140 generates a square wave signal and outputs it to the S input terminal of the SR flip-flop 1160, and the R input terminal of the SR flip-flop 1160 is at a low level at first, and the Q output terminal turns to a high level, when the DRV' pin is on When the level is pulled high, the externally connected transistor (not shown) will be turned on, and the current sense (CS') pin will also be pulled high accordingly, through the comparator 1110, the R input of the SR flip-flop 1160 The terminal will change to a high level. When the SR flip-flop 1160 receives a trigger next time, the S input terminal and the R input terminal of the flip-flop 1160 will be at a low level and a high level respectively. After the trigger, the Q output terminal will be at a low level. That is to say, in the operation of this circuit, the input of the S input terminal and the R input terminal are exactly inverting when triggered, so as to generate a pulse width modulation signal on the DRV' pin. For example, the square wave signal is a 1MHz square wave signal to reduce the power consumption of the power conversion controller 1100 in standby mode, and output the square wave signal on the DRV pin through the AND gate 1172 and the buffer 1180 . Then, the capacitor (not shown) outside the VDDp' pin slowly releases the stored power until the input voltage of the positive terminal of the hysteresis comparator 1130 reaches the second hysteresis reference voltage VDDL', so that the output of the hysteresis comparator 1130 is Quasi from high to low, so that the output of the AND gate 1170 is low, the output of the AND gate 1172 is low, the output of the DRV' pin is low, and the external transistor (not shown) connected to it is turned off and the external transformer ( (not shown) on the primary side, as shown in FIG. 12 , VDDP' oscillates back and forth between the voltage VDDH' and the voltage VDDL'. Alternatively, as shown in the waveform on the right side of Figure 12, when the PWM signal is to be generated on the DRV' pin, the voltage of the VDDp' pin is still higher than the voltage VDDL', because the positive input of the hysteresis comparator 1130 The voltage has not yet reached the second hysteresis reference voltage VDDL', the current source 1142 remains inactive, and the HV' pin does not draw external current; after the pulse width modulation signal is generated on the DRV' pin, it will pass through the transformer 1330 in Figure 13 The secondary winding 1332 of the capacitor C1' is charged, so that the voltage on the DRV' pin rises slightly.

13 is an extremely low power consumption display control circuit 1300 according to another specific embodiment of the present invention. The power conversion controller 1340 temporarily draws external power from node B' through the high-voltage power supply pin HV', so that the power conversion controller 1340 The internal controlled current source (not shown) charges the capacitor C1' through the voltage signal VDDp', briefly drives the signal DRV', and activates the primary side of the transformer 1330, so that the transformer 1330 charges the capacitor C1' and the secondary side of the transformer 1330. The large capacitor C2' on the side is charged to a predetermined voltage or charged for a predetermined period. For example, the power conversion controller 1100 in FIG. 11 can be applied to the power conversion controller 1340 in FIG. 13 for operation. In this embodiment, the display controller 1360 can change the voltage ratio of the secondary side of the transformer 1330 in the power saving mode through the GPIO pin, so as to greatly reduce the overall power consumption of the ultra-low power consumption display control circuit 1300 .

Please refer to FIG. 13. In the normal mode, the display controller 1360 turns off the switch SW' through the GPIO pin, and the display controller 1360 provides a normal voltage ratio through the resistor R1', so that the output voltage signal of the secondary side of the transformer 1330 The maximum value of VCC5V' is about 5 volts, and the switch SW' can be realized by using a transistor switch; in the power saving mode, the display controller 1360 reduces the voltage ratio of the secondary side, so that the output voltage signal VCC5V' is reduced to a predetermined low voltage, such as 4 volts, even 3.5 volts, as long as it can ensure that the display controller 1360 can supply enough voltage through the low-dropout linear regulator 1350 in the power-saving mode. For example, the display controller 1360 turns the switch SW' to Through the parallel connection of resistors R1' and R2', the cross-voltage generated by the parallel connection of resistors R1' and R2' is also reduced. Through appropriate design of the resistance of resistors R1' and R2', the output voltage signal is originally at VCC5V' The voltage of about 5 volts is reduced to a predetermined low voltage, such as 3.5 volts.

Please refer to FIG. 13 , for example, a shunt regulator Z' (shunt regulator) can be used to provide a reference voltage of 2.5 volts at node X, and resistors R1' and R2' can be selected to use 5K ohms. In the normal mode, the switch SW' is closed, and the normal voltage ratio is provided through the resistor R1', so that the output voltage signal VCC5V' of the secondary side of the transformer 1330 is 5 volts, and the current I' flowing through the resistor R1' is 0.5 milliseconds. Ampere (mA); after entering the power saving mode, turn on the switch SW', so that the resistors R1' and R2' are connected in parallel so that the parallel resistance value is 2.5K ohms, and the reference voltage and current of 2.5 volts provided by node X are 0.5mA , so that the voltage is reduced from 5 volts to 3.75 volts. On the other hand, the secondary side of the low dropout linear regulator 1350 mainly consumes power in the low dropout linear regulator 1350 and the display controller 1360, assuming the low dropout linear regulator 1350 The power consumption current Is required by the 1350 and the display controller 1360 in the power-saving mode is about 1mA. It can be seen that the power consumption in the power-saving mode can be greatly reduced from the original 5 milliwatts (mW) (=5V*1mA) to 3.75mW (=3.75V*1mA). That is to say, the voltage proportional unit 1370 is coupled to the output of the secondary side of the transformer 1330 and the display controller 1360. The voltage proportional unit 1370 includes resistors R1', R2', RX, and a switch SW'. The voltage proportional unit 1370 receives signals from the shunt The reference voltage provided by the regulator Z' at node X is controlled by the display controller 1360, such as using GPIO pins, so that when the display controller 1360 enters the power saving mode, the voltage ratio provided by the voltage ratio unit 1370 can be changed , thereby reducing the overall power consumption. The directions of the arrows indicate the main current flow directions in several circuit analyzes so that those skilled in the art can better understand the operation of this embodiment.

FIG. 14 is a signal waveform diagram of the output voltage signal VCC5V' according to a specific embodiment of the present invention. With reference to the operation of FIG. The resistor R1' provides a normal voltage ratio, so that the normal output of the voltage signal VCC5V' is 5 volts. When the display controller 1360 enters the power-saving mode, the output of GPIO is pulled high, and the switch SW' is turned on, so that the resistors R1' and R2' are connected in parallel to reduce the voltage ratio, so that the output of the voltage signal VCC5V' in the power-saving mode is reduced. is 3.75 volts, when the display controller 1360 is expected to return to the normal mode, pull down the output of GPIO, close the switch SW', and provide a normal voltage ratio through the resistor R1', so that the normal output of the voltage signal VCC5V' is 5 Volt level, and make the display controller 1360 enter the normal mode. Those skilled in the art can understand that by properly modifying the disclosed circuit, the output of the voltage signal VCC5V' can be further reduced, and the operation of the display controller 1360 can be maintained.

FIG. 15 is a flow chart of a method for controlling an ultra-low power consumption display according to a specific embodiment of the present invention. In step 1520, the display controller enters a power saving mode and activates a mechanism for extremely low power consumption; in step 1530, the display controller Change the voltage ratio through the GPIO pin to reduce the output voltage level of the secondary side of the transformer. voltage to generate a regulated output for displaying the operation of the controller. When the display controller leaves the power-saving mode, it restores the voltage ratio and outputs 5V voltage level through the GPIO pin.

In summary, the present invention discloses a display control circuit with extremely low power consumption, including a transformer having a primary side and a secondary side, a capacitor coupled to the secondary side of the transformer, a voltage regulator, a display controller, and a voltage ratio Unit; the transformer is used to receive high-voltage DC voltage on the primary side to convert it into DC voltage on the secondary side; the capacitor is used to stabilize the DC voltage; the voltage regulator is coupled to the capacitor to receive the DC voltage and generate a DC voltage output; display The controller is coupled to the voltage stabilizer to receive a DC regulated output for operation; the voltage ratio unit is coupled to the display controller and the secondary side of the transformer to receive a reference voltage and provide a voltage ratio to the secondary side; It enables the display controller to change the voltage ratio through the general-purpose input and output pins in the power-saving mode.

The present invention further discloses a method for controlling a very low power consumption power supply, including: displaying that the controller enters the power saving mode; displaying that the controller changes the voltage ratio to reduce the output voltage level of the secondary side of the transformer; The output voltage is regulated by a voltage regulator to generate a regulated output for displaying the operation of the controller in the power-saving mode.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and the scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (20)

1. A very low power consumption display control circuit, characterized in that it comprises: A transformer, having a primary side and a secondary side, is used to receive a high-voltage DC voltage on the primary side to convert it into a DC voltage on the secondary side; a capacitor coupled to the secondary side of the transformer for stabilizing the DC voltage; a voltage regulator, coupled to the capacitor, for receiving the DC voltage and generating a DC regulated output; a display controller, coupled to the regulator, for receiving the DC regulated output and operating; and a voltage ratio unit, coupled to the display controller and the secondary side of the transformer, for receiving a reference voltage and providing a voltage ratio to the secondary side; Wherein, the display controller changes the voltage ratio in a power-saving mode 2. The ultra-low power consumption display control circuit as claimed in claim 1, wherein the display controller changes the voltage ratio through a general-purpose input and output pin in the power-saving mode. 3. The ultra-low power consumption display control circuit as claimed in claim 1, wherein the display controller reduces the voltage ratio in the power saving mode. 4. The ultra-low power consumption display control circuit as claimed in claim 1, wherein the regulator is a low dropout linear regulator. 5. The ultra-low power consumption display control circuit as claimed in claim 1, wherein the voltage proportional unit receives the reference voltage from a shunt regulator. 6. The ultra-low power consumption display control circuit as claimed in claim 1, wherein the voltage proportional unit comprises a first resistor, a second resistor, a third resistor and a switch. 7. The ultra-low power consumption display control circuit as claimed in claim 6, wherein the display controller uses a general-purpose input and output pin to control whether the switch is turned on or not to change the voltage ratio. 8. The ultra-low power consumption display control circuit as claimed in claim 1, wherein the display controller changes the voltage ratio to reduce an output level of the DC voltage generated by the transformer on the secondary side. 9. The ultra-low power consumption display control circuit as claimed in claim 8, wherein the output level of the DC voltage is higher than a predetermined level to operate the display controller. 10. The ultra-low power consumption display control circuit as claimed in claim 9, wherein the predetermined level is 3.3 volts. 11. A display control method with extremely low power consumption, comprising: a display controller enters a power saving mode; The display controller changes a voltage ratio to reduce an output voltage level of a secondary side of a transformer; and The output voltage of the secondary side is regulated by a regulator to generate a regulated output for the display controller to operate in the power-saving mode. 12. The ultra-low power consumption display control circuit as claimed in claim 11, wherein the display controller changes the voltage ratio through a general-purpose input and output pin in the power-saving mode. 13. The ultra-low power consumption display control circuit as claimed in claim 11, wherein the display controller reduces the voltage ratio in the power saving mode to reduce the output voltage level of the secondary side of the transformer. 14. The ultra-low power consumption display control circuit as claimed in claim 11, wherein the regulator is a low dropout linear regulator. 15. The ultra-low power consumption display control circuit as claimed in claim 11, wherein the display controller changes the voltage ratio to reduce an output level of the DC voltage generated by the transformer on the secondary side. 16. The ultra-low power consumption display control circuit as claimed in claim 11, wherein the output level of the DC voltage is higher than a predetermined level to operate the display controller. 17. The ultra-low power consumption display control circuit as claimed in claim 11, wherein the predetermined level is 3.3 volts. 18. The ultra-low power consumption display control circuit as claimed in claim 11, further comprising: a step of the display controller leaving the power saving mode to restore the voltage ratio and the output voltage level. 19. The ultra-low power consumption display control circuit as claimed in claim 13, wherein the display controller turns on a switch to reduce the voltage ratio. 20. The ultra-low power consumption display control circuit as claimed in claim 13, wherein the display controller closes a switch to restore the voltage ratio.

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