CN101908560A - Semiconductor element and manufacturing method thereof - Google Patents

Abstract

The invention relates to a semiconductor element and a manufacturing method thereof. The semiconductor element includes a base, a gate structure, a doped region and a lightly doped region. The base has a stepped upper surface, wherein the stepped upper surface includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is configured on the first surface. The doping region is configured in the substrate on both sides of the gate structure and is located under the second surface. The lightly doped regions are respectively configured in the substrate between the gate structure and the doped regions. Each lightly doped region includes a first portion and a second portion connected to each other. The first part is configured under the second surface, and the second part is configured under the third surface. The semiconductor element has an inclined and curved lightly doped region as an extension of the source and drain, which helps to reduce the hot carrier effect without reducing the dopant concentration of the lightly doped region, and can also reduce the gate-induced drain leakage current Overlap capacitance with gate-drain.

Description

Semiconductor element and its manufacturing method

technical field

The invention relates to a semiconductor element and a manufacturing method thereof, in particular to a metal oxide semiconductor (MOS) transistor and a manufacturing method thereof.

Background technique

With the rapid development of semiconductor manufacturing process technology, in order to increase the speed and performance of components, the size of the entire circuit components must be continuously reduced, and the integration level of components must also be continuously improved. Under the trend of higher and higher requirements for component integration, it is necessary to take into account changes in component characteristics such as leakage current, hot carrier effect (hot carrier effect) or short channel effect (short channel effect, SCE) to Avoid seriously affecting the reliability and performance of the integrated circuit.

Taking a metal oxide semiconductor transistor as an example, FIG. 1 is a schematic cross-sectional view of a conventional metal oxide semiconductor transistor. As shown in FIG. 1 , the gate structure 102 is disposed on the substrate 100 , and the spacers 104 are disposed on sidewalls of the gate structure 102 . A sourcedrain extension (SDE) offset spacer 106 is formed between the gate structure 102 and the spacer 104 , and is located between the spacer 104 and the substrate 100 . The source region 108 a and the drain region 108 b are respectively disposed in the substrate 100 outside the spacer 104 . The source extension region 110 a and the drain extension region 110 b are respectively disposed in the substrate 100 below the spacer 104 . That is to say, the source extension region 110 a is located between the source region 108 a and the gate structure 102 , and the drain extension region 110 b is located between the drain region 108 b and the gate structure 102 . A salicide 112 is also disposed on the gate structure 102 , the source region 108 a and the drain region 108 b.

Considering that the concentration of the source extension region 110a and the drain extension region 110b will affect device performance, the doping dose of the source extension region 110a and the drain extension region 110b must be heavy enough to ensure device performance and quality. However, the heavily doped source extension region 110a and drain extension region 110b will cause high gate-induced drain leakage (GIDL) and serious hot carrier effect. Although the gate-induced drain leakage current and hot carrier effect can be slowed down by reducing the dopant dose of the source-drain extension, it will make the overlap capacitance between the sheet resistance and the gate-drain (gate- drain overlap capacity) rises and seriously affects device performance. Furthermore, the spacer 104 must be thick enough to prevent the dopant of the source region 108a and the drain region 108b from diffusing into the source extension region 110a and the drain extension region 110b, and must reserve enough space for the source and drain to diffuse, In order to fully suppress the occurrence of electrical breakdown (punch through) and short channel effect. In addition, when a stress layer is formed on the substrate 100 , the thick spacer 104 tends to cause the stress layer to be far away from the channel region, thereby reducing the effect of the stress layer on improving carrier mobility.

It can be seen that the above-mentioned existing semiconductor element and its manufacturing method obviously still have inconveniences and defects in structure and use, and need to be further improved urgently. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above-mentioned problems. How to effectively ensure the semiconductor components Reliability of components and improvement of the performance of semiconductor components are obviously problems that related companies are eager to solve. Therefore, how to create a new semiconductor device and its manufacturing method is one of the current important research and development topics, and has also become a goal that the industry needs to improve.

Contents of the invention

The main purpose of the present invention is to overcome the defects of existing semiconductor elements and provide a new semiconductor element. The technical problem to be solved is to improve the performance of the element, which is very suitable for practical use.

Another object of the present invention is to provide a new method for manufacturing a semiconductor device. The technical problem to be solved is to form inclined and curved source-drain extensions (SDEs), which is more suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to the semiconductor device provided by the present invention, it includes a substrate, a gate structure, a doped region and a lightly doped region. The base has a stepped upper surface, wherein the stepped upper surface includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is configured on the first surface. The doping region is configured in the substrate on both sides of the gate structure and is located under the second surface. The lightly doped regions are respectively configured in the substrate between the gate structure and the doped regions. Each lightly doped region includes a first portion and a second portion connected to each other. The first part is configured under the second surface, and the second part is configured under the third surface.

The purpose of the present invention and the solution to its technical problems can also be further realized by adopting the following technical measures.

In an embodiment of the present invention, the above-mentioned third surface is inclined to the first surface, and the angle formed by the extending direction of the first surface and the third surface is between 45° and 60°.

In an embodiment of the present invention, the above-mentioned first surface is substantially parallel to the second surface.

至之间，而第一表面与第二表面之间的水平间距介于

至

之间。In an embodiment of the present invention, the above-mentioned height difference between the first surface and the second surface is between

to between , and the horizontal distance between the first surface and the second surface is between

to

between.

至

之间，而第二部分的长度介于

至

之间。In one embodiment of the present invention, the length of the first part of each lightly doped region is between

to

between , and the length of the second part is between

to

between.

至

之间。间隙壁的材料可以是氧化物、氮氧化物(oxynitride)、氮化氧化物(nitrided oxide)、氮化物或上述材料的组合。In an embodiment of the present invention, the semiconductor device further includes a spacer disposed on the sidewall of the gate structure and located on the lightly doped region. The thickness of the spacer is, for example, between

to

between. The material of the spacer can be oxide, oxynitride, nitrided oxide, nitride or a combination of the above materials.

In an embodiment of the present invention, the semiconductor device further includes a salicide layer disposed on the gate structure and the doped region.

In an embodiment of the present invention, the semiconductor device further includes a stress layer disposed on the substrate. The stress layer is, for example, a nitride film that provides compressive stress or tensile stress to the channel region.

In an embodiment of the present invention, the semiconductor device further includes a well region disposed in the substrate, wherein the doped region and the lightly doped region are located in the well region.

In an embodiment of the present invention, the semiconductor device further includes pocket (ring) implanted regions disposed in the substrate under the gate structure, and each pocket (ring) implanted region is adjacent to each doped Miscellaneous area. The pocket (annular) implantation area is, for example, a localized (annular) pocket (annular) implantation area or a multiple (multiple) pocket (annular) implantation area.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. According to the manufacturing method of the semiconductor element proposed by the present invention. First, a substrate is provided, and a gate structure is formed on the substrate. Using the gate structure as a mask to remove part of the substrate to form a stepped upper surface, wherein the stepped upper surface includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. Lightly doped regions are formed in the substrate on both sides of the gate structure. Each lightly doped region includes a first portion and a second portion connected to each other. The first part is configured under the second surface, and the second part is configured under the third surface. Doped regions are formed in the base, and each doped region is located under the second surface and adjacent to the lightly doped region respectively.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In an embodiment of the present invention, the above-mentioned third surface is inclined to the first surface, and the angle formed by the extending direction of the first surface and the third surface is between 45° and 60°.

In an embodiment of the present invention, the above-mentioned first surface is substantially parallel to the second surface.

至之间，而第一表面与第二表面之间的水平间距介于

至

之间。In an embodiment of the present invention, the above-mentioned height difference between the first surface and the second surface is between

to between , and the horizontal distance between the first surface and the second surface is between

to

between.

至

之间，而第二部分的长度介于

至

之间。In one embodiment of the present invention, the length of the first part of each lightly doped region is between

to

between , and the length of the second part is between

to

between.

至

之间。In an embodiment of the present invention, the above method further includes forming a first spacer on the sidewall of the gate structure and the lightly doped region. The thickness of the first spacer is, for example, between

to

between.

In an embodiment of the present invention, the above-mentioned method for forming a first spacer includes the following steps. First, a spacer material layer is formed on a substrate. Next, a second spacer is formed on the sidewall of the gate structure, wherein the second spacer covers part of the material layer of the spacer on the lightly doped region. Using the second spacer as a mask to remove part of the material layer of the spacer, and then removing the second spacer.

In an embodiment of the present invention, after removing part of the spacer material layer, a doped region is formed using the second spacer as a mask. The lightly doped region is formed after the spacer material layer is formed and before the second spacer is formed; or, the lightly doped region is formed after the second spacer is removed.

In an embodiment of the present invention, after forming the first spacer, the lightly doped region and the doped region are formed. The lightly doped region and the doped region are formed by, for example, a single manufacturing process or a two-step manufacturing process.

In an embodiment of the present invention, the above method further includes forming a salicide layer on the gate structure and the doped region.

In an embodiment of the present invention, the above method further includes forming a stress layer on the substrate, such as a nitride film that provides compressive stress or tensile stress to the channel region.

In an embodiment of the present invention, before forming the gate structure, it further includes forming a well region in the substrate, wherein the doped region and the lightly doped region are formed in the well region.

In an embodiment of the present invention, the above method further includes forming pocket (ring) implanted regions in the substrate under the gate structure, and each pocket (ring) implanted region is adjacent to each doped Miscellaneous area. The pocket (annular) implantation area is, for example, a partial pocket (annular) implantation area or a compound pocket (annular) implantation area. The aforementioned pocket (annular) implanted region can be formed after forming the stepped upper surface, or after forming the lightly doped region, or after forming the spacer material layer and before forming the lightly doped region .

By virtue of the above technical solutions, the semiconductor element and its manufacturing method of the present invention have at least the following advantages and beneficial effects:

Based on the above, the semiconductor device of the present invention has inclined and curved lightly doped regions as source-drain extensions (SDEs), which can help alleviate hot carrier effects without reducing the dopant concentration of the lightly doped regions. Furthermore, since the lightly doped region has an inclined and curved profile, the overlapping capacitance between the gate-induced drain leakage (GIDL) and the gate-drain can be reduced.

In addition, the manufacturing method of the semiconductor element of the present invention forms an inclined and curved lightly doped region, so the diffusion of the lightly doped region will not be affected by the diffusion of the doped region, and a thinner gap can be formed in the structure of the semiconductor element wall. In this way, by forming a thinner spacer, the thinner spacer and the obliquely etched substrate can make the stress layer closer to the channel region, so that the stress layer can enhance the electron mobility more efficiently, so that the device performance can be obtained. further improvements.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a conventional metal oxide semiconductor transistor.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

3A to 3E are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

4A to 4C are schematic cross-sectional views of a manufacturing process of a semiconductor device according to another embodiment of the present invention.

5A to 5C are schematic cross-sectional views of a manufacturing process of a semiconductor device according to yet another embodiment of the present invention.

FIG. 6 shows the lateral electric field distribution curves corresponding to different positions in the channel region parallel to the first surface according to the conventional NMOS and the NMOS of the experimental example of the present invention.

100, 200, 300: substrate 102, 204, 310: gate structure

104, 210, 312a, 318, 402, 404, 502, 504: spacers

106: offset spacer 108a: source region

108b: drain region 110a: source extension region

110b: Drain extension region 112: Self-aligned metal silicide

201, 301: stepped upper surface 201a, 301a: first surface

201b, 301b: second surface 201c, 301c: third surface

202, 302: well area 204a: grid

204b: gate dielectric layer

206, 322, 408, 509, 509a, 509b: doped regions

208, 316, 412, 508: Lightly doped regions

208a, 316a, 412a, 508a: Part I

208b, 316b, 412b, 508b: Part II

210a: thickness

212, 324, 416, 510: self-aligned metal silicide layers

214, 326, 418, 512: stress layer

304: Dielectric layer 306: Conductor layer

308: Patterned hard mask layer 312: Spacer material layer

314, 320, 406, 410, 506, 507: Implant Manufacturing Process

D ₁ : height difference D ₂ : horizontal spacing

L ₁ , L ₂ : Length ψ: Angle

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation, structure, characteristics and methods of the semiconductor element and its manufacturing method according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. Its effect is described in detail below.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It should be noted that in the following embodiments, the P type is used to represent the first conductivity type, and the N type is used to represent the second conductivity type, but the invention is not limited thereto. Those skilled in the art should understand that in the present invention, the first conductivity type can be replaced by N type, and the second conductivity type can be replaced by P type to form a semiconductor device.

至

之间。在一实施例中，第一表面201a与第二表面201b之间的水平间距D₂介于

至之间。在一实施例中，第一表面201a的延伸方向与第三表面201c所形成的夹角ψ介于45°至60°之间。Referring to FIG. 2 , the semiconductor device of the present invention at least includes a substrate 200 , a gate structure 204 , a doped region 206 and a lightly doped region 208 . A substrate 200 with a first conductivity type is provided, which may be a P-type silicon substrate, a P-type epi-silicon (epi-silicon) substrate or a P-type semiconductor-on-insulator (SOI) substrate. The base 200 has, for example, a stepped upper surface 201 . The stepped upper surface 201 includes a first surface 201a, a second surface 201b and a third surface 201c, wherein the third surface 201c connects the first surface 201a and the second surface 201b. The second surface 201b lower than the first surface 201a may be substantially parallel to the first surface 201a. When the first surface 201a and the second surface 201b are substantially flat, the third surface 201c may be inclined to the first surface 201a. That is to say, the third surface 201c is an inclined surface between the first surface 201a and the second surface 201b, wherein the upper edge of the inclined surface is connected to the first surface 201a, and the lower edge of the inclined surface is connected to the second surface 201b. In one embodiment, the height difference _D1 between the first surface 201a and the second surface 201b is between

to

between. In one embodiment, the horizontal distance _D2 between the first surface 201a and the second surface 201b is between

to between. In one embodiment, the angle ψ formed by the extending direction of the first surface 201 a and the third surface 201 c is between 45° and 60°.

In addition, a well region 202 of the first conductivity type, such as a P-well region (P-well), is disposed in the substrate 200 . In one embodiment, a localized pocket (annular) implant region or a multiple pocket (annular) implant region with the first conductivity type (such as P-type) can be further configured in the well area 202 in. The partial pocket (ring) implant region or the compound pocket (ring) implant region is, for example, disposed under the gate structure 204 and adjacent to each doped region 206 respectively. The well area 202 is, for example, only a super steep retrograde (SSR) well. In another embodiment, the well region 202 may also be a combination of a super-steep setback well and a pocket (annular) implanted region.

至以抑制从栅极204a的漏电流。栅介电层204b的材料可以是氧化物、氮化氧化物(nitrided oxide)、氮氧化物(oxynitride)或高介电常数(high-K)材料，其中高介电常数材料例如是铪(Hf)、氧化钛(TiO_x)、氧化铪(HfO_x)、氮氧化硅铪(HfSiON)、氧化铝铪(HfAlO)、氧化铝(Al₂O₃)。The gate structure 204 is disposed on the first surface. The length of the gate structure 204 is, for example, corresponding to the length of the first surface 201a. The gate structure 204 includes a gate 204 a and a gate dielectric layer 204 b, wherein the gate dielectric layer 204 b is disposed between the gate 204 a and the substrate 200 . The length of the gate 204a can be as small as 90nm or other smaller dimensions. The material of the gate 204a can be metal, doped polysilicon, silicon-germanium or a combination of polysilicon and metal. The effective oxide thickness (EOT) of the gate dielectric layer 204b is, for example, about

to To suppress the leakage current from the gate 204a. The material of the gate dielectric layer 204b can be oxide, nitrided oxide (nitrided oxide), oxynitride (oxynitride) or high dielectric constant (high-K) material, wherein the high dielectric constant material is hafnium (Hf ), titanium oxide (TiO _x ), hafnium oxide (HfO _x ), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), aluminum oxide (Al ₂ O ₃ ).

The doped region 206 of the second conductivity type is disposed in the substrate 200 on both sides of the gate structure 204 . The doped region 206 is disposed under the second surface 201b. The doped region 206 may be an N+ doped region to serve as a source and a drain of the semiconductor device, respectively.

至

之间。在一实施例中，第一部分208a的长度L₁介于

至

之间。在一实施例中，第二部分208b的长度L₂介于

至

之间。值得注意的是，由于第三表面201c为倾斜面，因此各轻掺杂区208的倾斜角被控制在45°至60°的范围内，以保持元件的击穿特性(punch through characteristic)。The lightly doped region 208 of the second conductivity type is disposed in the substrate 200 between the gate structure 204 and the doped region 206 . The lightly doped region 208 having the same conductivity type as the doped region 206 is electrically connected to the corresponding doped region 206 on both sides of the gate structure 204 , thus serving as a source-drain extension (SDE). Each lightly doped region 208 includes a first portion 208 a and a second portion 208 b connected to each other. The first portion 208a is disposed under the second surface 201b and adjacent to the third surface 201c. The second portion 208b is disposed under the third surface 201c. In an embodiment, sometimes the second portion 208b slightly extends to the area below the first surface 201a. Since the total horizontal length of each lightly doped region 208 depends on the length of the gate 204a, when the length of the gate 204a shrinks, the distribution area of the lightly doped region 208 can be shortened. Taking the gate 204a with a length of about 90nm as an example, the horizontal distribution of each lightly doped region 208 is between about

to

between. In one embodiment, the length L ₁ of the first portion 208a is between

to

between. In one embodiment, the length L ₂ of the second portion 208b is between

to

between. It is worth noting that since the third surface 201c is an inclined plane, the inclination angle of each lightly doped region 208 is controlled within a range of 45° to 60° to maintain the punch through characteristic of the device.

Generally speaking, the lateral electric field only depends on the surface doping characteristics of the lightly doped region 208 . Since the lightly doped region 208 has an inclined and curved profile formed by the first portion 208a and the second portion 208b, the first portion 208a can provide a reserved space for the doped region 206 to diffuse. In the structure of this semiconductor device, the surface doping of a small part of the lightly doped region 208 under the first surface 201a is very light, so the doping dose of the lightly doped region 208 can be reduced and the lightly doped region 208 can be In the case of resistance, it effectively reduces the hot carrier effect, the overlapping capacitance between the gate and the drain, and the gate induced drain leakage (GIDL). In detail, since the doping concentration in the overlapping region between the gate and the drain is significantly reduced, the hot carrier effect, the gate induced drain leakage (GIDL) and the overlapping capacitance between the gate and the drain are also reduced. will decrease. Moreover, the diffusion of the lightly doped region 208 under the gate structure 204 has nothing to do with the diffusion of the doped region 206 , so the doping concentration of the doped region 206 can be heavy and deep enough.

至

之间。In addition, the semiconductor device of the present invention may further include a spacer 210 , a salicide layer 212 and a stress layer 214 . The spacer 210 is disposed on the sidewall of the gate structure 204 and located on the lightly doped region 208 . The spacer 210 has, for example, a curved shape corresponding to the contours of the sidewall of the gate structure 204 , the third surface 201c and a part of the second surface 201b. In other words, the spacer 210 can isolate the sidewall of the gate structure 204 from the outside, and cover the portion of the substrate 200 formed with the lightly doped region 208 . The material of the spacer 210 includes oxide, oxynitride, nitrided oxide, nitride or a combination of the above materials. In one embodiment, the thickness 210a of the spacer 210 is between about

to

between.

The salicide layer 212 is disposed on the gate structure 204 and the doped region 206 . The material of the salicide layer 212 is, for example, nickel silicide ( _NiSix ) or cobalt silicide ( _CoSix ). In one embodiment, a contact window (not shown) may also be formed on the gate structure 204 and the doped region 206 , since the salicide layer 212 is disposed, the resistance on the interface will be reduced.

至

的范围内，以缩短应力层214与沟道区之间的距离，因而可改善因应力层214所提升的元件效能。The stress layer 214 is disposed on the gate structure 204 and the substrate 200 . The stress layer 214 may be a nitride film that provides compressive stress or tensile stress to the channel region (ie, the channel region, hereinafter referred to as the channel region). In one embodiment, the nitride film that causes tensile stress in the channel region is used for NMOS, and the nitride film that causes compressive stress in the channel region is used for PMOS. For a technology node of 90nm, the thickness of the stress layer 214 will fall within to In the range. Generally speaking, the thickness 210a of the spacer 210 is one of the main factors affecting the short channel effect. By thinning the thickness 210a of the spacer 210 to

to

Within the range, the distance between the stress layer 214 and the channel region can be shortened, thereby improving the performance of the device due to the stress layer 214 .

In particular, since the diffusion of the lightly doped region 208 under the gate structure 204 has nothing to do with the diffusion of the doped region 206, the doping concentration of the doped region 206 will be heavy and deep enough to facilitate self-alignment. Formation of metal silicide layer 212 . In addition, because the lightly doped region 208 has the first portion 208a, the spacer 210 can be thinned. The thinner spacer 210 and the substrate 200 having a concave surface help to make the stress layer 214 closer to the channel region under the gate structure 204 , thereby improving carrier mobility and improving device performance.

Next, the method for manufacturing the semiconductor device according to the embodiment of the present invention will be described further by using a schematic cross-sectional view. The flow described below is only to illustrate the manufacturing flow of the method of the present invention in forming the semiconductor device shown in FIG. 2 so that those skilled in the art can implement it accordingly, but it is not intended to limit the scope of the present invention.

3A to 3E are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A , a substrate 300 with a first conductivity type is provided, which may be a P-type silicon substrate, a P-type epitaxial silicon substrate, or a P-type semiconductor-on-insulator (SOI) substrate. A well region 302 of the first conductivity type is formed in the substrate 300 , wherein the well region 302 is, for example, a P-type well region. In one embodiment, the well region 302 may be a profile forming a super steep setback (SSR) well.

至

之间，以防止漏电流的发生。Referring to FIG. 3B , a dielectric layer 304 , a conductive layer 306 and a patterned hard mask layer 308 are sequentially formed on a substrate 300 . The material of the dielectric layer 304 can be oxide, nitrided oxide (nitrided oxide), oxynitride (oxynitride) or high dielectric constant (high-K) material, wherein the high dielectric constant material is hafnium (Hf) for example , titanium oxide (TiO _x ), hafnium oxide (HfO _x ), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), aluminum oxide (Al ₂ O ₃ ). The material of the conductive layer 306 can be metal, doped polysilicon, silicon-germanium or a combination of polysilicon and metal. Using the patterned hard mask layer 308 as a mask, a portion of the dielectric layer 304 and a portion of the conductive layer 306 are removed to define a gate structure 310 on the substrate 300 . The patterned dielectric layer 304 is used as a gate dielectric layer, and the patterned conductive layer 306 is used as a gate. In one embodiment, the length of the gate can be 90nm or other smaller dimensions, and the effective oxide thickness (EOT) of the gate dielectric layer can be between about

to

between to prevent the occurrence of leakage current.

至

之间。在一实施例中，第一表面301a与第二表面301b之间的水平间距D₂介于

至

之间。在一实施例中，第一表面301a的延伸方向与第三表面301c所形成的夹角ψ介于45°至60°之间。Afterwards, a portion of the substrate 300 is removed to form a stepped upper surface 301 . A method for removing part of the substrate 300 is, for example, using the gate structure 310 as a mask to perform a sloped silicon etching process. In one embodiment, the oblique silicon etching process (ie, the process, referred to herein as the process) may be wet etching using a suitable recipe including various acids. In another embodiment, the oblique silicon etching process may also be plasma etching using a suitable combination of various gases (such as CHF ₃ , CF ₄ , Ar, O ₂ ). The formed stepped upper surface 301 includes a first surface 301a, a second surface 301b and a third surface 301c, wherein the third surface 301c connects the first surface 301a and the second surface 301b. The first surface 301 a is, for example, a position corresponding to the gate structure 310 . The second surface 301b lower than the first surface 301a may be substantially parallel to the first surface 301a. When the first surface 301a and the second surface 301b are substantially flat, the third surface 301c may be inclined to the first surface 301a. That is to say, the third surface 301c is an inclined surface between the first surface 301a and the second surface 301b, wherein the upper edge of the inclined surface is connected to the first surface 301a, and the lower edge of the inclined surface is connected to the second surface 301b. In one embodiment, the height difference _D1 between the first surface 301a and the second surface 301b is between

to

between. In one embodiment, the horizontal distance _D2 between the first surface 301a and the second surface 301b is between

to

between. In one embodiment, the angle ψ formed by the extension direction of the first surface 301 a and the third surface 301 c is between 45° and 60°.

Referring to FIG. 3C , the patterned hard mask layer 308 is removed. Next, a spacer material layer 312 is formed on the substrate 300 . The spacer material layer 312 covers, for example, the gate structure 310, the second surface 301b and the third surface 301c. In one embodiment, the thickness of the spacer material layer 312 is between about to between. The material of the spacer material layer 312 includes oxide, oxynitride, nitrided oxide, nitride or a combination of the above materials. The method for forming the spacer material layer 312 may be a deposition process or a rapid thermal process (rapid thermal process, RTP). The rapid thermal process is, for example, an in-situ steam generation (ISSG) oxidation process.

时，可以使用10-15KeV的能量与5e¹⁴-3e¹⁵cm^-2的剂量来进行植入制造工艺314，且可以利用5°-10°的倾斜角植入掺质。在一实施例中，当元件尺寸更缩减且间隙壁材料层312的厚度变薄至

时，植入制造工艺314的能量可减低至2-7KeV。Subsequently, an implantation process 314 is performed to form lightly doped regions 316 of the second conductivity type (N type) on the substrate 300 on both sides of the gate structure 310 . The lightly doped region 316 is, for example, a junction as a source-drain extension (SDE) in the substrate 300 . The lightly doped region 316 can be formed using a vertical implant or an angled implant using low energy to form a shallow source-drain extension (SDE) junction depth and using a sufficiently heavy dose to reduce sheet resistance. In one embodiment, when the gate length is about 90 nm and the thickness of the spacer material layer 312 is about

When , the implantation process 314 can be performed with an energy of 10-15KeV and a dose of 5e ¹⁴ -3e ¹⁵ cm ^-2 , and the dopant can be implanted with an inclination angle of 5°-10°. In one embodiment, when the device size is further reduced and the thickness of the spacer material layer 312 is thinned to

When , the energy of the implantation process 314 can be reduced to 2-7KeV.

It should be noted that the implantation process 314 may also be performed after the gate structure 310 is formed and before the spacer material layer 312 is formed. Taking the technology node of 90nm as an example, the implantation process 314 can be performed with an energy of 2-5KeV and a dose of 5e ¹⁴ -1e ¹⁵ cm ^-2 , and dopants can be vertically implanted with an inclination angle of 0°. When the device size is further reduced, lower energy is required to perform the implantation process 314, and an energy of about 0.1-1 KeV can be used.

In addition, in an embodiment, after the step-shaped upper surface 301 is formed or after the lightly doped region 316 is formed, a local pocket (annular pocket) of the first conductivity type (such as P-type) can also be formed in the well region 302. shape) or compound pocket (annular) implantation area. In another embodiment, after forming the spacer material layer 312 and before forming the lightly doped region 316 , a pocket-shaped (ring-shaped) implanted region may be formed in the well region 302 . That is, the well region 302 may be a super-steep setback (SSR) well only, or a combination of a super-steep setback well and a pocket (annular) implanted region. The partial pocket (ring-shaped) implanted regions or composite pocket (ring-shaped) implanted regions are respectively formed under the gate structure 310 and adjacent to the doped regions pre-formed later, for example. The aforementioned pocket (annular) region can be formed by vertical implantation, or by implantation at an inclination angle of 7°-45°.

Referring to FIG. 3D , a spacer 318 is formed on the sidewall of the gate structure 310 . The spacer 318 covers a portion of the spacer material layer 312 to define a source region and a drain region to be pre-formed later. A portion of the spacer material layer 312 is removed using the spacer 318 as a mask. The remaining spacer material layer 312 forms spacers 312 a, and each spacer 312 a is respectively disposed between the spacer 318 and the sidewall of the gate structure 310 . An implantation process 320 is performed to form doped regions 322 of the second conductivity type in the outer substrate 300 of the spacers 318 . The doped region 322 is formed under the second surface 301 b and is electrically connected to the lightly doped region 316 . The doped region 322 is, for example, an N+ doped region to serve as a source region and a drain region respectively. After the spacers 318 are formed, the implant process 320 may be performed in a vertical implant using higher energy than the implant process 314 . The deep and heavily doped region 322 can help reduce the sheet resistance and facilitate the subsequent metal silicide manufacturing process. In one embodiment, for a technology node of 90nm, ^the implantation process 320 may be performed using an energy of 10-20KeV and a dose of ^{1e15-3e15cm -2} .

Referring to FIG. 3E , a tempering process can also be performed to activate the dopant. In the technology node of 90nm, the tempering manufacturing process can be a general soak tempering manufacturing process or a spike tempering manufacturing process. For smaller components, other advanced tempering techniques can also be used, such as fast (flash) or laser (laser) tempering manufacturing process.

至

之间。须注意的是，上述自对准金属硅化物层324、应力层326等构件的形成方法及形成顺序当为此技术领域的人员所熟知，故于此不赘述其细节。Afterwards, the spacer 318 is removed, and a salicide layer 324 is formed on the gate structure 310 and the doped region 322 . The material of the salicide layer 324 may be nickel silicide ( _NiSix ) or cobalt silicide ( _CoSix ). In one embodiment, the salicide layer 324 may be formed before or after the spacer 318 is removed. Next, a stress layer 326 is formed on the substrate 300 to complete the semiconductor device of the present invention. The stress layer 326 may be a nitride film that provides compressive stress or tensile stress to the channel region. In this embodiment, the stress layer 326 induces tensile stress in the channel region of the NMOS. In another embodiment, the nitride film that induces compressive stress in the channel region can be used as the stress layer of the PMOS. For a technology node of 90nm, the thickness of the stress layer 326 is, for example, between about

to

between. It should be noted that the formation method and formation sequence of the aforementioned salicide layer 324 , stress layer 326 and other components are well known to those skilled in the art, so details thereof will not be repeated here.

至

之间。在一实施例中，第一部分316a的长度L₁介于

至

之间。在一实施例中，第二部分316b的长度L₂介于

至

之间。值得注意的是，由于第三表面301c为倾斜面，因此各轻掺杂区316的倾斜角被控制在45°至60°的范围内，以保持元件的击穿特性。倾斜且弯曲的轻掺杂区316在表面具有较轻的掺杂浓度，因此可减轻热载子效应，并在不增加源极漏极延伸(SDE)电阻的情况下减少栅极引发漏极漏电流(GIDL)与栅极漏极间的重叠电容。在回火制造工艺的过程中，由于轻掺杂区316具有倾斜且弯曲的轮廓，因此轻掺杂区316在栅极结构310下方的扩散与掺杂区322的扩散无关，而掺杂区322的掺杂浓度可以够重且够深以利进行金属硅化制造工艺。而且，由于间隙壁312a薄且顺应基底300的外型而弯曲，因此应力层326会更靠近沟道区，而可有效提升元件效能。Please refer to FIG. 3E again, each lightly doped region 316 disposed in the substrate 300 between the gate structure 310 and the doped region 322 includes a connected first portion 316a and a second portion 316b to form an inclined and curved Outline. The first portion 316a is disposed under the second surface 301b and adjacent to the third surface 301c. The second portion 316b is disposed under the third surface 301c, and a small portion of the second portion 316b may extend below the first surface 301a. When the gate length is about 90nm, the horizontal distribution of each lightly doped region 316 is, for example, between about

to

between. In one embodiment, the length L ₁ of the first portion 316a is between

to

between. In one embodiment, the length _L2 of the second portion 316b is between

to

between. It is worth noting that since the third surface 301c is an inclined plane, the inclination angle of each lightly doped region 316 is controlled within a range of 45° to 60° to maintain the breakdown characteristics of the device. The sloped and curved lightly doped region 316 has a lighter doping concentration at the surface, thereby mitigating hot carrier effects and reducing gate-induced drain leakage without increasing source-drain extension (SDE) resistance current (GIDL) and overlap capacitance between gate and drain. During the tempering manufacturing process, since the lightly doped region 316 has an inclined and curved profile, the diffusion of the lightly doped region 316 under the gate structure 310 has nothing to do with the diffusion of the doped region 322, while the doped region 322 The doping concentration can be heavy enough and deep enough to facilitate the metal silicide manufacturing process. Moreover, since the spacer 312 a is thin and curved following the shape of the substrate 300 , the stress layer 326 is closer to the channel region, which can effectively improve device performance.

4A to 4C are schematic cross-sectional views of a manufacturing process of a semiconductor device according to another embodiment of the present invention. It should be noted that the manufacturing process shown in FIG. 4A to FIG. 4C is a step after FIG. 3B . In FIGS. 4A to 4C , the same components as those in FIG. 3B are assigned the same reference numerals and their descriptions are omitted.

Referring to FIG. 4A , the patterned hard mask layer 308 is removed. Next, a spacer 402 and a spacer 404 are formed on the sidewalls of the gate structure 310 and part of the substrate 300 . The curved spacer 402 may be formed using a disposable spacer 404 . The spacers 402 are respectively disposed between the spacers 404 and the sidewalls of the gate structure 310 . The spacer 402 and the spacer 404 cover the third surface 301c and cover a part of the second surface 301b, so the spacer 402 and the spacer 404 can be used to define the source region and the drain region to be pre-formed later.

Next, an implantation process 406 is performed to respectively form doped regions 408 of the second conductivity type in the outer substrate 300 of the spacers 404 . The doped region 408 formed under the second surface 301b is, for example, an N+ doped region to serve as a source region and a drain region respectively. The implant fabrication process 406 may be performed in a vertical implant using higher energies than forming source drain extensions (SDE). In one embodiment, for a technology node of 90nm, ^the implantation process 406 may be performed using an energy of 10-20KeV and a dose of ^{1e15-3e15cm -2} .

时，可以使用10-15KeV的能量与5e¹⁴-3e¹⁵cm^-2的剂量来进行植入制造工艺410，且可以利用5°-10°的倾斜角植入掺质。在一实施例中，当元件尺寸更缩减且间隙壁402的厚度变薄至

时，植入制造工艺410的能量可减低至2-7KeV。Referring to FIG. 4B , the spacer 404 is removed. An implantation process 410 is performed to form lightly doped regions 412 of the second conductivity type (N type) in the substrate 300 on both sides of the gate structure 310 . The lightly doped region 412 can be formed using vertical implantation, or using low energy and using oblique angle implantation. In one embodiment, when the gate length is about 90 nm and the thickness of the spacer 402 is about

When , the implantation process 410 can be performed with an energy of 10-15KeV and a dose of 5e ¹⁴ -3e ¹⁵ cm ^-2 , and the dopant can be implanted with an inclination angle of 5°-10°. In one embodiment, when the device size is further reduced and the thickness of the spacer wall 402 is thinned to

When , the energy of the implant manufacturing process 410 can be reduced to 2-7KeV.

至

之间。在一实施例中，第一部分412a的长度L₁介于

至

之间。在一实施例中，第二部分412b的长度L₂介于至

之间。特别说明的是，由于第三表面301c为倾斜面，因此各轻掺杂区412的倾斜角可被控制在45°至60°的范围内，以保持元件的击穿特性。Referring to FIG. 4C , a tempering process can also be performed to activate the dopant. Afterwards, a salicide layer 416 is formed on the gate structure 310 and the doped region 408 . Next, a stress layer 418 is formed on the substrate 300 to complete the semiconductor device of the present invention. As shown in FIG. 4C, each lightly doped region 412 disposed in the substrate 300 between the gate structure 310 and the doped region 408 includes a first portion 412a and a second portion 412b, wherein the first portion 412a is connected to the second portion 412b . The first portion 412a is disposed under the second surface 301b and adjacent to the third surface 301c. The second portion 412b is disposed under the third surface 301c, and a small area of the second portion 412b may extend below the first surface 301a. When the length of the gate is about 90nm, the horizontal distribution of each lightly doped region 412 can be between about

to

between. In one embodiment, the length L ₁ of the first portion 412a is between

to

between. In one embodiment, the length L ₂ of the second portion 412b is between to

between. In particular, since the third surface 301c is an inclined plane, the inclination angle of each lightly doped region 412 can be controlled within a range of 45° to 60°, so as to maintain the breakdown characteristics of the device.

5A to 5C are schematic cross-sectional views of a manufacturing process of a semiconductor device according to yet another embodiment of the present invention. It should be noted that the manufacturing process shown in FIG. 5A to FIG. 5C is a step after FIG. 3B . In FIGS. 5A to 5C , the same components as those in FIG. 3B are assigned the same reference numerals and their descriptions are omitted.

Referring to FIG. 5A , the patterned hard mask layer 308 is removed. Next, a spacer 502 and a spacer 504 are formed on the sidewalls of the gate structure 310 and part of the substrate 300 . The curved spacer 502 is formed by, for example, a disposable spacer 504 . The spacers 502 are respectively disposed between the spacers 504 and the sidewalls of the gate structure 310 . The spacer 502 and the spacer 504 cover the third surface 301c and part of the second surface 301b, and can be used to define the subsequent pre-formed source-drain extension (SDE), source region and drain region.

Referring to FIG. 5B-1 , the spacer 504 is removed. The implantation process 506 is performed to form lightly doped regions 508 and doped regions 509 a of the second conductivity type (N type) in the substrate 300 on both sides of the gate structure 310 . The lightly doped region 508 is formed under the spacer 502 , and the doped region 509 a is formed outside the spacer 502 , for example.

Please refer to FIG. 5B-2. In another embodiment, low energy can be used to selectively perform implantation manufacturing process 507 to form the second conductivity type (N type) doped region 509b, so that the source-drain (SD) diffusion region is deeper. The doped region 509b is, for example, formed in the range of the doped region 509a. It is noted here that the present invention does not impose any limitation on the order of performing the implantation manufacturing process 506 and the implantation manufacturing process 507 , that is, the above-mentioned order of performing the implantation manufacturing process 506 and the implantation manufacturing process 507 can be reversed.

为例，可以使用约15KeV的能量与1e¹⁵-3e¹⁵cm^-2的剂量来进行单一植入制造工艺，并使用5°-10°的倾斜角来植入掺质，如此一来就可以同时形成所需的结轮廓。Based on the above, the shallow source-drain extension (SDE) region and the source-drain (SD) diffusion region can be formed simultaneously by a single implant process using appropriate energy, or by performing a double implant process to Dopants are implanted into the substrate 300 twice. In one embodiment, as shown in FIG. 5B-1 , during the single implantation process to simultaneously form the lightly doped region 508 and the doped region 509a, since the spacer 502 covers the substrate 300, the lightly doped The region 508 forms a shallow junction; the doped region 509a forms a deeper junction since there is no shielding from the spacer 502 . With a technology node of 90nm and the thickness of the spacer 502 is about

As an example, a single implantation process can be performed with an energy of about 15KeV and a dose of 1e ¹⁵ -3e ¹⁵ cm ^-2 , and a dopant can be implanted with an inclination angle of 5°-10°, so that simultaneous Form the desired knot profile.

为例，可以使用约15KeV的能量与1e¹⁵-3e¹⁵cm^-2的剂量来进行植入制造工艺506而同时形成轻掺杂区508与掺杂区509a，其中使用5°-10°的倾斜角来植入掺质。在相同于上述的条件下，可以使用约5-10KeV的能量与1e¹⁵-3e¹⁵cm^-2的剂量来进行植入制造工艺507，以增加掺杂区509b的掺杂浓度。In one embodiment, during the two-step implantation process to form the lightly doped region 508 and the doped regions 509a, 509b, the lightly doped region 508 and the doped region can be formed simultaneously by the implantation process 506 509a (as shown in FIG. 5B-1); and due to the shielding effect of the spacer 502, the implantation process 507 using lower energy will only increase the doping concentration of the doped region 509b (as shown in FIG. 5B-2 Show). With a technology node of 90nm and the thickness of the spacer 502 is about

For example, an energy of about 15KeV and a dose of 1e ¹⁵ -3e ¹⁵ cm ^-2 can be used to perform the implantation process 506 while simultaneously forming the lightly doped region 508 and the doped region 509a, wherein a slope of 5°-10° is used corners to implant dopants. Under the same conditions as above, the implantation process 507 can be performed with an energy of about 5-10 KeV and a dose of 1e ¹⁵ -3e ¹⁵ cm ⁻² to increase the doping concentration of the doped region 509 b.

至

之间。在一实施例中，第一部分508a的长度L₁介于

至

之间。在一实施例中，第二部分508b的长度L₂介于

至

之间。特别说明的是，由于第三表面301c为倾斜面，因此各轻掺杂区508的倾斜角可被控制在45°至60°的范围内，以保持元件的击穿特性。Referring to FIG. 5C , after performing the implantation process 506 or after performing the implantation process 507 , a tempering process may also be performed to activate dopants, thereby forming a doped region 509 . Afterwards, a salicide layer 510 is formed on the gate structure 310 and the doped region 509 . Next, a stress layer 512 is formed on the substrate 300 to complete the semiconductor device of the present invention. As shown in FIG. 5C, each lightly doped region 508 in the substrate 300 disposed between the gate structure 310 and the doped region 509 includes a first portion 508a and a second portion 508b, wherein the first portion 508a is connected to the second portion 508b . The first portion 508a is disposed under the second surface 301b and adjacent to the third surface 301c. The second portion 508b is disposed under the third surface 301c, and optionally includes a small portion extending below the first surface 301a. When the length of the gate is about 90nm, the horizontal distribution of each lightly doped region 508 is, for example, between about

to

between. In one embodiment, the length L ₁ of the first portion 508a is between

to

between. In one embodiment, the length L ₂ of the second portion 508b is between

to

between. In particular, since the third surface 301c is an inclined plane, the inclination angle of each lightly doped region 508 can be controlled within a range of 45° to 60°, so as to maintain the breakdown characteristics of the device.

In order to prove that the semiconductor device of the present invention can effectively improve the performance of the device, its characteristics will be described with experimental examples. The description of the following experimental example is only used to illustrate the influence of the structure configuration of the semiconductor device of the present invention on the lateral electric field, but is not intended to limit the scope of the present invention.

Experimental example

FIG. 6 shows the lateral electric field distribution curves corresponding to different positions in the channel region parallel to the first surface according to the conventional NMOS and the NMOS of the experimental example of the present invention.

As shown in FIG. 6 , the lateral electric field distribution in the channel region close to the interface between the gate structure and the silicon substrate is simulated respectively for the conventional NMOS and the NMOS proposed by the present invention. The gate lengths of the conventional NMOS and the NMOS of the experimental example of the present invention are about 90 nm. Under the condition that the same bias voltage is provided to the two elements respectively, the lateral electric field distribution of the conventional NMOS is much higher than that of the NMOS of the experimental example of the present invention. Since the lateral electric field significantly affects the hot carrier effect, the conventional NMOS with a relatively high lateral electric field suffers from severe hot carrier effects, resulting in reduced device performance. It can be seen that the NMOS structure proposed by the present invention has a lower lateral electric field value, and thus can achieve the effect of improving device performance.

To sum up, the semiconductor device of the present invention includes a lightly doped region having a first portion and a second portion, and the inclined and curved lightly doped region can reduce hot carriers without reducing the dopant concentration of the lightly doped region. effect. Moreover, by making the lightly doped region have an inclined and curved profile, leakage currents such as gate induced drain leakage (GIDL) and overlap capacitance between gate and drain can be reduced.

In addition, the manufacturing method of the semiconductor device of the present invention uses a disposable spacer to form an inclined and curved lightly doped region, and can be easily integrated into an existing manufacturing process. Therefore, the manufacturing process is simple without increasing the manufacturing cost, and the formed device has better performance. Furthermore, the manufacturing method of the semiconductor element of the present invention can be applied to all MOS element structures, even the MOS element whose element size is shrunk to below 90nm.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but all the content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence still belong to the scope of the technical solutions of the present invention.

Claims (20)

1. A semiconductor element, characterized in that it comprises: A base having a stepped upper surface, wherein the stepped upper surface includes a first surface, a second surface lower than the first surface, and a third surface connecting the first surface and the second surface; a gate structure configured on the first surface; two doped regions, disposed in the substrate on both sides of the gate structure, and located under the second surface; and Two lightly doped regions are respectively disposed in the substrate between the gate structure and the doped regions, wherein each of the lightly doped regions includes: a first portion located below the second surface; and A second part is connected with the first part and is located under the third surface. 2. The semiconductor device according to claim 1, wherein the third surface is inclined to the first surface, and an angle formed by an extension direction of the first surface and the third surface is between Between 45° and 60°. 3. The semiconductor device according to claim 1, wherein the first surface is parallel to the second surface. 4. The semiconductor device according to claim 1, wherein the height difference between the first surface and the second surface is between

to

between, and the horizontal distance between the first surface and the second surface is between to

between. 5. The semiconductor device according to claim 1, wherein the length of the first portion of the lightly doped region is between

to

between , and the length of the second part is between to

between. 6. The semiconductor device according to claim 1, further comprising a spacer disposed on the sidewall of the gate structure and located on the lightly doped regions, the thickness of the spacer is between to

between. 7. The semiconductor device according to claim 1, further comprising a stress layer disposed on the substrate. 8. The semiconductor device according to claim 1, further comprising two pocket-shaped implanted regions disposed in the substrate under the gate structure, each of the pocket-shaped implanted regions adjacent to each The doped regions, wherein the pocket implant regions are partial pocket implant regions or compound pocket implant regions. 9. A method of manufacturing a semiconductor element, characterized in that it comprises: provide a base; forming a gate structure on the substrate; removing part of the base to form a stepped upper surface, wherein the stepped upper surface includes a first surface, a second surface lower than the first surface, a third surface connecting the first surface and the second surface surface; Two lightly doped regions are formed in the substrate on both sides of the gate structure, wherein each of the lightly doped regions includes: a first portion formed below the second surface; and a second portion connected to the first portion and formed under the third surface; and Two doped regions are formed in the substrate, the doped regions are located under the second surface and adjacent to the lightly doped regions respectively. 10. The manufacturing method of a semiconductor element according to claim 9, wherein the third surface is inclined to the first surface, and an extending direction of the first surface forms a sandwich with the third surface. The angle is between 45° and 60°. 11. The method of manufacturing a semiconductor device according to claim 9, wherein the first surface is parallel to the second surface. 12. The manufacturing method of a semiconductor element according to claim 9, wherein the height difference between the first surface and the second surface is between

to

between, and the horizontal distance between the first surface and the second surface is between

to

between. 13. The method for manufacturing a semiconductor device according to claim 9, wherein the length of the first portion of the lightly doped region is between

to

between , and the length of the second part is between

to

between. 14. The method of manufacturing a semiconductor device according to claim 9, further comprising forming a first spacer on the sidewall of the gate structure and the lightly doped regions, the first spacer with a thickness between

to between. 15. The method for manufacturing a semiconductor element according to claim 14, wherein the method for forming the first spacer comprises: forming a layer of spacer material on the substrate; forming a second spacer on the sidewall of the gate structure, wherein the second spacer covers part of the spacer material layer on the lightly doped regions; using the second spacer as a mask to remove part of the spacer material layer; and The second spacer is removed. 16. The method of manufacturing a semiconductor device according to claim 15, wherein said doping regions are formed by using the second spacer as a mask after removing part of the spacer material layer. 17. The method of manufacturing a semiconductor device according to claim 15, wherein the lightly doped regions are formed before forming the second spacer or after removing the second spacer. 18. The manufacturing method of a semiconductor device according to claim 14, wherein after forming the first spacer, the lightly doped regions and the lightly doped regions are formed by a single manufacturing process or a two-step manufacturing process doped area. 19. The method of manufacturing a semiconductor device according to claim 9, further comprising forming a stress layer on the substrate. 20. The method for manufacturing a semiconductor device according to claim 9, further comprising: after forming the stepped upper surface or after forming the lightly doped regions or before forming the lightly doped regions Two pocket-shaped implant regions are formed in the substrate under the gate structure, each of the pocket-shaped implant regions is adjacent to each of the doped regions, wherein the pocket-shaped implant regions are partial pocket-shaped implant regions Entry zone or compound pocket implant zone.

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