CN101834169A - Measurement structure for substrate resistivity of integrated passive device and forming method thereof - Google Patents
Measurement structure for substrate resistivity of integrated passive device and forming method thereof Download PDFInfo
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- CN101834169A CN101834169A CN201010164873A CN201010164873A CN101834169A CN 101834169 A CN101834169 A CN 101834169A CN 201010164873 A CN201010164873 A CN 201010164873A CN 201010164873 A CN201010164873 A CN 201010164873A CN 101834169 A CN101834169 A CN 101834169A
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- silicide regions
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- 239000000758 substrate Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000005259 measurement Methods 0.000 title claims abstract description 15
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 63
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 63
- 238000002161 passivation Methods 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
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Abstract
The invention discloses a measurement structure for substrate resistivity of an integrated passive device, which is formed as follows: two electrode for measuring resistivity are led out through forming a first silicide region and a second silicide region on the surface of the substrate and forming a first open and a second open respectively corresponding to the first silicide region and the second silicide region, thus being capable of effectively measuring the substrate resistivity of the integrated passive device to further monitor the substrate resistivity and obtain the thermal influence of various processes on the substrate resistivity. In addition, the invention discloses a method for forming the measurement structure for substrate resistivity of the integrated passive device, the first silicide region and the second silicide region are formed through utilizing a photomask provided with the first open and the second open, thus the measurement structure can be realized without additionally manufacturing a photomask, therefore, the cost is lowered and the process is simplified.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly measuring resistivity of a kind of substrate of integrated passive devices and forming method thereof.
Background technology
Usually use a large amount of passive devices in the modern radio-frequency circuit, for example resistance, electric capacity and inductance etc.If these passive devices are integrated on the substrate, then can obviously improve product performance, reduce cost and reduce size, so occurred integrated passive devices (integrated passive device, IPD).
Fig. 1 has shown the cutaway view of an example of integrated passive devices in the prior art.Among Fig. 1, be formed with oxide layer 11 on the substrate 10, be formed with the first metal layer 12 in the oxide layer 11.Metal-dielectric-metal (MIM) electric capacity 18 is formed on the first metal layer 12 as passive device, and here, the first metal layer 12 is as the following capacitor board of this MIM electric capacity 18.Be formed with top layer metallic layer 14 on the oxide layer 11, top layer metallic layer 14 is electrically connected the last capacitor board (left side among Fig. 1) and the first metal layer 12 (right side among Fig. 1) of MIM electric capacity 18 by through hole 13.Wherein, can form inductance by top layer metallic layer 14 as passive device.(Passivation layer PA) is formed at the surface of top layer metallic layer 14 to passivation layer, and it comprises oxide layer 15 and is formed at silicon nitride layer 16 on the oxide layer 15.In addition, also be formed with opening 17 in the passivation layer in order to draw top layer metallic layer 14.Wherein, opening 17 utilizes the light shield with predetermined pattern to form by photoetching and etching technics.
Along with the integrated level of integrated passive devices is more and more higher, its characteristic size is constantly dwindled, and substrate and the interaction that is formed between the passive device on the substrate more and more receive publicity.Wherein, the resistivity of substrate is an important measurement parameter, selects the substrate of resistivity greater than 1000ohm*cm usually.Therefore, the measurement of how effectively substrate being carried out resistivity just seems particularly important.Yet, be difficult in the structure of integrated passive devices shown in Figure 1 the resistivity of substrate is measured.Simultaneously, promptly enable to use four probe method to measure to wafer rear, because wafer rear can deposit such as insulating barriers such as silicon dioxide, silicon nitrides in processing procedure, this will make measured deviation very big, and then cause measurement unstable, also inaccuracy.
Summary of the invention
The object of the present invention is to provide a kind of measuring resistivity and forming method thereof of substrate of integrated passive devices, can be effectively the resistivity of the substrate of integrated passive devices be measured, and can additionally be made light shield and realize this measurement structure.
The invention provides a kind of measuring resistivity of substrate of integrated passive devices, be formed with integrated passive devices on the described substrate, wherein, described measurement structure comprises: first silicide regions and second silicide regions that are formed at described substrate surface; First oxide layer is formed on the described substrate; First top-level metallic zone and the second top-level metallic zone are formed on described first oxide layer, and are oppositely arranged with described first silicide regions and second silicide regions; First through hole and second through hole, be formed in described first oxide layer, described first through hole is used to be electrically connected described first silicide regions and the described first top-level metallic zone, and described second through hole is used to be electrically connected described second silicide regions and the described second top-level metallic zone; Passivation layer, be formed at the surface in described first top-level metallic zone and the second top-level metallic zone, and be formed with in the described passivation layer and described first silicide regions and corresponding respectively first opening and second opening of second silicide regions, described first opening and second opening are in order to draw two electrodes that measured resistivity is used.
In the measuring resistivity of the substrate of above-mentioned integrated passive devices, described passivation layer comprises second oxide layer and is formed at silicon nitride layer on described second oxide layer.
The present invention also provides a kind of formation method of measuring resistivity of substrate of above-mentioned integrated passive devices, it may further comprise the steps: step 1, one substrate is provided and is used to form described first opening in the described passivation layer and the light shield of second opening, utilize described light shield to form described first silicide regions and second silicide regions at described substrate surface; Step 2 forms described first oxide layer by depositing operation on described substrate, and etches first perforate and second perforate to expose described first silicide regions and second silicide regions in described first oxide layer; Step 3, the deposition layer of metal is to form top-level metallic on described first oxide layer, and simultaneously, described first perforate and second perforate are by metal filled and form described first through hole and second through hole; Step 4, the described top-level metallic of etching are forming described first top-level metallic zone and the second top-level metallic zone, and the described passivation layer of surface deposition in and second top-level metallic zone regional at described first top-level metallic; Step 5 utilizes described light shield to form described first opening and second opening once more in described passivation layer.
Compared with prior art, the measuring resistivity of the substrate of a kind of integrated passive devices provided by the invention, by form first silicide regions and second silicide regions at substrate surface, and form with corresponding respectively first opening of this first silicide regions and second silicide regions and second opening to draw two electrodes that measured resistivity is used, thereby can be effectively the resistivity of the substrate of integrated passive devices be measured, and then can monitor, and obtain of the thermal impact of each manufacturing process to the resistivity of substrate to the resistivity of substrate.And, the formation method of the measuring resistivity of the substrate of integrated passive devices provided by the invention, by utilizing the light shield that forms first opening and second opening to form first silicide regions and second silicide regions, thereby need not additionally make light shield and realize this measurement structure, and then reduced cost, simplified processing procedure.
Description of drawings
Fig. 1 is the structure cutaway view of an example of integrated passive devices in the prior art;
Fig. 2 is the schematic diagram of the measuring resistivity of the substrate of integrated passive devices among the present invention;
Fig. 3 to Fig. 6 is the structural representation of each step of the formation method of the measuring resistivity of the substrate of integrated passive devices among the present invention.
Embodiment
For purpose of the present invention, feature are become apparent, the specific embodiment of the present invention is further described below in conjunction with accompanying drawing.
See also Fig. 2, Fig. 2 wherein, is formed with integrated passive devices (not shown) for the schematic diagram of the measuring resistivity of the substrate of integrated passive devices among the present invention on the substrate 20.This measurement structure comprises: first silicide regions 211 and second silicide regions 212 that are formed at substrate 20 surfaces; First oxide layer 22 is formed on the substrate 20; 241 and the second top-level metallic zone 242, first top-level metallic zone is formed on first oxide layer 22, and is oppositely arranged with first silicide regions 211 and second silicide regions 212; First through hole 231 and second through hole 232, be formed in first oxide layer 22, first through hole 231 is used to be electrically connected first silicide regions 211 and the first top-level metallic zone, 241, the second through holes 232 are used to be electrically connected second silicide regions 212 and the second top-level metallic zone 242; Passivation layer, be formed at the surface in the 241 and second top-level metallic zone 242, first top-level metallic zone, and be formed with first opening 271 corresponding and second opening, 272, the first openings 271 and second opening 272 in the passivation layer in order to draw two electrodes that measured resistivity is used with first silicide regions 211 and second silicide regions, 212 difference.Among Fig. 2, passivation layer comprises second oxide layer 25 and is formed at silicon nitride layer 26 on second oxide layer 25.
Thus, the measuring resistivity of the substrate of above-mentioned integrated passive devices, by forming first silicide regions 211 and second silicide regions 212 on substrate 20 surfaces, and form with corresponding respectively first opening 271 of this first silicide regions 211 and second silicide regions 212 and second opening 272 to draw two electrodes that measured resistivity is used, thereby can be effectively the resistivity of the substrate of integrated passive devices be measured, and then can monitor, and obtain of the thermal impact of each manufacturing process to the resistivity of substrate to the resistivity of substrate.
Below, complex chart 3 to Fig. 6 is described the formation method of measuring resistivity of the substrate of above-mentioned integrated passive devices, and Fig. 3 to Fig. 6 is the structural representation of each step of this formation method.Wherein, this formation method may further comprise the steps:
Step 1 provides a substrate 20 and is used to form first opening 271 in the passivation layer and the light shield of second opening 272 (with reference to Fig. 2), utilizes this light shield to form first silicide regions 211 and second silicide regions 212 on substrate 20 surfaces, as shown in Figure 3.Owing to (for example be used to form the light shield of first opening 271 in the passivation layer and second opening 272 and be exactly the opening that is used to form in the prior art in the passivation layer, opening 17 among Fig. 1) light shield, therefore, utilized the light shield of existing processing procedure in this step, and need not additionally make light shield, thereby reduced cost, simplified processing procedure.In addition, be the standard technology step that forms silicide in the prior art owing to form the processing step of first silicide regions 211 and second silicide regions 212, just no longer describe in detail here.
Step 2 forms first oxide layer 22 by depositing operation on substrate 20, and etches the first perforate 231A and the second perforate 232A to expose first silicide regions 211 and second silicide regions 212, as shown in Figure 4 in first oxide layer 22.
Step 3, the deposition layer of metal is to form top-level metallic 240 on first oxide layer 22, and simultaneously, the first perforate 231A and the second perforate 232A (with reference to Fig. 4) are by metal filled and form first through hole 231 and second through hole 232, as shown in Figure 5.
Step 4, etching top-level metallic 240 (with reference to Fig. 5) to be forming the 241 and second top-level metallic zone 242, first top-level metallic zone, and at the surface deposition passivation layer in the 241 and second top-level metallic zone 242, first top-level metallic zone, as shown in Figure 6.Among Fig. 6, this passivation layer comprises second oxide layer 25 and is formed at silicon nitride layer 26 on second oxide layer 25.
Step 5 utilizes the light shield in the step 1 to form first opening 271 and second opening 272 once more in passivation layer, obtains measurement structure as shown in Figure 2.Particularly, utilize the light shield in the step 1 to form first opening 271 and second opening 272 by photoetching and etching technics.
Thus, the formation method of the measuring resistivity of the substrate of above-mentioned integrated passive devices, by utilizing the light shield that forms first opening and second opening to form first silicide regions and second silicide regions, thereby need not additionally make light shield and realize this measurement structure, and then reduced cost, simplified processing procedure.
In sum, the measuring resistivity of the substrate of a kind of integrated passive devices provided by the invention, by form first silicide regions and second silicide regions at substrate surface, and form with corresponding respectively first opening of this first silicide regions and second silicide regions and second opening to draw two electrodes that measured resistivity is used, thereby can be effectively the resistivity of the substrate of integrated passive devices be measured, and then can monitor, and obtain of the thermal impact of each manufacturing process to the resistivity of substrate to the resistivity of substrate.And, the formation method of the measuring resistivity of the substrate of integrated passive devices provided by the invention, by utilizing the light shield that forms first opening and second opening to form first silicide regions and second silicide regions, thereby need not additionally make light shield and realize this measurement structure, and then reduced cost, simplified processing procedure.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (3)
1. the measuring resistivity of the substrate of an integrated passive devices is formed with integrated passive devices on the described substrate, it is characterized in that, described measurement structure comprises:
Be formed at first silicide regions and second silicide regions of described substrate surface;
First oxide layer is formed on the described substrate;
First top-level metallic zone and the second top-level metallic zone are formed on described first oxide layer, and are oppositely arranged with described first silicide regions and second silicide regions;
First through hole and second through hole, be formed in described first oxide layer, described first through hole is used to be electrically connected described first silicide regions and the described first top-level metallic zone, and described second through hole is used to be electrically connected described second silicide regions and the described second top-level metallic zone;
Passivation layer, be formed at the surface in described first top-level metallic zone and the second top-level metallic zone, and be formed with in the described passivation layer and described first silicide regions and corresponding respectively first opening and second opening of second silicide regions, described first opening and second opening are in order to draw two electrodes that measured resistivity is used.
2. the measuring resistivity of the substrate of integrated passive devices as claimed in claim 1 is characterized in that, described passivation layer comprises second oxide layer and is formed at silicon nitride layer on described second oxide layer.
3. the formation method of the measuring resistivity of the substrate of an integrated passive devices as claimed in claim 1 is characterized in that, may further comprise the steps:
Step 1 provides a substrate and is used to form described first opening in the described passivation layer and the light shield of second opening, utilizes described light shield to form described first silicide regions and second silicide regions at described substrate surface;
Step 2 forms described first oxide layer by depositing operation on described substrate, and etches first perforate and second perforate to expose described first silicide regions and second silicide regions in described first oxide layer;
Step 3, the deposition layer of metal is to form top-level metallic on described first oxide layer, and simultaneously, described first perforate and second perforate are by metal filled and form described first through hole and second through hole;
Step 4, the described top-level metallic of etching are forming described first top-level metallic zone and the second top-level metallic zone, and the described passivation layer of surface deposition in and second top-level metallic zone regional at described first top-level metallic;
Step 5 utilizes described light shield to form described first opening and second opening once more in described passivation layer.
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| CN201010164873A CN101834169A (en) | 2010-04-29 | 2010-04-29 | Measurement structure for substrate resistivity of integrated passive device and forming method thereof |
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| CN201010164873A CN101834169A (en) | 2010-04-29 | 2010-04-29 | Measurement structure for substrate resistivity of integrated passive device and forming method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9383404B2 (en) | 2014-12-05 | 2016-07-05 | Globalfoundries Inc. | High resistivity substrate final resistance test structure |
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2010
- 2010-04-29 CN CN201010164873A patent/CN101834169A/en active Pending
Patent Citations (7)
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| US6066561A (en) * | 1997-12-19 | 2000-05-23 | Lsi Logic Corporation | Apparatus and method for electrical determination of delamination at one or more interfaces within a semiconductor wafer |
| US6410353B1 (en) * | 2001-04-12 | 2002-06-25 | Promos Technologies Inc. | Contact chain for testing and its relevantly debugging method |
| JP2003068812A (en) * | 2001-08-17 | 2003-03-07 | Promos Technologies Inc | Testing contact chain and related debugging method |
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Application publication date: 20100915 |