CN101826025A - Device for upgrading firmware of field programmable logic device and method thereof - Google Patents

Abstract

The invention discloses a device for upgrading the firmware of a field programmable logic device, which comprises a microcontroller and a host connected with the microcontroller, and is characterized in that the microcontroller is connected with the field programmable logic device in a passive serial mode, after the host sends a firmware upgrading instruction, the microcontroller reads in the firmware upgrading data and configures the firmware upgrading data for the field programmable logic devices in passive serial mode. When upgrading the CPLD firmware, the device is simple to operate, and not only can eliminate the hardware problems caused by artificially welding or inserting/pulling the chip CPLD, but also can avoid the inconvenience caused by using the ISP.

Description

Field Programmable Logic Device Firmware Upgrading Device and Method

technical field

The invention belongs to the technical field of computers, and in particular relates to a simple on-site programmable logic device (CPLD) firmware upgrade device and an upgrade method thereof.

Background technique

Today's society is a society where digitization and digital integrated circuits are widely used. Digital integrated circuits themselves are constantly being updated. It has developed from early tubes, transistors, small and medium-scale integrated circuits, to very large-scale integrated circuits (VLSIC, more than tens of thousands of gates), and many application-specific integrated circuits with specific functions. However, with the development of microelectronics technology, the task of designing and manufacturing integrated circuits is not completely undertaken by semiconductor manufacturers independently. System designers prefer to design application-specific integrated circuit (ASIC) chips by themselves, and hope that the ASIC design cycle is as short as possible. It is best to design a suitable ASIC chip in the laboratory and put it into practical application immediately. As a result, Field Programmable Logic Devices (FPLDs) have emerged, and the most widely used ones are Complex Programmable Logic Devices (CPLDs).

However, since the function of the product must not only meet the needs of users, but also speed up product development and seize the market as soon as possible, it is necessary to implement more logic functions through CPLD firmware upgrades without major hardware changes. At present, the methods for upgrading CPLD firmware in the prior art mainly contain the following two kinds: 1. ISP online upgrade, which has the advantage of being able to upgrade CPLD through JTAG10, which is simple and convenient. But its shortcomings are also obvious. Because the circuit board must have a JTAG port, it not only increases the cost, but also requires a download cable and a download tool for on-site upgrades. 2. Use a writer. When programming the program into the chip, the chip must be placed in the socket of the programmer. Its advantages are low cost and simple operation. The disadvantage is that frequent plugging or re-soldering of the chip CPLD is likely to cause hardware damage and artificially increase unreliability.

In order to provide a method that is easy to operate, not only eliminates the hardware problems caused by manual welding or plugging and unplugging the chip CPLD, but also avoids the inconvenience caused by using the ISP, the prior art does not solve it well, which brings inconvenience to the staff. The present invention comes from this.

Contents of the invention

The purpose of the present invention is to provide a field programmable logic device firmware upgrade device, which solves the complicated operation of CPLD firmware upgrade in the prior art, the need for manual welding or plugging and unplugging of chips CPLD, hardware problems often occur, and ISP upgrades have many inconveniences and other problems. .

In order to solve these problems in the prior art, the technical solution provided by the invention is:

A field programmable logic device firmware upgrade device, including a microcontroller and a host connected to the microcontroller, is characterized in that the microcontroller is connected to the field programmable logic device in a passive serial manner, and the host issues firmware After the upgrade instruction, the microcontroller reads the firmware upgrade data, and configures the field programmable logic device through the passive serial mode with the firmware upgrade data.

Preferably, the device further includes an internal memory, which is connected to the microcontroller and stores firmware upgrade data of the Field Programmable Logic Device.

Preferably, the internal memory is an erasable read-only memory, and after the host issues a firmware data transmission instruction, the microprocessor receives the instruction and reads the firmware upgrade data into the internal memory.

Preferably, the DCONFIG, DCLK, DATA, INT_DONE, nSTATUS, CONF_DONE of the field programmable logic device are connected to the I/O interface of the microprocessor, wherein DCONFIG, DCLK, DATA pins are set to output states, and are controlled by the microprocessor Operate the field programmable logic device; nSTATUS, CONF_DONE, INT_DONE pins are set to input state, and the configuration state of the field programmable logic device is detected by the microprocessor.

Preferably, the I/O interface of the microprocessor includes CF, CON, INT, DL, CLK, DAT pins, and the DCONFIG, nSTATUS, INT_DONE, CONF_DONE, DCLK, DATA pins of the field programmable logic device and CF, CON, INT, DL, CLK, and DAT pins are matched and connected one by one. The microprocessor sets CF, DCLK, and DATA pins as output ports through internal registers, and sets CON, INT, and DL pins as input ports. mouth.

In specific use, after the device is powered on, the microcontroller reads the new CPLD binary configuration into the internal memory, and through passive serial configuration, the code is sent to the CPLD and runs; power off, restart the circuit board if If the logic function expected by CPLD is realized correctly, the debugging process will be completed. If the program is wrong, find the error in the program. After recompiling, repeat the above steps until the logic function expected by CPLD is realized correctly.

Another object of the present invention is to provide a method for easily upgrading the firmware of field programmable logic devices on the spot, characterized in that the method includes the following steps:

(1) On the field programmable logic device firmware upgrade device, connect the field programmable logic device through passive serial mode;

(2) The host computer generates binary configuration data of the field programmable logic device firmware;

(3) The host issues an instruction, and after the microcontroller reads the binary configuration data into the internal memory, it sends the binary configuration data to the field programmable logic device through a passive serial method.

Preferably, the method step (3) comprises that the microprocessor generates a jump from low to high on the DCONFIG of the field programmable logic device, so that the field programmable logic device enters the configuration state, and waits for the field programmable logic device to release After nSTATUS and nSTATuS become high, the configuration data is sent to DATA bit by bit through the rising edge of DCLK; after the field programmable logic device receives all the configuration data, it releases CONF_DONE and becomes high level, and outputs a pulse on DCLK to initialize the field programmable logic device. Program the logic device until INT_DONE is released and becomes high level, indicating that the field programmable logic device is initialized, enters the user state, and the configuration process ends.

Preferably, the method also includes a step of debugging after the configuration is completed, and the debugging step includes restarting the firmware upgrade device of the field programmable logic device. If the expected logic function of the field programmable logic device fails to be correctly realized, Then re-modify the firmware code, compile it into binary configuration data, and then re-passive serial configuration.

Preferably, the method further includes the step of dismantling the firmware upgrade device of the FPGA on the FPGA after successful configuration.

This method follows the JTAG protocol; the microprocessor first generates a negative pulse with a width greater than 8μs on the DCONFIG signal line, and then begins to detect the state of the nSTATUS signal. After the CPLD detects the falling edge of the DCONFIG signal, it will force the nSTATUS and CONF_DONE signals to be pulled low, and they will remain low until the DCONFIG signal is raised again. After the DCONFIG signal is raised, nSTATUS will be raised within 1μs. After the microprocessor detects this change, it thinks that the CPLD is ready to start configuration. Configure the time interval between the first rising edge and the rising edge of nSTATUS to be at least 1 μs. Since the configuration data is synchronized with the rising edge of the configuration, 1-bit configuration data should be prepared on the data line between the rising edges of the configuration clock, and the configuration data is sent out from the data line in the order of low order first and high order. When all the configuration data is sent, the CONF_DONE signal will be raised to indicate the end of the configuration. The microprocessor detects that the CONF_DONE signal is raised, and ends the configuration process. If an error occurs during the configuration process, the CPLD will force the nSTATUS signal to be low, and the microprocessor will restart the configuration when it detects this change.

The principle of the present invention is to send the binary code required for CPLD upgrade to CPLD by means of microcontroller and passive serial configuration, and then realize the required logic function. The preferred specific upgrade steps can be:

A. Add a passive serial configuration on the circuit board;

B. Generate new CPLD binary configuration data in the MAX+PLUSII environment;

C. The circuit board is powered on, the microcontroller reads the configuration data into the internal memory, and then generates a transition from low to high on DCONFIG to make the CPLD enter the configuration state, wait for the CPLD to release nSTATUS, and after nSTATUS becomes high, pass The rising edge of DCLK sends the configuration data to DATA bit by bit; after CPLD receives all the configuration data, it releases CONF_DONE and becomes high level, and then outputs pulses on DCLK to initialize the CPLD device until INT_DONE is released and becomes high level , indicating that the CPLD device is initialized, enters the user state, and the configuration process ends;

D. After restarting the circuit board, if the expected logic function of CPLD is realized correctly, proceed to step E; otherwise, re-modify the code, compile, and repeat steps B and C;

E. Finish debugging.

Among these steps, in step E, after the debugging is completed, the passive serial configuration can be removed. In step A, the passive serial configuration is defined and set according to the chip manual pins. In the step B, the CPLD binary configuration data is the code for realizing logic functions.

Through the above-mentioned upgrading process, the present invention obtains a debugging method that is simple to operate, not only eliminates hardware problems caused by manual welding or plugging and unplugging chip CPLD, but also avoids the inconvenience caused by using ISP, and designs a simple on-site CPLD The firmware upgrade method uses passive serial configuration to send the binary code required for the upgrade to the CPLD. The operation is simple. It not only solves the technical problem of hardware damage caused by frequent plugging or re-soldering of the CPLD, but also avoids the use of ISP Inconvenience caused.

Compared with the scheme in the prior art, the advantages of the present invention are:

In the technical solution of the present invention, the binary code required for CPLD upgrade is sent to the CPLD by means of the microcontroller and passive serial configuration, and then the required logic functions are realized; it not only solves the problem of hardware damage caused by frequent plugging and unplugging or re-welding of the CPLD technical issues, and avoid the inconvenience of using an ISP.

In summary, the present invention provides a method for on-site simple CPLD firmware upgrade, the method is simple to operate, not only eliminates the hardware problems caused by manual welding or plugging and unplugging the chip CPLD, but also avoids the inconvenience caused by using ISP, The technical solution adopted is to send the binary code required for CPLD upgrade to CPLD with the help of microcontroller and passive serial configuration, and then realize the required logic functions. The specific steps of this method are: add a passive serial configuration on the circuit board, after the circuit board is powered on, the microcontroller reads the new CPLD binary configuration into the internal memory, transmits the code to the CPLD through the passive serial configuration, and runs ; Power off, restart the circuit board, if the expected logic function of CPLD is realized correctly, then complete the debugging process, if the program is wrong, then find the error in the program, after recompiling, repeat the above steps until the expected logic function of CPLD until it is implemented correctly.

Description of drawings

The present invention will be further described below in conjunction with accompanying drawing and embodiment:

Fig. 1 is a schematic structural diagram of a device according to an embodiment of the present invention.

Detailed ways

The above solution will be further described below in conjunction with specific embodiments. It should be understood that these examples are used to illustrate the present invention and not to limit the scope of the present invention. The implementation conditions used in the examples can be further adjusted according to the conditions of specific manufacturers, and the implementation conditions not indicated are usually the conditions in routine experiments.

Embodiment As shown in Figure 1, this field programmable logic device firmware upgrade device, comprises the microcontroller of BCM5836 chip, the internal memory of A3S56D30ETP chip and the PC machine that is connected with microcontroller, it is characterized in that described microcontroller passes The passive serial mode is connected with the field programmable logic device, and after the host sends out a firmware upgrade command, the microcontroller reads in the firmware upgrade data, and configures the field programmable logic device with the firmware upgrade data through the passive serial mode. The internal memory is connected with the microcontroller and stores the firmware upgrade data of the Field Programmable Logic Device. The internal memory is an erasable read-only memory. After the host computer sends a firmware data transmission instruction, the microprocessor receives the instruction and reads the firmware upgrade data into the internal memory. The field programmable logic device is LCM640C of Lattice Company.

The DCONFIG, DCLK, DATA, INT_DONE, nSTATUS, CONF_DONE of the field programmable logic device are connected to the I/O interface of the microprocessor, wherein the DCONFIG, DCLK, and DATA pins are set to output states, and the field programmable logic is controlled by the microprocessor. The device operates; the nSTATUS, CONF_DONE, and INT_DONE pins are set to input states, and the configuration status of the field programmable logic device is detected by the microprocessor. The I/O interface of described microprocessor comprises CF, CON, INT, DL, CLK, DAT pin, and the DCONFIG of described field programmable logic device, nSTATUS, INT_DONE, CONF_DONE, DCLK, DATA pin and CF, CON , INT, DL, CLK, and DAT pins are matched and connected one by one, and the microprocessor sets CF, DCLK, and DATA pins as output ports through internal registers, and sets CON, INT, and DL pins as input ports.

When upgrading the firmware of the CPLD, you can follow the steps below:

A. Add a passive serial configuration on the circuit board;

B. Generate new CPLD binary configuration data in the MAX+PLUSII environment;

C. The circuit board is powered on, and the microcontroller reads the configuration data into the internal memory. Then, a transition from low to high is generated on DCONFIG, so that CPLD enters the configuration state, waits for CPLD to release nSTATUS, after nSTATuS becomes high, the configuration data is sent to DATA bit by bit through the rising edge of DCLK; CPLD receives all configurations After the data is released, CONF_DONE will be released and become high level, and then output pulses on DCLK to initialize the CPLD device until INT_DONE is released and become high level, indicating that the CPLD device is initialized and enters the user state, and the configuration process ends;

D. After restarting the circuit board, if the expected logic function of CPLD is realized correctly, proceed to step E; otherwise, re-modify the code, compile, and repeat steps B and C;

E. Finish debugging.

After commissioning is complete, the passive serial configuration can be removed.

Before the upgrade configuration, the microprocessor responds to the serial port interrupt and receives a data, the microprocessor first judges the command type represented by the data, if it is a configuration command, the microprocessor enters the configuration state. In the configuration state, the microprocessor writes the data to the CPLD device while receiving the configuration data; if it is the command to write the internal memory, the microprocessor enters the state of writing the internal memory, and the microprocessor will receive the configuration at the same time. Data, while writing these data to the internal memory for configuration (note that these data are not configured into the CPLD device at this time); if the command is to read the internal memory, the microprocessor will enter the read internal memory and configure the CPLD device At this time, the microprocessor will read the configuration data in the internal storage, and write the read configuration data to the CPLD device.

The above examples are only to illustrate the technical conception and characteristics of the present invention, and its purpose is to allow people familiar with this technology to understand the content of the present invention and implement it accordingly, and cannot limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (9)

1. device for upgrading firmware of field programmable logic device, comprise microcontroller and the main frame that is connected with microcontroller, it is characterized in that described microcontroller is connected with field programmable logic device by the passive serial mode, after described main frame sends the firmware upgrade instruction, described microcontroller reads in the firmware upgrade data, and the firmware upgrade data are disposed field programmable logic device by the passive serial mode.

2. device for upgrading firmware of field programmable logic device according to claim 1 is characterized in that described device also comprises internal storage, and described internal storage is connected with microcontroller, stores the firmware upgrade data of field programmable logic device.

3. device for upgrading firmware of field programmable logic device according to claim 2, it is characterized in that described internal storage selects EROM for use, after main frame sent the firmware data transfer instruction, microprocessor deposited internal storage in after accepting after the instruction firmware upgrade data are read in.

4. device for upgrading firmware of field programmable logic device according to claim 1, it is characterized in that DCONFIG, DCLK, DATA, INT_DONE, nSTATUS, the CONF_DONE of described field programmable logic device are connected to the I/O interface of microprocessor, wherein DCONFIG, DCLK, DATA pin are arranged to output state, by microprocessor field programmable logic device are operated; NSTATUS, CONF_DONE, INT_DONE pin are arranged to import attitude, are detected by the configuration status of microprocessor to field programmable logic device.

5. device for upgrading firmware of field programmable logic device according to claim 4, the I/O interface that it is characterized in that described microprocessor comprises CF, CON, INT, DL, CLK, DAT pin, the DCONFIG of described field programmable logic device, nSTATUS, INT_DONE, CONF_DONE, DCLK, DATA pin mate one by one and are connected with CF, CON, INT, DL, CLK, DAT pin, described microprocessor is arranged to delivery outlet by internal register with CF, DCLK, DATA pin, and CON, INT, DL pin are arranged to the input port.

6. the method for simple on-site upgrading field programmable logic device firmware is characterized in that said method comprising the steps of:

(1) connects field programmable logic device by the passive serial mode on the programmable logic device (PLD) device for upgrading firmware at the scene;

(2) main frame generates the scale-of-two configuration data of field programmable logic device firmware;

(3) main frame sends instruction, and micro controller sends to field programmable logic device by the passive serial mode with the scale-of-two configuration data after the scale-of-two configuration data is read in internal storage.

7. method according to claim 6, it is characterized in that described method step (3) comprises microprocessor upward saltus step from low to high of generation of DCONFIG of programmable logic device (PLD) at the scene, make field programmable logic device enter configuration status, wait for that field programmable logic device discharges nSTATUS, after nSTATuS uprises, deliver to configuration data on the DATA by turn by the DCLK rising edge; After field programmable logic device is received all configuration datas, discharge CONF_DONE, become high level, the last output of DCLK pulse comes the initialization field programmable logic device, be released up to INT_DONE and become high level, the initialization of expression field programmable logic device finishes, and enters User Status, the step that layoutprocedure finishes.

8. method according to claim 6, it is characterized in that also comprising in the described method step of debugging after configuration finishes, if the step of described debugging comprises that restarting behind the device for upgrading firmware of field programmable logic device the desired logic function of field programmable logic device fails correct the realization, then remodify firmware code, be compiled into passive serial configuration again behind the scale-of-two configuration data.

9. method according to claim 6 is characterized in that also comprising in the described method step of carrying out device for upgrading firmware of field programmable logic device dismounting on the field programmable logic device after the successfully configuration.

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