CN101819977A - Static random access memory - Google Patents
Static random access memory Download PDFInfo
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- CN101819977A CN101819977A CN201010164943A CN201010164943A CN101819977A CN 101819977 A CN101819977 A CN 101819977A CN 201010164943 A CN201010164943 A CN 201010164943A CN 201010164943 A CN201010164943 A CN 201010164943A CN 101819977 A CN101819977 A CN 101819977A
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Abstract
The invention provides a static random access memory, which comprises a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube, wherein the first NMOS tube is connected with the first PMOS tube and the second PMOS tube respectively; the second NMOS tube is connected with the first PMOS tube and the second PMOS tube respectively; and the first PMOS tube is connected with the second PMOS tube. The static random access memory provided by the invention only uses four MOS tubes, so the unit area of the static random access memory is furthest reduced, and an ultrahigh-density storage unit of the static random access memory is profitably formed.
Description
Technical field
The present invention relates to a kind of semiconductor device, relate in particular to a kind of static random access memory.
Background technology
Component density within the integrated circuit can be utilized integrated circuit (IC) design (the reducedgeometry integrated circuit designs) principle in reduction space, increases the performance of integrated circuit and reduces its actual cost.The modern integrated circuits memory device that comprises Flash, SRAM (static RAM), OUM, EEPROM, FRAM, MRAM etc. all is the obvious example that utilizes the principle of this poke unit (memory cell), wherein SRAM is except being in " medium " on memory capacity, in other every function aspects, all has remarkable advantages.
Density in the integrated circuit memory devices increases just constantly, and what follow with it is the corresponding reduction of the unit carrying cost of this class device.The increase of density is to utilize to make small construction in device, and utilization reduces between the element or the compartment between the structure of composed component is finished.Usually, the design criterion of this class reduced size (design rules) can be attended by layout, and the correction of design and structure is when using the design criterion of this class reduced size, these are revised and change and will could realize by the size of reduction element, but also will keep device performance.As a kind of example, the reduction of its operating voltage among multiple existing integrated circuits is because such as the reduction gate oxide thicknesses, and promotes that error in little shadow program control just may finish.On the other hand, the design criterion of size reduction also make to reduce operating voltage and becomes necessity, so that if small-sized component is limited the hot carrier (hot carriers) that generation is understood by institute during with existing higher operation voltage operation.First generation SRAM module adopts large scale DI P encapsulation, and this encapsulation has certain height, because battery and RAM chip are stacked among the DIP encapsulation.The advantage of DIP encapsulation is that device can insert the DIP socket, the convenient replacement and storage, or transfer to another from a printed board.Though these advantages are still very useful so far, by contrast, more be necessary to develop surface mounting technology, and operating voltage is become 3.3V by 5V.Second generation SRAM module adopts two-piece type scheme---PowerCap module (PCM), promptly is made up of the pedestal that is welded direct to printed panel (comprising SRAM) and PowerCap (lithium battery just) two parts.Compare with the DIP module, this class device has two major advantages: they adopt surface mount, and have the standard pin configuration.In other words, the SRAM of much capacity no matter, its encapsulation is identical with number of pins.Therefore, the designer can strengthen system memory size, and need not worry to need to change the PCB layout.Battery altering gets up and also is easy to.The SRAM module that the third generation is just up-to-date, it has not only solved the existing problem of previous product, has increased greater functionality simultaneously.This class novel sram is a monolithic BGA module, built-in chargeable lithium cell.The same with PCM, all SRAM that adopt this packing forms are its amount of capacity no matter, and package dimension all is identical with pin configuration.
Cellar area and cell stability are two importances of SRAM design.Cellar area has determined the size of memory chip to a great extent; Cell stability has determined the data reliability of memory, and stability described here comprises and reads stability and write stability.The main flow cellular construction of SRAM comprises 6 MOS transistor, and its formation can be the whole CMOS planar structure, also can be the laminated type three-dimensional structure.Please refer to Fig. 1, Fig. 1 is the structural representation of six transistorized SRAM in the prior art, among the figure, described SRAM is made of six transistors, in described six transistors, comprise four NMOS pipe (N1, N2, N3, N4) and two PMOS pipes (P1, P2), wherein a PMOS pipe P1, NMOS pipe N1 and the 2nd PMOS pipe P2, the 2nd NMOS pipe N2 form two COMS phase inverters, and cross-couplings forms flip and flop generator; Gate tube the 3rd NMOS pipe N3, the 4th NMOS pipe N4 provides the approach and the control of data input and output; BL among the figure,
Be the bit line control signal, WL is the word line of this unit, in read operation, when V1 voltage increases, just may cause the change of current lock-out state.And after the CMOS technology enters sub-micro; the bad stability of D S RAM; especially the bad stability of reading state; its main cause is that 2 PMOS load pipes are to be made by non-aligned back of the body grid technique technology; when the stored data of the same block in the memory is repeatedly read; the reading times between 100,000 to 1,000,000 times for example; probably the data that can take place to be read is wrong; even this data that is repeatedly read in the block to be stored can take place unusual or loses; this type of phenomenon has with field of the present invention knows that usually the knowledgeable is used to be called " reading interference " (read-disturb); therefore do not reducing the metal-oxide-semiconductor volume; guarantee under the prerequisite of metal-oxide-semiconductor stable performance; how to reduce the volume of the memory cell of static random access memory, become the target that all big enterprises are pursued.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of static random access memory, and the memory cell that solves static random access memory reduces the problem of volume under the impregnable prerequisite of stability.
To achieve these goals, the present invention proposes a kind of static random access memory, comprise: NMOS pipe, the 2nd NMOS pipe, PMOS pipe and the 2nd PMOS pipe, described NMOS pipe links to each other respectively with described PMOS pipe, described the 2nd PMOS pipe, described the 2nd NMOS pipe links to each other respectively with described PMOS pipe, described the 2nd PMOS pipe, and described PMOS pipe also links to each other with described the 2nd PMOS pipe.
Optionally, described NMOS pipe and described the 2nd NMOS pipe are N type Thin Film Transistor (TFT).
Optionally, the source electrode of the grid of a described PMOS pipe and described the 2nd PMOS pipe or drain electrode link to each other.
Optionally, the source electrode of the grid of a described PMOS pipe and described the 2nd NMOS pipe or drain electrode link to each other.
Optionally, the source electrode of the grid of described the 2nd PMOS pipe and a described PMOS pipe or drain electrode link to each other.
Optionally, the source electrode of the grid of described the 2nd PMOS pipe and a described NMOS pipe or drain electrode link to each other.
Optionally, described PMOS pipe and described the 2nd PMOS pipe are P type Thin Film Transistor (TFT).
Optionally, the grid of a described NMOS pipe links to each other with the source electrode or the drain electrode of described the 2nd NMOS pipe, the 2nd PMOS pipe respectively.
Optionally, the grid of described the 2nd NMOS pipe links to each other with the source electrode or the drain electrode of described NMOS pipe, a PMOS pipe respectively.
The useful technique effect of a kind of static random access memory of the present invention is: the present invention adopts four metal-oxide-semiconductors to form the memory cell of static random access memory, farthest reduce the cellar area of static random access memory, helped forming the memory cell of the static random access memory of super-high density; NMOS pipe adopts the Thin Film Transistor (TFT) of N type in addition, has bigger leakage current, easier maintenance store status, make memory performance stability obtain improving.
Description of drawings
Fig. 1 is the structural representation of six transistorized SRAM in the prior art.
Fig. 2 is the first example structure schematic diagram of a kind of static random access memory of the present invention.
Fig. 3 is the second example structure schematic diagram of a kind of static random access memory of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.
The present invention proposes a kind of static random access memory, comprise: NMOS pipe, the 2nd NMOS pipe, PMOS pipe and the 2nd PMOS pipe, described NMOS pipe links to each other respectively with described PMOS pipe, described the 2nd PMOS pipe, described the 2nd NMOS pipe links to each other respectively with described PMOS pipe, described the 2nd PMOS pipe, and described PMOS pipe also links to each other with described the 2nd PMOS pipe.
At first, please refer to Fig. 2, Fig. 2 is the first example structure schematic diagram of a kind of static random access memory of the present invention, present embodiment comprises a N type Thin Film Transistor (TFT) NTFT1, the 2nd N type Thin Film Transistor (TFT) NTFT2, the one PMOS pipe P1 and the 2nd PMOS pipe P2, Thin Film Transistor (TFT), has bigger leakage current, easier maintenance store status, make the stability of memory performance be improved, a described N type Thin Film Transistor (TFT) NTFT1 and described PMOS pipe P1, described the 2nd PMOS pipe P2 links to each other respectively, the grid of described PMOS pipe P1 links to each other with source electrode or the drain electrode of described the 2nd PMOS pipe P2, the grid of described PMOS pipe P1 and source electrode or the drain electrode of described the 2nd N type Thin Film Transistor (TFT) NTFT2 link to each other, and source electrode and drain electrode can be exchanged in actual use; The 2nd N type Thin Film Transistor (TFT) NTFT2 links to each other respectively with a described PMOS pipe P1, described the 2nd PMOS pipe P2, the grid of described the 2nd PMOS pipe P2 links to each other with source electrode or the drain electrode of described PMOS pipe P1, the grid of described the 2nd PMOS pipe P2 and source electrode or the drain electrode of a described N type Thin Film Transistor (TFT) NTFT1 link to each other, and described PMOS pipe P1 also links to each other with described the 2nd PMOS pipe P2.BL among the figure,
Be the bit line control signal, WL is a word line control signal, and Vdd is a high level.
The operation principle of present embodiment is: when word line control signal WL is high level, gate tube the one N type Thin Film Transistor (TFT) NTFT1, the 2nd N type Thin Film Transistor (TFT) NTFT2 conducting, the trigger that PMOS pipe P1 and the 2nd PMOS pipe P2 form can from bit line BL,
Output or input signal.
Concrete in the present embodiment to read process as follows: the signal of establishing the static random access memory memory cell is " 1 ", i.e. V2=" 1 " among Fig. 2, and V1=" 0 " chooses the word line (WL=V of this unit
DD), the level of node V1, V2 shifts out by gate tube and bit line.
Then, please refer to Fig. 3, Fig. 3 is the second example structure schematic diagram of a kind of static random access memory of the present invention, present embodiment comprises NMOS pipe N1, the 2nd NMOS manages N2, the one P type Thin Film Transistor (TFT) PTFT1 and the 2nd P type Thin Film Transistor (TFT) PTFT2, Thin Film Transistor (TFT), has bigger leakage current, easier maintenance store status, make the stability of memory performance be improved, the grid of a described NMOS pipe is managed with described the 2nd NMOS respectively, the source electrode of the 2nd PMOS pipe or drain electrode link to each other, and the grid of described the 2nd NMOS pipe is managed with a described NMOS respectively, the source electrode of the one PMOS pipe or drain electrode link to each other.BL among the figure,
Be the bit line control signal, WL is a word line control signal, and Vss is a low level.
The operation principle of present embodiment is: when word line control signal WL is low level, gate tube the one P type Thin Film Transistor (TFT) PTFT1, the 2nd P type Thin Film Transistor (TFT) PTFT2 conducting, the trigger that NMOS pipe N1 and the 2nd NMOS pipe N2 form can from bit line BL,
Output or input signal.Concrete in the present embodiment to read process as follows: the signal of establishing the static random access memory memory cell is " 1 ", it is V2=among Fig. 2 " 1 ", V1=" 0 " chooses the word line (WL=Vss) of this unit, and the level of node V1, V2 shifts out by gate tube and bit line.
The signal read is exported through behind the sense amplifier, and the amplifier that transistor constitutes will be accomplished without distortion signal voltage to be amplified, and just must guarantee that transistorized emitter junction positively biased, collector junction are anti-inclined to one side, and its working point promptly should be set.So-called working point is exactly that setting by external circuit makes transistorized base stage, emitter and collector be in desired current potential (can obtain according to calculating).These external circuits just are called biasing circuit (can be regarded as, the positive and negative inclined to one side circuit of PN junction is set), and biasing circuit just is called bias current to the electric current that transistor provides.Go ahead with total radio amplifier commonly used, main flow is the IC from the emitter to the collector electrode, and bias current is exactly the IB from the emitter to the base stage, and relative and main circuit is exactly so-called biasing circuit for base stage provides the circuit of electric current.
A kind of static random access memory of the present invention has adopted four metal-oxide-semiconductors, 6 pipes with respect to prior art, its memory cell area reduces greatly, but as static random access memory, the performance no change that it reads and stores, in addition, when making, the one NMOS pipe and the 2nd NMOS pipe can also be made in that a PMOS manages and the 2nd PMOS pipe on, further dwindle memory cell area, help forming the memory cell of the static random access memory of super-high density.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have in the technical field of the present invention and know the knowledgeable usually, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (9)
1. static random access memory, it is characterized in that comprising: NMOS pipe, the 2nd NMOS pipe, PMOS pipe and the 2nd PMOS pipe, described NMOS pipe links to each other respectively with described PMOS pipe, described the 2nd PMOS pipe, described the 2nd NMOS pipe links to each other respectively with described PMOS pipe, described the 2nd PMOS pipe, and described PMOS pipe also links to each other with described the 2nd PMOS pipe.
2. static random access memory according to claim 1 is characterized in that: described NMOS pipe and described the 2nd NMOS pipe are N type Thin Film Transistor (TFT).
3. static random access memory according to claim 2 is characterized in that: the source electrode of the grid of a described PMOS pipe and described the 2nd PMOS pipe or drain electrode link to each other.
4. static random access memory according to claim 2 is characterized in that: the source electrode of the grid of a described PMOS pipe and described the 2nd NMOS pipe or drain electrode link to each other.
5. static random access memory according to claim 2 is characterized in that: the source electrode of the grid of described the 2nd PMOS pipe and a described PMOS pipe or drain electrode link to each other.
6. static random access memory according to claim 2 is characterized in that: the source electrode of the grid of described the 2nd PMOS pipe and a described NMOS pipe or drain electrode link to each other.
7. static random access memory according to claim 1 is characterized in that: described PMOS pipe and described the 2nd PMOS pipe are P type Thin Film Transistor (TFT).
8. static random access memory according to claim 7 is characterized in that: the grid of a described NMOS pipe links to each other with the source electrode or the drain electrode of described the 2nd NMOS pipe, the 2nd PMOS pipe respectively.
9. static random access memory according to claim 7 is characterized in that: the grid of described the 2nd NMOS pipe links to each other with the source electrode or the drain electrode of described NMOS pipe, a PMOS pipe respectively.
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| CN201010164943A CN101819977A (en) | 2010-04-29 | 2010-04-29 | Static random access memory |
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| CN201010164943A CN101819977A (en) | 2010-04-29 | 2010-04-29 | Static random access memory |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1357922A (en) * | 2000-12-06 | 2002-07-10 | 三菱电机株式会社 | Semiconductor memory |
| CN1585986A (en) * | 2001-11-13 | 2005-02-23 | 英特尔公司 | Bias Technology for High Density Static Random Access Memory |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1357922A (en) * | 2000-12-06 | 2002-07-10 | 三菱电机株式会社 | Semiconductor memory |
| CN1585986A (en) * | 2001-11-13 | 2005-02-23 | 英特尔公司 | Bias Technology for High Density Static Random Access Memory |
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