CN101819974B - Groove type metal oxide semiconductor transistor - Google Patents

Abstract

The invention discloses a trench type metal oxide semiconductor transistor, the trench type metal oxide semiconductor transistor comprises: a semiconductor substrate; an epitaxial layer and a channel region sequentially formed in the semiconductor substrate; A plurality of grooves in the semiconductor substrate; gates formed in the plurality of grooves; a gate dielectric layer formed between the grooves and the gates; formed in corresponding channel regions The source region located on both sides of the groove; the insulating layer formed on the semiconductor substrate; the source contact plug penetrating through the insulating layer and extending into the corresponding source region and the corresponding channel region plug; a gate contact plug penetrating through the insulating layer, the bottom end surface of the gate contact plug is flush with the top surface of the corresponding gate, and the present invention can improve the stability of the semiconductor device.

Description

Trench Metal-Oxide-Semiconductor Transistor

technical field

The invention relates to the field of integrated circuit manufacturing, in particular to a trench type metal oxide semiconductor transistor.

Background technique

In trench metal oxide semiconductor transistor (Trench Metal Oxide Semiconductor Field Effect Transistor, MOSFET) or vertical transistor (vertical transistor), the gate is formed in the trench in the semiconductor substrate, and the trench The source of the MOS transistor is formed on both sides of the gate. In the trench metal-oxide-semiconductor transistor, in order to reduce its on-resistance per unit area and reduce current loss, the critical dimension of a single trench-type metal-oxide-semiconductor transistor is getting smaller and smaller, and the depth of the trench is also getting smaller. come smaller.

For details, please refer to FIG. 1 , which is a schematic diagram of an existing trenched metal oxide semiconductor transistor. As shown in FIG. 1 , an existing trenched metal oxide semiconductor transistor includes: a semiconductor substrate 100, Epitaxial layer 110 , channel region 120 , multiple grooves 130 , multiple gates 140 , gate dielectric layer 150 , source region 160 , insulating layer 170 , source contact plug 180 , gate contact plug 190 . The epitaxial layer 110 is formed in the semiconductor substrate 100, the channel region 120 is formed in the semiconductor substrate 100 and located on the epitaxial layer 110, the plurality of grooves 130 are formed in the semiconductor substrate 100, the The gate 140 is formed in the plurality of grooves 130, the gate dielectric layer 150 is formed between the groove 130 and the gate 140, and the source region 160 is formed in the corresponding channel region 120 and located On both sides of the groove 130, the insulating layer 170 is formed on the semiconductor substrate 100, the insulating layer 170 includes an oxide layer 171 and a borophosphosilicate glass layer 172 formed on the oxide layer 171, the source The pole contact plug 180 penetrates the insulating layer 170 and extends into the corresponding source region 160 and the corresponding channel region 120, and the gate contact plug 190 penetrates the insulating layer 170 and extends into the corresponding gate electrode 140 (the bottom surface of the gate contact plug 190 is lower than the top surface of the corresponding gate 140).

Wherein, the source contact plug 180 and the gate contact plug 190 are formed by using the same photolithography process (using a mask), therefore, the source contact plug 180 and the gate contact plug 190 The depth is also the same. Specifically, the formation process of the source contact plug 180 and the gate contact plug 190 includes the following steps: first, coat a photoresist on the insulating layer 170, and perform contact hole photolithography to form a patterned photoresist. a resist layer, the patterned photoresist layer has a pattern of gate contact holes and a pattern of source contact holes; then, dry etching is used to etch the insulating layer 170 not covered by the patterned photoresist layer, To form a gate contact hole and a source contact hole, the depth of the gate contact hole and the source contact hole are the same; Next, a metal layer is deposited in the source contact hole and the gate contact hole to form a source pole contact plugs 180 and gate contact plugs 190.

Please refer to FIG. 2 for details, which is a schematic diagram of another existing trench metal oxide semiconductor transistor. In detail, another existing trench metal oxide semiconductor transistor includes: a semiconductor substrate 200, an epitaxial Layer 210, channel region 220, multiple grooves 230, multiple gates 240, gate dielectric layer 250, source region 260, insulating layer 270, source contact plug 280, gate contact plug 290, the The insulating layer 270 includes an oxide layer 271 and a borophosphosilicate glass layer 272 formed on the oxide layer 271 . As the application range of trench metal-oxide-semiconductor transistors becomes wider and wider, and the size of semiconductor devices becomes smaller, as shown in FIG. The depth of the region 220 remains relatively deep to achieve the purpose of simultaneously contacting the source region and the well region; while the depth of the gate contact plug 290 needs to be reduced, thus producing a source contact plug 280 and a gate contact plug. The technical requirement that the plug 290 needs two photolithography processes to be formed. However, it has been found in actual production that when producing the trench metal-oxide-semiconductor transistor shown in FIG. The dry etching time is long, and the plasma used in this dry etching process can easily damage the gate dielectric layer 250, which affects the stability of the semiconductor device.

Contents of the invention

The invention provides a trench type metal oxide semiconductor transistor, which reduces plasma damage to a gate dielectric layer during dry etching and improves the stability of a semiconductor device.

In order to solve the above technical problems, the present invention provides a trench type metal oxide semiconductor transistor, comprising: a semiconductor substrate; an epitaxial layer and a channel region sequentially formed in the semiconductor substrate; A plurality of grooves in the plurality of grooves; gates formed in the plurality of grooves; a gate dielectric layer formed between the grooves and the gates; formed in the corresponding channel region and located in the Source regions on both sides of the groove; an insulating layer formed on the semiconductor substrate; a source contact plug that penetrates the insulating layer and extends into the corresponding source region and the corresponding channel region; The gate contact plug of the insulating layer, the bottom end surface of the gate contact plug is flush with the top surface of the corresponding gate.

Optionally, in the trench metal oxide semiconductor transistor, the semiconductor substrate is an N-type semiconductor substrate, the epitaxial layer is an N-type epitaxial layer, and the ion implantation concentration of the semiconductor substrate is higher than The ion implantation concentration of the epitaxial layer.

Optionally, in the trench metal oxide semiconductor transistor, the gate is an N-type polysilicon gate.

Optionally, in the trench metal oxide semiconductor transistor, the semiconductor substrate is a P-type semiconductor substrate, the epitaxial layer is a P-type epitaxial layer, and the ion implantation concentration of the semiconductor substrate is higher than The ion implantation concentration of the epitaxial layer.

Optionally, in the trench metal oxide semiconductor transistor, the gate is a P-type polysilicon gate.

Optionally, in the trench metal oxide semiconductor transistor, the insulating layer includes an oxide layer and a borophosphosilicate glass layer formed on the oxide layer.

Compared with the prior art, the trench metal oxide semiconductor transistor of the present invention has the following advantages:

The bottom end face of the gate contact plug of the present invention is flush with the top end face of the corresponding gate, that is to say, compared with the prior art, the depth of the gate contact plug is smaller, therefore, forming The dry etching time required for the gate contact plug is short, which can reduce the damage of the plasma to the gate dielectric layer during the dry etching process, and improve the stability of the semiconductor device.

Description of drawings

FIG. 1 is a schematic diagram of an existing trench metal-oxide-semiconductor transistor;

FIG. 2 is a schematic diagram of another existing trench metal-oxide-semiconductor transistor;

FIG. 3 is a schematic diagram of a trench metal-oxide-semiconductor transistor provided by an embodiment of the present invention.

detailed description

The trench metal-oxide-semiconductor transistor of the present invention will be described in more detail below in conjunction with a schematic cross-sectional view, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein and still realize Advantageous effects of the present invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such a development effort might be complex and time consuming, but would nevertheless be merely a routine undertaking for those skilled in the art.

In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

The core idea of the present invention is to provide a trenched metal oxide semiconductor transistor, the bottom end surface of the gate contact plug of the trenched metal oxide semiconductor transistor is flush with the top surface of the corresponding gate, That is to say, compared with the prior art, the depth of the gate contact plug is smaller, therefore, the dry etching time required for forming the gate contact plug is shorter, which can reduce the dry etching time. The plasma damages the gate dielectric layer during the etching process, improving the stability of the semiconductor device.

Please refer to FIG. 3 , which is a schematic diagram of a trenched metal oxide semiconductor transistor provided by an embodiment of the present invention. As shown in FIG. 3 , the trenched metal oxide semiconductor transistor includes: a semiconductor substrate 300, an epitaxial layer 310, A channel region 320 , a plurality of grooves 330 , a plurality of gates 340 , a gate dielectric layer 350 , a source region 360 , an insulating layer 370 , a source contact plug 380 , and a gate contact plug 390 .

The epitaxial layer 310 is formed in the semiconductor substrate 300, the channel region 320 is formed in the semiconductor substrate 300 and located on the epitaxial layer 310, the plurality of grooves 330 are formed in the semiconductor substrate 200, the The gate 340 is formed in the plurality of grooves 330, the gate dielectric layer 350 is formed between the groove 330 and the gate 340, and the source region 360 is formed in the corresponding channel region 320 and located On both sides of the groove 330, the insulating layer 370 is formed on the semiconductor substrate 300, and the source contact plug 380 penetrates the insulating layer 370 and extends into the corresponding source region 360 and the corresponding trench. In the channel region 320 , the gate contact plug 390 penetrates through the insulating layer 370 , and the bottom surface of the gate contact plug 390 is flush with the top surface of the corresponding gate 340 . Since the bottom surface of the gate contact plug 390 is flush with the top surface of the corresponding gate, that is, compared with the prior art, the depth of the gate contact plug 390 is smaller, therefore The dry etching time required to form the gate contact plug 390 is very short, which can reduce the damage of the plasma used in the dry etching process to the gate dielectric layer 350 and improve the stability of the semiconductor device.

In a specific embodiment of the present invention, the source contact plug 380 and the gate contact plug 390 can be respectively formed by two photolithography processes (using two masks), so that the gate contact plug The bottom surface of the plug 390 is flush with the top surface of the corresponding gate 340 .

In a specific embodiment of the present invention, the semiconductor substrate 300 is an N-type semiconductor substrate, the epitaxial layer 310 is an N-type epitaxial layer, and the ion implantation concentration of the semiconductor substrate 300 is higher than that of the epitaxial layer. 310 ion implantation concentration. Correspondingly, the gate 340 is an N-type polysilicon gate, the source region 360 is an N+ type source region, and the ion implantation concentration of the source region 360 is higher than that of the epitaxial layer 310 .

In another specific embodiment of the present invention, the semiconductor substrate 300 can also be a P-type semiconductor substrate, the epitaxial layer 310 can also be a P-type epitaxial layer, and the ion implantation concentration of the semiconductor substrate 300 is high The ion implantation concentration in the epitaxial layer 310. Correspondingly, the gate 340 is a P-type polysilicon gate, the source region 360 is a P+-type source region, and the ion implantation concentration of the source region 360 is higher than that of the epitaxial layer 310 .

In a specific embodiment of the present invention, the insulating layer 370 includes an oxide layer 371 and a borophosphosilicate glass layer 372 formed on the oxide layer 371 , and the gate oxide layer 350 is made of silicon dioxide.

To sum up, the present invention provides a trenched metal oxide semiconductor transistor, the bottom end surface of the gate contact plug of the trenched metal oxide semiconductor transistor is flush with the top surface of the corresponding gate, That is to say, compared with the prior art, the depth of the gate contact plug is smaller, therefore, the dry etching time required for forming the gate contact plug is shorter, which can reduce the dry etching time. The plasma damages the gate dielectric layer during the etching process, improving the stability of the semiconductor device.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (6)

1. A trench metal oxide semiconductor transistor, comprising: semiconductor substrate; sequentially forming an epitaxial layer and a channel region in the semiconductor substrate; a plurality of grooves formed in the semiconductor substrate; a gate formed in the plurality of grooves; a gate dielectric layer formed between the groove and the gate; a source region formed in the corresponding channel region and located on both sides of the groove; an insulating layer formed on the semiconductor substrate; a source contact plug penetrating through the insulating layer and protruding into the corresponding source region and the corresponding channel region; a gate contact plug penetrating through the insulating layer, the bottom surface of the gate contact plug being flush with the top surface of the corresponding gate; Wherein, the source contact plug and the gate contact plug are respectively formed by two photolithography processes. 2. The trench metal oxide semiconductor transistor according to claim 1, wherein the semiconductor substrate is an N-type semiconductor substrate, the epitaxial layer is an N-type epitaxial layer, and the semiconductor substrate The ion implantation concentration is higher than that of the epitaxial layer. 3. The trench metal oxide semiconductor transistor according to claim 2, wherein the gate is an N-type polysilicon gate. 4. The trench metal oxide semiconductor transistor according to claim 1, wherein the semiconductor substrate is a P-type semiconductor substrate, the epitaxial layer is a P-type epitaxial layer, and the semiconductor substrate The ion implantation concentration is higher than that of the epitaxial layer. 5. The trench metal oxide semiconductor transistor according to claim 4, wherein the gate is a P-type polysilicon gate. 6. The trench metal oxide semiconductor transistor according to claim 1, wherein the insulating layer comprises an oxide layer and a borophosphosilicate glass layer formed on the oxide layer.