CN101814477B - A Silicon through holes after the interlinked structure being passivated. - Google Patents

Abstract

The invention discloses an integrated circuit structure using a passivated interconnection structure to form a through-silicon via, comprising: a semiconductor substrate; a through-silicon via (TSV) extending into the semiconductor substrate; a pad formed above the semiconductor substrate, and spaced apart from the TSV; and an interconnection structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSVs.

Description

Through-silicon vias formed using post-passivation interconnect structures

Cross References to Related Applications

This application claims priority to US Provisional Application 61/154,979, filed February 24, 2009, the entire contents of which are hereby incorporated by reference.

technical field

One or more embodiments relate to the fabrication of semiconductor devices, and more particularly, to the fabrication of through silicon vias and post passivation interconnect structures.

Background technique

The semiconductor industry has experienced continuous rapid development due to continuous improvements in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has resulted from repeated reductions in minimum feature size, allowing more features to be integrated into a given chip area. These integration improvements are two-dimensional (2D) in nature, ie the volume occupied by the integrated components is mainly on the surface of the semiconductor wafer. Although major improvements in lithography have led to dramatic improvements in 2D integrated circuit formation, there are physical limits to the densities that can be achieved in two dimensions. One limitation lies in the need to minimize the size of these components. In addition, more complex designs are required when more devices are placed in one chip. Other limitations lie in the significant increase in the number and length of interconnections between devices as the number of devices increases. As the number and length of interconnections increase, circuit RC delays and power consumption increase. In efforts to address the above limitations, three-dimensional integrated circuits (3DICs) and stacked dies are commonly used.

Thus, through silicon vias (TSVs) are used in 3DICs and stacked dies for connecting the dies. In this case, TSVs are typically used to connect the integrated circuit on the die to the backside of the die. In addition, TSVs are also used to provide a short circuit ground path, which is used to ground the integrated circuit through the backside of the die covered by the ground metal film. Integrated circuits typically include contact areas for connecting the integrated circuit to other circuits. Contact-bonding (CB) pads are typically formed in the metal layer (ie, the top layer of metal), which is connected to the TSVs through a post-passivation interconnect (PPI) structure. However, the conventional PPI process provides weak adhesion to CB and causes high contact resistance. Therefore, improved structures and fabrication methods are needed to overcome the disadvantages of conventional techniques.

Contents of the invention

One or more disclosed embodiments describe an integrated circuit structure comprising: a semiconductor substrate; through-silicon vias (TSVs) extending into the semiconductor substrate; pads formed over the semiconductor substrate and connected to the TSVs; and an interconnection structure formed over the semiconductor substrate and electrically connecting the TSVs and the pads. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSVs.

At least one embodiment describes an integrated circuit structure comprising: a semiconductor substrate; a low-k dielectric layer overlying the semiconductor substrate; metal lines formed in the low-k dielectric layer; a first passivation layer , formed on the low-k dielectric layer and expose a portion of the metal line; pads, formed in the first passivation layer and on the exposed portion of the metal line; through-silicon vias (TSVs), through the first passivation layer and a low-k dielectric layer extending into the semiconductor substrate; and an interconnection structure formed over the first passivation layer and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion over the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSVs.

Description of drawings

Carry out following detailed description with reference to accompanying drawing, wherein:

1 to 7 are cross-sectional views of exemplary embodiments of post-passivation interconnect (PPI) structures formed in a TSV process.

Detailed ways

The present disclosure generally relates to the fabrication of via structures that can be applied to have post-passivation interconnect (PPI) structures (connected to contact bond (CB) pads for forming vertical interconnects on stacked wafers/die. even) through-silicon via (TSV) fabrication. Through-silicon vias (TSVs), also known as through-substrate vias or through-wafer vias, as defined herein, provide contact to one or more conductive layers (e.g., metal interconnect layers, including bond pads) on a substrate. pads), connections between conductive layers (e.g., metal interconnect layers) and semiconductor layers (such as silicon components), and/or other connections between components formed on or connected to a substrate Expect to connect. In some embodiments, this connection provided by the via provides an electrical path from one component to another. The vias may be filled with conductive materials, insulating materials, and/or other materials used in the art. Additionally, vias may be formed on a substrate that includes openings in one or more layers on the substrate, including dielectric layers, metal layers, semiconductor layers, and/or other components known in the art.

Here, cross-sectional views of FIGS. 1 to 7 illustrate exemplary embodiments of a PPI structure formed in a TSV process.

Referring now to FIG. 1 , there is shown a cross-sectional view of a wafer 100 including a semiconductor substrate 10 and an interconnect structure 12 over the semiconductor substrate 10 . Semiconductor substrate 10 is formed from silicon, although other semiconductor materials including Group III, IV, V elements and SiGe may also be used. Optionally, the semiconductor substrate 10 includes a non-conductive layer. An integrated circuit including transistors, resistors, capacitors and other known components is formed on the semiconductor substrate 10 .

Interconnect structure 12 includes metal lines and vias formed in dielectric layer 14 , typically low-k dielectric layer 14 . The interconnection structure 12 includes metallization layers stacked one by one, metal lines are formed in the metallization layers, and via holes connect the metal lines. The interconnect structure 12 interconnects the integrated circuits formed on the top surface of the semiconductor substrate 10 and connects the integrated circuits to bonding pads. For example, metal lines 12a and vias 12b are formed in dielectric layer 14, which is a low-k dielectric layer having a dielectric constant (k value) less than about 3.5. In one embodiment, dielectric layer 14 is formed of an ultra-low-k dielectric layer having a k value of less than about 2.5. In some embodiments, interconnect structure 12 also includes an upper dielectric layer on top of low-k dielectric layer 14 , wherein the upper dielectric layer includes a non-low-k dielectric material that does not have moisture absorption issues. The k value of the upper dielectric layer is greater than about 3.5, more preferably, greater than about 3.9. In one embodiment, the upper dielectric layer includes an undoped silica glass (USG) layer.

Figure 1 also shows contact bond (CB) pads 18, which are used in the bonding process to connect the integrated circuits in the respective chips to external components. A CB pad 18 is formed in the first passivation layer 16 to connect to the underlying metal line 12a. In the manufacture of the CB pad 18, a first passivation layer 16, for example comprising a first dielectric layer 16a and a second dielectric layer 16b, is deposited on top of the dielectric layer 14, then patterned and etched to form An opening that exposes the underlying metal line 12a. A conductive material is then deposited in the opening and patterned to form the CB pad 18 . The first passivation layer 16 may be formed of a dielectric material such as silicon oxide, silicon nitride, polyimide, or combinations thereof. In one embodiment, the first dielectric layer 16a is a silicon oxide layer and the second dielectric layer 16b is a silicon nitride layer. In some embodiments, the conductive material of the CB pad 18 includes a metal selected from the group consisting of aluminum, tungsten, silver, copper, aluminum alloys, copper alloys, and combinations thereof.

2 and 3 illustrate the formation of TSV openings 22 that extend into the semiconductor substrate 10 . Referring to FIG. 2 , a photoresist layer 20 is spin-coated on the first passivation layer 16 and the CB pad 18 . The photoresist layer 20 is then patterned by exposure, baking, development, and/or other photolithographic processes known in the art to provide openings 21 in the photoresist layer 20 exposing a portion of the first passivation layer 16. . As shown in FIG. 3, the method then proceeds to etch the exposed layer using the patterned photoresist layer 20 as a mask element to form a layer through the first passivation layer 16, the dielectric layer 14 and a portion of the semiconductor substrate. The TSV opening 22 of the bottom 10. Then, the photoresist layer 20 is peeled off. In some embodiments, TSV openings 22 are etched using any suitable etching method, including, for example, plasma etching, chemical wet etching, laser drilling, and/or other processes known in the art. In one embodiment, the TSV openings 22 are etched using reactive ion etching (RIE). In some embodiments, the depth of TSV opening 22 is approximately 100 μm to 300 μm. The etching process can result in openings with vertical sidewall profiles or tapered sidewall profiles.

FIG. 4 shows the formation of the second passivation layer 24 . A second passivation layer 24 , for example including a first isolation film 24 a and a second isolation film 24 b , is formed overlying the first passivation layer 16 and the CB pad 18 , and lines the sidewall and bottom of the TSV opening 22 . In some embodiments, second passivation layer 24 is formed of a dielectric material such as silicon oxide, silicon nitride, polyimide, or the like. Formation methods include plasma enhanced chemical vapor deposition (PECVD) or other common CVD methods. In one embodiment, the first isolation film 24a is a silicon oxide layer, and the second isolation film 24b is a silicon nitride layer.

5 and 6 illustrate the formation of a via opening 28 in the second passivation layer 24 adjacent to the CB pad 18 . Referring to FIG. 5, a mask 26 is formed over the previously formed structure. In one embodiment, mask 26 includes an organic material such as Ajinimoto buildup film (ABF). The ABF film was first laminated on the structure shown in Figure 5. Then, heat and pressure are applied to the laminated film to soften it so that a flat top surface is formed. In the resulting structure, mask 26 has a thickness greater than about 5 μm, more preferably between about 10 μm and about 100 μm. However, mask 26 may comprise other materials such as prepreg and resin coated copper (RCC). Optionally, the mask 26 is a photoresist, which can be a positive photoresist or a negative photoresist. The mask 26 is then patterned to form an opening 27 exposing a portion of the second passivation layer 24 over the CB pad 18 and its peripheral region. A patterned mask 26 covers the TSV openings 22 .

As shown in FIG. 6 , the method is performed using a patterned mask 26 as a mask element to etch the exposed portion of the second passivation layer 24 to expose the CB pad 18, and the second passivation layer adjacent to the CB pad 18 At least one via opening 28 is formed in the layer. In one embodiment, the via opening 28 is an annular opening surrounding the CB pad 18 , such as an annular opening having an octagonal profile. Via opening 28 is etched using any suitable etching method including, for example, plasma etching, chemical wet etching, and/or other processes known in the art. In one embodiment, via opening 28 is etched using reactive ion etching (RIE). After the passivation etch process, mask 26 is then removed. If the mask 26 is a dry film, it can be removed by an alkaline solution. If the mask 26 is formed of photoresist, it may be removed by acetone, N-methylpyrrolidone (NMP), dimethylsulfoxide (DMSO), aminoethoxyethanol, or the like. As a result, the TSV opening 22 lined with the second passivation layer 24 is exposed.

Next, as shown in FIG. 7 , a conductive material layer 30 is deposited on the resulting structure to fill the TSV openings 22 and desired areas outside the TSV openings 22 , thereby forming conductive plugs 32 . Throughout the description, the conductive plug 32 is referred to as a through silicon via (TSV). In one embodiment, the layer of conductive material 30 includes copper or a copper alloy. Other metals such as aluminum, silver, gold, titanium, tantalum, and combinations thereof may also be used. Formation methods may include sputtering, printing, electroplating, electroless plating, and common chemical vapor deposition (CVD) methods. At the moment the TSV opening 22 is filled with the layer of conductive material 30 , the same conductive material is also formed on the CB pad 18 and fills the via opening 28 , forming a post-passivation interconnect (PPI) structure 34 . The PPI structure 34 includes an upper portion 34 a and a lower portion 34 b for covering the CB pad 18 . The upper part 34a is called a conductive line 34a, and the lower part is called a support 34b. A conductive line 34a is formed on the CB pad 18 and connected to the underlying support 34b. Conductive lines 34a also extend to connect the top ends of TSVs 32. A support 34 b is formed in the via opening 28 of the second passivation layer 24 adjacent to the CB pad 18 . Thus, the PPI structure 34 covers the CB pad 18 to provide good adhesion and reduce contact resistance therebetween. In one embodiment, support 34 b is a metal ring surrounding CB pad 18 . Optionally, the support body 34 b includes a plurality of metal pillars adjacent to the CB pad 18 . In one embodiment, PPI structure 34 has a thickness of less than about 30 μm, such as between about 2 μm and about 25 μm. The layer of conductive material 30 is then patterned to form the resulting structure as shown in FIG. 7 . PPI structure 34 is formed using the same process as TSV 32, interconnecting TSV 32 to CB pad 18, which in turn is further connected to active circuitry.

In the embodiment of forming the conductive layer 30 , a copper seed layer may also be formed by PVD, sputtering or electroless plating, and then copper is sputtered to fill desired areas. Filling processes are known in the art and therefore will not be repeated here. Formation methods may include sputtering, printing, electroplating, electroless plating, and common chemical vapor deposition (CVD) methods. Before forming the copper seed layer and the copper layer, a diffusion barrier layer may be deposited to cover the exposed portions. The diffusion barrier layer can include common barrier materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof, and can be formed using physical vapor deposition, sputtering, and the like.

In a subsequent step, a glass wafer may be mounted on top of the structures formed in the previously discussed steps. Then, wafer grinding is performed to thin the backside of the semiconductor substrate 10 until the TSVs 32 are exposed. Then, remove the glass wafer. In some embodiments, the method further includes process steps such as a metallization process to provide interconnects and/or other processes known in the art.

In the foregoing detailed description, specific embodiments have been described. However, it should be understood that various modifications, structures, processes and changes can be made without departing from the spirit and scope of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative and not as limiting of the invention. It is to be understood that the disclosed embodiments are capable of using various other combinations and environments and are capable of changes or modifications within the scope of the concepts presented herein.

Claims (15)

1. An integrated circuit structure comprising: semiconductor substrate; through-silicon vias (TSVs) extending into the semiconductor substrate; a pad formed over the semiconductor substrate and spaced from the TSV; and an interconnection structure formed over the semiconductor substrate and electrically connecting the TSVs and the pads, Wherein, the interconnection structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSVs. 2. The integrated circuit structure of claim 1, wherein the lower portion of the interconnect structure is a ring surrounding the pad. 3. The integrated circuit structure of claim 1, wherein the interconnect structure and the TSVs are formed of the same conductive material, wherein the interconnect structure comprises copper and the TSVs comprise copper. 4. The integrated circuit structure of claim 1, wherein the bonding pad comprises aluminum or an aluminum alloy. 5. The integrated circuit structure of claim 1 , further comprising a passivation layer formed between said semiconductor substrate and said upper portion of said interconnect structure and surrounding said lower portion of said interconnect structure , the passivation layer extends into the semiconductor substrate to line the sidewalls and bottom of the TSV. 6. The integrated circuit structure of claim 5, wherein the passivation layer comprises two isolation layers. 7. The integrated circuit structure of claim 5, wherein the passivation layer comprises silicon oxide, silicon nitride, or a combination thereof. 8. An integrated circuit structure comprising: semiconductor substrate; a low-k dielectric layer overlying the semiconductor substrate; metal lines formed in the low-k dielectric layer; a first passivation layer formed on the low-k dielectric layer and exposing a portion of the metal line; pads formed in the first passivation layer and on exposed portions of the metal lines; a through silicon via (TSV) passing through the first passivation layer and the low-k dielectric layer and extending into the semiconductor substrate, wherein the TSV is spaced apart from the pad; and an interconnection structure formed over the first passivation layer and electrically connecting the TSV and the pad; Wherein, the interconnection structure includes an upper portion on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSVs. 9. The integrated circuit structure of claim 8, wherein the lower portion of the interconnect structure is a ring surrounding the pad. 10. The integrated circuit structure of claim 8, wherein the interconnect structure and the TSVs are formed of the same conductive material, wherein the interconnect structure comprises copper and the TSVs comprise copper. 11. The integrated circuit structure of claim 8, wherein the bonding pad comprises at least one of aluminum, copper, an aluminum alloy, or a copper alloy. 12. The integrated circuit structure of claim 8, further comprising a second passivation layer formed between said first passivation layer and said upper portion of said interconnect structure and surrounding said interconnect structure of the lower part. 13. The integrated circuit structure of claim 12, wherein the second passivation layer extends to line sidewalls and bottoms of the TSVs. 14. The integrated circuit structure of claim 12, wherein the second passivation layer comprises at least one of silicon oxide, silicon nitride, or combinations thereof. 15. The integrated circuit structure of claim 8, wherein the first passivation layer comprises at least one of silicon oxide, silicon nitride, or combinations thereof.

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