CN101764120B - leadless packaging structure of semiconductor device - Google Patents
leadless packaging structure of semiconductor device Download PDFInfo
- Publication number
- CN101764120B CN101764120B CN 200910202074 CN200910202074A CN101764120B CN 101764120 B CN101764120 B CN 101764120B CN 200910202074 CN200910202074 CN 200910202074 CN 200910202074 A CN200910202074 A CN 200910202074A CN 101764120 B CN101764120 B CN 101764120B
- Authority
- CN
- China
- Prior art keywords
- circuit die
- substrate
- district
- ground connection
- bonding region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910000679 solder Inorganic materials 0.000 claims abstract description 20
- 239000011230 binding agent Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920001568 phenolic resin Polymers 0.000 claims description 3
- 239000005011 phenolic resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000002002 slurry Substances 0.000 claims description 3
- 150000001875 compounds Chemical group 0.000 claims description 2
- 239000007767 bonding agent Substances 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a leadless packaging structure of a semiconductor device, which comprises a substrate and a circuit tube core, wherein the substrate at least comprises a top layer metal, the circuit tube core bonding area on the circuit tube core is connected with the substrate grounding bonding area through a grounding bonding wire, the first solder resist layer limits the bonding agent in an area within the substrate grounding bonding area, and the circuit tube core bonding area on the substrate is connected with the bottom metal through a through hole to be grounded. The invention reduces the packaging size of the semiconductor device and reduces the product cost.
Description
Technical field
The present invention relates to a kind of structure of semiconductor device, especially a kind of leadless packaging structure of semiconductor device.
Background technology
Wireless communication field is being faced with raising product integrated level, reduce the challenge of aspects such as product size and reduction product cost, littler to product, more complicated, require faster not only the design of circuit die to be challenged, the while has also proposed new challenge to the manufacturing of various encapsulating structures.
Form inductance through bonding line commonly used in the no lead packages, bonding line is a very thin metal wire, be used for connecting circuit tube core and package pins, wherein circuit die is to paste the district by the circuit die that binder is fixed on substrate, by bonding line circuit die bonding region and substrate ground connection bonding region are realized being electrically connected then, near the of substrate ground connection bonding region generally can be equipped with through hole, and substrate ground connection bonding region is connected with the ground pad of substrate underlying metal.Generally speaking, we wish that the bonding line of connecting circuit die bonding district and substrate ground connection bonding region can lack as far as possible, can reduce the bonding line inductance value like this.Some circuit die, power amplifier circuit tube core for example, relatively more responsive to the length of the bonding line of connecting circuit die bonding district and substrate ground connection bonding region, shorten bonding line length and can obviously improve equipment performance.Another benefit that shortens bonding line is to reduce package dimension, thereby reduces manufacturing cost.
Yet, several factors all can the limit key zygonema length, for example, when circuit die being fixed on the circuit die stickup district of substrate with binder, used binder can overflow the circuit die stickup district of substrate, will add the circuit die stickup district of large substrates and the distance between the substrate ground connection bonding region like this, thus the length of the bonding line of lengthening connecting circuit die bonding district and substrate ground connection bonding region.The factor that influences bonding line length also has a lot, for example the thickness of circuit die and circuit die bonding region all can influence the length of bonding line in the position of circuit die, wherein circuit die is thick more, the circuit die bonding region moves to the circuit die center from the circuit die edge, the length of capital lengthening bonding line, in addition, near the through hole the substrate ground connection bonding region also can increase the size of encapsulation.
Fig. 1 is traditional earth key zygonema encapsulating structure sectional drawing, wherein substrate 101 is a doubling plate, comprise top-level metallic and underlying metal, the middle material of double layer of metal is a phenolic resins, the substrate thickness of slab is 0.25mm, and substrate also can be multi-layer sheet during other were used, and material also can be epoxy resin FR4, pottery or other materials, thickness also can change.The design of substrate 101 top-level metallics has circuit die to paste district 102.Circuit die 103 is pasted district 102 by the circuit die that silver slurry 104 or other binders paste the substrate top-level metallic.Design has the ground connection bonding region around the circuit die of substrate top-level metallic is pasted district 102, this example is to paste the design of both sides, district in circuit die ground connection bonding region 105a is arranged, 105b, also can be at other Position Design ground connection bonding regions, ground connection bonding region 105a, 105b is by through hole 111a, and 111b receives substrate underlying metal ground, fills copper or other electrothermal conductor in the through hole.Earth key zygonema 106a, 106b be respectively with the bonding region 107a on the circuit die, the ground connection bonding region 105a of 107b and substrate top-level metallic, and 105b couples together.110a and 110b are solder mask.As can be seen from Figure 1, because substrate ground connection bonding region 105a, 105b and circuit die are pasted not adjacency of district 102, cause earth key zygonema 106a, 106b is longer, because the performance para-linkage line length of power amplifier circuit tube core is relatively more responsive, lengthening connecting circuit die bonding district 107a, 107b and substrate ground connection bonding region 105a, bonding line 106a between the 105b, the length of 106b can influence the equipment integral performance, and increases package dimension, increases equipment cost, while ground connection bonding region 105a, near the 105b through hole 111a, 111b also can increase package dimension, increases equipment cost.
Therefore, in no lead packages, we have strong demand to shorten the length of connecting circuit die bonding district and substrate ground connection bonding region bonding line, and save near the through hole the substrate ground connection bonding region, thus the size of dwindling encapsulation, the cost of reduction product.
Summary of the invention
Technical problem to be solved by this invention provides a kind of leadless packaging structure of semiconductor device, adopts simple structure, and can dwindle the package dimension of semiconductor device, reduces product cost simultaneously.
For solving the problems of the technologies described above, the technical scheme of leadless packaging structure of semiconductor device of the present invention is, comprise substrate and circuit die, described substrate comprises top top-level metallic at least, middle dielectric layer and following underlying metal, described underlying metal is ground, described top-level metallic comprises circuit die stickup district, described circuit die is pasted between district and the described circuit die and is bonded together by binder, the top, edge that described circuit die is pasted the district is provided with the first protruding solder mask, top-level metallic is pasted the district in described circuit die and is outside equipped with the substrate ground connection bonding region that is electrically connected with described circuit die stickup district, described substrate ground connection bonding region is outside equipped with second solder mask, circuit die bonding region on the described circuit die is connected with substrate ground connection bonding region by the earth key zygonema, described first solder mask is limited in substrate ground connection bonding region with in the interior zone with binder, only has circuit die to paste the district on the described substrate and connects underlying metal and ground connection by through hole.
The present invention has solder mask in the substrate top-level metallic upper surface design that connects between substrate ground connection bonding region and the circuit die stickup district, effectively stoped the circuit die binder in encapsulation process, to spill into substrate ground connection bonding region, reduced the distance between substrate circuit tube core stickup district and the substrate ground connection bonding region, thereby shortened the length of the bonding line of connecting circuit die bonding district and substrate ground connection bonding region, and saved near the substrate ground connection bonding region through hole, dwindle the package dimension of semiconductor device, reduced product cost.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is the sectional drawing of conventional semiconductor device leadless packaging structure;
Fig. 2 is the sectional drawing of leadless packaging structure of semiconductor device of the present invention;
Fig. 3 is the vertical view of leadless packaging structure of semiconductor device of the present invention.
Reference numeral is among the figure:
In the prior art: 101. substrates; 102. circuit die is pasted the district; 103. circuit die; 104. binder; 105a, 105b. substrate ground connection bonding region; 106a, 106b. earth key zygonema; 107a, 107b. circuit die bonding region; 110a, 110b. solder mask; The grounding through hole of 111a, 111b. substrate ground connection bonding region; 112. circuit die is pasted the grounding through hole in district; 113. underlying metal.
Among the present invention: 201. substrates; 202. circuit die is pasted the district; 203. circuit die; 204. binder; 205a, 205b. substrate ground connection bonding region; 206a, 206b. earth key zygonema; 207a, 207b. circuit die bonding region; 208a, 208b. overflow the zone that the postadhesion agent is piled up; 209a, 209b. first solder mask; 211a, 211b. second solder mask; 212. circuit die is pasted the grounding through hole in district; 213. underlying metal; 214a, 214b. circuit die are pasted the edge in district; 301. substrate; 302. circuit die is pasted the district; 303. circuit die; 305a, 305b. substrate ground connection bonding region; 306a, 306b. earth key zygonema; 307a, 307b. circuit die bonding region; 308a, 308b. overflow the zone that the postadhesion agent is piled up; 309a, 309b. first solder mask.
Embodiment
The invention discloses a kind of leadless packaging structure of semiconductor device, as shown in Figures 2 and 3, comprise substrate 201,301 and circuit die 203,303, described substrate 201,301 comprise top top-level metallic at least, middle dielectric layer and following underlying metal 213, described underlying metal 213 is ground, described top-level metallic comprises circuit die stickup district 202,302, described circuit die is pasted district 202,302 with described circuit die 203, bond together by binder 204 between 303, described circuit die is pasted the edge 214a in district, the 214b top is provided with the first solder mask 209a of projection, 209b, 309a, 309b, top-level metallic is pasted district 202 in described circuit die, 302 are outside equipped with and described circuit die stickup district 202, the 302 substrate ground connection bonding region 205a that are electrically connected, 205b, 305a, 305b, described substrate ground connection bonding region 205a, 205b, 305a, 305b is outside equipped with the second solder mask 211a, 211b, described circuit die 203, circuit die bonding region 207a on 303,207b, 307a, 307b is by earth key zygonema 206a, 206b, 306a, 306b and substrate ground connection bonding region 205a, 205b, 305a, 305b connects, the described first solder mask 209a, 209b, 209a, 209b is limited in substrate ground connection bonding region 205a with binder 204,205b, 305a, 305b is with in the interior zone, described substrate 201, circuit die is pasted district 202 on 301,302 pass through through hole 212 connects underlying metals 213 and ground connection.
Dielectric layer in the middle of the described substrate 201 can be a multi-layer compound structure.
The material of described substrate is a kind of in phenolic resins, epoxy resin FR4 or the pottery.
Described circuit die is pasted the district and is connected underlying metal by one or more through holes.
Described binder is silver slurry or other adhesives.
The main distinction of prior art is substrate ground connection bonding region 205a among embodiment among Fig. 2 of the present invention and Fig. 1,205b and circuit die are pasted the district is pasted in district 202 by circuit die in the substrate top-level metallic edge 214a, 214b is connected, the through hole 111a that can save the ground connection among Fig. 1 like this, 111b, the present invention simultaneously pastes the edge 214a in district in circuit die, and the 214b upper surface is provided with solder mask 209a, 209b.In encapsulation process, circuit die binder 204 is the tops of pasting district 202 with the form of liquid state attached to circuit die, be connected fully in order to make circuit die 203 and circuit die paste district's 202 foundation, to apply certain pressure to circuit die 203, will cause circuit die binder 204 to flow out circuit die like this and paste the zone in district 202 to substrate ground connection bonding region 205a, on the 205b, thereby cause substrate ground connection bonding region 205a, 205b can't use bonding line to connect.Traditional solution is by with substrate ground connection bonding region 205a, 205b pastes district 202 away from circuit die, to prevent that circuit die binder 204 is diffused into substrate ground connection bonding region 205a, on the 205b, bonding line 206a like this can extend, the length of 206b, because the performance para-linkage line length of power amplifier circuit tube core is relatively more responsive, lengthening connecting circuit die bonding district 207a, 207b and substrate ground connection bonding region 205a, the bonding line 206a between the 205b, the length of 206b can influence the equipment integral performance, simultaneously also can increase package dimension, increase equipment cost.The present invention is by pasting the edge 214a in district in circuit die, the design of 214b upper surface has solder mask 209a, 209b, can play and stop circuit die binder 204 to flow out the zone in circuit die stickup district 202 to substrate ground connection bonding region 205a, on the 205b, make it be stacked into 208a, the 208b zone, the thickness of solder mask and width can require to adjust according to actual design.Because substrate ground connection bonding region 205a, it is adjacent that 205b and circuit die are pasted district 202, thereby shorten connecting circuit die bonding district 207a, 207b and substrate ground connection bonding region 205a, the bonding line 206a between the 205b, the length of 206b, dwindle the size of encapsulation, reduce the cost of product.
In sum, the present invention has solder mask in the substrate top-level metallic upper surface design that connects between substrate ground connection bonding region and the circuit die stickup district, effectively stoped the circuit die binder in encapsulation process, to spill into substrate ground connection bonding region, reduced the distance between substrate circuit tube core stickup district and the substrate ground connection bonding region, thereby shortened the length of the bonding line of connecting circuit die bonding district and substrate ground connection bonding region, and saved near the substrate ground connection bonding region through hole, dwindle the package dimension of semiconductor device, reduced product cost.
Claims (6)
1. leadless packaging structure of semiconductor device, comprise substrate and circuit die, described substrate comprises top top-level metallic at least, middle dielectric layer and following underlying metal, described underlying metal is ground, described top-level metallic comprises circuit die stickup district, it is characterized in that, described circuit die is pasted between district and the described circuit die and is bonded together by binder, the top, edge that described circuit die is pasted the district is provided with the first protruding solder mask, top-level metallic is pasted the district in described circuit die and is outside equipped with the substrate ground connection bonding region that is electrically connected with described circuit die stickup district, described substrate ground connection bonding region is outside equipped with second solder mask, circuit die bonding region on the described circuit die is connected with substrate ground connection bonding region by the earth key zygonema, described first solder mask is limited in substrate ground connection bonding region with in the interior zone with binder, and circuit die is pasted to distinguish by through hole and connected underlying metal and ground connection on the described substrate.
2. leadless packaging structure of semiconductor device according to claim 1 is characterized in that, the dielectric layer in the middle of the described substrate is a multi-layer compound structure.
3. leadless packaging structure of semiconductor device according to claim 1 is characterized in that, the material of described substrate is a kind of in phenolic resins, epoxy resin FR4 or the pottery.
4. leadless packaging structure of semiconductor device according to claim 1 is characterized in that, described circuit die is pasted the district and connected underlying metal by a through hole.
5. leadless packaging structure of semiconductor device according to claim 1 is characterized in that, described circuit die is pasted the district and connected underlying metal by a plurality of through holes.
6. leadless packaging structure of semiconductor device according to claim 1 is characterized in that, described binder is the silver slurry.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910202074 CN101764120B (en) | 2009-12-31 | 2009-12-31 | leadless packaging structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910202074 CN101764120B (en) | 2009-12-31 | 2009-12-31 | leadless packaging structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101764120A CN101764120A (en) | 2010-06-30 |
| CN101764120B true CN101764120B (en) | 2011-12-21 |
Family
ID=42495192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910202074 Expired - Fee Related CN101764120B (en) | 2009-12-31 | 2009-12-31 | leadless packaging structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101764120B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN211555869U (en) * | 2019-12-13 | 2020-09-22 | 深圳市绎立锐光科技开发有限公司 | Ceramic substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433573A (en) * | 2000-03-30 | 2003-07-30 | Ats服务有限公司 | Leadless semiconductor product packaging apparatus having window lid and method for packaging |
| CN1525544A (en) * | 2003-02-24 | 2004-09-01 | 三星电机株式会社 | Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same |
| JP2005354114A (en) * | 2005-08-30 | 2005-12-22 | Ibiden Co Ltd | Electronic component mounting substrate and manufacturing method therefor |
| US7638863B2 (en) * | 2006-08-31 | 2009-12-29 | Semiconductor Components Industries, Llc | Semiconductor package and method therefor |
-
2009
- 2009-12-31 CN CN 200910202074 patent/CN101764120B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433573A (en) * | 2000-03-30 | 2003-07-30 | Ats服务有限公司 | Leadless semiconductor product packaging apparatus having window lid and method for packaging |
| CN1525544A (en) * | 2003-02-24 | 2004-09-01 | 三星电机株式会社 | Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same |
| JP2005354114A (en) * | 2005-08-30 | 2005-12-22 | Ibiden Co Ltd | Electronic component mounting substrate and manufacturing method therefor |
| US7638863B2 (en) * | 2006-08-31 | 2009-12-29 | Semiconductor Components Industries, Llc | Semiconductor package and method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101764120A (en) | 2010-06-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7799611B2 (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
| US7928551B2 (en) | Semiconductor device and method of manufacturing the same | |
| US7042398B2 (en) | Apparatus of antenna with heat slug and its fabricating process | |
| CN103400819B (en) | A kind of lead frame and its preparation method and application its encapsulating structure | |
| US20060071308A1 (en) | Apparatus of antenna with heat slug and its fabricating process | |
| CN204792778U (en) | Semiconductor substrate structure and semiconductor package | |
| JP2011014883A (en) | Method for manufacturing ceramic capacitor | |
| CN100418218C (en) | Semiconductor die package with reduced inductance and reduced die attach flow out | |
| CN108538803A (en) | Assembling fan-out package structure and production method after a kind of chip | |
| CN114530445A (en) | Chip packaging structure and packaging method | |
| CN216902947U (en) | Chip packaging structure | |
| US6617198B2 (en) | Semiconductor assembly without adhesive fillets | |
| CN101764120B (en) | leadless packaging structure of semiconductor device | |
| US10373930B2 (en) | Package structure and the method to fabricate thereof | |
| CN117833857B (en) | Filter packaging structure and manufacturing method thereof | |
| JP3508905B2 (en) | Wiring board and its manufacturing method | |
| US7982293B2 (en) | Multi-chip package including die paddle with steps | |
| DE10147375B4 (en) | Electronic component with a semiconductor chip and method for producing the same | |
| CN105244348A (en) | Package substrate and manufacturing method thereof | |
| KR100336778B1 (en) | Stacked chip size package and fabricating method thereof | |
| EP4270455A1 (en) | Semiconductor package and method for fabricating the same | |
| CN101770993A (en) | Leadless packaging structure of semiconductor device | |
| CN222690676U (en) | An ultra-thin single-layer circuit packaging structure | |
| KR100377267B1 (en) | Leadframe of die pad and method for manufacturing the same | |
| CN217216519U (en) | Multilayer electronic ceramic base |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111221 Termination date: 20131231 |