CN101752384B

CN101752384B - One-time programmable memory and manufacture and programming reading method

Info

Publication number: CN101752384B
Application number: CN200810240174XA
Authority: CN
Inventors: 朱一明; 苏如伟
Original assignee: GigaDevice Semiconductor Beijing Inc
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2008-12-18
Filing date: 2008-12-18
Publication date: 2012-06-13
Anticipated expiration: 2028-12-18
Also published as: CN101752384A

Abstract

The invention discloses a one-time programmable memory and a manufacture and programming reading method of a semitransistor structure. A semitransistor comprises a programmable capacitor formed by a polysilicon layer, a gate oxide layer, a lightly doped drain zone and an ion implantation zone, and a diode formed by the ion implantation zone and a heavily doped zone, wherein the programmable capacitor is connected with the diode in series, and the ion implantation zone is positioned on an adjacent insulating layer; and the polysilicon layer is connected with a word line, and the heavily doped zone is connected with a bit line. By utilizing the characteristics that the programmable capacitor forms an on resistance when being broken down and is still taken as an insulation capacitor when not being broken down, and the forward conducting and reverse-closing characteristic of the diode, the one-time programmable memory which has small memory cell area and high integration level, can further improve integration level with the development of process, is based on the existing logical process without adding a special process, and has high stability and reliability of data storage can be achieved.

Description

One-time programmable memory, manufacturing and programming reading method

Technical Field

The present invention relates generally to the field of semiconductor memory, and more particularly to one-time programmable memory, and methods of manufacturing and programming read.

Background

At present, the one-time programmable memory based on the logic process is mainly designed by adopting a dynamic random access memory structure, and data programming is carried out by utilizing the breakdown characteristic of a gate oxide layer of a transistor. Each unit of the one-time programmable memory comprises two transistors, wherein one transistor is a thick gate oxide layer transistor for input and output, and the gate oxide layer of the transistor is thick, so that the transistor has high voltage resistance; the other transistor is a thin gate oxide layer transistor used for a circuit inside a chip, and is easily broken down at a lower voltage because of a thin gate oxide layer. Since the thick gate oxide layer transistor has a gate characteristic and the thin gate oxide layer transistor has a breakdown-capable capacitance characteristic, this circuit structure is also referred to as a circuit structure including one gate transistor and one breakdown-capable capacitance (1T 1C). The one-time programmable memory with the structure needs a gate tube with higher voltage resistance due to higher programming voltage, but the area of each memory cell is larger due to the relatively larger area of the thick gate oxide layer transistor, so that the manufacturing cost is increased and the integration level is reduced.

Disclosure of Invention

In view of the above, an objective of the present invention is to provide an otp memory, a method for manufacturing the otp memory, and a method for reading the otp memory, so as to provide an otp memory with a small memory cell area, a high integration level, and a high data storage stability and reliability, which can further improve the integration level with the development of the process, without adding a special process based on the existing logic process.

According to an aspect of an embodiment of the present invention, there is provided a one-time programmable memory of a half transistor structure, the half transistor including:

the programmable capacitor is formed by a polycrystalline silicon layer, a gate oxide layer, a lightly doped drain region and an ion implantation region;

a diode formed by an ion implantation region and a heavily doped region;

the programmable capacitor is connected in series with the diode; wherein,

the ion implantation area is positioned on the insulating layer adjacent to the ion implantation area;

the polycrystalline silicon layer is connected with the word line, and the heavily doped region is connected with the bit line.

According to a feature of an embodiment of the present invention, the half transistor includes:

an isolation trench for isolating the ion implantation region; wherein the isolation trench extends deep into the insulating layer.

According to another feature of an embodiment of the present invention, the half transistor includes:

the doping concentration of the ion implantation area is smaller than that of the heavily doped area.

According to a further feature of an embodiment of the present invention, the ion implantation region includes an n-type or p-type ion implantation region.

According to another feature of an embodiment of the present invention, the heavily doped region comprises an n-type or a p-type heavily doped region.

According to another feature of an embodiment of the present invention, the lightly doped drain region is of an opposite doping type to the heavily doped region.

According to another feature of an embodiment of the present invention, the insulating layer includes a silicon oxide layer or a sapphire layer.

According to another aspect of the embodiments of the present invention, there is provided a method for manufacturing a one-time programmable memory with a half transistor structure, including the following steps:

generating a shallow isolation trench, wherein the isolation trench extends deep to the insulating layer on the substrate;

forming an ion implantation region on the insulating layer;

generating a gate oxide layer on the ion implantation region;

generating a polysilicon layer on the gate oxide layer;

forming a lightly doped drain region in the ion implantation region;

forming side walls on two sides of the gate oxide layer and the polycrystalline silicon layer;

forming a heavily doped region in the ion implantation region;

the polysilicon layer, the thin gate oxide layer, the lightly doped drain region and the ion implantation region form a programmable capacitor;

the ion implantation region and the heavily doped region form a diode;

the programmable capacitor and the diode are connected in series.

According to a feature of an embodiment of the present invention, the isolation trench is configured to isolate the ion implantation region; wherein the isolation trench extends deep into the insulating layer.

According to a feature of an embodiment of the present invention, a doping concentration of the ion implantation region is less than a doping concentration of the heavily doped region.

According to a feature of an embodiment of the present invention, the ion implantation region comprises an n-type or p-type ion implantation region.

According to a feature of an embodiment of the present invention, the heavily doped region comprises an n-type or a p-type heavily doped region.

According to a feature of an embodiment of the present invention, the lightly doped drain region and the heavily doped region are of opposite doping types.

According to a feature of an embodiment of the present invention, the insulating layer includes a silicon oxide layer or a sapphire layer.

According to another aspect of the embodiments of the present invention, there is provided a programming method of a one-time programmable memory of a half transistor structure, the half transistor including:

a diode formed by an ion implantation region and a heavily doped region;

the programmable capacitor is connected in series with the diode; wherein,

the polycrystalline silicon layer is connected with a word line, and the heavily doped region is connected with a bit line;

the programming method comprises the following steps:

a first voltage is applied to the word line, a second voltage is applied to the bit line, the programmable capacitor is broken down to form an on-resistance, and the diode is turned on.

According to a feature of an embodiment of the present invention,

the difference between the first voltage and the second voltage is a voltage value capable of breaking down the programmable capacitor.

According to another aspect of the embodiments of the present invention, there is provided a method for reading a one-time programmable memory of a half transistor structure, the half transistor including:

a diode formed by an ion implantation region and a heavily doped region;

the programmable capacitor is connected in series with the diode; wherein,

the reading method comprises the following steps:

applying a third voltage on the word line, applying a fourth voltage on the bit line, detecting whether the sense amplifier has current, if so, indicating that the programmable capacitor is broken down to form a resistor, the diode is conducted, and the output is logic '1'; otherwise, it indicates that the programmable capacitor is not broken down, and a logic "0" is output.

The one-time programmable memory, the manufacturing method and the programming reading method of the invention have the following beneficial effects:

1. because of adopting a half transistor structure, the one-time programmable memory unit only occupies the area of a half transistor, thereby reducing the area of the memory unit and improving the integration level;

2. because the memory is manufactured based on the existing logic process, the one-time programmable memory unit can be reduced in equal proportion with the process characteristic size, so that the integration level of the one-time programmable memory is further improved along with the development of the process;

3. the one-time programmable storage unit can be directly embedded into the SOC chip because no special process is needed to be added;

4. the programmable capacitor breakdown region is concentrated in the lightly doped drain region during programming, so that the ion injection region and the heavily doped region of the transistor are not influenced by breakdown voltage, and the reliability of the one-time programming memory is improved.

5. Because the insulating layer is adopted to replace an inverted trap of the traditional bulk silicon process, and the ion implantation area is effectively isolated through the insulating layer and the isolation groove, the stability and the reliability of data storage are improved, and the area of a storage unit is further reduced.

Drawings

FIG. 1 is a side view of a one-time programmable memory cell structure of a first embodiment of the present invention;

FIG. 2 is a partial top view of a one time programmable memory array with an n-type half transistor structure according to a first embodiment of the present invention;

FIG. 3 is a side view of a one-time programmable memory cell structure of a p-type half transistor structure according to a second embodiment of the present invention;

FIG. 4 is a partial top view of a one time programmable memory array with a p-type half transistor structure according to a second embodiment of the present invention;

FIG. 5 is a side view of a one-time programmable memory cell structure of a third embodiment of the present invention;

FIG. 6 is a partial top view of a one time programmable memory array with an n-type half transistor structure according to a third embodiment of the present invention;

FIG. 7 is a side view of a one-time programmable memory cell structure of a p-type half transistor structure according to a fourth embodiment of the present invention;

FIG. 8 is a partial top view of a one time programmable memory array with a p-type half transistor structure according to a fourth embodiment of the present invention;

FIG. 9 is a side view of a one-time programmable memory cell structure of a fifth embodiment of the present invention in an n-type half transistor structure;

FIG. 10 is a partial top view of a one time programmable memory array having an n-type half transistor structure according to a fifth embodiment of the present invention;

FIG. 11 is a side view of a one-time programmable memory cell structure of a sixth embodiment of the present invention in an n-type half transistor structure;

FIG. 12 is a side view of a one-time programmable memory cell structure of a p-type half transistor structure according to a seventh embodiment of the present invention;

FIG. 13 is a side view of a one-time programmable memory cell structure of an eighth embodiment of the present invention;

FIG. 14 is a side view of a one-time programmable memory cell structure of a p-type half transistor structure according to a ninth embodiment of the present invention;

FIG. 15A is a schematic diagram of an equivalent circuit of an OTP cell with an n-type half transistor structure in the first, third, fifth, sixth and eighth embodiments of the invention;

FIG. 15B is a schematic diagram of an equivalent circuit of a one-time programmable memory cell with an n-type half transistor structure after program breakdown in the first, third, fifth, sixth and eighth embodiments of the present invention;

FIG. 16 is a partial schematic diagram of an OTP memory array with n-type half-transistor structures according to the first, third, fifth, sixth and eighth embodiments of the invention;

FIG. 17A is a schematic circuit diagram of a one-time programmable memory cell with a p-type half transistor structure according to a second, fourth, seventh or ninth embodiment of the present invention;

FIG. 17B is a schematic diagram of an equivalent circuit of a one-time programmable memory cell with a p-type half transistor structure after program breakdown in the second, fourth, seventh and ninth embodiments of the present invention;

FIG. 18 is a partial schematic diagram of a OTP memory array with a p-type half transistor structure according to the second, fourth, seventh and ninth embodiments of the invention.

Detailed Description

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Example one

FIG. 1 is a side view of a one-time programmable memory cell structure of a first embodiment of the present invention, wherein FIG. 1 comprises: the structure comprises a polysilicon layer 101, a thin gate oxide layer 102, a p-type ion implantation region 103, an n-type heavily doped region 104, a shallow isolation trench 105, an n-type well 106 and a p-type substrate 107. The polycrystalline silicon layer 101 is connected with the thin gate oxide layer 102, the thin gate oxide layer 102 is connected with the p-type ion implantation region 103, the p-type ion implantation region 103 is positioned in the n-type well 106, and the heavily doped region 104 is positioned in the p-type ion implantation region 103; the polysilicon layer 101 is connected to Word lines (WL, Word Line), and the heavily n-doped region 104 is connected to Bit lines (BL, Bit Line). The thin gate oxide layer 102 is connected to a p-type ion implantation region 103. A predetermined distance is maintained between the thin gate oxide layer 102 and the heavily n-doped region 104.

The polysilicon layer 101, the thin gate oxide layer 102, and the p-type ion implantation region 103 form a programmable capacitor, and the p-type ion implantation region 103 and the n-type heavily doped region 104 form a diode. The shallow isolation trench 105 is used to isolate the p-type ion implantation region 103, wherein the depth of the shallow isolation trench 105 is greater than the depth of the p-type ion implantation region 103. The doping concentration of the p-type ion implantation region 103 is greater than that of the n-type well 106 but less than that of the n-type heavily doped region 104.

The following describes a method for manufacturing a one-time programmable memory cell with an n-type half transistor structure according to a first embodiment of the present invention, which includes the following steps:

step 101S, generating a shallow isolation groove according to a mask pattern;

step 102S, forming an n-well on a p-type substrate;

step 103S, forming a p-type ion implantation area in the n-well;

step 104S, generating a gate oxide layer on the p-type ion implantation area;

step 105S, generating a polysilicon layer on the gate oxide layer;

and step 106S, carrying out high-dose n-type ion implantation in the p-type ion implantation region to form an n-type heavily doped region.

In the above steps, the polysilicon layer, the gate oxide layer and the p-type ion implantation region form a programmable capacitor, and the p-type ion implantation region and the n-type heavily doped region form a diode. The depth of the shallow isolation trench is smaller than that of the n trap but larger than that of the p-type ion implantation area, so that the shallow isolation trench can well isolate the p-type ion implantation area, the distance between every two one-time programmable storage units is small, and the occupied area of the one-time programmable storage array is reduced.

Fig. 2 is a partial top view of an otp memory array with an n-type half transistor structure according to a first embodiment of the present invention, and in fig. 2, each otp memory cell includes a polysilicon layer 201, a metal layer 202, a contact hole 203, an n-type heavily doped region 204, and a p-type ion implantation region 205. The polysilicon layer 201 is connected to a word line WL1, and the metal layer 202 connected to a bit line BL1 is connected to the heavily n-doped region 204 through a contact hole 203.

Table 1 shows the programming and reading methods of the otp memory cell with n-type half transistor structure according to the first embodiment of the present invention:

		V_WL	V_BL	whether or not to program
					Programming	Select WL/select BL	V_pp	0V	Is that
	Select WL/unselect BL	V_pp	V_ppOr high resistance	Whether or not
						Unselected WL/selected BL	0V	0V	Whether or not
	Unselected WL/unselected BL	0V	V_ppOr high resistance	Whether or not
									Whether to detect sense amplifier current
Reading	Select WL/select BL	V_read	0V	Is that
						Select WL/unselect BL	V_read	V_dd	Whether or not
	Unselected WL/selected BL	0V	0V	Whether or not
						Unselected WL/unselected BL	0V	V_dd	Whether or not

TABLE 1

In Table 1, breakdown voltage V_ppMore than or equal to 2 times of working voltage V_ddRead voltage V_readLess than or equal to working voltage V_dd

And (3) programming process:

applying a breakdown voltage V on the word line WL_ppAnd applying 0V voltage to the bit line BL, namely applying 0V voltage to the n-type heavily doped region, so as to break down the programmable capacitor formed by the polysilicon layer, the thin gate oxide layer and the p-type ion implantation region, and make the diode formed by the p-type ion implantation region and the n-type heavily doped region be in forward conduction. Breakdown voltage V under 0.13um logic process_ppSelectable voltage value such as 6.5V, and working voltage V_ddSelectable voltage value, e.g. 1.3V, read voltage V_readThe voltage can be selected to be 0.8-1.3V.

And (3) reading:

applying a read voltage V to the word line WL_readApplying 0V voltage to a bit line BL (bit line), namely applying 0V voltage to an n-type heavily doped region, detecting whether the current exists in the sense amplifier, if so, indicating that a programmable capacitor formed by a polycrystalline silicon layer, a thin gate oxide layer and a p-type ion implantation region is broken down to form a resistor, and outputting logic '1' if a diode formed by the p-type ion implantation region and the n-type heavily doped region is in forward conduction; otherwise, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer and the p-type ion implantation region is not broken down, and logic '0' is output.

Example two

FIG. 3 is a side view of a one-time programmable memory cell structure of a p-type half transistor structure according to a second embodiment of the present invention, wherein FIG. 3 comprises: polysilicon layer 301, thin gate oxide layer 302, n-type ion implantation region 303, p-type heavily doped region 304, shallow isolation trench 305, p-type well 306 and p-type substrate 307. The polysilicon layer 301 is connected to the thin gate oxide layer 302, the thin gate oxide layer 302 is connected to the n-type ion implantation region 303, the n-type ion implantation region 303 is located in the p-type well 306, and the p-type heavily doped region 304 is located in the n-type ion implantation region 303. The polysilicon layer 301 is connected to the word lines WL and the heavily p-doped regions 304 are connected to the bit lines BL. The thin gate oxide layer 302 is connected to an n-type ion implantation region 303. A predetermined distance is maintained between the thin gate oxide layer 302 and the heavily p-doped region 304.

The polysilicon layer 301, the thin gate oxide layer 302 and the n-type ion implantation region 303 form a programmable capacitor, and the n-type ion implantation region 303 and the p-type heavily doped region 304 form a diode. The shallow isolation trench 305 is used to isolate the n-type ion implantation region 303, wherein the depth of the shallow isolation trench 305 is greater than the depth of the n-type ion implantation region 303. The doping concentration of the n-type ion implantation region 303 is greater than the doping concentration of the p-type well 306 but less than the doping concentration of the p-type heavily doped region 304.

The following describes a method for manufacturing a one-time programmable memory cell with a p-type half transistor structure according to a second embodiment of the present invention, which includes the following steps:

step 201S, generating a shallow isolation groove according to a mask pattern;

step 202S, forming a p-well on a p-type substrate;

step 203S, forming an n-type ion implantation area in the p-well;

step 204S, generating a gate oxide layer on the n-type ion implantation area;

step 205S, generating a polysilicon layer on the gate oxide layer;

in step 206S, a p-type heavily doped region is formed by performing a high dose of p-type ion implantation in the n-type ion implantation region.

In the above steps, the polysilicon layer, the gate oxide layer and the n-type ion implantation region form a programmable capacitor, and the n-type ion implantation region and the p-type heavily doped region form a diode. The depth of the shallow isolation groove is smaller than that of the p trap but larger than that of the n-type ion implantation area, so that the shallow isolation groove can well isolate the n-type ion implantation area, the distance between every two one-time programmable storage units is small, and the occupied area of the one-time programmable storage array is reduced.

Fig. 4 is a partial top view of an otp memory array with p-type half transistor structure according to a second embodiment of the present invention, and in fig. 4, each otp memory cell includes a polysilicon layer 401, a metal layer 402, a contact hole 403, a p-type heavily doped region 404, and an n-type ion implantation region 405. The polysilicon layer 401 is connected to the word line WL1, and the metal layer 402 connected to the bit line BL1 is connected to the p-type heavily doped region 404 through the contact hole 403.

Table 2 shows the programming and reading methods of the otp memory with p-type half transistor structure according to the second embodiment of the present invention:

		V_WL	V_BL	whether or not to program
					Programming	Select WL/select BL	0V	V_pp	Is that
	Select WL/unselect BL	0V	0V	Whether or not
						Unselected WL/selected BL	V_ppOr high resistance	V_pp	Whether or not
	Unselected WL/unselected BL	V_ppOr high resistance	0V	Whether or not
									Whether to detect sense amplifier current
Reading	Select WL/select BL	0V	V_read	Is that
						Select WL/unselect BL	0V	0V	Whether or not
	Unselected WL/selected BL	V_dd	V_read	Whether or not
						Unselected WL/unselected BL	V_dd	0V	Whether or not

TABLE 2

In Table 2, breakdown voltage V_ppMore than or equal to 2 times of working voltage V_ddRead voltage V_readLess than or equal to working voltage V_dd

And (3) programming process:

a voltage of 0V is applied to the word line WL, and a breakdown voltage V is applied to the bit line BL_ppI.e. applying a breakdown voltage V to the heavily p-doped region_ppSo as to break down the programmable capacitor formed by the polysilicon layer, the thin gate oxide layer and the n-type ion implantation region and make the diode formed by the p-type heavily doped region and the n-type ion implantation region be conducted in the forward direction.

And (3) reading:

a voltage of 0V is applied to the word line WL, and a read voltage V is applied to the bit line BL_readI.e. applying a read voltage V to the heavily p-doped region_readDetecting presence or absence of current in the sense amplifier, e.g.If yes, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer and the n-type ion implantation region is broken down to form a resistor, and the diode formed by the p-type heavily doped region and the n-type ion implantation region is conducted in the forward direction, so that the output is logic '1'; otherwise, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer and the n-type ion implantation region is not broken down, and logic '0' is output.

EXAMPLE III

FIG. 5 is a side view of a one-time programmable memory cell structure of a third embodiment of the present invention, wherein FIG. 5 comprises: the structure comprises a polycrystalline silicon layer 501, a thin gate oxide layer 502, a p-type lightly doped drain region 503, an n-type heavily doped region 504, a p-type ion implantation region 505, a shallow isolation trench 506, an n-type well 507 and a p-type substrate 508. The polysilicon layer 501 is connected with the thin gate oxide layer 502, the thin gate oxide layer 502 is adjacent to the p-type lightly doped drain region 503, the p-type lightly doped drain region 503 and the n-type heavily doped region 504 are located in the p-type ion implantation region 505, and the p-type ion implantation region 505 is located in the n-type well 507. The polysilicon layer 501 is connected to word lines (WL, WordLine), and the heavily n-doped region 504 is connected to Bit lines (BL, Bit Line). The thin gate oxide layer 502 is connected to a p-type ion implantation region 505.

The polysilicon layer 501, the thin gate oxide layer 502, the p-type lightly doped drain region 503 and the p-type ion implantation region 505 form a programmable capacitor, and the p-type ion implantation region 505 and the n-type heavily doped region 504 form a diode. The shallow isolation trench 505 is used to isolate the p-type ion implantation region 505, wherein the depth of the shallow isolation trench 505 is greater than the depth of the p-type ion implantation region 505. The doping concentration of the p-type ion implantation region 505 is greater than that of the n-type well 507 but less than that of the n-type heavily doped region 504.

The following describes a method for manufacturing a one-time programmable memory cell with an n-type half transistor structure according to a third embodiment of the present invention, which includes the following steps:

step 301S, generating a shallow isolation trench according to a mask pattern;

step 302S, forming an n-well on a p-type substrate;

step 303S, forming a p-type ion implantation area in the n-well;

step 304S, generating a gate oxide layer on the p-type ion implantation area;

step 305S, generating a polysilicon layer on the gate oxide layer;

step 306S, carrying out low-dose p-type ion implantation in the p-type ion implantation area to form a p-type lightly doped drain area;

step 307S, forming side walls (sidewalls) on two sides of the gate oxide layer and the polysilicon layer;

and step 308, performing high-dose n-type ion implantation in the p-type ion implantation region to form an n-type heavily doped region, wherein due to the blocking of the side wall, a part of the p-type lightly doped drain region is reserved in the region where the ion implantation region is contacted with the side wall, so that the p-type lightly doped drain region is formed.

In the above steps, the polysilicon layer, the gate oxide layer, the p-type lightly doped drain region and the p-type ion implantation region form a programmable capacitor, and the p-type ion implantation region and the n-type heavily doped region form a diode. The depth of the shallow isolation trench is smaller than that of the n trap but larger than that of the p-type ion implantation area, so that the shallow isolation trench can well isolate the p-type ion implantation area, the distance between every two one-time programmable storage units is small, and the occupied area of the one-time programmable storage array is reduced.

Fig. 6 is a partial top view of an otp memory array with an n-type half transistor structure according to a third embodiment of the present invention, in fig. 6, each otp memory cell includes a polysilicon layer 601, a metal layer 602, a contact hole 603, an n-type heavily doped region 604, a p-type lightly doped drain region 605, and a p-type ion implantation region 606. The polysilicon layer 601 is connected to the word line WL1, and the metal layer 602 connected to the bit line BL1 is connected to the heavily n-doped region 604 through the contact hole 603. A p-type ion implantation region 606, which is indicated by a dashed line frame, is partially covered with the polysilicon layer 601.

Table 3 shows the programming and reading methods of the otp memory with n-type half transistor structure according to the third embodiment of the present invention:

TABLE 3

In Table 3, breakdown voltage V_ppMore than or equal to 2 times of working voltage V_ddRead voltage V_readLess than or equal to working voltage V_ddAnd (3) programming process:

applying a voltage V to the word line WL_ppA voltage of 0V is applied to the bit line BL, i.e., a voltage of 0V is applied to the n-type heavily doped region. At this time, the p-type ion implantation region and the n-type heavily doped region form a diode structure, so that the p-type ion implantation region is clamped at the diode starting voltage V_th(ii) a In addition, an n-type inversion layer is formed in a portion connected to the thin gate oxide layer in the p-type ion implantation region, and the potential of the n-type inversion layer may be due to the voltage V on the word line WL_ppThe potential difference between the p-type lightly doped drain region and the thin gate oxide layer is larger than the potential difference between the p-type ion implantation region and the thin gate oxide layer, so that a programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer, the p-type lightly doped drain region and the p-type ion implantation region is broken down at the connecting part of the p-type lightly doped drain region and the thin gate oxide layer, and a diode formed by the p-type ion implantation region and the n-type heavily doped region is conducted in the forward direction.

And (3) reading:

applying a voltage V to the word line WL_readApplying 0V voltage to a bit line BL (bit line), namely applying 0V voltage to an n-type heavily doped region, detecting whether the current exists in the sense amplifier, if so, indicating that a programmable capacitor formed by a polycrystalline silicon layer, a thin gate oxide layer, a p-type lightly doped drain region and a p-type ion implantation region is broken down to form a resistor, and outputting logic '1' if a diode formed by the p-type ion implantation region and the n-type heavily doped region is conducted in the forward direction; otherwise, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer, the p-type lightly doped drain region and the p-type ion implantation region is not broken down, and logic 0 is output.

Example four

FIG. 7 is a side view of a one-time programmable memory cell structure of a p-type half transistor structure according to a fourth embodiment of the present invention, wherein FIG. 7 comprises: a polysilicon layer 701, a thin gate oxide layer 702, an n-type lightly doped drain region 703, a p-type heavily doped region 704, an n-type ion implantation region 705, a shallow isolation trench 706, a p-type well 707 and a p-type substrate 708. The polysilicon layer 701 is connected to the thin gate oxide layer 702, the thin gate oxide layer 702 is adjacent to the n-type lightly doped drain region 703, the n-type lightly doped drain region 703 and the p-type heavily doped region 704 are located in the n-type ion implantation region 705, and the n-type ion implantation region 705 is located in the p-type well 707. The polysilicon layer 701 is connected to the word line WL and the p-type heavily doped region 704 is connected to the bit line BL. Thin gate oxide layer 702 is connected to n-type ion implanted region 705.

The polysilicon layer 701, the thin gate oxide layer 702, the n-type lightly doped drain region 703 and the n-type ion implantation region 705 form a programmable capacitor, and the n-type ion implantation region 705 and the p-type heavily doped region 704 form a diode. The shallow isolation trench 705 is used to isolate the n-type ion implantation region 705, wherein the depth of the shallow isolation trench 705 is greater than the depth of the n-type ion implantation region 705. The doping concentration of the n-type ion implantation region 705 is greater than the doping concentration of the p-type well 706 but less than the doping concentration of the p-type heavily doped region 704.

step 401S, generating a shallow isolation trench according to a mask pattern;

step 402S, forming a p-well on a p-type substrate;

step 403S, forming an n-type ion implantation region in the p-well;

step 404S, generating a gate oxide layer on the n-type ion implantation region;

step 405S, generating a polysilicon layer on the gate oxide layer;

in step 406, a small dose of n-type ion implantation is performed in the n-type ion implantation region to form an n-type lightly doped drain region.

Step 407S, forming side walls (sidewalls) on two sides of the gate oxide layer and the polysilicon layer;

and step 408, performing high-dose p-type ion implantation in the n-type ion implantation region to form a p-type heavily doped region, and reserving part of the n-type lightly doped drain region in a region where the ion implantation region is contacted with the side wall due to the blocking of the side wall to form the n-type lightly doped drain region.

In the above steps, the polysilicon layer, the gate oxide layer, the n-type lightly doped drain region and the n-type ion implantation region form a programmable capacitor, and the n-type ion implantation region and the p-type heavily doped region form a diode. The depth of the shallow isolation groove is smaller than that of the p trap but larger than that of the n-type ion implantation area, so that the shallow isolation groove can well isolate the n-type ion implantation area, the distance between every two one-time programmable storage units is small, and the occupied area of the one-time programmable storage array is reduced.

Fig. 8 is a partial top view of an otp memory array with a p-type half transistor structure according to a fourth embodiment of the present invention, and in fig. 8, each otp memory cell includes a polysilicon layer 801, a metal layer 802, a contact hole 803, a p-type heavily doped region 804, an n-type lightly doped drain region 805, and an n-type ion implantation region 806. The polysilicon layer 801 is connected to the word line WL1, and the metal layer 802 connected to the bit line BL1 is connected to the p-type heavily doped region 804 through the contact hole 803. An n-type ion implantation region 806 indicated by a dashed line frame is partially covered with the polysilicon layer 801.

Table 4 shows the programming and reading methods of the otp memory with p-type half transistor structure according to the fourth embodiment of the present invention:

V_WL

V_BL

whether or not to program

Programming	Select WL/select BL	0V	V_pp	Is that
						Select WL/unselect BL	0V	0V	Whether or not
	Unselected WL/selected BL	V_ppOr high resistance	V_pp	Whether or not
						Unselected WL/unselected BL	V_ppOr high resistance	0V	Whether or not
				Whether to detect sense amplifier current
					Reading	Select WL/select BL	0V	V_read	Is that
	Select WL/unselect BL	0V	0V	Whether or not
						Unselected WL/selected BL	V_dd	V_read	Whether or not
	Unselected WL/unselected BL	V_dd	0V	Whether or not

TABLE 4

In Table 4, breakdown voltage V_ppMore than or equal to 2 times of working voltage V_ddRead voltage V_readLess than or equal to working voltage V_dd

And (3) programming process:

a voltage of 0V is applied to a word line WL, and a voltage V is applied to a bit line BL_ppI.e. applying a breakdown voltage V to the heavily p-doped region_pp. At this time, the n-type ion implantation region and the p-type heavily doped region form a diode structure, so that the n-type ion implantation region is clamped at V_pp-V_th(ii) a In addition, a p-type inversion layer is formed at the part connected with the thin gate oxide layer in the n-type ion implantation region, and the potential of the p-type inversion layer is correspondingly reduced due to the action of 0V voltage on the word line WL, so that the potential difference between the n-type lightly doped drain region and the thin gate oxide layer is larger than the potential difference between the n-type ion implantation region and the thin gate oxide layer, therefore, a programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer, the n-type lightly doped drain region and the n-type ion implantation region is broken down at the connecting part of the n-type lightly doped drain region and the thin gate oxide layer, and at the moment, a diode formed by the n-type ion implantation region and the p-type heavily doped region is in forward conduction.

And (3) reading:

a voltage 0V is applied to a word line WL, and a voltage V is applied to a bit line BL_readI.e. applying a read voltage V to the heavily p-doped region_readDetecting whether the current exists in the sensitive amplifier, if so, indicating that the polycrystalline silicon layer, the thin gate oxide layer, the n-type lightly doped drain region and the n-type ion implantation region are formedThe programmable capacitor is broken down to form a resistor, and the diode formed by the n-type ion injection region and the p-type heavily doped region is conducted in the forward direction, so that the output is logic '1'; otherwise, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer, the n-type lightly doped drain region and the n-type ion implantation region is not broken down, no current passes through the programmable capacitor, and logic '0' is output.

EXAMPLE five

Fig. 9 is a side view of a one-time programmable memory cell structure of a fifth embodiment of the present invention, wherein fig. 9 includes: the structure comprises a polycrystalline silicon layer 901, a thin gate oxide layer 902, a p-type lightly doped drain region 903, an n-type heavily doped region 904, a p-type ion implantation region 905, a shallow isolation trench 906, an n-type well 907 and a p-type substrate 908. The polysilicon layer 901 is connected with the thin gate oxide layer 902 and is connected with the region outside the p-type ion implantation region 905, the p-type lightly doped drain region 903 and the p-type ion implantation region 905 are positioned in the n-type well 907, the n-type heavily doped region 904 is positioned in the p-type ion implantation region 905, and the p-type lightly doped drain region 903 is adjacent to the p-type ion implantation region 905. The polysilicon layer 901 is connected to the word line WL and the heavily n-doped region 905 is connected to the bit line BL. A thin gate oxide layer 902 is adjacent to the p-type lightly doped drain region 903.

The polysilicon layer 901, the thin gate oxide layer 902, the p-type lightly doped drain region 903 and the p-type ion implantation region 905 form a programmable capacitor, and the p-type ion implantation region 905 and the n-type heavily doped region 905 form a diode. The shallow isolation trench 906 is used to isolate the p-type ion implanted region 905, wherein the depth of the shallow isolation trench 906 is greater than the depth of the p-type ion implanted region 905. The doping concentration of the p-type ion implantation region 905 is greater than the doping concentration of the n-type well 907 but less than the doping concentration of the n-type heavily doped region 905.

The following describes a method for manufacturing a one-time programmable memory cell with an n-type half transistor structure according to a fifth embodiment of the present invention, which includes the following steps:

step 501S, generating a shallow isolation groove according to a mask pattern;

step 502S of forming an n-well on a p-type substrate;

step 503S, depositing silicon dioxide to form a gate oxide layer;

step 504S, generating a polysilicon layer on the gate oxide layer;

step 505, performing low-dose p-type ion implantation in the n-well to form a p-type lightly doped drain region;

step 506S, forming side walls (sidewalls) on two sides of the gate oxide layer and the polysilicon layer;

in step 507S, n-type heavily doped region is formed by performing n-type ion implantation with large dose in the n-well.

And step 508S, forming a p-type ion implantation region in the n-well, wherein the p-type lightly doped drain region is located outside the p-type ion implantation region, and the n-type heavily doped region is located inside the p-type ion implantation region.

In the above steps, the polysilicon layer, the thin gate oxide layer, the p-type lightly doped drain region and the p-type ion implantation region form a programmable capacitor, and the p-type ion implantation region and the n-type heavily doped region form a diode. The depth of the shallow isolation trench is smaller than that of the n trap but larger than that of the p-type ion implantation area, so that the shallow isolation trench can well isolate the p-type ion implantation area, the distance between every two one-time programmable storage units is small, and the occupied area of the one-time programmable storage array is reduced.

In addition, in the third embodiment of the present invention, since the gate oxide layer does not cover the p-type ion implantation region and the p-type lightly doped drain region, silicon dioxide may be deposited first to form the gate oxide layer, and then the p-type ion implantation region and the p-type lightly doped drain region may be formed in the n-well.

Fig. 10 is a partial top view of an otp memory array with an n-type half transistor structure according to a fifth embodiment of the present invention, in which each otp memory cell in fig. 10 includes a polysilicon layer 1001, a metal layer 1002, a contact hole 1003, a p-type lightly doped drain region 1004, an n-type heavily doped region 1005, and a p-type ion implantation region 1006. The polysilicon layer 1001 is connected to the word line WL1, and the metal layer 1002 as the bit line BL1 is connected to the p-type heavily doped region 1004 through the contact hole 1003. A p-type ion implantation region 1006 is indicated by a dashed box.

Table 5 shows the programming and reading methods of the otp memory with n-type half transistor structure according to the fifth embodiment of the present invention:

TABLE 5

In Table 5, breakdown voltage V_ppMore than or equal to 2 times of working voltage V_ddRead voltage V_readLess than or equal to working voltage V_dd

And (3) programming process:

applying a voltage V to the word line WL_ppA voltage of 0V is applied to the bit line BL, that is, a voltage of 0V is applied to the n-type heavily doped region. At this time, the p-type ion implantation region and the n-type heavily doped region form a diode structure, so that the p-type ion implantation region is clamped at the diode starting voltage V_th(ii) a In addition, an n-type inversion layer is formed in a portion connected to the thin gate oxide layer in the p-type ion implantation region, and the potential of the n-type inversion layer may be due to the voltage V on the word line WL_ppThe potential difference between the p-type lightly doped drain region and the thin gate oxide layer is larger than the potential difference between the p-type ion implantation region and the thin gate oxide layer, so that a programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer, the p-type lightly doped drain region and the p-type ion implantation region is broken down at the connecting part of the p-type lightly doped drain region and the thin gate oxide layer, and at the moment, a diode formed by the p-type ion implantation region and the n-type heavily doped region is conducted in the forward direction.

And (3) reading:

applying a voltage V to the word line WL_readApplying 0V voltage on bit line BL, namely applying 0V voltage on n-type heavily doped region, detecting whether current exists in sense amplifier, if so, indicating that programmable capacitor formed by polysilicon layer, thin gate oxide layer, p-type lightly doped drain region and p-type ion implantation region is broken downForming a resistor, and outputting logic '1' if a diode formed by the p-type ion implantation area and the n-type heavily doped area is conducted in the forward direction; otherwise, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer, the p-type lightly doped drain region and the p-type ion implantation region is not broken down, and logic 0 is output.

EXAMPLE six

FIG. 11 is a side view of a one-time programmable memory cell structure of a sixth embodiment of the present invention, wherein FIG. 11 includes: a polysilicon layer 1101, a thin gate oxide layer 1102, a p-type ion implantation region 1103, an n-type heavily doped region 1104, a shallow isolation trench 1105, an insulating layer 1106 and a p-type substrate 1107. The polycrystalline silicon layer 1101 is connected below the thin gate oxide layer 1102, the thin gate oxide layer 1102 is connected below the p-type ion implantation region 1103, the p-type ion implantation region 1103 is positioned on the insulating layer 1106, and the heavily doped region 1104 is positioned in the p-type ion implantation region 1103; the polysilicon layer 1101 is connected to the word line WL and the heavily n-doped region 1104 is connected to the bit line BL. The thin gate oxide layer 1102 is connected to a p-type ion implantation region 1103. A predetermined distance is maintained between the thin gate oxide layer 1102 and the heavily n-doped region 1104.

The polysilicon layer 1101, the thin gate oxide layer 1102 and the p-type ion implantation region 1103 form a programmable capacitor, and the p-type ion implantation region 1103 and the n-type heavily doped region 1104 form a diode. The shallow isolation trench 1105 is directly connected to the insulating layer 1106, thereby reliably isolating the p-type ion implantation region 1103, wherein the doping concentration of the p-type ion implantation region 1103 is less than that of the n-type heavily doped region 1104. The insulating layer 1106 may be manufactured by a Silicon On Insulator (SOI) process or a Silicon On Sapphire (SOS) process, which is a dielectric material having a high dielectric constant such as Silicon dioxide, Sapphire, or the like. Since the insulating layer 1106 has good insulating properties, an inversion well does not need to be formed on the substrate 1107, thereby further reducing the area of the memory cell, and in addition, the insulating layer is used to replace the inversion well in the conventional bulk silicon process, thereby avoiding the disadvantages in the bulk silicon process performance, such as latch-up effect and the like. For the one-time programmable memory adopting the silicon-on-sapphire process to manufacture the insulating layer, the sapphire has strong stability and is not easily influenced by various severe external environments such as radiation, high temperature and high pressure, and the like, so the stability and the reliability of data storage of the one-time programmable memory are greatly improved.

The following describes a method for manufacturing a one-time programmable memory cell with an n-type half transistor structure according to a sixth embodiment of the present invention, which includes the following steps:

step 601S, generating a shallow isolation groove according to a mask pattern; wherein, the shallow isolation trench extends into the insulating layer;

step 602S, forming a p-type ion implantation region on the insulating layer;

step 603, generating a gate oxide layer on the p-type ion implantation region;

step 604S, generating a polysilicon layer on the gate oxide layer;

in step 605S, n-type ion implantation with large dose is performed in the p-type ion implantation region to form an n-type heavily doped region.

In the above steps, the polysilicon layer, the gate oxide layer and the p-type ion implantation region form a programmable capacitor, and the p-type ion implantation region and the n-type heavily doped region form a diode. The shallow isolation trench is directly connected to the insulating layer from top to bottom, so that the p-type ion implantation region is reliably isolated, the space between every one-time programmable memory unit is small, and the occupied area of the one-time programmable memory array is reduced.

The partial plan view of the sixth embodiment is the same as that of fig. 2.

Table 6 shows the programming and reading methods of the otp memory with n-type half transistor structure according to the sixth embodiment of the present invention:

TABLE 6

In Table 6, breakdown voltage V_ppMore than or equal to 2 times of working voltage V_ddRead voltage V_readLess than or equal to working voltage V_dd

And (3) programming process:

applying a breakdown voltage V on the word line WL_ppAnd applying 0V voltage to the bit line BL, namely applying 0V voltage to the n-type heavily doped region, so as to break down the programmable capacitor formed by the polysilicon layer, the thin gate oxide layer and the p-type ion implantation region, and make the diode formed by the p-type ion implantation region and the n-type heavily doped region be in forward conduction.

And (3) reading:

applying a read voltage V on the word line WL_readApplying 0V voltage to a bit line BL (bit line), namely applying 0V voltage to an n-type heavily doped region, detecting whether the current exists in the sense amplifier, if so, indicating that a programmable capacitor formed by a polycrystalline silicon layer, a thin gate oxide layer and a p-type ion implantation region is broken down to form a resistor, and outputting logic '1' if a diode formed by the p-type ion implantation region and the n-type heavily doped region is in forward conduction; otherwise, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer and the p-type ion implantation region is not broken down, and logic '0' is output.

EXAMPLE seven

FIG. 12 is a side view of a one-time programmable memory cell structure of a p-type half transistor structure according to a seventh embodiment of the present invention, wherein FIG. 12 comprises: polysilicon layer 1201, thin gate oxide layer 1202, n-type ion implantation region 1203, p-type heavily doped region 1204, shallow isolation trench 1205, insulating layer 1206 and p-type substrate 1207. The polysilicon layer 1201 is connected to the thin gate oxide layer 1202, the thin gate oxide layer 1202 is connected to the n-type ion implantation region 1203, the n-type ion implantation region 1203 is located on the insulating layer 1206, and the p-type heavily doped region 1204 is located in the n-type ion implantation region 1203. The polysilicon layer 1201 is connected to the word line WL and the p-type heavily doped region 1204 is connected to the bit line BL. The thin gate oxide layer 1202 is connected to an n-type ion implantation region 1203. A predetermined distance is maintained between the thin gate oxide layer 1202 and the p-type heavily doped region 1204.

The polysilicon layer 1201, the thin gate oxide layer 1202, and the n-type ion implantation region 1203 form a programmable capacitor, and the n-type ion implantation region 1203 and the p-type heavily doped region 1204 form a diode. The shallow isolation trench 1205 is directly connected to the insulating layer 1206, thereby reliably isolating the n-type ion implantation region 1203. The doping concentration of the n-type ion implantation region 1203 is less than that of the p-type heavily doped region 1204. The insulating layer 1206 can be fabricated by a silicon-on-insulator process or a silicon-on-sapphire process, using a dielectric material with a high dielectric constant, such as silicon dioxide, sapphire, or the like. Since the insulating layer 1206 has good insulating properties, it is not necessary to fabricate an inversion well on the substrate 1207, thereby further reducing the area of the memory cell. For the one-time programmable memory adopting the silicon-on-sapphire process to manufacture the insulating layer, the sapphire has strong stability and is not easily influenced by various severe external environments such as radiation, high temperature and high pressure, and the like, so the stability and the reliability of data storage of the one-time programmable memory are greatly improved.

step 701S, generating a shallow isolation trench according to a mask pattern; wherein, the shallow isolation trench extends into the insulating layer;

step 702S, forming an n-type ion implantation region on the insulating layer;

step 703S of generating a gate oxide layer on the n-type ion implantation region;

step 704S, generating a polysilicon layer on the gate oxide layer;

in step 705S, a p-type heavily doped region is formed by performing a high dose of p-type ion implantation in the n-type ion implantation region.

In the above steps, the polysilicon layer, the gate oxide layer and the n-type ion implantation region form a programmable capacitor, and the n-type ion implantation region and the p-type heavily doped region form a diode. The shallow isolation trench is directly connected to the insulating layer from top to bottom, so that the n-type ion implantation region is reliably isolated, the space between every one-time programmable memory unit is small, and the occupied area of the one-time programmable memory array is reduced.

The partial top view of the seventh embodiment is the same as that of fig. 4.

Table 7 shows the programming and reading methods of the otp memory with p-type half transistor structure according to the second embodiment of the present invention:

TABLE 7

In Table 7, breakdown voltage V_ppOperating voltage V of not less than 2_ddRead voltage V_readLess than or equal to working voltage V_dd

And (3) programming process:

And (3) reading:

a voltage 0V is applied to a word line WL, and a read voltage V is applied to a bit line BL_readI.e. applying a read voltage V to the heavily p-doped region_readDetecting whether the current exists in the sensitive amplifier, if so, indicating that a programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer and the n-type ion implantation region is broken down to form a resistor, and outputting logic '1' if a diode formed by the p-type heavily doped region and the n-type ion implantation region is conducted in the forward direction; otherwise, it represents polysilicon layer, thin gate oxide layer, n-type ionsThe programmable capacitor formed by the injection region is not broken down and outputs a logic '0'.

Example eight

Fig. 13 is a side view of a otp memory cell with an n-type half transistor structure according to an eighth embodiment of the present invention, where fig. 13 includes: the structure comprises a polysilicon layer 1301, a thin gate oxide layer 1302, a p-type lightly doped drain region 1303, an n-type heavily doped region 1304, a p-type ion implantation region 1305, a shallow isolation trench 1306, an insulating layer 1307 and a p-type substrate 1308. The polysilicon layer 1301 is connected to the thin gate oxide layer 1302, the thin gate oxide layer 1302 is adjacent to the p-type lightly doped drain region 1303, the p-type lightly doped drain region 1303 and the n-type heavily doped region 1304 are located in the p-type ion implantation region 1305, and the p-type ion implantation region 1305 is located on the insulating layer 1307. The polysilicon layer 1301 is connected to the word line WL and the heavily n-doped region 1304 is connected to the bit line BL. A thin gate oxide layer 1302 underlies the p-type ion implanted region 1305.

The polysilicon layer 1301, the thin gate oxide layer 1302, the p-type lightly doped drain region 1303 and the p-type ion implantation region 1305 form a programmable capacitor, and the p-type ion implantation region 1305 and the n-type heavily doped region 1304 form a diode. The shallow isolation trench 1306 is directly connected to the insulating layer 1307, thereby reliably isolating the p-type ion implantation region 1305, wherein the doping concentration of the p-type ion implantation region 1305 is less than that of the n-type heavily doped region 1304. The insulating layer 1307 may be manufactured by a Silicon On Insulator (SOI) process or a Silicon On Sapphire (SOS) process, which is a dielectric material having a high dielectric constant such as Silicon dioxide, Sapphire, or the like. Because the insulating layer 1307 has good insulating property, an inversion well does not need to be manufactured on the substrate 1308, thereby further reducing the area of the memory cell, and in addition, the insulating layer is adopted to replace the inversion well of the traditional bulk silicon process, thereby avoiding the disadvantages of the bulk silicon process performance, such as latch-up effect and the like. For the one-time programmable memory adopting the silicon-on-sapphire process to manufacture the insulating layer, the sapphire has strong stability and is not easily influenced by various severe external environments such as radiation, high temperature and high pressure, and the like, so the stability and the reliability of data storage of the one-time programmable memory are greatly improved.

step 801S, generating a shallow isolation groove according to a mask pattern; wherein, the shallow isolation trench extends into the insulating layer;

step 802S, forming a p-type ion implantation region on the insulating layer;

step 803S, generating a gate oxide layer on the p-type ion implantation region;

step 804, generating a polysilicon layer on the gate oxide layer;

step 805S, performing low-dose p-type ion implantation in the p-type ion implantation region to form a p-type lightly doped drain region;

step 806S, forming side walls (sidewalls) on two sides of the gate oxide layer and the polysilicon layer;

in step 807S, a large amount of n-type ions are implanted into the p-type ion implantation region to form an n-type heavily doped region, and due to the blocking of the sidewall, a part of the p-type lightly doped drain region is reserved in the region where the ion implantation region and the sidewall are in contact, so as to form a p-type lightly doped drain region.

In the above steps, the polysilicon layer, the gate oxide layer, the p-type lightly doped drain region and the p-type ion implantation region form a programmable capacitor, and the p-type ion implantation region and the n-type heavily doped region form a diode. The shallow isolation trench is directly connected to the insulating layer from top to bottom, so that the p-type ion implantation region is reliably isolated, the space between every one-time programmable memory unit is small, and the occupied area of the one-time programmable memory array is reduced.

The partial plan view of the eighth embodiment is the same as that of fig. 6.

Table 8 shows the programming and reading methods of the otp memory with n-type half transistor structure according to the first embodiment of the present invention:

V_WL

V_BL

whether or not to program

Programming	Select WL/select BL	V_pp	0V	Is that
						Select WL/unselect BL	V_pp	V_ppOr high resistance	Whether or not
	Unselected WL/selected BL	0V	0V	Whether or not
						Unselected WL/unselected BL	0V	V_ppOr high resistance	Whether or not
				Whether to detect sense amplifier current
					Reading	Select WL/select BL	V_read	0V	Is that
	Select WL/unselect BL	V_read	V_dd	Whether or not
						Unselected WL/selected BL	0V	0V	Whether or not
	Unselected WL/unselected BL	0V	V_dd	Whether or not

TABLE 8

In Table 8, breakdown Voltage V_ppMore than or equal to 2 times of working voltage V_ddRead voltage V_readLess than or equal to working voltage V_dd

And (3) programming process:

And (3) reading:

Example nine

FIG. 14 is a side view of a one-time programmable memory cell structure of a p-type half transistor structure according to a ninth embodiment of the present invention, wherein FIG. 14 includes: polysilicon layer 1401, thin gate oxide layer 1402, n-type lightly doped drain region 1403, p-type heavily doped region 1404, n-type ion implantation region 1405, shallow isolation trench 1406, insulating layer 1407, and p-type substrate 1408. The polysilicon layer 1401 is connected to the thin gate oxide layer 1402, the thin gate oxide layer 1402 is adjacent to the n-type lightly doped drain region 1403, the n-type lightly doped drain region 1403 and the p-type heavily doped region 1404 are located in the n-type ion implantation region 1405, and the n-type ion implantation region 1405 is located on the insulating layer 1407. The polysilicon layer 1401 is connected to the word lines WL and the heavily p-doped regions 1404 are connected to the bit lines BL. A thin gate oxide layer 1402 underlies the n-type ion implanted region 1405.

The polysilicon layer 1401, the thin gate oxide layer 1402, the n-type lightly doped drain region 1403, and the n-type ion implantation region 1405 form a programmable capacitor, and the n-type ion implantation region 1405 and the p-type heavily doped region 1404 form a diode. The shallow isolation trench 1406 is directly connected to the insulating layer 1407 to reliably isolate the n-type ion implantation region 1405. The doping concentration of the n-type ion implantation region 1405 is less than the doping concentration of the p-type heavily doped region 1404. The insulating layer 1407 may be manufactured by a silicon-on-insulator process or a silicon-on-sapphire process, and the insulating layer is manufactured using a dielectric material having a high dielectric constant such as silicon dioxide, sapphire, or the like. Since the insulating layer 1407 has good insulating properties, it is not necessary to fabricate an inversion well on the substrate 1408, thereby further reducing the area of the memory cell, and in addition, the insulating layer is used to replace the inversion well in the conventional bulk silicon process, thereby avoiding the disadvantages in the bulk silicon process performance, such as latch-up effect. For the one-time programmable memory adopting the silicon-on-sapphire process to manufacture the insulating layer, the sapphire has strong stability and is not easily influenced by various severe external environments such as radiation, high temperature and high pressure, and the like, so the stability and the reliability of data storage of the one-time programmable memory are greatly improved.

step 901S, generating a shallow isolation trench according to the mask pattern; wherein, the shallow isolation trench extends into the insulating layer;

step 902S, forming an n-type ion implantation region on the insulating layer;

step 903S, generating a gate oxide layer on the n-type ion implantation area;

step 904S, generating a polysilicon layer on the gate oxide layer;

step 905S, an n-type lightly doped drain region is formed by implanting n-type ions with a small dose into the n-type ion implantation region.

Step 906S, forming side walls (sidewalls) on two sides of the gate oxide layer and the polysilicon layer;

and step 907S, performing high-dose p-type ion implantation in the n-type ion implantation area to form a p-type heavily doped area, and reserving part of the n-type lightly doped drain area in an area where the ion implantation area is contacted with the side wall due to the blocking of the side wall to form the n-type lightly doped drain area.

In the above steps, the polysilicon layer, the gate oxide layer, the n-type lightly doped drain region and the n-type ion implantation region form a programmable capacitor, and the n-type ion implantation region and the p-type heavily doped region form a diode. The shallow isolation trench is directly connected to the insulating layer from top to bottom, so that the n-type ion implantation region is reliably isolated, the space between every one-time programmable memory unit is small, and the occupied area of the one-time programmable memory array is reduced.

The partial plan view of the ninth embodiment is the same as that of fig. 8.

Table 9 shows the programming and reading methods of the otp memory with p-type half transistor structure according to the ninth embodiment of the present invention:

TABLE 9

In Table 9, breakdown Voltage V_ppMore than or equal to 2 times of working voltage V_ddRead voltage V_readLess than or equal to working voltage V_dd

And (3) programming process:

And (3) reading:

a voltage 0V is applied to a word line WL, and a voltage V is applied to a bit line BL_readI.e. applying a read voltage V to the heavily p-doped region_readDetecting whether the current is present in the sense amplifier, if soIf yes, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer, the n-type lightly doped drain region and the n-type ion implantation region is broken down to form a resistor, so that a diode formed by the n-type ion implantation region and the p-type heavily doped region is conducted in the forward direction, and the output is logic 1; otherwise, the programmable capacitor formed by the polycrystalline silicon layer, the thin gate oxide layer, the n-type lightly doped drain region and the n-type ion implantation region is not broken down, and logic 0 is output.

Fig. 15A is an equivalent circuit schematic diagram of an otp memory with an n-type half transistor structure according to the first, third, fifth, sixth, and eighth embodiments of the invention, where fig. 15 includes a diode 1501 and a capacitor 1502 connected in series, where the diode 1501 is connected to a bit line BL, and the capacitor 1502 is connected to a word line WL.

Fig. 15B is an equivalent circuit schematic diagram of the otp memory cell with n-type half transistor structure according to the first, third, fifth, sixth and eighth embodiments of the present invention after program breakdown, which includes a diode 1501 and a resistor 1503 connected in series, wherein the resistor 1503 is formed after the capacitor 1502 in fig. 15A is broken down by the program voltage. The current I flows in the direction of the word line WL to the bit line BL.

Fig. 16 is a partial schematic view of an otp memory array with n-type half transistor structure in the first, third, fifth, sixth and eighth embodiments of the invention, where fig. 16 includes a plurality of otp memory cells with n-type half transistor structure, a word line WL1, a word line WL2, a word line WL3, a bit line BL1, a bit line BL2 and a bit line BL3, and each otp memory cell is connected to one word line and one bit line. The one-time programmable memory cell connected to the word line WL2 and the bit line BL2 at the center of the figure has been programmed to break down, and therefore is represented by an equivalent circuit of a resistor-series diode.

Fig. 17A is a schematic circuit diagram of an otp memory with p-type half transistor structure according to the second, fourth, seventh and ninth embodiments of the invention, and fig. 17A includes a diode 1701 and a capacitor 1702 connected in series, where the diode 1701 is connected to the bit line BL and the capacitor 1702 is connected to the word line WL.

Fig. 17B is an equivalent circuit schematic diagram of a one-time programmable memory cell with a p-type half transistor structure according to the second, fourth, seventh, and ninth embodiments of the present invention after program breakdown, in which fig. 17B includes a diode 1701 and a resistor 1703 connected in series, and in which the resistor 1703 is formed after the capacitor 702 in fig. 17A is broken down by a program voltage. The current I flows in the direction from the bit line BL to the word line WL.

Fig. 18 is a partial schematic view of an otp memory array with p-type half transistor structure in the second, fourth, seventh and ninth embodiments of the invention, where fig. 18 includes a plurality of otp memory cells with p-type half transistor structures, a word line WL1, a word line WL2, a word line WL3, a bit line BL1, a bit line BL2 and a bit line BL3, and each otp memory cell is connected to one word line and one bit line. The one-time programmable memory cell connected to the word line WL2 and the bit line BL2 at the center of the figure has been programmed to break down, and therefore is represented by an equivalent circuit of a resistor-series diode.

In the first, second, sixth and seventh embodiments of the present invention, the programmable capacitor is formed by the polysilicon layer, the thin gate oxide layer and the ion implantation region, and the diode connected in series with the programmable capacitor is formed by the ion implantation region and the heavily doped region; in the third, fourth, fifth, eighth and ninth embodiments, the programmable capacitor is formed by the polysilicon layer, the thin gate oxide layer, the lightly doped drain region and the ion implantation region, the diode connected in series with the programmable capacitor is formed by the ion implantation region and the heavily doped region, and by utilizing the characteristics that the programmable capacitor forms an on-resistance when being broken down and is still an insulating capacitor when not being broken down and the forward on and reverse off characteristics of the diode, the area of the memory cell only occupies half of the area of the transistor, the integration density is high, the memory cell can be reduced in the same proportion along with the reduction of the process characteristic size, a special process is not required to be added, and the one-time programmable nonvolatile memory with high reliability is realized.

In addition, in the sixth, seventh, eighth and ninth embodiments of the present invention, the insulating layer in the silicon-on-insulator or silicon-on-sapphire process is used to replace the inverted well in the traditional bulk silicon process, so as to greatly improve the stability and reliability of the data storage of the otp nonvolatile memory.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention, and any modifications, alterations, combinations, equivalents, improvements and the like made to the embodiments of the present invention within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A one time programmable memory of a half transistor structure, the half transistor comprising:

a diode formed by the ion implantation region and the heavily doped region;

the programmable capacitor is connected in series with the diode; wherein,

2. The one time programmable memory of claim 1, wherein the half transistor comprises:

3. The one time programmable memory of claim 1, wherein the half transistor comprises:

4. The one time programmable memory of claim 1,

the ion implantation region comprises an n-type or p-type ion implantation region.

5. The one time programmable memory of claim 1,

the heavily doped region comprises an n-type or p-type heavily doped region.

6. The one time programmable memory of claim 1,

the lightly doped drain region and the heavily doped region are opposite in doping type.

7. The one time programmable memory of claim 1,

the insulating layer includes a silicon oxide layer or a sapphire layer.

8. A manufacturing method of a one-time programmable memory with a half transistor structure is characterized by comprising the following steps:

generating a shallow isolation trench;

forming an ion implantation region on the insulating layer;

generating a gate oxide layer on the ion implantation region;

generating a polysilicon layer on the gate oxide layer;

forming a lightly doped drain region in the ion implantation region;

forming a heavily doped region in the ion implantation region;

the polycrystalline silicon layer, the gate oxide layer, the lightly doped drain region and the ion implantation region form a programmable capacitor;

the ion implantation region and the heavily doped region form a diode;

the programmable capacitor and the diode are connected in series.

9. The manufacturing method according to claim 8,

the isolation trench is used for isolating the ion implantation area; wherein the isolation trench extends deep into the insulating layer.

10. The manufacturing method according to claim 8,

11. The manufacturing method according to claim 8,

12. The manufacturing method according to claim 8,

the heavily doped region comprises an n-type or p-type heavily doped region.

13. The manufacturing method according to claim 8,

14. The manufacturing method according to claim 8,

the insulating layer includes a silicon oxide layer or a sapphire layer.

15. A programming method of one-time programmable memory with a half transistor structure is characterized in that,

the half transistor includes:

a diode formed by an ion implantation region and a heavily doped region;

the programmable capacitor is connected in series with the diode; wherein,

the programming method comprises the following steps:

and applying a first voltage to the word line, applying a second voltage to the bit line, breaking down the programmable capacitor to form an on-resistance, and turning on the diode.

16. The programming method according to claim 14,

17. A method for reading a one-time programmable memory with a half transistor structure,

the half transistor includes:

a diode formed by the ion implantation region and the heavily doped region;

the programmable capacitor is connected in series with the diode; wherein,

the reading method comprises the following steps: