CN101594363A - Full-speed wired remote-transmission module - Google Patents

Abstract

The invention discloses a kind of full-speed wired remote-transmission module, it comprises SOPC and SHDSL processor two major parts, SOPC is responsible for finishing mutual with the SHDSL processor by the soft nuclear of CPU NIOS II, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime, and provide three kinds of business datum interfaces and one road management information interface for the user; SHDSL digital front-end be responsible for finishing based on the ITU tissue G.991.2, G.994.1, the G.997.1 TC-PAM modulation of agreement regulation expansion, realize the twisted-pair feeder transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading.Useful technique effect of the present invention is: not only solved traditional remote-transmission module and need adopt SHDSL and two kinds of existing deficiencies of technology of VDSL and circuit to disturb and the difficult problems such as interlocking of finishing principal and subordinate two ends clock of traditional remote-transmission module, and aspect transmission range, with identical speed rates the time, its transmission range is compared traditional remote-transmission module also lifting largely, makes this module just can reach the transmission distance of 1～10km by light-duty insulate line.

Description

Full-speed wired remote-transmission module

Technical field

Present technique relates to the SHDSL technical standard, relates in particular to a kind of full-speed wired remote-transmission module.

Background technology

In some specific application, the DSL technology not only solves professional access, and simultaneously also for relay transmission provides means, this just needs to select to provide the DSL technology of bi-directional symmetrical rate of loading.In the following speed of 4Mbit/s, the SHDSL technology is a best choice.When the user proposed the demand of the following speed of the above 8Mbit/s of 4Mbit/s, because the high-transmission rate of loading that G.991.2 ITU demarcates in agreement and the appendix thereof is 5696kbit/s, most of solutions adopted the VDSL technology.VDSL adopts the MCM-DMT of multi-carrier modulation technology or the SCM-QAM of single-carrier modulated technology, and SHDSL adopts the pulse amplitude modulation technology (TC-PAM) of grid coding.Comparatively speaking, the SHDSL technology can realize farther transmission range, and the VDSL technology then can reach higher transmission rate.Traditional remote-transmission module adopts SHDSL and two kinds of technology of VDSL to realize the twisted-pair feeder transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading, but adopt these two kinds of Technology Needs, two covers to realize circuit, thereby aspect integrated level, power consumption and the cost of system, exist not enough.

The present invention adopts the SHDSL standard to realize the transmission of full rate twisted-pair feeder, has both solved the deficiency of above-mentioned traditional remote-transmission module, and aspect transmission range, during with identical speed rates, comparing traditional remote-transmission module also has lifting largely.

Summary of the invention

Full-speed wired remote-transmission module disclosed in this invention, mainly constitute by SOPC (programmable system on chip) and SHDSL processor two large divisions, SOPC is responsible for finishing mutual with the SHDSL processor by the soft nuclear of CPU NIOS II, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime, and provide three kinds of professional number a tree name interfaces and one road management information interface for the user; The SHDSL processor digital front-end be responsible for finishing based on the ITU tissue G.991.2, G.994.1, the G.997.1 TC-PAM modulation of agreement regulation expansion, realize the twisted-pair feeder transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading.

The SOPC central processing unit mainly by the soft nuclear of CPU NIOS II, UART (asynchronous serial data) transmitting-receiving, ethernet mac, AAL5 is adaptive, AAL2 is adaptive and hardware program such as interface processing is formed: the soft nuclear of CPU NIOS II be responsible for finishing with the SHDSL processor alternately, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime; UART finishes the transmitting-receiving of asynchronous serial data; Ethernet mac is finished the MAC layer function that Ethernet inserts; It is adaptive that AAL5 finishes the cell of Ethernet data; It is adaptive that AAL2 finishes the cell of voice bitstream.By the processing of these programs, for the user provides three kinds of data-interfaces: transparent bitstream interface, Ethernet interface, cable voice port.Bitstream interface directly realizes transparent transmission by the TDM interface of SHDSL processor; Ethernet interface both can directly be realized inserting by the MII interface of SHDSL processor, also can be adapted to cell and realize inserting by the UTOPIA interface of SHDSL processor; Cable voice port is realized inserting by the UTOPIA interface of SHDSL processor through being adapted to ATM cell after the digital coding.Management information is transmitted by DSP embedded processing passage EOC.

SHDSL processor part mainly is made up of unit such as embedded microprocessor, data-interface, clock unit, digital front-end, AFE (analog front end), circuit drivings: embedded microprocessor is responsible for finishing the parsing to cpu command, the processing of EOC message, to the configuration of other processing unit, and cooperate with the NIOS processor finish that circuit is shaken hands, process that pretrigger, nuclear start to synchronous data mode.Data interface unit is in charge of data transmission rate, frame synchronizing signal source, data loopback mode, sampled level and sampling clock edge, the read-write time-delay of slip buffering area etc.DSL becomes/separates frame unit according to ITU agreement regulation G.991.2, with data and EOC message maps to the SHDSL frame, otherwise decomposite data flow and EOC message from the SHDSL frame.Digital front-end has comprised Trellis encoder, Viterbi decoder, scrambler, precoder, frequency spectrum shaping device, Echo Cancellation algorithm unit, near-end cross algorithm unit etc., and digital front-end is responsible for finishing the encoding and decoding and the modulation of SHDSL frame.Clock unit is controlled the source of reference symbol clock according to the configuration of embedded microprocessor, and to data interface unit, framing separate frame unit, data processing unit provides the clock source; In the application of this module, the symbol send-receive clock of CO end and cpe end all is synchronized with on the local crystal oscillator clock of CO end, but the clock that finally is sent to data-interface is locked in the time receiving clock of remote data interface, and its phase demodulation information source is in dynamic filling bit information.AFE (analog front end) is finished automatic gain control, filter, D and D/A converter, circuit driving, synthesizer.By these functional modules, digital modulation signals is by the analog signal that converts to of digital to analog converter highly linear, and the circuit driver module through having strong driving force and low distortion characteristic is delivered on the DSL twisted-pair feeder by synthesizer at last again.At receiving terminal, analog input converts digital signal through behind the automatic gain controller to by analog to digital converter.

In order to realize full-speed wired remote-transmission, the present invention adopt based on the ITU tissue G.991.2, G.994.1, the TC-PAM modulation system of agreement regulation expansion G.997.1, modulation level is expanded to 64TC-PAM: 5 Bit datas of each information symbol carrying this moment; Simultaneously according to ITU-T G.991.2 in the agreement to the regulation of technical parameters such as handshake method, clock module, circuit gain, power spectral density, set up the G.991.2 transmission of the 8192kbit/s speed of protocol extension.The bracelet that wherein is in one's hands joint utilizes the expanding element in the performance inventory that defines in the agreement G.994.1, finishes the mutual of data such as transmission rate that the principal and subordinate holds setting, each information symbol carrying bit number.

Be example below with the sending direction, flow chart of data processing to this module is further described, the data type that data processing partly need be handled comprises management information data and business information data, wherein the business information data have bitstream data, Ethernet data and voice-data signal: management information inserts by the UART interface, arrive the SHDSL processor through cpu bus, be sent to the DSL framer then, management information is embedded into EOC passage in the DSL frame as EOC message; When business is the bit stream form, directly be linked into the serial data interface of SHDSL processor, in the DSL framer, according to the clock of bit stream with data allocations in each time slot of DSL frame; Ethernet data is adapted to the AAL5 cell again through ethernet mac layer among the FPGA, delivers to the SHDSL processor by the UTOPIA interface then, the SHDSL processor with the load distribution in the cell in the DSL frame slot; And voice data is adapted to the AAL2 cell after encoding, and delivers to the DSL framer by the UTOPIA interface, and load is carried by the DSL time slot.

In the SHDSL processor, the DSL frame makes its randomization through scrambler, delivers to then and finishes the TC-PAM modulation in the TCM encoder, then comes balanced signal loss in the line by precoder, process frequency spectrum shaping device is finished the reformation shape to the signal frequency parameter then, delivers on the circuit at last.

The data processing of receive direction is the inverse operation of sending direction.

The software control flow process of this module is, software section, according to ITU G.991.2 to the regulation of SHDSL setting up procedure, the initialization of SHDSL processor experience, pretrigger, start a series of states, reach the stable data pattern at last: at first, NIOSII is as master controller, the firmware downloads and the start-up course of control SHDSL processor, by the CRC check sign indicating number in the firmware, detect the integrality of download firmware, after DSP started smoothly, master controller sent order notice DSP and enters init state, send configuration parameter with the form of message then to DSP, the type that wherein mainly comprises data-interface, characteristic, clock mode, the DSL framing is separated frame parameter, the parameter of modulating unit, selection of principal and subordinate's end or the like; Subsequently, NIOS II notice DSP enters pre-actuated state, and at this moment, DSP is with the parameter of configuration, according to G.994.1 agreement and opposite end communication of ITU, if shake hands and just can finish smoothly in parameter configuration unanimities such as transmission rate, clock mode, modulating modes in two ends; DSP shakes hands success message behind master controller in transmission then, enter the nuclear starting state: in the nuclear start-up course, the DSP of principal and subordinate's end links up the data rate that obtains to shake hands, under the clock of data-interface drives, the activation signal that comes mutual ITU G.991.2 to stipulate in the agreement with the 2-PAM modulation system, after the principal and subordinate holds correct finishing to examine start-up course, DSP will formally enter data pattern: at first by the data-interface parameter of configuration before and the clock of the synchronous opposite end of clock module, then always according to ITU regulation G.991.2, finish framing to data, modulation, demodulation, separate the work of frame; To the data pattern process, if mistake, DSP will report the master controller error reason from the pretrigger of DSP, after NIOS II receives, DSP be put get back to init state, finish above-mentioned start-up course operation again.

When the circuit stable transfer, NIOS II is with the input of poll UART mouth, when input information, pass to DSP with importing the form of data with message, DSP is sent to the opposite end with these data by the EOC passage then, after receiving the successful message of opposite end reception, DSP also will inform master controller with form of message; Simultaneously, also can detect whether the EOC data are arranged from the SHDSL frame that receives at DSP, just send it to NIOS II if having, NIOS II is sent to UART with these data and exports to host computer.

Useful technique effect of the present invention is: the full-speed wired remote-transmission module that the present invention adopts the single standard of SHDSL to realize, not only having solved traditional remote-transmission module need adopt SHDSL and two kinds of existing deficiencies of technology of VDSL and circuit to disturb and the difficult problems such as interlocking of finishing principal and subordinate two ends clock of traditional remote-transmission module, and aspect transmission range, with identical speed rates the time, its transmission range is compared traditional remote-transmission module also lifting largely, makes this module just can reach the transmission distance of 1～10km by light-duty insulate line.

Description of drawings

Fig. 1, full-speed wired remote-transmission module pie graph;

Fig. 2, flow chart of data processing figure;

Fig. 3, software control flow chart;

Embodiment

Below in conjunction with relevant drawings, full-speed wired remote-transmission module disclosed in this invention done further in detail introduce: full-speed wired remote-transmission module of the present invention mainly is made of SOPC and SHDSL processor two large divisions: SOPC is responsible for finishing mutual with the SHDSL processor by the soft nuclear of CPU NIOS II, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime, and provide three kinds of professional number a tree name interfaces and one road management information interface for the user; The SHDSL processor digital front-end be responsible for finishing based on the ITU tissue G.991.2, G.994.1, the G.997.1 TC-PAM modulation of agreement regulation expansion, realize the twisted-pair feeder transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading.

The SOPC central processing unit mainly by the soft nuclear of CPU NIOS II, UART transmitting-receiving, ethernet mac, AAL5 is adaptive, AAL2 is adaptive and hardware program such as interface processing is formed: the soft nuclear of CPU NIOS II be responsible for finishing with the SHDSL processor alternately, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime; UART finishes the transmitting-receiving of asynchronous serial data; Ethernet mac is finished the MAC layer function that Ethernet inserts; It is adaptive that AAL5 finishes the cell of Ethernet data; It is adaptive that AAL2 finishes the cell of voice bitstream.By the processing of these programs, this module provides three kinds of data-interfaces for the user: transparent bitstream interface, Ethernet interface, cable voice port and one road management information interface.Bitstream interface directly realizes transparent transmission by the TDM interface of SHDSL processor; Ethernet interface both can directly be realized inserting by the MII interface of SHDSL processor, also can be adapted to cell and realize inserting by the UTOPIA interface of SHDSL processor; Cable voice port is realized inserting by the UTOPIA interface of SHDSL processor through being adapted to ATM cell after the digital coding; Management information is transmitted by the treatment channel EOC of DSP.

SHDSL processor part mainly is made up of unit such as embedded microprocessor, data-interface, clock unit, digital front-end, AFE (analog front end), circuit drivings: embedded microprocessor is responsible for finishing the parsing to cpu command, the processing of EOC message, to the configuration of other processing unit, and cooperate with the NIOS processor finish that circuit is shaken hands, process that pretrigger, nuclear start to synchronous data mode; Data interface unit is in charge of data transmission rate, frame synchronizing signal source, data loopback mode, sampled level and sampling clock edge, the read-write time-delay of slip buffering area etc.; DSL becomes/separates frame unit according to ITU agreement regulation G.991.2, with data and EOC message maps to the SHDSL frame, otherwise decomposite data flow and EOC message from the SHDSL frame; Digital front-end has comprised Trellis encoder, Viterbi decoder, scrambler, precoder, frequency spectrum shaping device, Echo Cancellation algorithm unit, near-end cross algorithm unit etc., is responsible for finishing the encoding and decoding and the modulation of SHDSL frame; Clock unit is according to the configuration of embedded microprocessor, control the source of reference symbol clock, and to data interface unit, framing separate frame unit, data processing unit provides the clock source, in the application of this module, the symbol send-receive clock of CO end and cpe end all is synchronized with on the local crystal oscillator clock of CO end, but the clock that finally is sent to data-interface is locked in the time receiving clock of remote data interface, and its phase demodulation information source is in dynamic filling bit information; AFE (analog front end) is finished automatic gain control, filter, D and D/A converter, circuit driving, synthesizer; By these functional modules, digital modulation signals is by the analog signal that converts to of digital to analog converter highly linear, and the circuit driver module through having strong driving force and low distortion characteristic is delivered on the DSL twisted-pair feeder by synthesizer at last again; At receiving terminal, analog input converts digital signal through behind the automatic gain controller to by analog to digital converter.

In order to realize full-speed wired remote-transmission, the present invention adopt based on the ITU tissue G.991.2, G.994.1, the TC-PAM modulation system of agreement regulation expansion G.997.1, modulation level is expanded to 64TC-PAM: 5 Bit datas of each information symbol carrying this moment; Simultaneously according to ITU-T G.991.2 in the agreement to the regulation of technical parameters such as handshake method, clock module, circuit gain, power spectral density, set up the G.991.2 transmission of the 8192kbit/s speed of protocol extension; The bracelet that wherein is in one's hands joint utilizes the expanding element in the performance inventory that defines in the agreement G.994.1, finishes the mutual of data such as transmission rate that the principal and subordinate holds setting, each information symbol carrying bit number.

Problem for convenience of explanation, present embodiment is example with the sending direction, flow chart of data processing to this module is described as follows: the data type that data processing partly need be handled comprises management information data and business information data, wherein the business information data have bitstream data, Ethernet data and voice-data signal: management information inserts by the UART interface, arrive the SHDSL processor through cpu bus, be sent to the DSL framer then, management information is embedded into EOC passage in the DSL frame as EOC message; When business is the bit stream form, directly be linked into the serial data interface of SHDSL processor, in the DSL framer, according to the clock of bit stream with data allocations in each time slot of DSL frame; Ethernet data is adapted to the AAL5 cell again through ethernet mac layer among the FPGA, delivers to the SHDSL processor by the UTOPIA interface then, the SHDSL processor with the load distribution in the cell in the DSL frame slot; And voice data is adapted to the AAL2 cell after encoding, and delivers to the DSL framer by the UTOPIA interface, and load is carried by the DSL time slot.

In the SHDSL processor, the DSL frame makes its randomization through scrambler, delivers to then and finishes the TC-PAM modulation in the TCM encoder, then comes balanced signal loss in the line by precoder, process frequency spectrum shaping device is finished the reformation shape to the signal frequency parameter then, delivers on the circuit at last.

For the data processing section of receive direction, the briefly inverse operation of process of transmitting just.

The software control flow process of this module as shown in Figure 3, software section, according to ITU G.991.2 to the regulation of SHDSL setting up procedure, the initialization of SHDSL processor experience, pretrigger, start a series of states, reach the stable data pattern at last: at first, NIOS II is as master controller, the firmware downloads and the start-up course of control SHDSL processor, by the CRC check sign indicating number in the firmware, detect the integrality of download firmware, after DSP started smoothly, master control sent order notice DSP and enters init state, send configuration parameter with the form of message then to DSP, the type that wherein mainly comprises data-interface, characteristic, clock mode, the DSL framing is separated frame parameter, the parameter of modulating unit, selection of principal and subordinate's end or the like; Subsequently, NIOS II notice DSP enters pre-actuated state, and at this moment, DSP is with the parameter of configuration, according to G.994.1 agreement and opposite end communication of ITU, if shake hands and just can finish smoothly in parameter configuration unanimities such as transmission rate, clock mode, modulating modes in two ends; DSP shakes hands success message behind master controller in transmission then, enter the nuclear starting state: in the nuclear start-up course, the DSP of principal and subordinate's end links up the data rate that obtains to shake hands, under the clock of data-interface drives, the activation signal that comes mutual ITU G.991.2 to stipulate in the agreement with the 2-PAM modulation system, after the principal and subordinate holds correct finishing to examine start-up course, DSP will formally enter data pattern: at first by the data-interface parameter of configuration before and the clock of the synchronous opposite end of clock module, then always according to ITU regulation G.991.2, finish framing to data, modulation, demodulation, separate the work of frame; To the data pattern process, if mistake, DSP will report the master controller error reason from the pretrigger of DSP, after NIOS II receives, DSP be put get back to init state, finish above-mentioned start-up course operation again.

When the circuit stable transfer, NIOS II is with the input of poll UART mouth, when input information, pass to DSP with importing the form of data with message, DSP is sent to the opposite end with these data by the EOC passage then, after receiving the successful message of opposite end reception, DSP also will inform master controller with form of message; Simultaneously, also can detect whether the EOC data are arranged from the SHDSL frame that receives at DSP, just send it to NIOS II if having, NIOS II is sent to UART with these data and exports to host computer.

Claims (6)

1, a kind of full-speed wired remote-transmission module, it is characterized in that: this module comprises SOPC and SHDSL processor two major parts, SOPC is responsible for finishing mutual with the SHDSL processor by the soft nuclear of CPU NIOS II, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime, and provide three kinds of business datum interfaces and one road management information interface for the user; SHDSL digital front-end be responsible for finishing based on the ITU tissue G.991.2, G.994.1, the G.997.1 TC-PAM modulation of agreement regulation expansion, realize the twisted-pair feeder transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading.

2, full-speed wired remote-transmission module according to claim 1, it is characterized in that: the SOPC central processing unit mainly by the soft nuclear of CPU NIOSII, UART transmitting-receiving, ethernet mac, AAL5 is adaptive, AAL2 is adaptive and hardware program such as interface processing is formed: the soft nuclear of CPU NIOS II be responsible for finishing with the SHDSL processor alternately, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime; UART finishes the transmitting-receiving of asynchronous serial data; Ethernet mac is finished the MAC layer function that Ethernet inserts; It is adaptive that AAL5 finishes the cell of Ethernet data; It is adaptive that AAL2 finishes the cell of voice bitstream; By the processing of these programs, for the user provides three kinds of business datum interfaces: transparent bitstream interface, Ethernet interface, cable voice port, bitstream interface are directly realized transparent transmission by the TDM interface of SHDSL processor; Ethernet interface both can directly be realized inserting by the MII interface of SHDSL processor, also can be adapted to cell and realize inserting by the UTOPIA interface of SHDSL processor; Cable voice port is realized inserting by the UTOPIA interface of SHDSL processor through being adapted to ATM cell after the digital coding; Management information is by the embedded processing passage EOC transmission of DSP.

3, full-speed wired remote-transmission module according to claim 1, it is characterized in that: SHDSL processor part mainly is made up of unit such as embedded microprocessor, data-interface, clock unit, digital front-end, AFE (analog front end), circuit drivings: embedded microprocessor is responsible for finishing the parsing to cpu command, the processing of EOC message, to the configuration of other processing unit, and cooperate with the NIOS processor finish that circuit is shaken hands, process that pretrigger, nuclear start to synchronous data mode; Data interface unit is in charge of data transmission rate, frame synchronizing signal source, data loopback mode, sampled level and sampling clock edge, the read-write time-delay of slip buffering area; DSL becomes/separates frame unit according to ITU agreement regulation G.991.2, with data and EOC message maps to the SHDSL frame, otherwise decomposite data flow and EOC message from the SHDSL frame; Digital front-end has comprised Trellis encoder, Viterbi decoder, scrambler, precoder, frequency spectrum shaping device, Echo Cancellation algorithm unit, near-end cross algorithm unit, finishes the encoding and decoding and the modulation of SHDSL frame; Clock unit is controlled the source of reference symbol clock according to the configuration of embedded microprocessor, and to data interface unit, framing separate frame unit, data processing unit provides the clock source; AFE (analog front end) is finished automatic gain control, filter, D and D/A converter, circuit driving, synthesizer, and by these functional modules, digital modulation signals is by the analog signal that converts to of digital to analog converter highly linear; Circuit driver module through having strong driving force and low distortion characteristic is delivered on the DSL twisted-pair feeder by synthesizer at last again; At receiving terminal, analog input converts digital signal through behind the automatic gain controller to by analog to digital converter.

4, full-speed wired remote-transmission module according to claim 1, it is characterized in that: adopt based on the ITU tissue G.991.2, G.994.1, the TC-PAM modulation system of G.997.1 agreement regulation expansion is: modulation level is expanded to 64TC-PAM, 5 Bit datas of each information symbol carrying this moment, simultaneously according to ITU-T G.991.2 in the agreement to the regulation of technical parameters such as handshake method, clock module, circuit gain, power spectral density, set up the G.991.2 transmission of the 8192kbit/s speed of protocol extension; The bracelet that wherein is in one's hands joint utilizes the expanding element in the performance inventory that defines in the agreement G.994.1, finishes the mutual of data such as transmission rate that the principal and subordinate holds setting, each information symbol carrying bit number.

5, full-speed wired remote-transmission module according to claim 1, it is characterized in that: the flow chart of data processing of this module sending direction is: the data type that data processing partly need be handled comprises management information data and business information data, wherein the business information data are divided into bitstream data, Ethernet data and voice-data signal: management information inserts by the UART interface, arrive the SHDSL processor through cpu bus, be sent to the DSL framer then, management information is embedded into EOC passage in the DSL frame as EOC message; When business is the bit stream form, directly be linked into the serial data interface of SHDSL processor, in the DSL framer, according to the clock of bit stream with data allocations in each time slot of DSL frame; Ethernet data is adapted to the AAL5 cell again through ethernet mac layer among the FPGA, delivers to the SHDSL processor by the UTOPIA interface then, the SHDSL processor with the load distribution in the cell in the DSL frame slot; And voice data is adapted to the AAL2 cell after encoding, and delivers to the DSL framer by the UTOPIA interface, and load is carried by the DSL time slot.

In the SHDSL processor, the DSL frame makes its randomization through scrambler, delivers to then and finishes the TC-PAM modulation in the TCM encoder, then comes balanced signal loss in the line by precoder, process frequency spectrum shaping device is finished the reformation shape to the signal frequency parameter then, delivers on the circuit at last;

Flow chart of data processing for receive direction is the inverse operation of direction of transfer flow chart of data processing.

6, full-speed wired remote-transmission module according to claim 1, it is characterized in that: the software control flow process of this module is: software section, according to ITU G.991.2 to the regulation of SHDSL setting up procedure, the initialization of SHDSL processor experience, pretrigger, start a series of states, reach the stable data pattern at last: at first, NIOS II is as master controller, the firmware downloads and the start-up course of control SHDSL processor by the CRC check sign indicating number in the firmware, detect the integrality of download firmware, after DSP starts smoothly, master control sends order notice DSP and enters init state, sends configuration parameter to DSP with the form of message then, wherein mainly comprises the type of data-interface, characteristic, clock mode, the DSL framing is separated frame parameter, the parameter of modulating unit, the selection of principal and subordinate's end; Subsequently, NIOS II notice DSP enters pre-actuated state, and at this moment, DSP is with the parameter of configuration, according to G.994.1 agreement and opposite end communication of ITU, if shake hands and just can finish smoothly in parameter configuration unanimities such as transmission rate, clock mode, modulating modes in two ends; DSP shakes hands success message behind master controller in transmission then, enter the nuclear starting state: in the nuclear start-up course, the DSP of principal and subordinate's end links up the data rate that obtains to shake hands, under the clock of data-interface drives, the activation signal that comes mutual ITU G.991.2 to stipulate in the agreement with the 2-PAM modulation system, after the principal and subordinate holds correct finishing to examine start-up course, DSP will formally enter data pattern: at first by the data-interface parameter of configuration before and the clock of the synchronous opposite end of clock module, then always according to ITU regulation G.991.2, finish framing to data, modulation, demodulation, separate the work of frame; To the data pattern process, if mistake, DSP will report the master controller error reason from the pretrigger of DSP, after NIOS II receives, DSP be put get back to init state, finish above-mentioned start-up course operation again.

When the circuit stable transfer, NIOS II is with the input of poll UART mouth, when input information, pass to DSP with importing the form of data with message, DSP is sent to the opposite end with these data by the EOC passage then, after receiving the successful message of opposite end reception, DSP also will inform master controller with form of message; Simultaneously, also can detect whether the EOC data are arranged from the SHDSL frame that receives at DSP, just send it to NIOS II if having, NIOS II is sent to UART with these data and exports to host computer.

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