CN101578590A - Full protocol engine for reconfigurable bit stream processing in high speed networks - Google Patents

Abstract

The present invention provides a reconfigurable and protocol independent bitstream processing engine and related systems and data communication methods suitable for achieving the goal of providing inter-architecture interoperability between high speed networks operating at speeds of at least 10 gbits/sec. The bitstream processing engine operates as a protocol-wide, multi-stage processor that can be configured with appropriate switches and associated network components to form a seamless network architecture that not only enables interoperability between existing various communication protocols, but is also capable of accommodating future communication protocols. The method and system of the present invention are applicable to networks including memory networks, communication networks, and processor networks.

Description

Be used for the full protocol engine that reconfigurable bit stream is handled in the express network

The present invention advocates the right of priority based on following U.S. Provisional Patent Application case: be called No. the 60/710th, 561, the U.S. Provisional Patent Application case of " being used for the full protocol engine (Omni-ProtocolEngine for Reconfigurable Bit-Stream Processing in High-Speed Networks) that reconfigurable bit stream is handled in the express network " on August 23rd, 2005 application and name; No. the 60/761st, 129, the U.S. Provisional Patent Application case that is called " the shelf Management Controller (Shelf ManagementController with Hardware/Software Implemented Dual RedundantConfiguration) that has the dual redundant configuration of implementing with hardware/software " on January 23rd, 2006 application and name; No. the 60/820th, 243, the U.S. Provisional Patent Application case that is called " having " on July 25th, 2006 application and name based on the encapsulation of senior TCA and the telecommunications and the computing platform (Telecommunication and Computing Platforms Having Advanced TCA BasedPackaging and Ethernet Switched Fabric) of Ethernet architecture for exchanging; And be called the U.S. Provisional Patent Application case the 60/822nd of " being used in the limited neighborhood enhancing Ethernet protocol (Enhanced Ethernet Protocol for Shortened DataFrames Within a Constrained Neighborhood based on Unique ID) " based on the shortening Frame of unique ID on August 11st, 2006 application and name, No. 181, the disclosure of each above-mentioned U.S. Provisional Patent Application case all is incorporated herein with way of reference.

Technical field

The present invention relates to the data communication field in the network by and large.More specifically, the present invention relates to a kind of configurable, with the bit stream processing engine of protocol-independent, and relate to relevant system and data communications method, it is applicable to the express network of speed operation with lucky position p.s.s 10 at least.

Background technology

Traditionally, based on the purposes of given network network is divided into different types of infrastructure or framework.Therefore, developed different types of network at storage network, communication network and processor network, each network all has different agreements and different network requirements, and each network is all through designing to satisfy the particular requirement of carrying out data communication in this framework.

For processor network, network performance is that High-Performance Computing Cluster is calculated (high-performance clustercomputing; HPCC) key element in the application.Usually, High-Performance Computing Cluster computing application long-play, and need manage between the device throughout and between the client-server by network I/O constantly (I/O) large data sets.Can estimate ground, must the number of support lucky bit strip of infrastructure is wide, low delay, available rate are served greatly, and these all are the absolute demands of high-end cluster interprocess communication.By convention, the High-Performance Computing Cluster computational grid utilizes the lucky position of switch type Ethernet.Also has purposes widely such as in Myrinet, InfiniBand and the Processing Cluster of specialized protocol under being connected the High-Performance Computing Cluster computing environment such as Quadrics.

Be necessary the networking processing device (for example) in the High-Performance Computing Cluster computing application is connected to the storage network framework effectively to the demand of mass data is feasible.By convention, High-Performance Computing Cluster is calculated and is supported that infrastructure comprises the attached network of storer (storage attached network; SAN) architecture for exchanging or deposit (network attached storage based on the network-attached storage of lucky position Ethernet; NAS) environment.Because have at move a large amount of block storage data and lucky bit rate of optimized number and host-host protocol between client computer and storage arrangement, fiber channel is the main agreement and the transmission channel of the attached network architecture of storer.

Internet protocol (Internet Protocol; IP) the communication network communication and the main framework of between client-server, generally communicating by letter between different High-Performance Computing Cluster computing applications often by the Internet architecture widely.Some storage network have adopted the lift-launch agreement (piggyback protocols) that is applicable to by Internet protocol storage network (as the fiber channel (FCIP) of internet SCSI (iSCSI), the Internet fibre channel protocol (iFCP), internet protocol-based) movable block memory data.Yet these carry agreement and not necessarily allow to carry out direct interoperability between communication network and storage network.

Provide between these different types of network architectures that the target of interoperability is well-known target between framework.Although can implement this target certainly in the slow network that all required processing all can utilize the programmable processor of standard to finish in network, this solution is feasible anything but under the required high communication speed of the express network that lucky position and more speed are moved with p.s.s 10.As a rule, adopted private adapter between the common protocol of concrete agreement on the framework and centrex node, to change.Although this method may be transparent for the terminal user, those skilled in the art's easy to understand, this adapter patch work can brought index blast problem aspect the ever-increasing agreement of quantity.In subnetwork equipment manufacturers at least, it is impossible solution that the express network switch that can handle a plurality of agreements is provided.Silvano Gai, " about being used for the unified shader of LAN/WAN/WLAN/SAN switch and router " the 23rd page, HSPR 2003, Cisco System company (noting still not possessing the cheap lan switch of 10 lucky bps).Therefore, people need find a solution is implemented in provides interoperability between framework between the network target, this solution for express network not only efficiently, but also can expand.

Summary of the invention

The invention provides a kind of bit stream processing engine of reconfigurable and protocol-independent, and relevant system and data communications method, described reconfigurable and be suitable for being implemented in the target that interoperability between framework is provided between the express network of speed operation with lucky position p.s.s 10 at least with the bit stream processing engine of protocol-independent and relevant system and data communications method.The bit stream processing engine is as full agreement, the operation of multiple-stage treatment device, it can dispose and be used for suitable switch and relevant networking component, not only makes the Seamless Network framework that might carry out interoperability but also can adapt to following agreement between existing communication protocol to form.Method and system of the present invention is applicable to the network that comprises storage network, communication network and processor network.

In one embodiment of the invention, full network protocol processing engine is engine-operated as Data Stream Processing, and it includes notch portion and exit portion, and each part all has at least one bit stream level processor.Preferably, each level processor all carries out optimization at a certain a specific order in the data stream.In concept, the work of Data Stream Processing engine is very similar to the production assembly line: when data stream moves through processing engine, finish different processing in the different phase of this assembly line, and all are handled all with respect to data stream regularly.To determining a speed by the data stream of processing engine, this speed allows processing engine to move continuously with the linear velocity of the network that links to each other with processing engine.The data flow model that uses has in the present embodiment been avoided needed in traditional protocol processor and has been tracking data required intensive, buffer management demand widely.In addition, but all cascades inherently of engine in any level, to support extensibility.

At full network protocol processing engine (omini-protocol engine; OPE) among the embodiment, multistage at least one inlet level bit stream processor, a compole state machine, a news affair processor, a scheduler and the outlet level bit stream processor of comprising.The Physical layer of inlet level bit stream processor and data stream is situated between and connects, and determines the frame and/or the flow of bit stream according to the agreement of determining at bit stream.The compole state machine is analyzed described frame/flow with very long instruction word able to programme (VLIW) traffic classifier that pipeline system produces key according to determined agreement, preferable utilization.News affair processor carries out frame/flow to be handled.Scheduler management is from the data stream output of news affair processor, and outlet level bit stream processor is situated between with Physical layer from the data stream of full network protocol processing engine and connects.All levels all can dynamically reconfigure and reprogramming, so that full network protocol processing engine and protocol-independent.

In one embodiment, compole state machine Homeway.com affair processor uses new type key to search layout, to improve the efficient of full network protocol processing engine.News affair processor can be embodied as multi-region segment data stream handle and arrange, each section in its CTC's affair processor depends on that the given agreement of frame/flow implements.In the embodiment of news affair processor, multi-region segment data stream handle implement ruling and/or time division multiplexing (TDM) method visit frame data stream/flow resident public shared memory buffer.In this way, each data flow processor does not need the some or all data in frame/flow are copied in the internal buffer in this processor to handle this data.In addition, data flow processor can and can be expanded by the abstract and clock of level abstract both and cascade.

In one embodiment of the invention, use four full network protocol processing engine that connect with SPI4.2 digital switch Jie to implement full agreement, 48 ports, the lucky position of non-locking QoS switch.In the present embodiment, each full network protocol processing engine all is situated between to connect to carry out the outside with 12 SerDes ports and is connected, and connects to be connected to the SPI4.2 digital switch with 3 SPI4.2 ports Jie.When being positioned at storage network, High-Performance Computing Cluster computation processor cluster, in-house network and Internet traffic network middle, as an integration framework (convergent fabric), any and all above-mentioned networks between carry out with the network of protocol-independent be connected effectively by its permission for described switch.This embodiment of the present invention provides a kind of intelligent switching solution, wherein, switch is instant able to programme and reconfigurable, each bag can both differently be handled (promptly according to the full network protocol processing engine of instant reprogramming/reconfigure, for example speed 100% ground with 10Gbps wraps route one by one), described full network protocol processing engine comprises " porthandler " or forms the digital switch of centrex framework.In this way, this switching solution provide high-performance (each port bandwidth 〉=10Gbps), low delay (exchange＜5 μ s), with protocol-independent, based on the exchange of strategy, described exchange can expand to thousands of nodes, cooperate each other with existing network infrastructure, and provides telco reliability/fault-tolerant ability (i.e. 99.999% available rate) with the cost effective and efficient manner.

In another embodiment of the present invention, full network protocol processing engine and the networking component that is associated all can use the register access control that has the graphical user interface management system and submodule access control layout dynamically to reconfigure and programme, the generation of described management system management code, flow control, performance is described and add up, and the diagnosis of system and maintenance.In a specific embodiment, the graphical user interface management system comprises the module of in fact carrying out system design, can carry out the simulation engine of emulation to the estimated performance of the framework that designs and produce microcode full network protocol processing engine and any other Reprogrammable/network equipment (if desired) that reconfigures are carried out the code generator (microcode manager) of reprogramming in the mode of " What You See Is What You Get ".

Description of drawings

Figure 1A and 1B are the functional-block diagram of full protocol engine according to an embodiment of the invention;

Fig. 2 is the more more detailed block diagram that the entry data of the full network protocol processing engine of Fig. 1 flows;

Fig. 3 is the constitutional diagram that is embodied as a part of bag state machine of entry data stream shown in Figure 2;

Fig. 4 is the more more detailed block diagram that the outlet data of the full network protocol processing engine of Fig. 1 flows;

Fig. 5 and 6 is the schematic representation of preprocessor packet framing system that comprises the initial part of multistage engine according to an embodiment of the invention;

Fig. 7 is for implementing the block scheme according to an embodiment of bit stream level processor of the present invention of preprocessor;

Fig. 8 A and 8B are the sketch from the general format of the general ethernet format of XGMII and Ethernet;

Fig. 9-11 is the sketch of the selected portion of multistage full network protocol processing engine;

Figure 12 is the sketch of the programmable state machine of one embodiment of the present of invention;

But Figure 13 is the exemplary expansion table of the programmable state machine of Figure 12;

Figure 14 is the example state diagram of the programmable state machine of Figure 12;

Figure 15 is the exemplary table of decoding table able to programme;

Figure 16 shows basic function more complete graphic of preprocessor framer;

Figure 17 graphic extension increases the method that the ability that has sub-state in the state was selected and made in input;

Figure 18 graphic extension expansion is from the method for the output control of state machine;

Figure 19 shows can be by the mask Compare Logic of state machine selection;

Figure 20 is can be by the Ethernet example flow diagram of this state machine programming;

Figure 21 is the block scheme of main-process stream control according to an embodiment of the invention;

Figure 22 is graphic extension operation register access control/submodule access controller with supervision and controls the sketch of operation of the interconnection level of full network protocol processing engine;

Figure 23 is the sketch of the standard ethernet frame that runs at inlet device according to the present invention place;

Figure 24 and 25 is the schematic representation that show the operation configuration of programmable state machine according to an embodiment of the invention and mask and comparator circuit;

Figure 26 briefly illustrates example frame sorter according to an embodiment of the invention.

Level 0 and level 1 engine that Figure 27 graphic extension moves in backfeed loop according to one exemplary embodiment of the present invention;

Figure 28 is the sketch of the Frame Handler expanded according to a particular embodiment of the invention, and wherein said Frame Handler comprises P-SerDes and core engine;

Figure 29,30 and 31 briefly illustrates the HPC port card that has full protocol engine of the present invention;

Figure 32 is to use the embodiment of third party FPGA with the exemplary switch of enforcement architecture for exchanging;

Figure 33 is the sketch according to the switch of general embodiment of the present invention;

Figure 34 A and 34B are the sketches of graphic extension ATMCA mTCA extra heavy pipe road switch according to a particular embodiment of the invention;

Figure 35 A and 35B are exemplary programming model and environment;

Figure 36 A and 36B show the block scheme of describing according to the shelf Management Controller of main embodiment of the present invention;

Figure 37 A graphic extension is according to exemplary I2C hardware finite state machine embodiment of the present invention;

Figure 37 B is the block scheme that the exemplary of different interface bridge-sets is used in graphic extension;

The block scheme of an embodiment of Figure 38 graphic extension bit stream protocol processor according to an embodiment of the invention;

The block scheme of another embodiment of Figure 39 graphic extension bit stream protocol processor according to an embodiment of the invention;

Figure 40 is the block scheme that data stream according to an embodiment of the invention is arranged; And

Figure 41 is the abstract block scheme of the various osi layers of the present invention.

Embodiment

The present invention includes new device, the system and method for the linear speed data routing processing that is used for network.Figure 1A graphic extension is according to the block scheme of an embodiment of system of the present invention.The center of present embodiment is full protocol engine.Full network protocol processing engine is a kind of and bit stream, multiple-stage treatment device protocol-independent, and it comprises dual-use function: 1) the relevant agreement of everybody basis in the bit stream is assembled in the protocol Data Unit that suitably defines; And 2) protocol Data Unit that collects is handled to run into assorted the one agreement linear speed handling capacity all is provided.Different with private adapter popular in the prior art, described two functions in the full network protocol processing engine all are dynamically programmables.Therefore, arbitrary or two protocol Data Units of given agreement or the processing rule that is applicable to protocol Data Unit dynamically mode change.

Except as otherwise noted, otherwise the term among the present invention " agreement " means the serializing communication protocol packet with the control bit that defines and data or information bit (it can be sky) grouping, and all control bits and data or information bit are all followed the instruction or the rule of one group of standard.Table 1 provides the summary according to some attribute of an embodiment of full protocol engine of the present invention.

Table 1

	Attribute	Describe in detail
			1	Immediately (on-the-fly) programmability	For example, in process, redefine machine instruction set
2	Able to programme/dynamically multi-protocols support	" standard " and " enhancing " ethernet ip v4, IPv6, the senior exchange of MPLS Infiniband/user-defined, the custom protocol of PCI-Express fiber channel SONET/ATM
			3	More high-level characteristic able to programme	Layer 2 to layer 4 classification able to programme use aging rule to support the 1M flow to support flow control, congestion management to 64Kbps degree of quantization news affair able to programme management, moulding and control protocol packaging V LAN, VSAN, VCAN
4	Use and support	TCP/IP unloads iSCSI, iSER, RDMA MPLS, DiffServ flexibly
			5	Industrial standard MIB	Industrial standard management information base, i.e. one group of variable that meets Internet Standard MIB II or other Internet Standard MIB.MIB II is found among the RFC 1213 " Management Information Base for Network Management of TCP/IP-based Internets:MIB-II ".

Shown in Figure 1B, full network protocol processing engine is that the multiple-stage treatment device arranges that wherein it comprises the processing block of a plurality of uniquenesses.At full protocol traffic processing capacity each piece is carried out optimization.Each processing block provides " door " so that more handle with linear speed along data routing." door " interface uses high-speed serial I/O channel and high-speed parallel channel to satisfy the delay requirement of processing block.The state of each processing block, feature and functional parameter preferably can be as " in real time " described in hereinafter programmings.Therefore, full network protocol processing engine is Reprogrammable both, and is reconfigurable again.

Referring to Figure 41, on basic layer, can and change at the data flow dependency between ingredient, the each several part and each level or processing block be carried out abstract aspect the control structure of described data flow dependency.At the highest level of abstraction, each level is all implemented general-purpose interface, this general-purpose interface is implemented control structure so that level can receive input bag flow object, and output after handling the bag flow object and with input with the metadata object that is associated of the Bao Liuzhong after handling any one or both.Each grade all is a member in the base class.Each base class is implemented an interface, and described interface is by the method collection regulation of implementing at described base class.At middle level of abstraction, can expand each base class by increasing additional modules, described additional modules is expanded the function of base class and is formed a subclass.Each subclass is implemented its oneself subclass interface, and this subclass interface provides extra method to expand the function of base class method.At minimum level of abstraction, can be by providing other method and/or non-existent part further expands the interface that subclass provides in the base class to provide by increasing submodule.By change method and object reconfigurable class and the subclass thereof of this method with effect.In this way, can each level of bit stream processor be reconfigured by programming, so that discrepant resource and service to be provided.In this way, each grade is configured to have data (bag) stream machine with the framework of protocol-independent.

With frame definition is bit stream, and wherein each and each implication is defined by one or more predefined agreement framing rules.Abstract model has the method for input acceptance as bit stream.Each and each implication is undertaken abstract by method, so that each level can receive bit stream.Protocol processes is defined by other method, and described method is carried out one group of operation based on the information in one or more positions of the bit stream that is positioned at any position in the bit stream.Enforceable any class or subclass (for example method) treatment step that can carry on an agreement potentially.In an alternate embodiment, each class or subclass are through programming to handle certain protocol by implementation method in the general-purpose interface that is provided by described class or subclass.Therefore, the details of described embodiment " can be hidden " back, so that can reuse code and part in one or more methods.Abstract result is: data stream architecture comes down to the pipeline of a series of layings, and predictable delay stages is finished at inter packet gap in the time (that is, before the arrival of next one bag) through being arranged as to make to the processing in the deciding grade and level.

Each level is carried out abstract making might be to the one or more streamline sub levels of each grade increase.Each sub level in one level production line is equaling to wrap the operation of finishing in the time of time of arrival divided by the quantity of the sub level in the one-level bag.Therefore, the first order can comprise the subclass that enforcement is used for the method for bag decoding (that is, it produces metadata of relevant data bag).Metadata can comprise the information of the position of the bit pattern that depends on specific protocol in the relevant input bag stream.In this respect, packet decoder carries out " analysis " to frame (bit stream that defines).Notice that term used herein " enforcement " is illustrated in the embodiment of one or more firmwares and hardware aspect.Can use the incompatible enforcement said method of any firmware, hardware or firmware-hardware group of implementing above-mentioned basic function.For example, the bag decoder stage can be embodied as the programmable state machine that has the comparison accelerator.When given a kind of protocol type, programmable state machine extracts level processor and carries out field in the required bag of (for example) address search.Packet decoder carries out 2/ layer 3/ layer 4 analysis of layer, with information extraction from described three layers header.Therefore, can method that implement this function be customized, handling described three layers agreement, and therefore expanded base class.

In one embodiment, each all has a plurality of bit stream level processors that are situated between and connect with Multi-ported Data stream packet memory in the intake section of Data Stream Processing engine and the exit portion.Each bit stream level processor all provides unique command memory.In one embodiment, first cross bus is connected between data stream packets storer and Fabric Interface and the processor interface, and second cross bus is connected between data stream packets storer and a plurality of bit stream level processor.In the present embodiment, the 3rd cross bus is connected between a plurality of bit stream level processors and the common memory interface.Common memory interface can with external memory storage or with Content Addressable Memory (Content-addressable-Memory; CAM) interface connects.

In one embodiment, complete one group of required common process piece of the most normal agreement that runs into of network protocol processing engine support.Can implement extra function by increasing proprietary processing block able to programme, multi-functional, as the computation-intensive protocol processes.These computing pieces can also have " immediately " programmability, thereby give full network protocol processing engine and under any protocol environment, move required extensibility, and can not cause prior art peculiar cost type or performance loss when attempting to reach the Converged Network framework.In fact, by the multi-protocols processing capacity is provided, that is, can be with the different combination of components of computing center to needing between different high speed protocols, to use gateway and switch together and not, full network protocol processing engine can realize the integration framework.Full network protocol processing engine solution is worked on OSI 2-7 layer.

In one embodiment, preferably utilize name to be called the United States Patent (USP) the 6th of " method and apparatus that is used for programmable circuit is carried out graphical programming ", 671, the code generator based on graphic user interface described in No. 869 comes the processing block of full network protocol processing engine is programmed, United States Patent (USP) the 6th, the content that is disclosed in 671, No. 869 is incorporated herein by reference.The display protocol template will be dragged and dropped into operation tool to the operation of physical child segment, and system produces " communication engines code " thus.In addition, graphic user interface is with the estimated performance of the mode display engine of " What You See Is What You Get ".System is the maximum required operation of performance of acquisition to user prompt.In chip environments, use these functions to select suitable link speed.At the programmable platform environment, for example among the FPGA, can select more jumbo chip.

In as Figure 35 A and 35B graphic extension should specific embodiment based on the code generator of graphic user interface in, display protocol template, and will be dragged and dropped into operation tool to the operation of concrete field.System produces " communication engines code " and with the estimated performance of the mode display engine of " What You See Is What You Get ".This system is the maximum required operation of performance of acquisition to user prompt.In chip environments, can use these functions to select suitable link speed.In programmable platform environment (for example previous FPGA example), can select more jumbo chip.

Can provide " immediately " function in conjunction with one or more general purpose processors (CPU) of sharing public local bus by for example field programmable gate array.Be called in name in No. the 6th, 721,872, the United States Patent (USP) of " reconfigurable network interface framework " and disclosed a kind of such method, the disclosure of described United States Patent (USP) is incorporated herein with the method for quoting.At U.S. Cambridge, MA 02139, the people such as Bove Jr of MIT Media Lab (MITMedia Lab) " using the field programmable gate array on the local bus of microprocessor to carry out media " in a kind of alternative method that described " immediately " function is provided has been described, the content that discloses in the described file is incorporated herein in the mode of introducing.

Referring now to Fig. 2,, will an embodiment of " the inlet operation " of the full network protocol processing engine shown in Fig. 1 be described.The port integration relates to PHY and the peculiar physical layer protocol framing of mac device and the bag data of concrete medium is converted to the SPI4.2 burst frame.To be delivered to the SPI4.2 engine in the mode of circulation, time division multiplexing from the little SPI4.2 burst of a plurality of ports.Port number based on integration is a time slot with the SPI4.2 channel distribution; 8 port integration devices are 8 equal parts with the SPI4.2 channel distribution.On bus, produce idle burst for the notch/port of not working or do not have data to supply to transmit.

Mac device in the present embodiment is 8x1GbE MAC chip (" a MAC chip ").With the pattern that is called " burst interleaved (burst-interleaved) " the MAC chip is configured, " burst interleaved " pattern means in the mode of circulation (port 0 to port 9) from the configurable byte quantity of the Ethernet bag data of each 1GbE (for example, 32 bytes) dispatched, to be transferred to the SPI-4.2 interface.Then, the burst (burst) from 1GbE MAC is interlocked and on the SPI-4.2 bus, transmit.Small burst (less than the burst of 32 bytes) may be positioned at the bag starting point and finish the delimiter place.The operation of the Ethernet bag being carried out by the MAC chip comprises: (1) divests preamble and frame starting point delimiter (Start of Frame Delimiter; SFD); And (2) keep FCS.

The SPI-4.2 engine preferably comprises the core of the substantive function that the SPI-4.2 engine is provided, and described substantive function is converted to the SPI-4.2 framing inside framing format that is similar to SPI4.1.Data arrive with 16 bursts from SPI4.2, and 16 words of first of burst comprise control word, and described control word comprises the information of relevant burst; Comprise that burst is starting point, the end of bag or the continuing of bag of bag, and the channel number that produces burst.In the future being assembled into 64 words and transmitting up to 8 16 bit data word of self-channel is converted to " inner routing label " with 16 control words simultaneously.

In the present embodiment, when frame moved through forwarding logic, " inner routing label " transmitted on internal bus together with the bag bursty data." inner routing label " comprises 1 of expression " data are effective ", 1 of expression " bag starting point ", 1 of expression " end-of-packet ", 1 of expression " error in data ", 3 (it is 1-8 that 0-7 indicates burst sizes respectively) and 3 of expression " channel address " of expression burst sizes.The port that " channel address " indication is associated with burst.In another embodiment, " inner routing label " can be Network Based layer priority or VLAN appointment priority and comprise QOS/COS information.

Frame Handler needing when frame is handled to carry out the interesting characteristic of recognition network bag.These characteristics comprise destination address and source address, bag type, layer 3 and layer 4 datagram and session addressing.In addition, Frame Handler is kept a state machine to each bag of forwarding logic processing.

As shown in Figure 3, the composition of " bag state machine " streams of trace data.For the HPC solution, data stream is made up of a plurality of bursts of bag data, and described a plurality of bursts will be classified based on the bit field in the SPI4.2 control word.For receive at SPI4.2 or from each bag illustration of SPI4.2 transmission a bag state machine.When assert " SPI is (PACKET_VALID) effectively " signal, bag enters " effectively " state.When assert " SPI wraps starting point " signal, bag enters " bag starting point " state, and " SPI end-of-packet " causes transitting to " end-of-packet " state.If the error condition misdirection, then state machine enters the ERROR state, otherwise state machine transitions is to INIT.

Referring to Fig. 2, the task of analysis engine (parser) is that the information of utilizing Frame Handler to provide makes up multibyte classifiers key again.In one embodiment, produce " sorter key " and only need destination address.In alternate embodiment, can strengthen " searching engine ", when making up " sorter key ", also comprising any amount of bag characteristic, thus when switch is transmitted single bag or bag stream the performance of modification switch.

By " the sorter key " that use parser to produce, " searching engine " will enter the forwarding Content Addressable Memory in a jumble, to search the outlet target port.The export goal port is placed in " inner route header ".In one embodiment, " inner route header " is made up of the endpiece slogan fully.Perhaps, " inner route header " can comprise out of Memory.Such as based on the management entities such as management station of SNMP with addressable forwarding Content Addressable Memory clauses and subclauses.

" news affair guides " is responsible for transmitting and/or duplicated frame to CPU based on the port address of finding in " inner route header ".The appropriate interface logic is provided between the microprocessor in forwarding logic and FPGA.

Data stream between the frame processing logic of " queuing engine " responsible processing switch framework and " port card "." queuing engine " comprises the virtual queue of each 1GbE MAC in the exchange board structure in 8 port card switches, in this 8 port card switch it is summed into a plurality of virtual queues.Each virtual queue is very big, is enough to hold a plurality of large-scale (9K) bag.For each virtual queue is kept an index, will be placed on which position in the virtual queue to follow the tracks of next 64 bit data, described index is called VQ queuing index.Inquiry VQ dequeue (VQ dequeue) is to determine to pass to next 64 bit data of scheduler.So, will put into the VQ of target port from the data of " news affair guides " with the skew of VQ dequeue index indication.On the contrary, use VQ dequeue index to determine which data transfer to give scheduler with." queuing engine " also provides " rate variation " between exchange board structure and " virtual queue " FIFO, and the flow control mechanism that shows the back pressure between exchange board structure and the forwarding logic.

When transmitting frame to the switch framework, scheduler uses the dequeue mechanism of " queuing engine ".In round-robin mode (from port 0 to port 31) frame that will be delivered to exchange board structure is dispatched.Dequeue relates to the frame that encapsulated among the XGMII before " XAUI core " is converted to frame XAUI.In the transition period, use " inner routing label " and " inner route header ".

Referring now to Fig. 3,, will an embodiment of " the outlet operation " of full network protocol processing engine be described." queuing engine " provides the queuing of outlet one side that is positioned at the inlet opposition side." XAUI core " will be converted to XGMII from the XAUI frame of switch framework.Based on the port numbers in the XGMII frame XGMII frame is queued in " virtual queue ".

Scheduler is to finish the inlet scheduling with the closely similar mode that enters the mouth.Make the frame dequeue in the round-robin mode, but the outlet data frame must be converted to local bus interface, and generation " inner routing label ".In one embodiment, scheduler design is self-adaptation and heuristic, so that only by searching broadcasting and using source address update content addressable memory to reduce the outer Content Addressable Memory of transmitting of band and upgrade.

Outlet SPI4.2 conversion shown in Fig. 4 is opposite with inlet.Use proprietary core that local framing format is converted to SPI4.2.Outlet port integration relates to SPI4.2 frame bursty data is assembled in the medium bag, and by the addressing discharge coupling of SPI4.2 frame bursty data it is transferred out.These interfaces also preferably are described MAC chip above.The operation of outlet is opposite with inlet.Ethernet bag data from SPI-4.2 receive in the outlet FIFO with staggered Ethernet bag data burst (port 0 is to port 9).When receiving 5 bursts, outlet FIFI (depends on perhaps when packet length is worked as EOP arrival) that outlet FIFO will start the transmission to 1GbE MAC.Preferably, egress frame is handled the port status machine of also keeping, and described port status machine is carried out the frame state inspection, and for example frame is aging, vlan header divests, the inner header of transmitting removes and similar operations.The operation of the Ethernet bag being carried out by the MAC chip comprises: (1) increases preamble; And (2) increase frame starting point delimiter (SFD), and optionally (3) increase FCS.

In the exemplary embodiment of graphic extension, full network protocol processing engine provides selected level 0, level 1, the level 2 of being named as in Fig. 5 and 6 ... the pipelining level engine sequence of level n.Depend on it is the full network protocol processing engine that is equipped with at which function, each grade engine can have different, extendible and re-programmable framework.Therefore, different with the processor (wherein bag being characterized with its software instruction that carries) of prior art, the present invention is the data stream architecture that has the assembly line of special level, and described special level is illustration immediately, to reflect the variation of the data that flow along the line.

Although the present invention does not limit the quantity of porch port, the present invention is described by the life-span of the bag of the data routing of full network protocol processing engine in the packet and the tracking edge that preferably just arrive single port.Be important to note that the width of each in these data bit streams can be numerical digit.Described width provides the measuring of available processing time (or clock period) of each grade engine place of streamline, thereby can realize the linear speed handling capacity.If look and realize in the time restriction that the processing at any one-level engine place can not set in initial level, then each grade engine is limited in the specific time range and moves by the quantity that increases the engine of forming each grade.

Fig. 7 has illustrated one embodiment of the present of invention, and described embodiment provides level 0 engine, and described level 0 engine comes down to the preprocessor packet framing device that part comprises programmable state machine.Because the width of each bag that arrives is 64, the various types of frames shown in framer identification and the component-bar chart 1.Framer is by forming with the lower part: programmable storage basic status machine, the basic look-up table of short-access storage, have the various comparers that can load numerical value and select logic.State machine is selected the bag field be concerned about, and itself and setting value or other frame data are compared, and this is with driving condition machine algorithm, and described algorithm carries out the type of mark and definite frame to the frame of being concerned about.Then, this information is delivered to parser, how the help command parser is analyzed frame.

For describing this embodiment of preprocessor bit stream processor in more detail, with reference to appendix A, the content that is disclosed in the appendix A is incorporated herein by reference.Other please refer to appendix B, and the content that is disclosed among the appendix B is incorporated herein by reference, and it describes an embodiment of " forwarding logic register file " in detail.

Full network protocol processing engine preferably comprises at least one predictable programmable state machine (ProgrammableState Machines; PSMs).In one embodiment, each programmable state machine is one 32 state machines, and the time of every programmable state machine is 50ns under 156MHz internal clocking frequency, is equivalent to per 10 instruction 5ns.Yet each programmable state machine can have the variable clock of quantity.By comparatively faster serial bit stream being converted to relatively slow parallel n bit wide data stream, level 0 engine is provided with the bandwidth processing residence time.Adjust the bandwidth processing residence time according to linear speed.For example, for handling the data transfer rate of 10Mbps, the residence time is that every grade of full network protocol processing engine is 50ns.

Preferably, base register is made up of programmable look up table, the default numerical value of packing into as the part of configuration that is equipped with of described programmable look up table.Then, these registers are through selecting to use with mask, comparer sum counter as the engine-operated part of complete level.An exemplary configuration of level engine configuration is described as follows: programmable look up table comprises nearly 34 16 bit value that will compare.The table carry-out bit is promptly corresponding to this comparison (if comparing).In this example, has the comparer of 48 bit wides, two down counters (for maximum depreciation counting 256, it is 8 that maximum can be loaded numerical value).The bag data select width to can be 1 byte, and the register value field size is represented by 16 8 bit wide pre-registers.State machine instruction can be single-word instruction (Single Word Instruction; SWI).The single-word instruction group can be selected from the set that comprises setting, test and redirect, wherein each field of every instruction can be rendered as counterfoil field as follows, wherein each counterfoil field separates with comma, and each main fields separates with branch, for example, SWI:set1, set2, set3 ... setn; Test1, test2, test3 ... testn; Br1, br2, br3 ... brn;

Be in operation, state machine will be based on selectable vector input carrying out condition redirect.Therefore, for example, condition (frame byte 2==R2) will compare byte in 8 package location bytes 2 and pre-register R2 numerical value.Described redirect determines next state of a control usually, but also can be used for changing the operational mode of the current state of programmable state machine.

Referring now to Fig. 8 A and 8B,, wherein illustrate preprocessor packet framing method is applied to input Ethernet bag from the XGMII interface.From this, the XGMII interface block is peeled off preamble, and 32 interface conversion are inside 64 bit representations shown in " Fig. 8 B: the general format of Ethernet ".

When 64 bit wide bags flow through streamline, state machine selected it to want which 16 bit field is sent to decoding RAM able to programme.Referring to " Fig. 9: bag type selecting " and " Figure 10: decoding RAM able to programme ".

State machine is also selected out of Memory from the bag for the treatment of to compare with programmable register, and the result is fed back to state machine, as shown in figure 10.Figure 10 has for example shown that VLAN and SNAP input is selected and has compared with selected register, and the result has been fed back to state machine analysis.

The purposes of state machine according to an embodiment of the invention is the extraction of control protocol layer header information.Described state machine is made up of the programmable block storer, and 5 output data lines feed back in 5 address inputs to carry out the NextState timing.The various functions of other output control of state machine, for example, frame data to be caught, frame layer offset detection and the various input that is used for Compare Logic are selected, and import to the next one of state machine itself.Shown this state machine among Figure 12.Figure 13 has shown that a state machine table example is to help this being carried out graphic extension.

A task of described programmable state machine is the extraction of control decoding and bag data.Constitutional diagram among Figure 14 has shown that how this state machine is set is handled the Ethernet bag.In this example, state machine is only operated ethernet layer 2, but also can continue operational example such as layer 4 always.

Decoding RAM provide a kind of method of selected field being carried out quick decoding able to programme.To the input of this decoding RAM circuit be optional 16 bit fields from bag, and output is 4 " type " decoding, shown in Figure 10 as in the preamble.A kind of method of carrying out described operation is at first to use all zero padding storeies, and " type " wanting to decode at you writes decoded bit then.16 bit address are corresponding to " type ", and data are corresponding to the desired decode value of the type.Under normal circumstances, only be provided with 2,1 is used for port B, and 1 is used for port A.For port B and port A, decoded bit should be identical value.An example of this respect may be, 0x809B AppleTalk Phase 1 is decode value " 1 " if desired, 0x8137 IPX (Novell Netware) is decode value " 2 ", 0x8847 MPLS Unicast is decode value " 3 ", and 0x8848 MPLS Multicast is decode value " 4 ".The above results as shown in figure 15.

Figure 16 shows the more fully figure of the basic functional blocks of preprocessor framer.

Figure 17 graphic extension is a kind of to be increased the input selection and makes the method that can have sub-state in the state.

A kind of expansion of Figure 18 graphic extension is from the method for the output control of state machine.

Figure 19 shows can be by the mask Compare Logic of state machine selection.

Figure 20 is can be by the Ethernet example flow diagram of this state machine programming.

Referring to Fig. 5 and Fig. 6, the preprocessor framer can be configured to provide greater flexibility in wrapping selection again, or can optionally take a step back in streamline is selected.Stronger if desired function then all the time can be by increasing one or more extra state machines and/or decoding RAM able to programme provides described function.It should be noted that in addition shown RAM is embedded among the XILINX as block RAM, and can dispose in a different manner and grouping etc., and this design only shows and used two block RAMs that is used for a state machine, another is used for the TYPE decoding.Minimum Xilinx XC2VP2 has 12 block RAMs, and the Xilinx XC2VP2 of next specification has 28 block RAMs, and maximum Xilinx XC2VP2 has 556 block RAMs.

In a general embodiment of the present invention as shown in figure 26, the data routing of full network protocol processing engine streamline is to level 1 engine from level 0 engine.Level 1 engine is implemented rule-based classification to bag.Can because classification must take place, thereby have real linear speed handling capacity in the time interval that Stage_0 (level 0) located to define with a plurality of engine cascades to obtain required result.Each engine is all based on data flow model, rather than traditional storage-forwarding model.An output of this grade has been based on before on the basis of the related content that unpacks and has produced key.In current embodiment, this level will need two instruction cycles.Each engine all adopts single impact damper.Different with floating-point coprocessor, all engines all are dynamically programmables, that is, instruction is programmable, so that they are suitable for concrete application.Usually, level 1 will comprise at least one very-long instruction word processor.In an alternate embodiment, the task customized processor mode of level 1 engine described in can preamble is configured.

In a specific embodiment of the present invention as shown in figure 27, level 0 and level 1 engine move in feedback cycle, the status information of using level 0 bit stream of programmable state machine to handle is passed to level 1 classification engine, and is fed with the operation with engine from the information of sorter and is notified to level 0.Feedforward/rear feed exchange architecture makes and might obtain any content bit stream of giving constant current from the supported a plurality of stream of full network protocol processing engine, when data stream is crossed engine, content is analyzed (or classification), and the information feedback that described operation obtains is got back to previous stage, so that next classification results of operating based on original state and original state carries out.

This method can be advantageously used in (for example) and handle variable-length/variable protocol package, and the bag that loses sequence is carried out dynamic order, perhaps is used for other wrong control function.The elementary cell of data becomes 1, the feedback and feedforward system storage or bonding is provided, make each all with arrive its front and that follow in its back each be associated.Can expand this normal form, " storer " being injected in the macro-cell data structural system (for example, byte, word, frame or complete session, this depends on the specific tasks of level), but can not cause the time-delay and the hardware spending of storage-forwarding structure.Above-mentioned macro-cell data structure can be moment---it exists when data have specific characteristic, and is used at all follow-up data stream the performance of full network protocol processing engine being carried out reprogramming.With the operation of legacy protocol processor is hard wired different, in this way, full network protocol processing engine is a kind of hardware unit that transforms into, it is adapted to the constantly data stream of variation in the prejudgementing character mode, that is solution provided by the invention has overcome prior art and has attempted to provide the shortcoming of solution peculiar " state explosion " by extension state machine and amount of state to tackle the data stream that increases.

Figure 40 has shown a data stream layout embodiment who implements one embodiment of the present of invention at multistage bit stream processor.

An attractive function of multistage technology is, the effective decoupling of parameter of each " level " engine.For example, between at different levels, do not need public clock.This has greatly simplified the design of full network protocol processing engine.Can be each grade the one or more engines that customize according to this grade operation demand at any given time are provided.Can carry out instant reprogramming to each engine, the function that is complementary with the characteristic of giving its data stream that runs in particular moment with full network protocol processing engine.

In general embodiment of the present invention, level 2 engine back are with level 3 engines are arranged.Level 3 engines provide more senior control plane function, for example route, signaling, protocol stack, policy definition, table safeguard, with the datum plane interface etc.Similar with previous level, level 3 has special engine, and it is reproducible to be complementary with the processing time and the functional requirement that are applied on the full network protocol processing engine.Figure 28-31 graphic extension has the Frame Handler expanded of P-SERDES and core engine and has the HPC port card of full network protocol processing engine of the present invention.

In one embodiment, the illustration described in the preamble has shown one 32 clauses and subclauses * 48 Content Addressable Memory on each port card in (for example) switch.Each clauses and subclauses is represented a particular port in the switch.Therefore, the first entry in the port card forwarding Content Addressable Memory is represented the port one of switch.It should be noted that the size that can increase these Content Addressable Memories, to adapt to a plurality of nodes on the attached LAN section.Preferably, define an aging mechanism, its will be only actual clauses and subclauses in the forwarding Content Addressable Memory of reserved port card.Because High-Performance Computing Cluster is calculated and is not used the LAN section, so may not need aging mechanism.

Because one of design object is to transmit Content Addressable Memory by the SNMP visit, so the SNMP that moves on shelf manager agency will need the forwarding Content Addressable Memory high-speed cache that resides on the support card is carried out read.Will be by shifting port card onto under the Content Addressable Memory IPMI information of upgrading to transmitting any change that high-speed cache carries out, and as noted before the processing.

Dynamic MAC address study.For making switch between any two switch ports themselvess, transmit bag, must search destination-mac address, to find the target switch port that will send the input bag.Look-up table (be also referred to as and transmit) preferably comprises 48 place values, and described 48 place values comprise destination-mac address and 6 switch ports themselves identifiers.By transmitting of keeping of switch manage on each single port card transmit between distribute.Need grow these and transmit (it is implemented by Content Addressable Memory) in hardware.There are two kinds of methods to grow: dynamic and static into transmitting.By will transmit via the SNMP enterprise mib that is similar to the forwarding database described in the RFC 1493 Content Addressable Memory be exposed to management entity realize to the static state of these Content Addressable Memories grow into.

The design's a target is to regulate broadcast packet and multicast bag.This is because broadcast frame is very expensive aspect bandwidth and switch resource, and the multicast frame is expensive more.People have carried out exhaustive search, but to find a kind of method to make the switch dynamic knowledge be attached at MAC Address on the LAN section on each switch ports themselves, no matter and which kind of topology switch may be arranged as, and need not use broadcast packet and multicast bag and not need attached port network logic is made amendment.At present, have single method or in groups step make switch can be in all cases dynamically determine to be connected to all MAC Address of switch ports themselves.In brief, the Internet of IEFT RFC definition or Ethernet require switch/bridge/router to want one initiatively to understand MAC Address, one switch/bridge/router to provide a kind of administrative mechanism to grow into transmitting with static state.

Therefore, will imitate the performance of self-study formula bridge according to the switch of present embodiment of the present invention.To analyze and source address will be put into suitable forwarding Content Addressable Memory input broadcasting (for example standard ethernet frame shown in Figure 23).This will be finished by the embedded FPGA microprocessor that is independent of the bag forwarding logic in the FPGA.Hereinafter describe the dynamic MAC address new discovery in detail:

The place receives broadcast packet at the switch ingress port.Bag passes to portable Management Controller (Mobile Management Controller via frame FIFO with frame with frame up to news affair guides by the forwarding logic transmission; MMC).

Portable Management Controller will extract the source address of data link layer header.

Portable Management Controller is the packaged source address, and with switch ports themselves number import IPMI message and via based on the IPMI bus of SPI with the microprocessor of described forwards to the support card (IPMC).

IPMC will catch the source address transmitted in the high-speed cache and switch ports themselves number, can be via the described high-speed cache of transmitting of register access control visit based on the management entity of SNMP.

IPMC is broadcast in the switch all other portable Management Controller with the Content Addressable Memory updating message.

Internal microprocessor is received content addressable memory updating message, and upgrades it and transmit Content Addressable Memory by the MAC Address of described Content Addressable Memory updating message is put into the Content Addressable Memory clauses and subclauses with the skew of switch ports themselves number expression.

It should be noted that to need to revise the described whole program of transmitting on a large scale, to support the bigger topology of robustness, that is, and a plurality of nodes on the attached LAN section.

Preferably, internal microprocessor reads 32 bit wide FIFO, with selected frame in the visit data stream.Forwarding logic writes FIFO with " inner routing tag " and top 32 bytes input bag.Read status register is to determine when FIFI is sky.

As previously mentioned, can be by register access controlling mechanism visit FPGA control and status register, with the message-oriented of the IPMI encapsulation microprocessor in the FPGA, then, described FPGA carries out actual register and reads or writes thus.In one embodiment, microprocessor is as the register access controller, and it is explained the register access control messages, determines the register access which forwarding logic assembly/submodule access controller (submodule access controller) is message be addressed to and be convenient to the submodule access controller.With resulting state/response return messages source.The block scheme of an embodiment of Figure 22 display sub-module access controller bus.Should be appreciated that submodule access controller bus is unique for submodule and may adopts various ways.

Ieee specification regulation can or be set at unique DA at the station that will suspend with the destination address of PAUSE bag, perhaps is set at the multicast address 01-80-C2-00-00-01 (sexadecimal) of global assignment.In addition, bridge will can not be transmitted the bag that has PAUSE bag multicast address, can not propagate into beyond the local link section to guarantee frame.The bit time quantity that will suspend, from 0 to 65535 are specified in MAC controlled variable territory." time-out " that " time-out " time formerly received then will cause new bit time value to replace current " time-out " time value.This can be reset " time-out " time is 0, thereby makes news be engaged in and can recover.

Preferably, the MAC chip adapts to two kinds of flow control modes.When being configured to full-duplex mode, the MAC chip can automatically produce " time-out " bag.By suitable high and low watermark is set, the MAC chip will be managed the beginning of " time-out " signaling and stop, and impel MAC chip inlet to be full of with FIFO from the back pressure of SPI-4.2 bus.Second kind of pattern walked around FIFO, and relies on the transmission of SPI-4.2 flow control messages to produce " time-outs " to begin and stop to wrap.

To keep a port status machine for each switch ports themselves on the port card.FGPA logic and the addressable state machine of microprocessor both.State machine described in the presents comprises three fundamental elements: the state of incident, definition and the operation of carrying out when entering this state.Above state is arrived in Ding Yi Event triggered transition between states, and described state can be carried out diagram shown in Figure 24 and the operation shown in the constitutional diagram among Figure 25.

Figure 32 shows an embodiment, and the wherein hardware unit by transforming into, that is Virtex LX 200 communication engines are couple to Virtex Pro 4 communication engines that constitute entrance and exit " port " and are configured as 48 port switch.The problem of this configuration is, switch is arranged and only limited to handle the single agreement that is used for the packet that exchanged by being arranged by the switch of Virtex Pro 4 communication engines supports.

Figure 33 shows the concrete framework according to a switch of the present invention, the full network protocol processing engine that wherein forms porthandler engine and digital switch one is Virtex LX 200 communication engines possibly, one be the special-purpose full network protocol processing engine that forms intelligence, Reprogrammable architecture for exchanging.Arrange different with the switch shown in Figure 32, utilize the embodiment according to full network protocol processing engine of the present invention to provide a kind of full agreement switch/bridge to arrange among Figure 33, described layout can be handled the packet of any agreement in a plurality of agreements that full network protocol processing engine supports.Figure 33 briefly illustrates the concrete configuration of switch of the present invention.

Except the incident that is produced when getting the hang of, microprocessor needs monitoring MAC chip, SFP, and listens attentively to IPMI incident and message, so that the incident that causes switch ports themselves transition between states to be provided.Notice that any incident may take place under any state, and must be hunted down and suitably processing.For simplicity's sake, described constitutional diagram does not show all possible transition between states.In addition, most of incident transition cause producing the IPMI event message, and SNMP may hold back.

The INIT state is the original state of the switch ports themselves of illustration port status machine.When importing this state first, SFP enables, and produces the TX_ENABLE incident, unless described port is forbidden by managerial personnel.

When switch ports themselves enters the ENABLED state, check to determine whether to exist SFP.If there is SFP, then produce the MOD_DETECT incident.

The switch ports themselves that enters the FAULTED state is considered as shutting down.For transition goes out this state, need human intervention.

MOD_EXISTS-checks light signal when entering this state.If signal is normal, then produce the SIGNAL_DETECT incident.

Synchronous at SIGNAL state verification word.If signal is synchronous, then produce the SIGNAL_SYNC incident.

SYNCed。After signal Synchronization, check, consult automatically whether to finish to determine Ethernet.Automatically consult if finished Ethernet, then produce the AUTO_NEG_DONE incident.

In the UP state, switch ports themselves is UP, and frame can be forwarded to exchange board structure.Yet, do not understand the MAC Address of the node connected as yet.

Under the READY state, switch ports themselves moves.

In another embodiment of the present invention, along the route identical but use the full protocol engine discussed to dispose and implement the free of losses packet switch with the flow route described in the paper " Next Generation Internet protocol traffic route " (being that by founder Lawrence doctor G.Roberts of CTO Caspian Networks company on July 29th, 2003 provided in the SSGRR 2003S international conference that Italian L ' Aquila holds).The content of described paper is incorporated herein by reference.In addition, the content in this paper can extend to implements end-to-end flux control in full network protocol processing engine of the present invention, to meet the suggestion of IEEE 802.3AR working group about flow control and congestion management.

Be applied to comprise the level of an embodiment of full network protocol processing engine disclosed herein, can utilize engine (to form by the tertiary treatment device: the bit stream processor that (a) is attached in two required XAUI interfaces each according to " time-out " of QOS level; (b) search key or rule-based news affair priority identification traffic classification level for carrying out flow identification generation; (c) be used for to more upper-layer protocol storehouse or buffer-manager produce the processor level of suitable back pressure notice) implement, to meet of the expection suggestion of IEEE 802.3AR working group about flow control and congestion management.The paper of delivering at Asif Hazarika (ahazirik@fma.fujitsu.com) and Bob Brunner (Robert.Brunner@ericsson.com) " is selected to carry out congestion management (Congestion Management Why Priority/Class Based PAUSEis Required ?) based on " time-out " of priority/class for assorted one " introduce the demand of priority identification among the P802.3ar, the content of described paper is incorporated herein by reference.

So piece has two XAUI interfaces and one or two SPI4.2 interface that uses level processor to implement.After increasing news affair guides or switching stage, piece also can be used for discerning input flow rate and the Crypto engine that leads, and perhaps comes processing engine based on any other mark in VLAN mark or the tape identification.This can utilize 8SerDesPort Xilinx (FX-40) to implement.Perhaps, can use AMC.This card also satisfies the 3rd and requires (perhaps selecting XAUI to carry out I/O from RTM or from front panel).

Should be understood that and undertaken by full network protocol processing engine of the present invention aspect the flow processing,, claim that then described circuit is programmable if can change the function of circuit in each clock period.Usually be referred to as processor.Use instruction set architecture (ISA) and register file (RF) to come definition processor.Here it is is called as the processor of programmer's viewpoint, and is hardware and the interface between the software of carrying out on the described processor that constitutes processor.Referring to Thomas Henriksson " bag in Apple talk Data Stream Protocol Apple Ta processor (Intra-packet Data-FlowProtocol Processor) " ( Studies in Science and Technology, No. 813 disquisition) and " computer architecture: quantivative approach (Computer Architecture:A Quantitative Approach) " (Morgan KaufmanPublishers of John L.Henessy and David A.Patterson, Inc., ISBN 1-55860-329-8,1996 the 2nd edition), the content of described paper is incorporated herein by reference.Under background of the present invention, each cycle becomes a data interarrival time, must be in described interval time deal with data.Be similar to ISA, the level of full network protocol processing engine can be defined as flow PSA-flow and handle collection framework-and RF is defined as the pipeline register file.An ISA is one group of macrocode, and (instruction and/or data), decoding, deferred (to obtain more data), (to data) execution (instruction), storage sequence (von Neumann model) are got in its execution.The function that can represent flow PSA similarly.

Hereinafter describe all IPM controllers are connected to the embodiment that the used IPMI of cabinet in one embodiment of the present of invention expands.For illustrating in greater detail this aspect of embodiments of the invention, be called " the temporary patent application case that has the shelf Management Controller (Shelf ManagementController with Hardware/Software Implemented Dual RedundantConfiguration) of the dual redundant configuration that hardware/software implements with reference to the name that provides in the preamble.

Figure 36 A and 36B have illustrated the block scheme of shelf Management Controller according to an embodiment of the invention or shelf Management Controller 230.Shown in the block scheme of Figure 36 A and 36B, the invention provides the first shelf Management Controller 310, its second shelf Management Controller 315 with symmetric arrangement is coupled in communication mode, in order to providing redundant shelf management function with having work/standby framework that automatic fault shifts.In first embodiment, each in the shelf Management Controller 310 and 315 is identical on framework.Each shelf Management Controller 310 (315) comprises the independent processor 320 of operation small-scale operations system (OS) 325 (the ucLinux operating system that for example, has thin storehouse).Shelf Management Controller 310 (315) relies on independently power work, and obtains system's normal variable by autopolling intelligent platform management controller (IPMC) 235.That shelf Management Controller 310 (315) is configured to detect is unusual, recording events, generation and transmission warning be with unusual to notifications and start recovery operation.

Shown in Figure 36 A, each shelf Management Controller 310 (315) all is connected at least two I2C/IPMB bus IPMB-A 270 and IPMB-B 275.Shelf Management Controller 310 (315) can be arranged to active-active or active-passive I2C/IPMB fail-over mode.This embodiment of the present invention imagines unified message system, and it transmits the message on the abstract channel (AbCh).In this embodiment of the present invention, channel is a physical link, for example I2C, JTAG, renewal channel and free space.Viewpoint according to AbCh, each channel has such as capacity, time-delay and the CoS of principal and subordinate's channel of client-server channel, reciprocity channel, indication inquiry and response direction, bandwidth aspect or QoS, main path, alternative route, feedback channel attributes such as (for example, response or positive acknowledgement message transmission).Suppose that the able to programme or hardware of attribute obtains (for example) impact damper and assists.Can arbitrarily check all properties state, so it can support (for example) register.AbCh makes the messaging system can be arbitrarily or along with the demand route messages of system change.Preferably, can use the graphic user interface programming tool to come to create one or more channels, attribute is passed to hardware platform and measurement performance, operation emulation etc. for given hardware platform.Those skilled in the art recognizes that easily the ability that executes instruction can be expanded application program on EEPROM.

Again referring to Figure 36 A, will IPMI messaging system model according to the present invention illustrate and be dual client-server messaging system.The independence that client-server message transmission scheme between a plurality of shelf component uses the channel level of abstraction to come sustaining layer.Renewal channel 330 and the work control channel 335 of shelf Management Controller 310 by special use is coupled in communication mode with shelf Management Controller 315.Upgrade channel 330 and be adapted at the sound and status information of transmitted in both directions between the shelf Management Controller 310 (315).Two examples based on the messaging system of client-server are gone up operation at each shelf Management Controller 310 (315).In exemplary embodiments, (for example) but assigned work shelf Management Controller 310 (for example) are as server during system start-up, this does not deviate from scope of the present invention.Then, shelf Management Controller 315 is appointed as client computer.Work shelves Management Controller 310 when the status information that receives from IPMC 235 the fill order collection to implement the shelf management function.

In the embodiment of Figure 36 A and 36B graphic extension, the independent processor 320 of shelf Management Controller 310 (315) is through being set to and bit stream processor (Bit Stream Processor; BSP) 340 communicate, bit stream processor (BSP) 340 is equipped with at least one processor interface, and described processor interface (includes but not limited to the IPMI on the IPMB, command line interface (the CommandLine Interface on the serial port for all physical interface type; CLI), Telnet and SSH Secure Shell) be general.In one embodiment, shelf Management Controller 310 (315) comprises use, and for example bit stream processor 340, the RCMP-IPMI bridge 312 of enforcement, bit stream processor 340 bridge joint RMCP and IMPI message.When receiving RMCP message bag from system administration manager, open bag and check udp port number.If udp port number and IPMI match messages then divest the header of bag and encapsulation IPMI header (if there is).Then, send a message to appropriate interface.Shelf Management Controller kernel may be asked " duplicating ".Encapsulation is sent to the IPMI message of system administration manager and sends by the system administration manager physical port.

Figure 37 A and 37B show the exemplary of the I2C hardware finite state machine 475 that uses BSP 440.In the present embodiment, BSP is according to full agreement bit stream processor of the present invention.Configuration BSP handles the bit stream on IPMB-A270 and IPMB-B 275 buses is carried out linear speed bag data routing.BSP is fit to protocol data (information) unit of the bit combination in the bit stream to definition, and protocol data (information) unit that collects is handled, so that how the agreement that runs into all provides the linear speed handling capacity.Above-mentioned two kinds of functions all can use (for example) register access control/submodule access controller (487/489) as described below to carry out dynamically programmable.Therefore, the information unit of agreement or the processing rule that is applicable to protocol data (information) unit all inherently can the dynamical fashion changes.

In one embodiment, hardware finite state machine 475 comprises the bit stream processor 440 that disposes selected pipeline stages engine sequence.Each grade engine all has different, extendible and re-programmable framework, for each IPMC 235 to hardware finite state machine 475 message transfers (for example system is normal, temperature, rotation speed of the fan etc.), described framework all forms device finite state machine (the device finite statemachine of instantiation; DFSM) 480.DFSM 480 preferable data flow communication at the level engine that leads to BSP 440 are configured, and described level engine is fit to form the example that message is transmitted finite state machine (MFSM) 485.Usually, hardware finite state machine (and DFSM and MFSM) uses three basic structures.The hardware finite state machine is kept: operation table, and it comprises the operation that will implement when receiving given incident when FSM is in given state; The NextState table, it comprises the NextState that will import when receiving given incident when FSM is in given state; Button.onrelease, it drives when running into incident and carries out event handling, searches and implement required operation, and upgrades current status information.By register access control 487 mechanism addressable level machine (or BSP or FPGA) control and status register files, thus with the microprocessor in the message-oriented level machine (or BSP or FPGA) of IPMI encapsulation, then, the actual register of described level machine (or BSP or FPGA) execution reads or writes.Microprocessor is as the register access controller, and it explains the register access control messages, and which forwarding logic assembly/submodule access controller 489 decision is addressed to message, and is convenient to the register access of submodule access controller.With resulting state/response return messages source.Register access control/submodule access controller 487/489 provides instant setting or revises the mode of the message delivery method of each device (being IPMC 235), thereby a kind of mechanism of implementing programmability level of the present invention and dirigibility is provided.

In one embodiment, hardware finite state machine 475 is fit to detect I2C bus failure and plant failure.If determine that fault is on the device that one of them monitored by IMPC 235, then shelf Management Controller 310 (315) is forbidden this device visit backboard.

Again referring to Figure 36 A, client computer 315 is used inquiry and the response of upgrading channels 330 follow-up work shelf Management Controllers 310, and calculates the state of transaction, and makes these states and work shelves Management Controller 310 synchronous.If the error condition that client computer shelf Management Controller 315 detects in the shelf Management Controller 310, then it gives system administration manager 265 with described event report, system administration manager 265, and makes standby shelf Management Controller 315 can finish fault to shift and need not carry out state consuming time and upgrade removing work shelves Management Controller 310 as judge and action.Although the present invention is adapted at AdvancedTCA well and is obedient in the system and moves, it also can (wherein ternary standby as stipulating among Figure 36 B) work in the MicroTCA environment.

In another embodiment, shelf Management Controller 310 (315) is strengthened by the protocol stack of thin hardware assist.Another embodiment of system implements OS and walks around scheme, to guarantee to obtain microminiature and manageable shelf Management Controller embodiment.Main embodiment comprises that EEPROM with execution command, for example uses SOC (system on a chip) (System-On-Chip; SOC) EEPROM that has the microminiature chip of notion, it can make the function of shelf Management Controller processor 320 be expanded on the basis of saving cost.

In one embodiment, use 310 (315) configurations of dual redundant shelf Management Controller to introduce the fault-tolerant operation of shelf Management Controller.In first embodiment, insert checkpoint by in hardware finite state machine 475, increasing extra checkpoint state.When the current state in the hardware finite state machine 475 is the checkpoint state, can start the checkpoint process.When misdirection, hardware finite state machine 475 can shift by the fault that private bus 335 starts to shelf Management Controller 315, and starts rejuvenation on shelf Management Controller 310, and can not introduce unusual in the ATCA shelf.Can by reset with its original order be stored in recording status on the shelf Management Controller 315 produce the fault of shelf Management Controller 310 again before state finish rejuvenation with the internal fault status of recovering shelf Management Controller 310.In another embodiment, can use extra shelf Management Controller 492 to strengthen shelf Management Controller 310 (315), and obtain correct state by between three or more state backups that remain between three or more the shelf Management Controllers, putting to the vote.In one embodiment, voting result is loaded in the register of each hardware finite state machine 475, so that solve the voting of any conflict.

In one embodiment of the present of invention shown in Figure 38, shown the bit stream protocol processor (perhaps be called bridge, or abbreviate the bit stream protocol processor as) that SPI4.2 is provided to XUAI bidirectional bridge framework based on the bit stream protocol processor.First type Serial Data Transport Interface is equivalent to the SPI4.2 interface, and second type Serial Data Transport Interface is the XAUI interface.

The bit stream protocol processor of present embodiment provides dual SPI4.2 to the XAUI bridge.SPI4.2 provides parallel, point-to-point, bidirectional interface.The SPI4.2 framing is supported up to maximum 256 ports.Use 16 LVDS data channels,, data are sent by the SPI4.2 frame with a complete bag or a plurality of data burst.The control word header that is attached on the sub-channel data is described burst.Use bag starting point position (S) in the control word and end-of-packet mode bit (EOPS) to identify the complete packet that to form by a plurality of bursts.Use address bit [0:7] to define subchannel.For each subchannel, flow control and status information transmission are gone out band.The interface bandwidth scope can be from 10Gbit/s (using for low expense) to 20Gbit/s (for such as needing bandwidth to quicken to support the application such as exchange board structure of Overhead).

Should see that for 10GgiE, each stream protocol processor can be supported the 10Gbps full duplex by every port, make to reach 2.560Tbps exchange throughput capacity.For 40GgiE, each stream protocol processor can be supported the 40Gbs full duplex by every port, makes to reach 10Tbps exchange throughput capacity.Usually, it should be understood that the reconfigurable and programmability according to full protocol engine of the present invention allows processor can expand inherently in a plurality of clock speed scopes.

It should be understood that bit stream protocol processor according to an embodiment of the invention can between the system processor (CPU) of (for example) PC and system storage, provide N interconnected.During N is interconnected each all can be configured to the speed transmission data of 40Gbps, thereby causes the 10N Gbps handling capacity expanded.SPI4.2 is the point-to-point interface between the mutually positioning device in several inches.In system, expect that usually the intercommunicated backboard of crossing is positioned on the interior different cards of cabinet (Intra-Chassis) or is positioned at SPI4.2 device on the different cabinets (Inter-Chassis).In these cases, advantageously use serial point-to-point link of the present invention, it is provided at Intra-Chassis and is connected with high bandwidth under the Inter-Chassis environment.The exemplary series link comprises the ASI that uses PCI-Express, the Ethernet that uses XAUI, and the Infiniband that uses IB.In fact this be converted into use " dummy line " interface and connect hundreds of geographical any two of going up in the SPI4.2 device of isolating.In one embodiment, the present invention can be configured and be single board computer (PC).In another embodiment, the invention provides industrial standard (for example picoTCA) cabinet that has detachable attaching blade,, can buy described blade in the scene when carrying out the terminal user when upgrading.

For use serial link or via dummy line with transmission control word (comprising band external flux control information available on port address, data and the parallel SPI4.2 interface), utilize tunnel protocol.For guaranteeing the high bandwidth utilization, these tunnel protocols are preferably light weight.Tunnelling function can be embedded into the SPI4.2 device or can be used in combination in the bridge chip that this conversion is provided with the SPI4.2 device.For supporting to utilize the various serial line interfaces that use increasingly mature tunnel protocol to carrying out this bridge joint between the SPI4.2 device, described bridge is programmable.In the present embodiment, provide with the SPI4.2 interface of XAUI based on the bridge of bit stream protocol processor and be used for other serial line interface and the flexible means of various tunnel protocols.The bit stream protocol processor provides dynamic programming described in the appendix A and function expansibility, and appendix A is incorporated herein in full.

Referring now to Figure 39,, wherein shown another embodiment of bit stream protocol processor.In the present embodiment, direct and Front Side Bus (the Front Side Bus of bit stream protocol processor; FSB) how many interfaces has saved thus in conjunction with the conversion process in the described bit stream protocol processor of Figure 38.In addition, the bit stream protocol processor among Figure 39 provides tubule and extra heavy pipe parallel-to-serial converter, and therefore permission is disposed at extra heavy pipe one or more ethernet ports are carried out the selectivity integration.

In one embodiment, the bit stream protocol processor makes it possible to carry out linear speed QoS packet switch, utilizes the next communication of implementing in Ethernet based on single token (token) of described linear speed QoS packet switch.Use source address (SourceAddress; SA) and destination address (Destination Address; DA) and such as the E type of VLAN label come unique token between the negotiation communication link upper extreme point.The expansion of E type for example can be, request " unique identifier " or " token permission "; Carry out data communication and request withdrawal token with the token of permission.In case token obtains permission, use source address and DAF destination address field to transmit the short date together with the E type.This also can expand to and comprise the big data block that is used for STA and SAS.In other embodiments, in case at end points with connect between the intermediate node of these end points and consult unique identifier, the measurable performance when then using fixing frame sign to come to give the transmission anchor-frame to link, and therefore satisfy various delay requirements.For example, can use source address/destination address to transmitting 12 byte datas, 2 E type-words joints and 2 bytes " sign ", rather than be used for the 64 traditional byte loads of conventional Ethernet bag.For illustrating in greater detail an embodiment of this expansion ethernet communication technology, with reference to the temporary patent application case of the title that identifies in the preamble for " being used in the limited neighborhood enhancing Ethernet protocol " based on the shortening Frame of unique identifier.

In another embodiment, described same interface can be the frame that Disc (data are followed E-Type and TAG) provides fixing 2K block size.In this respect, the present invention can realize programmable frame sign Ethernet structure, rather than the variable frame size structure of prior art.This function is particularly useful in the application of iTDM type, because its interior encapsulation of scope TDM news that can be implemented in ATCA are engaged in.

In one embodiment, the ethernet vlan header is as tunnel protocol, so that the industrial standard Ethernet switch can be used to any two SPI4.2 devices that exchange is arranged in " cabinet " or " between cabinet " environment.Main embodiment of the present invention uses lucky position Ethernet (GbE) as second Data Transport Protocol.Can use other agreement, and not deviate from scope of the present invention.SPI4.2 control word and flow control information are converted to the standard ethernet vlan header.At inlet SPI4.2 sub-channel data and header information are encapsulated.In outlet, divest the header information of ethernet frame and convert it back to the SPI4.2 frame, and flow control information is converted into the SPI4.2 electric signal.In addition, the bit stream protocol processor is provided for embedding the effective means of " class " of information on services, and the programmable way that is used to produce and propagate congestion management message.

In one embodiment, the bit stream protocol processor is configured to support such as interfaces such as GbE, PCI-Express, RGMII, pci bus and universal serial bus, so that it becomes the desirable fexible unit that uses in ATCA and microTCA system.Those skilled in the art will recognize that, also (for example can use other interconnection technique, XS410 lucky position Ethernet and HiGig SPI4.2 bridge from MorethanIP company) the SPI4.2 interface bridge is received the XAUI interface, to satisfy a plurality of designing requirements, the bag or the Ethernet on the SONET/SDH that for example install on bridge joint (for example, NPU is bridged to Ethernet switch), the application of serial backboard, the SONET/SDH are used.

The intercommunicated function of crossing on the different cards that backboard is positioned at " in the cabinet " or being positioned at the SPI4.2 device of " between cabinet " provided by the invention makes one embodiment of the present of invention can realize measured PC, for example, based on the PC framework of picoTCA or microTCA standard.

An embodiment of the bit stream protocol processor of graphic extension among Figure 38 and 39 advantageously utilizes register access control/submodule access controller controller, and it gives dynamic programming and functional expansionary to the bit stream protocol processor.Use register access control/submodule access controller controller architecture contraposition stream protocol processor to programme immediately.Can use the resident blade (plate) thereon of this function contraposition stream protocol processor to be configured.In one embodiment, use instant dynamic programming function to connect or close blade (plate), blade is brought into shifted out computer system thus.In another embodiment, can use instant dynamic programming function to change the characteristic of bridge, so that make its bridge joint between (for example) SPI4.2 and PCI-Express.Those skilled in the art will recognize that, can use register access control/submodule access controller controller to implement other configuration variation within the scope of the present invention.For example, can use programmability to come to implement real end-to-end QoS at difference news affair flow by computer system.

In another embodiment, the bit stream protocol processor can be realized the exchange by the precedence arrangement.In conjunction with the modularization described in the last period and can expand picoTCA PC framework, the invention enables the N layer layering that can form multiprocessor, wherein N both had been independent of hardware, can come Dynamic Selection by the priority that change gives different processor subclass in the bit stream protocol processor arbitration framework again.Present embodiment makes PC can be configured to shared storage type machine and message transmission type multiprocessor machine.Perhaps, PC according to an embodiment of the invention can be configured to server, storage area network controller, based on high performance network node in the model of grid computing or the switch/router in the communication network.It should be understood that when needed, same basic machine can be changed in the previously described specific purposes machine one or more by programming mode or manual mode.

Those skilled in the art are easy to described method is carried out various changes after reading this disclosure.Scope of the present invention is not subjected to content constraints above, and it is limited by the claim in the preamble only.

Appendix A

Act on behalf of file number:

3510.35WO01

1) state machine (suppose that the 63rd is least significant bit (LSB) (msb), and suppose that the 0th byte is highest significant position (MSB)) input (address: 10):

State: (5) state variable allows 32 kinds of states.Usually just the form of depositing of state output (NextState), it can change according to lookup result etc.Referring to NextState (Next Layer/State) part.

Input: the control input of (5) state machine.These 5 is the output of multiplexer, and this multiplexer is used to select various comparers outputs, from the flag of previous state and data or the like.

Output

(49): 5 openings

State: (5) state variable.Be fed to the NextState logic.Explanation referring to the state importation.

The RegWr:(3 position) register writes and enables signal, be used for layer sign indicating number (LayerCode) register with in use register.(64 bit register)

0: write disabled

1: write general-purpose register.RegVal is the position of the data that will write.

2: write LayerCode2.RegVal is a value.

3: write VLAN.RegVal is the quantity of VLAN

4: write MPLS.RegVal is the quantity of MPLS mark

5: write LayerCode3.RegVal is a value.

6: write LayerCode4.RegVal is a value.

7: write LayerCodeN.RegVal is a value.This register is user-defined.

The RegVal:(4 position) as if RegWr/=1, then this is the value that will write in the register.

If then this is the end nib (Right Aligns) of the data that will write to RegWr=1..

(, seeing also comparer/search allocation list part) about the summary description of following input

The LU_en:(1 position) searches enabling of random access memory (LookUp RAM) (and comparer)

0: enable Comp0a and CompLT

1: enable LU and Comp1

The LU_size:(1 position) size of searching (LookUp) that will carry out

The 0:8 position

The 1:16 position

The LU_stage:(1 position) the pipeline stages selector switch that is used to search.

0: level 1

1: level 2

The LU_nlb:(4 position) the end nib (Right Aligns) of the data that will search.

The CompEn:(1 position) comparer enables.

0: enable Comp0a, Comp0b and CompLT

1: enable Comp1 and Comp2

The CompByte:(3 position) the end byte of Comp0a, CompLT and Comp1

The CompByte2:(3 position) the end byte of Comp0b and Comp2

The CompSel:(3 position) is used for the fiducial value/mask selector switch of the register array of Comp0a, CompLT and Comp1

The CompSel2:(3 position) is used for the fiducial value/mask selector switch of the register array of Comp0b and Comp2

The CountSize:(2 position) people from unit of the value in the regulation count value field is little

The 0:8 position? the 2:32 position (IPv4, TCP)

The 1:16 position? 3:64 position (IPv6)

The CountSel:(1 position) how to select pad count device register

0: counter register is written into the value among the CountVal.

1: counter register is written into the data (Right Aligns) with CountVal nib ending pointed.

The CountVal:(4 position) as if CountSel=0, then this value is written to counter register.

If CountSel=1, then nib position (Right Aligns) is written to counter register.

Enable by nonzero value and to write.

CountStage:(2 should) be used to be written to the pipeline stages selector switch of counter register.

The SOL:(2 position) new layer where the beginning in present data word of indication.Present the SOL input.

The Tag:(5 position) label (Tag) is indicated each layer to begin and is where ended at.Its definition is referring to the ## part.

The Error:(1 position) mistake flag.(treat decision (TBD): coding can be shared or be special-purpose.)

State machine storer detail drawing

2) comparer/search allocation list (out-of-date)

The comparer detail drawing

3.Look UP/Next State (searching/NextState) logic

The final output of searching (Look Up) agreement is the NextState of decision finite state machine (FSM).For each port in these 2 ports, the output of searching block random access memory (LookUp BRAM) is 18.For greater than search (a for example E-type) of 10, search data and will between these ports, divide.The output vector of these 2 ports will be carried out and (AND) computing, and in the one-hot mode each result's row (result lines) be decoded, thereby allow to exist the agreement of 18 kinds of uniquenesses.(the block random access memory is changed over 512 * 36 from 1k * 18 36 kinds of possible agreements can be provided, but regularly ...).Have one group of 18 register that comprises " NextState ", wherein each register is all corresponding to an output row/agreement.Packet starting point (Start of Packet; SOP) and packet ending (End of Packet; EOP) also will have corresponding status register.Perhaps, the output of searching the block random access memory can be a kind of state that directly is in minimum 5.This is indicated by upper port is exported to encode.This coding is fed to comparer, to check with reference to a register.These two state vectors are fed to the NextState multiplexer.NextState from finite state machine provides the 3rd input state to next state logic.Packet starting point and packet ending have corresponding status register, and these status registers also belong to input.Then, deposit this result phase and it is fed back to finite state machine.

Search the detail drawing of storer

4. Ethernet constitutional diagram example

5. the example of Ethernet instruction

Below be the position/byte benchmark of byte order in this instruction example:

63 32 31 0

Byte 0	Byte 1	Byte 2	Byte 3	Byte 4	Byte 5	Byte 6	Byte 7
								?7	?6	?5	?4	?3	?2	?1	?0

6. Ceng label (preliminary label)

00 null value/free time can only insert between each frame

01 valid data (not being other type)

02 L2 in preceding 32 begins and the beginning of Payload

03 beginning of L2 in whole 64

04 beginning of L2 in preceding 32, the and then beginning of L2.5 in back 32

05 beginning of L2 in preceding 32, the and then beginning of L3 in back 32

06 beginning of L2 in preceding 32, the and then beginning of Payload in back 32

07 L2 reserves

08 ------------------

The beginning of L2.5 in whole 64

09

The beginning of L2.5 in back 32

0a

The beginning of L2.5 in preceding 32, the and then beginning of L3 in back 32

0b

The beginning of L2.5 in preceding 32, the and then beginning of Payload in back 32

0c

L2.5 reserves

0d

The beginning of L3 in whole 64

0e

The beginning of L3 in back 32

0f

The beginning of L3 in preceding 32, the and then beginning of L4 in back 32

10

The beginning of L3 in preceding 32, the and then beginning of Payload in back 32

11

L3 reserves

12

The beginning of L4 in whole 64

13

The beginning of L4 in back 32

14

15 L4 reserve

16 beginnings of Payload in preceding 32

17 beginnings of Payload in back 32

18 EOPa, all bytes are all effective

19 EOPb are not that all bytes are all effective.MSBytc (it is invalid certainly) comprises the quantity of effective byte

1a EOPa reaches the beginning of L4 in preceding 32

1b EOPa reaches the beginning of L4 in back 32

1c EOPb reaches the beginning of L4 in preceding 32

1d EOPb reaches the beginning of L4 in back 32

But 1e User Defined

But 1f User Defined

The SAP value

04 IBM?SNA

06 ^＊ IP

80 3Com

AA ^＊ SNAP

BC 8anyan

EO ^＊ Novell(1PX)

F4 LAN?Manager?FE

Appendix B

Act on behalf of file number:

3510.35WO01

12 appendix B1-IPMI expansion

12.1 message

Intelligent Platform Management Bus (IPMB) is defined as a kind of two universal serial bus (dual serial bus) that are used for connecting all intelligent platform managements of base plate (IPM) controller.The Intelligent Platform Management Bus agreement is the information receiving system of a kind of request/response type, and source and the destination and the predetermined bid value of its indication one request, this predetermined bid value are used to the operation of indicating this request to originate and will carry out.

Any data byte relevant with this command request, all follow command byte back, verification and before.

Below each table show the main body respectively ask and receive the response.

The Intelligent Platform Management Bus request

The IPMI response

The rsSA-transponder from the address

The rqSA-requester from the address

The LUN of rsLUN/rqLUN-transponder/requester

NetFn-network function (all CEN IPMI extended message will be us 0x31)

The operation that cmd-will carry out

Check and-2 complement sum of each byte of front.CHECKSUM is set to 0 when beginning, for each subsequent byte: CHECKSUM=(CHECKSUM+data byte) modulo 256.At CHECKSUM=CHECKSUM with verification and before writing this message.After receiving, will carry out after message byte and verification and the addition 256 being the computing of mould, end value is 0 to show that promptly data are effective.

All CEN IPMI extended message (request and respond) all comprise the header of byte, the extended arithmetic that will carry out according to following table in order to indication:

CEN IPMI explosion command

The command byte value	Explanation
		0x01	RAC message
0x02	The CAM updating message

12.1.1RAC message

RAC message is used for reading the register data of forwarding logic.Following table shows the form of RAC message.RAC message is:

The RAC request message format

The RAC response message format

12.1.2 Content Addressable Memory (CAM) updating message

The Content Addressable Memory updating message

13 appendix B2-forwarding logic register files

Following table shows the forwarding logic register that can conduct interviews by RAC.The forwarding logic register is 64 bit registers, has skew with respect to the base address that maps to logical function/module.The base address is transformed into preceding 4 of RAC message addresses, and 7 of all the other of this address are the indicator register side-play amount then.According to following table conversion is carried out in the base address:

The conversion of table 1 base address

The base address	RAC message transformation (preceding 4)	The module title	The register side-play amount	The register title
					0xb0000000	?0x0	QDREGR	0x0	Status register
			0x1	Configuration register
								0x2	Tested word 1 successful counter
			0x3	Tested word 2 successful counters
								0x4	The not successful counter of tested word 1
			0x5	The not successful counter of tested word 2
					0xb0010000	0x1	QDR?IN		?QDR?IN
			0x0-0x5	Identical with QDR EGR
					0xb0020000	0x2	SPI4.2PHY		?SPI4.2PHY
			0x0	Status register
								0x1	Configuration register

			0x2	The success counter
								0x3	Not successful counter
			0x4	RX SOP counter
								0x5	RX SOF counter
			0x6	RX EOP counter
								0x7	RX EOF counter
			0x8	The RX error counter
								0x9	TX SOP counter
			0xa	TX SOF counter
								0xb	TX EOP counter
			0xc	TX EOF counter
								0xd	The TX error counter
0xb0030000	0x3	SPI4.2-SPI4.2	0x0-0xd	Identical with SPI4.2PHY
					0xb0040000	0x4	XAUI?SYS	0x0	Status register
			0x1	Configuration register
								0x2	The success counter
			0x3	Not successful counter
					0xb0050000	0x5	XAUIA	0x0-0x3	Identical with XAUI SYS
0xb0060000	0x6	XC40	0x0-0x3	Identical with XAUI SYS
					0xb0070000	0x7	XC50	0x0-0x3	Identical with XAUI SYS

Table 2QDR EGR/IN status register

Success/success one test is not finished, in single operational mode

Table 3QDR EGR/IN configuration register

Table 4 test data is selected

The command byte value	Explanation
		‘000’	Complete 0
‘001’	Complete 1
		‘010’	Full A
‘011’	Complete 5
		‘100’	Alternately be A and 5
‘101’	It alternately is F and 0
		‘110’	Alternately be 5 and A
‘111’	Alternately be 0 and F

Beginning-beginning diagnostic test

All-all patterns of operation, ignore " test data selection "

Operation test always-ad infinitum

Zero clearing-with success/unsuccessful counter O reset

Table 5 SPI4.2 PHY/SPI4.2 status register

Table 6 SPI4.2 PHY/SPI4.2 configuration register

The UCDR-user_clk territory resets

The UC2DR-user_clk_2x territory resets

LOOP-RX to TX loopback

Beginning-beginning diagnostic test

Operation test always-ad infinitum

RDR-rdclk dcm resets

Zero clearing-with success/unsuccessful counter O reset

Operate-make the interface and be in operator scheme, ignore loopback and diagnostic mode

Table 7 XAUI SYS/A/XC40/XC50

Loopback-make transceiver be in the loopback state

Power supply-transceiver is cut off the power supply

Local reset-this earth fault is resetted

The state RX linking status that resets-make resets

TX tests-enables the TX test

TX tests selection-TBD

The XAUI XAUI core that resets-make resets

The 0-that resets resets transceiver 0

The 1-that resets resets transceiver 1

The 2-that resets resets transceiver 2

The 3-that resets resets transceiver 3

The test of operation-operational diagnostics

Operation-operator scheme

Zero clearing-make counter O reset

The clock circulation delay-in the clock cyclic delay values between each TX frame between diagnostic period

The frame length of representing with byte number in frame length-diagnostic mode

Claims (9)

1. full protocol data packet processing engine, it is used for management processor and has data packet communication between the express network framework of linear speed of at least 10 lucky bps, and described processing data packets engine comprises:

The intake section of described processing data packets engine, it comprises:

A plurality of inlet bit stream level processors, each inlet bit stream level processor all have this inlet bit stream level processor exclusive control store able to programme;

And the gateway interface between the described processor;

And the inlet network interface between the described network architecture; And

Multi-ported Data stream packet memory, it is operably connected to described a plurality of inlet bit stream level processor, described gateway interface and described inlet network interface; And

The exit portion of described processing data packets engine, it comprises:

A plurality of outlet bit stream level processors, each outlet bit stream level processor all have this outlet bit stream level processor exclusive control store able to programme;

And the outlet processor interface between the described processor;

And the outlet network interface between the described network architecture; And

Multi-ported Data stream packet memory, it is operably connected to described a plurality of outlet bit stream level processor, described outlet processor interface and described outlet network interface;

Wherein, one of them agreement that the described control store of each all can be based upon in a plurality of agreements that the given data stream of one or more packets determines in the described bit stream level processor is carried out independent, selectable dynamic programming, and described bit stream level processor is bit stream data stream by described Multi-ported Data stream packet memory with described given Data Stream Processing, so that the processing that described a plurality of bit stream level processor carries out described given data stream is carried out timing according to described bit stream data stream, and described bit stream data stream is to set up with a speed, and described speed is used in the described processing data packets engine of all described a plurality of agreements and can be in fact moves continuously with the speed of the described linear speed that equals described express network framework at least.

2. processing data packets engine as claimed in claim 1 is characterized in that described a plurality of bit stream level processors of the described intake section of described processing data packets engine comprise:

Input stage bit stream processor, the Physical layer of itself and described inlet network interface are situated between and connect, and according to one of them agreement in described a plurality of agreements of determining at described given packet, set up the frame of described bit stream data stream;

The compole state machine, it analyzes described frame according to one of them agreement in described a plurality of agreements of determining at described given packet;

News affair level processor, it carries out frame to the described frame of being analyzed by described compole state machine and handles;

The scheduler stage processor, its management is from the output of the described frame of described news affair level processor; And

The output stage bit stream processor, it will be situated between and connect from the described described frame of condition handler and the Physical layer of described gateway interface through scheduling.

3. processing data packets engine as claimed in claim 2, it is characterized in that when described compole state machine is analyzed described frame, described compole state machine utilizes cipher key lookup to arrange, described cipher key lookup arranges and comprises programmable very long instruction word traffic classifier that the key that described traffic classifier is arranged described cipher key lookup produces pipelining.

4. processing data packets engine as claimed in claim 2, it is characterized in that described news affair level processor is configured to the data flow processor with a plurality of sections, wherein basis is at described one of them agreement in the definite described a plurality of agreements of described given data stream, the described a plurality of sections in the described news affair of the dynamic construction level processor.

5. processing data packets engine as claimed in claim 1, the at least a portion that it is characterized in that described bit stream level processor is used the wherein a kind of method in arbitration or the time division multiplexing method to be situated between with corresponding Multi-ported Data stream packet memory and is connect, so that do not need during the some or all data in handling described given data stream in the described bit stream level processor each all to duplicate these data.

6. processing data packets engine as claimed in claim 1, it is characterized in that each described control store in the described bit stream level processor can be selected from one of them in command memory or the status register, and can use register access control and submodule access control system carry out independent, selectively dynamically reconfigure and programme.

7. processing data packets engine as claimed in claim 6, it is characterized in that described register access is controlled and the submodule access control system is controlled code generation, flow control, performance report, diagnosis and the maintenance of the described processing data packets engine of described graphical user interface management by graphic user interface.

8. processing data packets engine as claimed in claim 1 is characterized in that described express network framework is selected from the set of being made up of following network: storage network, communication network, processor network or its arbitrary combination.

9. processing data packets engine as claimed in claim 1 is characterized in that further comprising:

Multiport high-speed data packet switching exchange,

Wherein a plurality of processing data packets engines are operably connected to described multi port switch respectively, arrange to form full protocol bridge, and in wherein said a plurality of processing data packets engine each all are connected to the different express networks that use different agreement to communicate.

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