CN101521164A - Lead-bonding chip-scale packaging method - Google Patents
Lead-bonding chip-scale packaging method Download PDFInfo
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- CN101521164A CN101521164A CN 200810033895 CN200810033895A CN101521164A CN 101521164 A CN101521164 A CN 101521164A CN 200810033895 CN200810033895 CN 200810033895 CN 200810033895 A CN200810033895 A CN 200810033895A CN 101521164 A CN101521164 A CN 101521164A
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Abstract
本发明提供了一种引线键合芯片级封装方法，包括如下步骤：提供带有若干半导体器件的晶圆；将第一个半导体器件的表面的焊盘与相邻的半导体器件的表面的焊盘通过引线相连接，形成若干个由第一个半导体器件与相邻半导体器件相连接构成的半导体器件组；在晶圆的上表面涂覆绝缘胶；对晶圆进行第二次切割；在晶圆的第二次切割表面涂覆绝缘胶；在露出来的硅层上生长导电层；沿着半导体器件组的边界进行切割形成独立的封装器件。本发明还提供了另外一种引线键合芯片级封装方法。本发明的优点在于不需要特殊的先进工艺设备和特殊芯片布局，降低制造成本；封装器件被绝缘胶包裹，充分的保护芯片不受诸如湿气等环境因素的损害，提高器件的使用寿命。
The invention provides a wire bonding chip-level packaging method, comprising the steps of: providing a wafer with a plurality of semiconductor devices; Connected by wires to form several semiconductor device groups composed of the first semiconductor device and adjacent semiconductor devices; apply insulating glue on the upper surface of the wafer; cut the wafer for the second time; The second cutting surface is coated with insulating glue; a conductive layer is grown on the exposed silicon layer; cutting is performed along the boundary of the semiconductor device group to form an independent packaging device. The invention also provides another wire bonding chip-level packaging method. The advantages of the present invention are that no special advanced process equipment and special chip layout are required, and the manufacturing cost is reduced; the packaged device is wrapped by insulating glue, which fully protects the chip from environmental factors such as moisture and improves the service life of the device.
Description
[technical field]
The present invention relates to the semiconductor packages field, particularly comprise lead-bonding chip-scale packaging method.
[background technology]
Along with the development of society, society to the requirement of chip to littler, thinner development.A method that reduces the electronic device volume is exactly to increase the space that the complexity of chip reduces to occupy in device.Simultaneously, the volume that dwindles the Chip Packaging shell also can reach this target.Traditional Chip Packaging shell is that metal framework of employing comes the signal of telecommunication between the inside and outside pin of turning circuit, but the size of traditional package casing can be subjected to the restriction of size lead frame.
Demand to miniaturized device has also promoted more advanced Development of Packaging Technology, is exactly the encapsulation technology of a kind of advanced person in the present semiconductor packages field as wafer-level package technology (CSP).The wafer-level package technological development littler exterior contour and solder side.Different with traditional semiconductor packaging employing lead frame is that the wafer-level package technology adopts metallization to generate contact-making surface, realizes inside chip and the extraneous function that contacts.In addition, chip gets up with black glue plastic packaging and is not subjected to the influence of environment and prevents warpage with protection.The volume of the volume of semiconductor device and chip itself was very approaching after the employing of above technology made and encapsulates, and can not cause the volume of encapsulation back semiconductor chip obviously to increase.The reducing of encapsulation volume helps the volume that integrated more circuit is simultaneously strengthened the function of electronic device and dwindled whole electronic function device.
The shortcoming of traditional CSP is to need to adopt more advanced process equipment and special chip layout, has improved the technology cost of encapsulation; And the chip that traditional CSP encapsulation technology can't be protected fully is not subjected to the infringement such as environmental factors such as moistures, can influence the useful life of device like this.
[summary of the invention]
Technical problem to be solved by this invention is; a kind of special advanced technologies equipment and chip-scale packaging method of special chip layout of not needing is provided; reduce the technology cost; and this method can protect chip not to be subjected to infringement such as environmental factors such as moistures fully, improves the useful life of device.
In order to address the above problem, the invention provides a kind of lead-bonding chip-scale packaging method, comprise the steps: to provide the wafer that has the several semiconductor device, these devices all separate each other by scribe area, and each semiconductor device has a pad at least; Wafer is carried out the cutting first time,, and do not cut the transcrystalline circle from the upper surface cutting scribe area of wafer; The pad on the surface of first semiconductor device pad with the surface of adjacent semiconductor device is connected by lead-in wire, forms the semiconductor device group that several are connected to form by first semiconductor device and adjacent semiconductor device; Upper surface at wafer applies insulating cement, and insulating cement fills up the cutting groove that cutting for the first time forms, and covers the lead-in wire on semiconductor device group surface; Wafer is carried out the cutting second time, cut corresponding zone from the lower surface cutting and the first time of wafer; Cut the surface-coated insulating cement in the second time of wafer, fill up the cutting groove that cutting for the second time forms; The wafer polishing back side is to exposing silicon layer; The conductive layer of on the pad that exposes, growing; Border cutting along the semiconductor device group forms independently packaging, and formed packaging comprises the semiconductor device group that is connected to form by one or more lead-in wire by first semiconductor device semiconductor device adjacent with several.
Optionally, described lead-in wire is insulated the glue plastic packaging fully.
Optionally, described insulating cement is black glue.
Optionally, described pad by adjacent two semiconductor device of lead-in wire connection is included in and adds the conductive solder projection on the pad on first semiconductor device and the adjacent semiconductor device surface.
Optionally, the cutting groove degree of depth sum of the cutting groove of the described cutting first time and cutting for the second time is not less than the thickness of wafer.
Optionally, the cutting groove width of the described cutting first time is less than the width of the cutting groove that cuts for the second time.
Optionally, the material of described conductive layer of growing on the pad that exposes is a metal.
Optionally, an Active Terminal on described first semiconductor device has been connected to the pad on the first surface of wafer, other Active Terminal is positioned at the second surface of wafer reverse side on first semiconductor device, and on corresponding other his pad of first surface that has been connected to wafer by its second adjacent semiconductor device.
The present invention also provides another kind of lead-bonding chip-scale packaging method, comprises the steps: to provide the wafer that has the several semiconductor device, and these devices all separate each other by scribe area, and each semiconductor device has a pad at least; Grind the design thickness of wafer rear to chip; Wafer is carried out the cutting first time,, and do not cut the transcrystalline circle from the upper surface cutting scribe area of wafer; At wafer rear growth conductive layer; Zone along cutting is for the first time carried out the cutting second time at the upper surface of wafer to wafer, and does not cut the transcrystalline circle; The pad on the surface of first semiconductor device pad with the surface of adjacent semiconductor device is connected by lead-in wire, forms the semiconductor device group that several are connected to form by first semiconductor device and adjacent semiconductor device; Upper surface at wafer applies insulating cement, the cutting groove that insulating cement fills up for the first time and cutting for the second time forms; Wafer is cut for the third time, and the back side of cutting crystal wafer is to exposing the insulating cement that cuts for the second time in the cutting groove that forms; In the cutting groove for the third time of wafer rear, apply insulating cement; Border cutting along the semiconductor device group forms independently packaging, and formed packaging comprises the semiconductor device group that is connected to form by one or more lead-in wire by first semiconductor device semiconductor device adjacent with several.
Optionally, described lead-in wire is insulated the glue plastic packaging fully.
Optionally, the described insulating cement that applies after cutting groove does not for the third time cover pad.
Optionally, described insulating cement is black glue.
Optionally, described conductive layer in wafer rear growth covers the back side of whole wafer.
Optionally, the material of described conductive layer is a metal.
Optionally, the cutting groove width of described cutting for the third time is greater than the cutting groove width that cuts for the first time.
Optionally, the cutting groove degree of depth of described cutting for the third time is greater than the cutting groove degree of depth of cutting for the first time.
Optionally, the cutting groove width of described cutting for the third time is greater than the cutting groove width that cuts for the second time.
Optionally, described pad by adjacent two semiconductor device of lead-in wire connection is included in and adds the conductive solder projection on the pad on first semiconductor device and the adjacent semiconductor device surface.
Optionally, the cutting groove degree of depth sum of the cutting groove of the described cutting second time and cutting for the third time is not less than the thickness of wafer.
Optionally, an Active Terminal on described first semiconductor device has been connected to corresponding bonding pad on the semiconductor device group surface, and other Active Terminal has been connected on the corresponding pad in semiconductor device group surface by its other adjacent semiconductor device on first semiconductor device.
The invention has the advantages that:
1, process provided by the invention does not need the special advanced technologies equipment and the chip-scale packaging method of special chip layout, reduces manufacturing cost.
2, all surfaces of packaging are insulated glue parcel, protect chip not to be subjected to infringement such as environmental factors such as moistures, the useful life of improving device fully.
[description of drawings]
Accompanying drawing 1 is depicted as the process chart of first kind of embodiment of lead-bonding chip-scale packaging method provided by the present invention;
Accompanying drawing 2 to accompanying drawing 9 is depicted as the process schematic representation of first kind of embodiment of lead-bonding chip-scale packaging method provided by the present invention;
Accompanying drawing 10 is depicted as the process chart of second kind of embodiment of lead-bonding chip-scale packaging method provided by the present invention;
Accompanying drawing 11 is the process schematic representation of second kind of embodiment of lead-bonding chip-scale packaging method provided by the present invention to accompanying drawing 19.
[embodiment]
Below in conjunction with accompanying drawing the specific embodiment of the present invention is illustrated.
Be illustrated in figure 1 as the process chart of first kind of embodiment of lead-bonding chip-scale packaging method provided by the present invention.Execution in step S10 provides the wafer that has the several semiconductor device, and these devices all separate each other by scribe area, and each semiconductor device has a pad at least; Execution in step S11 carries out the cutting first time to wafer, from the upper surface cutting scribe area of wafer, and does not cut the transcrystalline circle; Execution in step S12 is connected the pad on the surface of first semiconductor device pad with the surface of adjacent semiconductor device by lead-in wire, form the semiconductor device group that several are connected to form by first semiconductor device and adjacent semiconductor device; Execution in step S13, at the upper surface coating insulating cement of wafer, insulating cement fills up the cutting groove that cutting for the first time forms, and covers the lead-in wire on semiconductor device group surface; Execution in step S14 carries out the cutting second time to wafer, cuts corresponding zone from the lower surface cutting and the first time of wafer; Execution in step S15 cuts the surface-coated insulating cement in the second time of wafer, fills up the cutting groove that cutting for the second time forms; Execution in step S16, the wafer polishing back side is to exposing silicon layer; Execution in step S17, the conductive layer of on the silicon layer that exposes, growing; Execution in step S18, border cutting along the semiconductor device group forms independently packaging, and formed packaging comprises the semiconductor device group that is connected to form by one or more lead-in wire by first semiconductor device semiconductor device adjacent with several.
Fig. 2 to Fig. 9 is the process schematic representation of this embodiment.
Refer step S10 provides the wafer that has the several semiconductor device, and these devices all separate each other by scribe area, and each semiconductor device has a pad at least.The basis of wafer-level package is a wafer that a large amount of circuit units is arranged, and these circuit units all are separate, and each circuit unit all has pad to be used to connect other circuit or external devices.Circuit above the wafer all is to combine with adjacent circuit, and can be divided into independent packaging.
As shown in Figure 2, refer step S11 carries out the cutting first time to wafer 101, and the upper surface cutting scribe area from wafer 101 forms cutting groove 111,112 and 113, and does not cut the transcrystalline circle.
Step S11 is from the front cutting and the formation multiple tracks cutting groove of wafer.The cutting groove that cutting produces has certain degree of depth and width.Cutting groove also has other shape except rectangle as shown in the figure, as triangle or V font.Cutting groove 111,112 and 113 is that cutting forms for the first time, and these cutting grooves all have identical width and height, and this cutting is not cut the transcrystalline circle.These cutting grooves are all in the scribe area between device.The position of cutting groove and size can be by case depth control method controls for the first time.For example, the depth control method in typical cutting machine is to adopt contact platform on the blade to test the height of cutting.But the thickness of any wafer all has tolerance, and therefore, also can there be a corresponding tolerance in the height of cutting groove.The method of an apparent height control of utilization in the specific embodiment of the present invention, cutting-height can be measured from crystal column surface.For example can adopt the software of highly measuring to apply in the operating system and cutting process of equipment, thereby improve the precision of cutting.
As shown in Figure 3, refer step S12, the pad on the surface of first semiconductor device pad with the surface of adjacent semiconductor device is connected by lead-in wire, forms the semiconductor device group that several are connected to form by first semiconductor device and adjacent semiconductor device.
The material of lead-in wire can be gold, copper or other electric conducting material.One of the lead-in wire 121 on the surface of first semiconductor device terminates on the bonding pad 122, and lead-in wire 121 other end end is connected on the bonding pad 123 on surface of adjacent circuit.For example the lead-in wire at 122 places can adopt ball bonding, and the lead-in wire at 123 places can adopt wedge bonding; All be to use ball bonding perhaps at 122,123 places.Before welding lead, can on pad, increase the conductive solder projection, this can help wire bonds on weld tabs.For example, on the weld tabs that can be used to weld before the welding lead, add the conductive solder projection.Adding conductive projection and welding lead can be finished by same machine.
As shown in Figure 4, refer step S13, at the upper surface coating insulating cement 131 of wafer 101, insulating cement 131 fills up the cutting groove that cutting for the first time forms, and covers the lead-in wire 121 on semiconductor device group surface.Described insulating cement 131 can adopt liquid or pulverous black glue for black glue.Black glue is a kind of material that is made of electrically non-conductive material.Black glue is received in the cutting groove that cutting for the first time forms, and forms the metal wire 121 that colloid covers bonding.The filler full-size of black glue is less than 30 μ m.Undersized filler can make black glue surface keep the quality of smooth raising device, and the protection crystal column surface reduces to be subjected to humidity corrosion and residue in order to avoid be subjected to environmental disruption, has also protected lead-in wire wherein simultaneously better.
As shown in Figure 5, refer step S14 carries out the cutting second time to wafer 101, cuts corresponding zone from the lower surface cutting and the first time of wafer 101, forms cutting groove 141,142 and 143.The cutting groove 141,142 of the cutting second time and 143 width are greater than the cutting groove 111,112 of cutting for the first time and 113 width.For the second time the cutting groove 141,142 of cutting and 143 height are less than the degree of depth of wafer 101, promptly do not cut the transcrystalline circle.And cutting groove 141,142 and 143 is distributed in two scribe areas between the device.Cutting groove 141,142 and 143 is at the back side of wafer, and with cut for the first time corresponding cutting groove 111,112 and 113 crossovers.If the degree of depth of cutting is enough for the second time, will switches to the bottom of the cutting groove that forms for the first time and connect.The total height sum of primary cutting groove and secondary cutting groove is not less than the height of wafer, and secondary cutting groove is to submit in the position repeatedly with primary cutting groove, and cutting so for the second time can switch to black glue 131.This will get rid of most of material of borderline region.The control method of the degree of depth of cutting for the second time will be depended on the position and the size of the cutting groove of cutting for the first time.Can need to survey the layout of wafer front surface like this, for example can realize by an infrared camera from the reverse side of wafer.
As shown in Figure 6, refer step S15, the upper surface coating insulating cement 151 at wafer 101 fills up the cutting groove 141,142 and 143 that cutting for the second time forms.Described insulating cement 151 is black glue.The advantage of implementing this step is protective circuit to be exposed to outer marginal portion.Black glue 151 and black glue 131 combine, and border in the middle of the adjacent like this device is just by black glue complete filling.Black glue penetrates into second road cutting groove and the wafer rear, thereby surrounds all faces of individual devices.
As shown in Figure 7, refer step S16 grinds wafer 101 back sides to exposing silicon layer.Back side abrasive disc can be removed a part of material at wafer 101 back sides, exposes silicon layer.Grinding off 161 parts of black glue 151 formation exposes fully up to the silicon layer of wafer.
As shown in Figure 8, refer step S17, the conductive layer of on the pad 171,172,173 and 174 that exposes, growing.The material of the conductive layer of growth is a metal on the pad 171,172,173 and 174 that exposes.This metal can be the nickel gold, nickel cobalt (alloy).Conductive layer is grown in pad that is used to go between of device 171,172,173 and 174, forms the surface of a conduction like this.In this embodiment, device 177 is by a negative electrode 175 and the diode that anode 176 is formed.Another one device 178 is electric conductors, the doped silicon of low-resistance for example, and its connects 177 the anode another side to chip.Accordingly, 177 negative electrode and pad 172 conductings.Anode 176 is by lead-in wire, conductive component 178 and pad 173 conductings.These all will be finished before receiving printed circuit board (PCB) (PCB).Need according to device in this step, as diode, to the degrees of tolerance of temperature, the temperature that monitoring is electroplated is not so that the circuit in the protection device is damaged in electroplating process.
What below set forth is how to encapsulate for different substrate diode, and the diode for a N type substrate is connected to pad 172 with negative electrode, and anode is linked on other the pad by the another one device.And, anode is connected to pad 172, and negative electrode is linked on other the pad by the another one device for the diode of a P type substrate.And for bipolar transistor, this method for packing needs two conductive devices and two lead-in wires to realize.Collector electrode directly is connected on the pad, and base stage and emitter are connected on other pads by conductive devices and lead-in wire.For MOSFET, need two conductive devices and two lead-in wires to realize equally.Drain electrode directly is connected on the pad, and source electrode and grid are connected on other pads by conductive devices and lead-in wire.This shows that any complicated circuit can be realized by the combination of above-mentioned device.An active end of circuit is directly coupled to surface of silicon substrate, and other active end is produced on another surface of substrate, realizes vertical electricity conducting of substrate by being coupled to adjacent device.For example the circuit of forming for the circuit of forming by two BJT, by a BJT and MOSFET by six active ends by six active ends, by a BJT and the circuit that five active ends are arranged and other the similar complicated circuit that diode is formed, can copy above-mentioned method to encapsulate.
As shown in Figure 9, refer step S18, border cutting along the semiconductor device group forms independently packaging, and formed packaging comprises the semiconductor device group that is connected to form by one or more lead-in wire by first semiconductor device semiconductor device adjacent with several.Cutting will be passed black glue 131 and 151.The semiconductor device group of these moulding is exposed to the outside to be used for connecting the external devices except the projection that has plated metal, and other parts are all covered by black glue 131 and 151 fully.In this embodiment, cutting is carried out from scribe area 181 and 182 positions, forms semiconductor device group 195, and it is made up of two circuit that couple together with metal wire, can be used to be attached on other the external devices.
Below in conjunction with accompanying drawing second kind of embodiment provided by the present invention elaborated.
As shown in figure 10, be the process chart of second embodiment provided by the present invention.Execution in step S20 provides the wafer that has the several semiconductor device, and these devices all separate each other by scribe area, and each semiconductor device has a pad at least; Execution in step S21 grinds the design thickness of wafer rear to chip; Execution in step S22 carries out the cutting first time to wafer, from the upper surface cutting scribe area of wafer, and does not cut the transcrystalline circle; Execution in step S23 is at wafer rear growth conductive layer; Execution in step S24 carries out second time cutting at the upper surface of wafer to wafer along the zone of cutting for the first time, and does not cut the transcrystalline circle; Execution in step S25 is connected the pad on the surface of first semiconductor device pad with the surface of adjacent semiconductor device by lead-in wire, form the semiconductor device group that several are connected to form by first semiconductor device and adjacent semiconductor device; Execution in step S26, at the upper surface coating insulating cement of wafer, insulating cement fills up for the first time and cuts for the second time the cutting groove of formation; Execution in step S27 cuts for the third time to wafer, and the back side of cutting crystal wafer is to exposing the insulating cement that cuts for the second time in the cutting groove that forms; Execution in step S28 applies insulating cement in the cutting groove for the third time of wafer rear; Execution in step S29, border cutting along the semiconductor device group forms independently packaging, and formed packaging comprises the semiconductor device group that is connected to form by one or more lead-in wire by first semiconductor device semiconductor device adjacent with several.
Figure 11 to Figure 19 is the process schematic representation of this embodiment.
Refer step S20 provides the wafer that has the several semiconductor device, and these devices all separate each other by scribe area, and each semiconductor device has a pad at least.
As shown in figure 11, refer step S21 grinds the design thickness of wafer 201 back sides to chip.211 parts are removed from wafer 201 by abrasive disc.Reach the height that chip needs by grind off a part from wafer rear.
As shown in figure 12, refer step S22 carries out the cutting first time to wafer 201, from the upper surface cutting scribe area of wafer 201, and does not cut transcrystalline circle 201.Cutting for the first time forms cutting groove 221,222 and 223 from the back side cutting of wafer.About the cutter volume description, can be with reference to the related content in the previous embodiment.
As shown in figure 13, refer step S23 is at wafer 201 back sides growth conductive layer 231.Described conductive layer is a metal.Consider the tolerance degree of circuit, need to monitor the temperature of plating in this technology temperature.
As shown in figure 14, refer step S24 carries out second time cutting at the upper surface of wafer to wafer along the zone of cutting for the first time, and does not cut the transcrystalline circle.Cutting for the second time is in the wafer frontside cutting and forms cutting groove.Cutting for the second time will generate cutting groove 241,242 and 243.
As shown in figure 15, refer step S25, the pad 253 on the pad 252 on the surface of first semiconductor device and the surface of adjacent semiconductor device 251 is connected by going between, forms the semiconductor device group that several are connected to form by first semiconductor device and adjacent semiconductor device.This step is included in adds the conductive solder projection on the pad 252 and 253 on first semiconductor device and the adjacent semiconductor device surface.Described lead-in wire 251 is a metal wire.One end of lead-in wire 251 will be soldered on the pad 252 of a circuit upper surface, and the other end will be soldered on the pad 253 of adjacent circuit upper surface.About the description of wire bonds, can be with reference to the related content in the last embodiment.
As shown in figure 16, refer step S26, at the upper surface coating insulating cement 261 of wafer, insulating cement fills up for the first time and cuts for the second time the cutting groove of formation.Described insulating cement 261 is black glue.Black glue will be received in the cutting groove 241,242 and 243 that cutting for the second time forms, and cover lead-in wire 251 simultaneously.The surface that black glue covers wafer makes it avoid environment damage, protects metal wire simultaneously.Because black glue is electrically non-conductive material, the circuit on the wafer will keep their original functions.
As shown in figure 17, refer step S27 cuts for the third time to wafer, and the back side of cutting crystal wafer is to exposing the insulating cement that cuts for the second time in the cutting groove that forms.Qie Ge cutting groove width is greater than the cutting groove width that cuts for the first time for the third time.Qie Ge the cutting groove degree of depth is greater than the cutting groove degree of depth of cutting for the first time for the third time.The cutting groove width of described cutting for the third time is greater than the cutting groove width that cuts for the second time.The cutting groove degree of depth sum of the cutting groove of cutting and cutting for the third time is not less than the thickness of wafer for the second time.
Qie Ge the degree of depth will be subjected to the control of a case depth control system for the third time.It will use infrared ray go to survey above-mentioned wafer upper surface the second time Cutting Road the degree of depth.In case for the second time the degree of depth of cutting is determined, Qie Ge the degree of depth thickness that can deduct the cutting groove second time by the thickness of wafer obtains for the third time.Thereby make and cut to the degree that black glue 261 exposes for the third time.This step has formed cutting groove 271,272 and 273, and forms independently conductive layer on the surface of pad 274,275,276 and 277.
As shown in figure 18, refer step S28 applies insulating cement 281 in the cutting groove for the third time of wafer rear.This step comprises in the cutting groove 271,272 and 273 that insulating cement 281 implantation step S27 are formed.Described insulating cement is black glue.When device is cut into separately when individual, black glue also plays the function of the circuit on the protection wafer 201.And the cutting groove of cutting for the second time and cutting for the third time couples together, and makes insulating cement 261 and 281 inject the raceway groove of the lower surface that runs through the wafer upper surface fully, and these raceway grooves all are positioned at the border region of two adjacent circuit.This position will be used for independent circuit is cut into device one by one.Pad 271～277 will can not be insulated glue 281 and cover, and can use these pads when being attached to device on the pcb board.
As shown in figure 19, refer step S29, border cutting along the semiconductor device group forms independently packaging, and formed packaging comprises the semiconductor device group that is connected to form by one or more lead-in wire by first semiconductor device semiconductor device adjacent with several.As in scribe area 291 and the cutting of 292 places, will form an independently packaging 295.Except being used to connect the pad of external devices, packaging 295 will be insulated glue 261 and 281 fully and wrap.Afterwards these independently packaging can be used to be attached on other the external devices.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; may make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (20)
1. a lead-bonding chip-scale packaging method is characterized in that, comprises the steps:
The wafer that has the several semiconductor device is provided, and these devices all separate each other by scribe area, and each semiconductor device has a pad at least;
Wafer is carried out the cutting first time,, and do not cut the transcrystalline circle from the upper surface cutting scribe area of wafer;
The pad on the surface of first semiconductor device pad with the surface of adjacent semiconductor device is connected by lead-in wire, forms the semiconductor device group that several are connected to form by first semiconductor device and adjacent semiconductor device;
Upper surface at wafer applies insulating cement, and insulating cement fills up the cutting groove that cutting for the first time forms, and covers the lead-in wire on semiconductor device group surface;
Wafer is carried out the cutting second time, cut corresponding zone from the lower surface cutting and the first time of wafer;
Cut the surface-coated insulating cement in the second time of wafer, fill up the cutting groove that cutting for the second time forms;
The wafer polishing back side is to exposing crystal column surface;
The conductive layer of on the crystal column surface that exposes, growing;
Border cutting along the semiconductor device group forms independently packaging, and formed packaging comprises the semiconductor device group that is connected to form by one or more lead-in wire by first semiconductor device semiconductor device adjacent with several.
2. the lead-bonding chip-scale packaging method according to claim 1 is characterized in that described lead-in wire is insulated the glue plastic packaging fully.
3. according to claim 1 or 2 described lead-bonding chip-scale packaging methods, it is characterized in that described insulating cement is black glue.
4. the lead-bonding chip-scale packaging method according to claim 1, it is characterized in that, described pad by adjacent two semiconductor device of lead-in wire connection is included in and adds the conductive solder projection on the pad on first semiconductor device and the adjacent semiconductor device surface.
5. the lead-bonding chip-scale packaging method according to claim 1 is characterized in that, the cutting groove of the described cutting first time and the cutting groove degree of depth sum of cutting for the second time are not less than the thickness of wafer.
6. the lead-bonding chip-scale packaging method according to claim 1 is characterized in that, the cutting groove width of the described cutting first time is less than the width of the cutting groove that cuts for the second time.
7. the lead-bonding chip-scale packaging method according to claim 1 is characterized in that the material of described conductive layer of growing is a metal on the pad that exposes.
8. the lead-bonding chip-scale packaging method according to claim 1, it is characterized in that, an Active Terminal on described first semiconductor device has been connected to the pad on the first surface of wafer, other Active Terminal is positioned at the second surface of wafer reverse side on first semiconductor device, and on corresponding other pad of first surface that has been connected to wafer by its second adjacent semiconductor device.
9. a lead-bonding chip-scale packaging method is characterized in that, comprises the steps:
The wafer that has the several semiconductor device is provided, and these devices all separate each other by scribe area, and each semiconductor device has a pad at least;
Grind the design thickness of wafer rear to chip;
Wafer is carried out the cutting first time,, and do not cut the transcrystalline circle from the upper surface cutting scribe area of wafer;
At wafer rear growth conductive layer;
Zone along cutting is for the first time carried out the cutting second time at the upper surface of wafer to wafer, and does not cut the transcrystalline circle;
The pad on the surface of first semiconductor device pad with the surface of adjacent semiconductor device is connected by lead-in wire, forms the semiconductor device group that several are connected to form by first semiconductor device and adjacent semiconductor device;
Upper surface at wafer applies insulating cement, the cutting groove that insulating cement fills up for the first time and cutting for the second time forms;
Wafer is cut for the third time, and the back side of cutting crystal wafer is to exposing the insulating cement that cuts for the second time in the cutting groove that forms;
In the cutting groove for the third time of wafer rear, apply insulating cement;
Border cutting along the semiconductor device group forms independently packaging, and formed packaging comprises the semiconductor device group that is connected to form by one or more lead-in wire by first semiconductor device semiconductor device adjacent with several.
10. the lead-bonding chip-scale packaging method according to claim 9 is characterized in that described lead-in wire is insulated the glue plastic packaging fully.
11. the lead-bonding chip-scale packaging method according to claim 9 is characterized in that, the described insulating cement that applies after cutting groove does not for the third time cover pad.
12., it is characterized in that described insulating cement is black glue according to claim 9 or 10 or 11 described lead-bonding chip-scale packaging methods.
13. the lead-bonding chip-scale packaging method according to claim 9 is characterized in that, described conductive layer in the wafer rear growth covers the back side of whole wafer.
14. the lead-bonding chip-scale packaging method according to claim 13 is characterized in that the material of described conductive layer is a metal.
15. the lead-bonding chip-scale packaging method according to claim 9 is characterized in that, the cutting groove width of described cutting for the third time is greater than the cutting groove width that cuts for the first time.
16. the lead-bonding chip-scale packaging method according to claim 9 is characterized in that, the cutting groove degree of depth of described cutting for the third time is greater than the cutting groove degree of depth of cutting for the first time.
17. the lead-bonding chip-scale packaging method according to claim 9 is characterized in that, the cutting groove width of described cutting for the third time is greater than the cutting groove width that cuts for the second time.
18. the lead-bonding chip-scale packaging method according to claim 9, it is characterized in that, described pad by adjacent two semiconductor device of lead-in wire connection is included in and adds the conductive solder projection on the pad on first semiconductor device and the adjacent semiconductor device surface.
19. the lead-bonding chip-scale packaging method according to claim 9 is characterized in that, the cutting groove of the described cutting second time and the cutting groove degree of depth sum of cutting for the third time are not less than the thickness of wafer.
20. the lead-bonding chip-scale packaging method according to claim 9, it is characterized in that, an Active Terminal on described first semiconductor device has been connected to corresponding bonding pad on the semiconductor device group surface, and other Active Terminal has been connected on the corresponding pad in semiconductor device group surface by its other adjacent semiconductor device on first semiconductor device
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012040873A1 (en) * | 2010-09-29 | 2012-04-05 | Nxp B.V. | Singulation of ic packages |
| CN112885720A (en) * | 2021-01-14 | 2021-06-01 | 江西译码半导体有限公司 | Wafer cutting method |
| CN114351202A (en) * | 2021-03-18 | 2022-04-15 | 青岛惠芯微电子有限公司 | Wafer electroplating method and wafer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6649445B1 (en) * | 2002-09-11 | 2003-11-18 | Motorola, Inc. | Wafer coating and singulation method |
| CN101068005B (en) * | 2006-05-02 | 2010-12-29 | 捷敏服务公司 | Semiconductor device package lead frame made of multiple metal layers |
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2008
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012040873A1 (en) * | 2010-09-29 | 2012-04-05 | Nxp B.V. | Singulation of ic packages |
| US8809121B2 (en) | 2010-09-29 | 2014-08-19 | Nxp B.V. | Singulation of IC packages |
| CN112885720A (en) * | 2021-01-14 | 2021-06-01 | 江西译码半导体有限公司 | Wafer cutting method |
| CN114351202A (en) * | 2021-03-18 | 2022-04-15 | 青岛惠芯微电子有限公司 | Wafer electroplating method and wafer |
| CN114351202B (en) * | 2021-03-18 | 2023-08-25 | 青岛惠芯微电子有限公司 | Electroplating method of wafer |
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| CN101521164B (en) | 2011-01-05 |
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