CN101409111A - Method for formatting/testing general sequence bus device - Google Patents

Abstract

A high volume testing/formatting process is provided for Universal Serial Bus-based (USB-based) electronic data flash cards (USB devices) that meets the increasing demand for USB electronic data flash cards (USB devices). A test host is simultaneously coupled to the multiple USB devices (e.g., using a multi-port card reader or a probe fixture), a controller endpoint value is read from each of the USB devices and verified with a known good value, and then testing/formatting is performed on each of the USB devices by writing predetermined data into each USB device in a pipelined manner, then reading out and testing the predetermined data. In one embodiment, the test host implements a special USB driver that blocks standard USB registration procedures upon detecting the plurality of USB devices. Control and/or boot code data are written onto the flash memory device (i.e., instead of being provided on a controller ROM).

Description

Method of Formatting/Testing Universal Serial Bus Devices

technical field

The present invention relates to an electronic data flash card, in particular to a system and method for testing a USB electronic data flash card during manufacture.

Background technique

Confidential data files are often stored in a floppy disk drive (floppydisk), or are transmitted through a network that requires passwords or encryption codes to ensure security, and confidential data files will be added with a safety seal (safety seal) and watermark (watermark) during transmission. mark) to send. However, once passwords, encryption codes, security seals and imprints are cracked, confidential data files and documents are exposed to danger, and unauthorized persons can use this confidential information.

As flash memory technology becomes more advanced, flash memory is gradually replacing traditional disk drives as storage media for mobile systems. Flash memory has significant advantages over floppy disk drives or magnetic hard disks, such as high G-shock resistance and low power consumption. Due to the small size of flash memory, it is also conductive to mobile systems. Therefore, due to its compatibility with portable (mobile) systems and low-power features, the trend of flash memory has gradually grown.

USB electronic data flash card (flashcard) is the device of portability and low power, and it utilizes universal serial bus (USB) technology, as the interface of the flash memory device of computer mainframe and flash card, and USB electronic data flash card has Various forms, such as pen drive storage devices, MP3 players, digital cameras. In each instance, USB electronic data flash memory cards typically include a flash memory device, a processor and USB interface circuitry.

Due to the rapid popularity of USB electronic data flash cards, the manufacturing volume of USB electronic data memory cards (or USB flash cards) continues to grow. With increasing manufacturing volumes, the problem facing the manufacturing industry is how to efficiently and reliably test USB flash memory cards before shipment to end users. For the factors of low cost, compatibility and reliability, the existing test method is to use a personal computer (PC) to test the USB flash card (that is, the end user generally uses the USB flash card to will be able to use the USB flash card quickly and reliably). The problem that this existing test method using PC has is that the general PC window TM (or MAC TM) operating system only supports some USB devices at a time, and it takes a lot of time for the operating system to detect and test the USB flash card Insert each USB flash card by hand, and then remove each USB flash card by hand. As a result, existing testing methods cannot keep up with the increase in manufacturing throughput.

In view of this, there is a need for a mass testing method to meet the increasing demand for USB electronic data flash cards.

Contents of the invention

The main purpose of the present invention is to provide an electronic data flash card, which includes a flash memory device, an optional fingerprint sensor, an input/output interface circuit, and a processor. The electronic data flash card is suitable for use by a host computer, such as a personal computer, notebook computer or other electronic host device. Since the electronic data flash card is easy to carry and durable, personal data can be stored in the flash memory device in an encrypted manner, so it is possible to use the fingerprint sensor combined with the card body, so that only those whose fingerprints match can use the memory card, ensuring that no The authorized person cannot use the memory card.

The present invention also provides a mass testing/formatting process for USB-based electronic data flash cards (USB devices) to meet the increasing demand for electronic data flash cards (USB devices). The present invention provides a method and system for a large number of testing/formatting of USB devices, utilizes a test host to be coupled to multiple USB devices (such as a card reader with multiple slots or a probe fixture) at the same time, from each The USB device reads a controller endpoint value, and confirms the controller endpoint value with a known good value, and then formats each USB device, and writes predetermined data to each USB device in a "pipeline" manner . The USB device is then read out for testing to test the predetermined data. In one embodiment, the test host blocks the standard USB registration process when most USB devices are detected using a specific USB driver. The present invention ignores the existing USB registration procedure and confirms the controller endpoint value before testing/formatting, and helps to effectively and mass-test/format USB devices by deleting the time-consuming and unnecessary registration process. In addition, the present invention writes data into the USB device in a "pipeline" manner, which helps to test/format a large number of USB devices and greatly reduces production time.

According to an aspect of the present invention, each USB device is modified to store selected handle and boot code data, device information and configuration information on a flash memory device to reduce the size of the controller ROM. Because the existing USB registration process needs to use many such handles, startup codes, device information, and configuration information (because the existing USB registration process assumes that such codes and information are obtained from the controller ROM), so ignore the existing The USB registration process is provided to avoid system failure or long delay, because when an unformatted USB device (with a blank flash memory device) is coupled to the test host system, the host system will wait for the handle, boot code and information.

According to another aspect of the present invention, the purpose of the testing/formatting process is to include checking that all chips are soldered correctly, that the current consumption levels are within specifications, that each component device (such as the controller and flash memory device) is connected to the test host to implement The test/formatting is compatible. The formatting process provides downloading of all entry point values required for correct controller operation, erases flash memory, creates a remaining bad block list (bad_block_list) file for future bad block management, and provides a low-level format.

According to an embodiment of the present invention, the controller endpoint values read at the initial stage of the testing/formatting process include a configuration descriptor value, a mass storage class code value and a product identification value. When the controller endpoint values read from each USB device match the good values stored in the test host, a flag displayed on the test host monitor will indicate a successful status (e.g. the flag changes from red to green ).

According to another embodiment of the present invention, the testing/formatting process includes storing one or more of the scan bad block data in the flash memory device, and confirming whether the storage capacity reserved by each flash memory device is equal to a predetermined size ( e.g. a specific percentage of the entire memory capacity), at least two copies of the bad block data are written to the flash memory device, the handle and/or boot code is written to the flash memory device, provided customer data is written to the flash memory device, and Write the new serial number, date code, and product version code values into the flash memory device.

Description of drawings

FIG. 1(A) is a block diagram showing an electronic data flash card and a host system according to an embodiment of the present invention;

FIG. 1(B) is a block diagram showing an electronic data flash card and a host system according to another embodiment of the present invention;

Fig. 1 (C) is another embodiment of the present invention, shows the block diagram of electronic data flash card and host computer system;

FIG. 1(D) is another embodiment of the present invention, showing a block diagram of an electronic data flash card and a host system;

FIG. 2 is a flow chart showing a method for high-volume manufacturing of a USB device according to an embodiment of the present invention;

FIG. 3(A) is a schematic diagram showing a surface mount technology panel according to an embodiment of the present invention;

Figure 3(B) is a schematic plan view showing the printed circuit board assembly separated from the panel of Figure 3(A);

Figure 3 (C) is a schematic plan view of the printed circuit board device shown in Figure 3 (B) after packaging of the present invention;

4(A) and 4(B) are simplified perspective views showing a test host used according to another embodiment of the present invention;

FIG. 5(A) and FIG. 5(B) are simplified flowcharts showing existing and innovative testing and formatting USB devices, respectively;

6 is a flowchart showing a simplified method of testing and formatting a USB device according to an embodiment of the present invention;

Fig. 6 (A), Fig. 6 (B), Fig. 6 (C), Fig. 6 (D) and Fig. 6 (E) are flowcharts, further showing the testing and formatting method in Fig. 6;

FIG. 7 is a schematic diagram showing a generated USB device according to an embodiment of the present invention;

8 is a simplified block diagram showing different address structures and partitions of a flash memory device used in a USB device according to an embodiment of the present invention;

FIG. 9 shows a bad block list structure of a flash memory device stored in a USB device according to an embodiment of the present invention;

FIG. 10(A) is a flow chart showing a manufacturing software algorithm for performing a test or formatting process according to another embodiment of the present invention;

FIG. 10(B) is a flow chart showing the manufacturing software algorithm used to perform USB device calculations according to another embodiment of the present invention;

11 is a flow chart showing the entire operation of the test host system for the USB device according to an embodiment of the present invention;

FIG. 12(A) and FIG. 12(B) are simplified flow charts showing the operation of defective flash chips with dual routing and single routing, respectively, according to another embodiment of the present invention;

FIG. 13(A) and FIG. 13(B) are block diagrams, respectively describing the flash memory configurations for the operation of the defect flash chip with dual and single routes in FIG. 12(A) and FIG. 12(B);

14 is a schematic block diagram showing information stored in different memory areas of each USB device according to an embodiment of the present invention;

FIG. 15 is a diagram showing multilevel cell voltage sensing of an MLC memory cell according to an embodiment of the present invention;

FIG. 16 shows a programmable reference generator and a comparator connected in series according to an embodiment of the present invention;

FIG. 17 is a flow chart of MLC degradation during write or erase operations according to an embodiment of the present invention;

18 is a flow chart of reading error correction using ECC bytes and adjusting reference voltages according to an embodiment of the present invention;

19(A)-FIG. 19(C) are block diagrams showing the structure of an extended USB device according to an embodiment of the present invention;

20(A)-20(C) are block diagrams showing the structure of the extended USB device according to an embodiment of the present invention;

FIG. 21(A)-FIG. 21(G) are schematic diagrams showing the structure of the expansion USB connector and slot according to an embodiment of the present invention;

FIG. 22(A)-FIG. 22(I) are schematic diagrams showing the structure of the expansion USB connector and the slot according to an embodiment of the present invention.

Description of reference signs: 1-card body; 2-processing unit; 3-flash memory device; 4-fingerprint sensor; 5-input/output interface circuit; 6-display unit; 7-power supply; 8-functional button group; 9 -computer; 10-electronic data flash card; 13-interface bus; 2A-processing unit; 3A-flash memory device; 4A-fingerprint sensor; 5A-input/output interface circuit; 2B-processing unit; 3B-flash memory device; 5B -Input/output interface circuit; 6B-display unit; 8B-functional button group; 9B-computer; 22-power regulator; 23-reset circuit; 10-BUSB device; 201-monitor; 202-test host; 203-USB slot; 204-compound card reader; 205-probe fixture; 206-probe; 207-SMT probe test host; 208-collection cable; 211-panel; 212-PCB device; Flash card controller; 215-flash memory device; 215-1-flash memory chipset; 215-1A-flash memory chipset; 215-1B-flash memory chipset; 215-2-flash memory chipset; 217-USB pin; 413 -bad block data; 415A-control selection bit; 415B-control firmware; 420-entry point register; 421-non-volatile register; 450-microprocessor; 451-control endpoint register; 452-address translation 453-static ROM; 453A-RAM buffer; 453B-flash access time buffer; 454-read-only memory; 454A-jump boot firmware; 454B-descriptor; 456-only bulk transfer instruction decoding 470-input/output interface circuit; 470A-physical layer USB transceiver; 470B-continuous interface engine; 470C-data buffer; 94-good block; 95-original bad block; 96-generated bad block; 97-preparation area; 1030-1040-comparator; 1041-1051-reference-current generator; 1052-control engine; 1054-flash memory unit; 1056-bit line; Resistor; 1161-1171-amplifier; 1181-1191-grounding resistor; 1120-voltage reference generator; 1122-correction buffer; 1300-USB expansion plug; 1303-shell; 1306-spring; 1307-contact pin; 1311-PCB substrate; 1312-upper surface; 1313-bottom surface; 1314-memory controller; 1315-memory device; 1400-USB expansion plug; 1403-shell; 1404-USB connector substrate; 1405-contact finger; 1406-spring; 1407-contact pin; 2132-contact pin; 2134- Pin substrate; 2138-metal cover; 2170-pin substrate; 2172-contact pin; 2173-metal cover; 2176-plastic shell; 2178-metal cover; 2180-contact pin; 2184-pin Substrate; 2185-substrate extension; 2186-contact pin; 2188-contact pin; 2190-pin substrate; 2193-metal cover; 2196-plastic shell; 2198-metal cover; Contact pins; 2204-pin substrate; 2206, 2207-contact pins.

Detailed ways

The present invention is about an improvement on the method for manufacturing electronic data flash cards. Although the following is a specific reference to USB electronic data flash cards, the innovation of the present invention can be used in a wide range of flash card types. Manufacturing, including PCIExpress, SecureDigital (SD), MemoryStick (MS), CompactFlash (CF), IDE and SATA flash memory cards, but not limited to these flash card types mentioned above.

Referring to Fig. 1 (A), according to an embodiment of the present invention, an electronic data flash card 10 is passed through an external (host) computer 9 through any interface bus (interfacebus) 13 or a card reader (not shown in the figure) ) or other interface mechanisms (not shown), and the electronic data flash card 10 includes a card body 1, a processing unit 2, one or more flash memory devices 3, an optional fingerprint sensor (security device ) 4, an input/output interface circuit 5, an optional display unit 6, an optional power supply 7 (such as a battery), and an optional functional key set 8.

The flash memory device 3 is mounted on the card body 1, and stores data files, reference passwords, and fingerprint reference data in a well-known manner, wherein the fingerprint reference data is obtained by scanning the fingerprint of the person who has the right to use the data file. Data files can be image files or text files. It will be further mentioned below that the flash memory device 3 also includes boot code data and handle data.

The fingerprint sensor 4 is located on the card body 1 and is used to scan the user's fingerprint of the electronic data flash card to generate fingerprint scan data. An example of the fingerprint sensor 4 used in the present invention is disclosed in US Patent No. 6,547,130, Integrated circuit card with Finger print Verification Capability, the entire content of which is incorporated herein by reference. The fingerprint sensor described in the above patent includes an array of scanning units to define a fingerprint scanning area. The fingerprint scan data includes multiple scan line data, which is obtained by scanning the scan lines corresponding to the array of scan units. Moreover, the scanning lines of the scanning unit array are scanned in the horizontal direction and the vertical direction of the array. Each scanning unit will generate a first logic signal when detecting the fingerprint ridge of the holder of the card body, and will generate a first logic signal when detecting the fingerprint valley of the holder of the card body a second logic signal.

The input/output interface circuit 5 is located on the card body 1 and is actuated to establish a communication relationship with the host computer through an interface bus 5B or a card reader using a suitable socket. In one embodiment, the input/output interface circuit 5 includes circuitry and control logic, wherein the control logic is related to one of the Universal Serial Bus (USB), PCMCA, RS232 interface structures to connect to a host computer 9 or a socket located on the host computer 9 . In another embodiment, the input/output interface circuit 5 may include an SD interface circuit, an MMC interface circuit, a CF interface circuit, an MS interface circuit, a PCI-Express interface circuit, and an integrated drive electronics (IDE) interface One of the circuit and a SATA interface circuit is in contact with the host computer 9 through the interface bus 13 or the card reader.

The processing unit 2 is located on the card body 1 , and is connected to the memory device 3 , the fingerprint sensor 4 and the input/output interface circuit 5 by using relevant conductive lines or wires located on the card body 1 . In one embodiment, the processing unit 2 may be one of 8051, 8052, and 80286 microprocessors produced by Intel Corporation. In other embodiments, the processing unit 2 includes a RISC, ARM, MIPS or other signal processor. According to an aspect of the present invention, the processing unit 2 is controlled by at least part of the program stored in the flash memory device 3, so that the processing unit is selectively operable in: (1) a programming mode (programming mode), wherein the processing unit 2 is consistent with The dynamic input/output interface circuit 5 receives data files from the host computer, boot code data and handle data, optional fingerprint reference data, and stores stored data in the flash memory device (compressed format can be selected to increase the storage space of the memory device) ; (2) a reset mode (resetmode), wherein the boot code data and handle data are read from the flash memory device 3, and are used to set and control the operation of the processing unit; (3) a data retrieval mode (dataretrievingmode ), wherein the processing unit 2 reads the fingerprint scan data from the fingerprint sensor 4, and compares the fingerprint scan data with at least a part of the fingerprint reference data in the flash memory device 3, to confirm whether the user of the electronic data flash card has Right to use the data files stored in the flash memory device 3, and once it is confirmed that the user has the right to use the data files stored in the flash memory device 3, then actuate the input/output interface circuit 5 to send the data files to the host computer 9; (4) a Code is also new mode (codeupdatingmode), also new boot code data and handle data in the flash memory device; (5) a data reset mode (dataresetmode), erases data file and fingerprint reference data from flash memory device 3. In terms of operation, the host computer 9 transmits the write request and the read request to the electronic data flash card 10 through the card reader or the interface bus 13, and the input/output interface circuit is sent to the processing unit 2, and the flash memory controller is used in turn for one or Multiple flash memory devices 3 are read or written. In one embodiment, the processing unit 2 automatically initiates the data reset mode operation upon detecting that a preset time period has elapsed from the data file and the fingerprint reference data stored in the memory device 3 .

8051, 8052 and 80286 are microprocessors developed by Intel Corporation, which use complex instruction sets. The 8051 and 8052 have an 8-bit data bus, and the 80286 has a 16-bit data bus. RISC, ARM, MIPS are microprocessors that use a reduced instruction set architecture. 8051 and 8052 are widely used in low-cost applications. 80286 can be used in high-speed operation applications. RISC, ARM, and MIPS are relatively high-cost microprocessors, which are more suitable for complex applications, such as advanced error correction codes (ECC) and data decoding.

The optional power supply 7 is located on the card body 1 and connected to the processing unit 2 and other related units located on the card body to supply the required power.

The optional functional key set 8 is located on the card body 1 and connected to the processing unit 2, and is operable so that the processing unit 2 is in the programming, reset, data retrieval, code renewal or data reset mode Choose one of them to get started. The functional key set 8 is operable to provide an input password for the processing unit 2 . The processing unit 2 compares the input password with the reference password stored in the flash memory device 3 , and once it is confirmed that the input password is consistent with the reference password, the electronic data flash card 10 starts authorization operation.

The optional display unit 6 is located on the card body 1 and is connected to the processing unit 2 and controlled by the processing unit 2 for displaying data files exchanged with the host computer 9 and displaying the operating status of the electronic data flash card 10 .

The following are some advantages of disclosing the present invention: firstly, the electronic data memory card has a small volume but has a large storage capacity, which causes convenience in the data transmission process; secondly, because each person has a unique fingerprint , so the electronic data flash card only allows authorized persons to use the data files stored therein, thus enhancing security.

Other features and advantages of the present invention will be further presented below.

FIG. 1(B) is a block diagram showing an electronic data flash card 10A according to another embodiment of the present invention, which provides a general sensor unit 4A instead of the fingerprint sensor mentioned above. Exemplary sensor units include retinal scanners or voice recognition devices capable of detecting physiological characteristics of authorized users, and operate in a manner similar to the fingerprint sensor 4 described above.

FIG. 1(C) is a block diagram showing an electronic data flash card 10B according to another embodiment of the present invention. The electronic data flash card 10B eliminates the fingerprint sensor and related user identification process. In order to reduce the cost, the electronic data flash card 10B also includes a highly integrated processing unit 2B, which includes an input/output interface circuit 5B and a flash memory controller 21 . The I/O interface circuit 5B includes a transceiver block, a serial interface engine block, data buffers, registers, and interrupt logic. The I/O interface circuit 5B is coupled to the internal bus to allow various components of the I/O interface circuit 5B and various components of the flash memory controller 21 to communicate with the components of the flash memory controller. The flash controller 21 includes a microprocessing unit, a read only memory (ROM), a static random access memory (RAM), flash controller logic, error correction code logic, and general-purpose input and output (GPIO) logic. In this embodiment, the general-purpose input-output (GPIO) logic is coupled with a plurality of diodes as status indications, such as indicating good power or read/write flashing activity, etc., and the GPIO logic is connected to other I/O devices. The flash memory controller 21 is coupled to one or more flash memory devices 3B.

In this embodiment, the host computer 9B includes a functional button group 8B, which is connected to the processing unit 2B through a card reader or an interface bus when the electronic data flash card 10B is in operation. The functional key set 8B can be used to selectively set the electronic data flash card 10B from one of the programming, reset, data retrieval, program code refresh or data reset modes. The functional key set 8B can also be used in operation to provide an input password to the host computer 9B. The processing unit 2B compares the input password with the reference password stored in the flash memory device 3B. Once the input password is confirmed to be consistent with the reference password, the electronic data flash card 10B starts the authorization operation.

Meanwhile, in this embodiment, the host computer 9B includes a display unit 6B, which is connected to the processing unit 2B through a card reader or an interface bus when the electronic data flash card 10B is in operation. The display unit 6B is used for displaying data files exchanged with the host computer 8 and displaying the operating status of the electronic data flash card 10B.

According to an embodiment of the present invention, the processing unit 2 includes a flash memory typeal gorithm for detecting whether the flash memory type is dominated by the flash memory controller. Advances in flash memory have resulted in a variety of flash memory types due to performance, cost, and capacity factors. Due to potential shortages and cost factors, the need for flexibility in the source of flash memory and the need for unique controls to use different types of flash memory, it is important to use processing units with intelligent algorithms to detect and use different types of flash memory. A general flash memory includes an identification (ID) code to identify the type of flash memory, the manufacturer, and the characteristics/parameters of the flash memory, such as page capacity, block size, organization, capacity, and other characteristics/parameters. The intelligent algorithm controls the processing unit 2 to read the ID of the flash memory 3 in the reset state, and compares this ID with a table of flash memory types controlled by the flash memory controller. If Flash 3 is not dominated by the Flash controller, the Flash controller will not be able to use Flash 3 and the incompatibility will be indicated by an LED at the output of the Flash controller. If the flash memory is already preoccupied, before the flash controller starts using the flash memory, the flash controller proceeds in the following manner. For example, a flash memory controller having such an intelligent algorithm is disclosed in the pending US Patent No. 11/466,759 "flash memory controller for electronic data flash card", which is hereby incorporated by reference.

The electronic data flash card is a kind of flash memory system, which uses flash memory to store data. The general flash memory system architecture includes a flash memory controller with a processor, ROM and RAM, wherein the boot code and handle are located in the ROM as ROM code. Once power is up, the processor fetches the boot code to execute, which initializes the system components and downloads the handles into RAM. Once the handle is downloaded into RAM, the handle takes control of the system. Handlers include drivers to perform basic tasks such as controlling and allocating memory, assigning priority to processing instructions, and controlling input and output ports. The handle also includes the flash type detection algorithm and flash parameter data.

ROM is a kind of read-only memory. When the flash memory controller is designed and put into production, the software code in the ROM is fixed and cannot be changed to support new flash types that will be supplied to the market in the future. In this situation, it is necessary to develop a new flash memory controller to support new flash memory from time to time, which is time-consuming and expensive.

FIG. 1(D) also shows the processing unit 2A of FIG. 1(B) in detail. The electronic data flash card 10A includes a power regulator to provide one or more power supplies. The power regulator provides different voltages to the processing unit 2A and other related units of the electronic data flash card 10A according to power requirements. Capacitors (not shown) may be required to keep the power steady. The electronic data flash card 10A includes a reset circuit 23 to provide a reset signal (reset signal) to the processing unit 2A. Once the power is increased, the reset circuit 23 asserts the reset signal to all the processing units 2A. After the internal voltage reaches a stable state, the reset signal is not present, and registers and capacitors (not shown) are provided for proper reset time adjustment. The electronic data flash card 10A also includes a quartz crystal oscillator (not shown in the figure) to provide the fundamental frequency to the PLL located in the processing unit 2A.

According to an embodiment of the present invention, the input/output interface circuit 5A, the reset circuit 23 and the power regulator 22 are integrated or partially integrated in the processing unit 2A. High integration can reduce the overall required space, and lower the complexity and manufacturing cost. For removable devices, such as the electronic data flash cards described herein, compactness and cost reduction are key factors. Today's IC packages can integrate different IC components into a single IC package using different technologies and materials. For example, the input/output interface circuit is an analog/digital hybrid circuit, which can also be integrated into a multi-chip package (Multi-Chip package, MCP) with a processing unit. The nature of mixed-signal IC technology is to allow a mixture of analog and digital circuits. Therefore, high integration can be incorporated into the same chip/die, so that the processing unit contains I/O interface circuits, flash memory controller, reset circuit, power regulator.

According to another aspect of the present invention, the electronic data flash card includes the boot code and handle stored in the flash memory instead of the ROM of the flash memory controller. So the boot code and handle can be refreshed in this field without changing the flash controller. For example, in U.S. Patent Application Serial No. 11/611,811, flash memory controller for electronic dataflash card, filed on December 13, 2006, the open boot code and handle are stored in the flash memory, which is hereby incorporated by reference.

2 is a flowchart showing the main method of manufacturing a USB device according to another embodiment of the present invention, and FIGS. 3A-3B are simplified plan views showing the USB device during different stages of the manufacturing process. Referring to block 50 of FIG. 2, the manufacturing method begins by mounting all components of the USB device on the panel (such as flash memory, controller, and all passive components such as resistors and capacitors) using surface mount technology (SMT). ), wherein the panel includes a plurality of printed circuit boards PCB. FIG. 3(A) shows an exemplary SMT panel 211 having multiple printed circuit board assemblies 211 joined together along individual edges to facilitate efficient assembly of various SMT components, such as controller chips. , flash chips, and other components. The PCB assembly 212 includes wiring to facilitate electrical connections between the various SMT components and between the controller chip 212 and the four USB pins 217 (ie, VDD, D+, D- and GND). Referring again to FIG. 2, individual PCB devices are then tested/formatted according to the process used in the present invention, which is further disclosed below. In one embodiment, the panel 211 (see FIG. 3A ) is based on singulation (block 52A), so that individual PCB devices can be cut or separated from each other, and then a single PCB device 212 (see FIG. 3A ) is tested/ Formatter (block 52B). In another embodiment, while the PCB assembly 212 is still connected to the panel 211 for testing (block 53A), then the formatted/tested PCB assembly is singulated (block 53B). Among them, the inventor's current preference for testing/formatting the PCB assembly 212 is to allow multiple PCB assemblies 212 to be maintained in a fixed relationship to be tested by a single fixture, thus avoiding additional processing time for each PCB device 212 (for example inserting PCB device 212 piece by piece in a single test fixture). Please refer to FIG. 2 again, each PCB device 212 that has successfully completed testing/formatting will receive a product package (block 54), and a body is molded or installed on the components of each PCB device 212, and then the USB device is completed. The final test of 10B (block 55) is ready for shipping. And, please note that the final test performed at block 55 is different from the test/format performed at blocks 52B and 53A, since all initial content is downloaded to each packaged device 10B, the final test performed at block 55 Testing is concerned with a simple plug-in test verification, such as verifying device capability to ensure end-user satisfaction. FIG. 4(A) and FIG. 4(B) are schematic diagrams respectively showing an exemplary system for testing/formatting a USB device according to the present invention. FIG. 4(A) is based on block 52B of FIG. 2 , showing a first system for testing a single PCB device (refer to the device under test (DUT) below). The first system includes a PC test host (such as a general-purpose personal computer) 202, a monitor 201, a USB composite card reader 204 and other necessary peripheral I/O devices, such as a keyboard and a mouse (not shown). In one embodiment, all test parameters are displayed on the monitor 201 to monitor the test status, wherein colored flags (flag) are used to distinguish test pass or fail, and some parameters used during the test can be manipulated or input, as parameters shown on monitor 201. The USB card reader 204 includes multiple (more than 16) USB slots, and each slot has a designated number (such as #1, #2, etc.) according to the flag on the monitor 201 . The card reader 204 is connected to a standard USB slot 203 of a test host 202 through a common USB transmission line to connect with the test host 202 . When each device under test (DUT) is inserted into a corresponding port (port) of the multi-card reader 204, the multi-card reader 204 is connected to the test host 202 through the USB slot 203, and when each inserted DUT is detected, A corresponding flag will be generated on the monitor 201 to reflect the detection result (eg, once detected, the corresponding flag will change from red to green). FIG. 4B shows a second system for testing the pre-assembled PCB device 212 still connected to the panel 211 using a probing fixture. The second system includes an SMT probe test host (such as a general-purpose computer) 207, a monitor 201, a probe fixture 205, and other necessary peripheral IO devices. The probe fixture 205 includes a plurality of test probes 206 gathered for contacting the USB pins 217 of each PCB device 212 when the fixture 205 is lowered onto the panel 211 . Probes 206 provide four signal paths for each device on formatting/testing panel 211 . In addition, an integrated cable 208 is used to connect the jig 205 to the test host 207 . FIG. 5A is a simplified flowchart showing a conventional USB test system using a conventional host operating system (OS) USB driver (block 301 ) to test and format an existing USB device. As shown in block 302, upon connecting an existing USB device to a host system, the host OS temporarily stores the pre-established USB protocol used by the existing USB device under test (DUT). This pre-established USB protocol is based on the assumption that device-specific data (eg, device ID and serial number may be the same prior to testing) is stored in a predetermined location on a ROM device provided by the controller on the DUT. In addition, the pre-established USB protocol requires the registration procedure to be performed one DUT at a time (ie, one registration procedure must be completed for one DUT before starting the registration procedure for another DUT). And, in case of failure, all DUTs will wait until the operator reinstalls the program before starting. As shown in block 302, the problem with these pre-established USB protocols is that it will take a lot of time to register each DUT, and these registration data will be stored in the temporary storage area (registrybank) of the host OS (and finally stored in the registry bank). hard disk of the host computer), and it is not suitable for testing/formatting a large number of DUTs at the same time. An additional problem with using these pre-established USB protocols is that it is not compatible with new USB devices (boot code, handles and component and device identification data are stored in the flash memory device, not in a predetermined location in ROM). As shown in blocks 304 and 305, because the untested/unformatted device formed according to the present invention does not contain a device identification number and a product identification number, the existing pre-set USB protocol may cause the host test system to be interrupted ( hangup) (block 306), or it may take some time to complete the test (block 307), and/or just fail to complete the formatting/testing process (block 308). FIG. 5B is a simplified flowchart showing testing and formatting a new USB device according to another embodiment of the present invention. As shown in block 501, new software is downloaded to the test host to block legacy operating system (OS) USB drivers for a dedicated USB test. The purpose of blocking the USB drive of the existing OS is to shorten the test time by eliminating the time taken for the registration process. This dedicated USB test requires data from the USB device (not written into the flash memory device) through a part of the registration process, and directly writes at least one of the start program code, handle and device identification data to the flash through the controller of the USB device. flash device to start the testing/formatting process. In particular, as shown in block 502, to avoid the typically lengthy registration process of more than 16 USB devices at a time, the test/formatting software executed on the test host system was modified to read the controller's hard-coded descriptor ( hard-codeddescriptor) values and compare these descriptor values with the stored program parameters to confirm that the DUT is ready to be formatted and to provide the DUT with the correct parameters for use in normal operation. Only continuous inspection will continue the software process. Next, as shown in block 503, in order to make the USB device available to end users, the master boot block (MBR), file allocation table (FAT) and initial system files are written into the flash device. Because conventional USB devices are properly programmed using read-only memory (ROM) for initial system operation, conventional USB devices will not go through the formatting process. This procedural step is important for manufacturing software purposes and for subsequent use. Additionally, as shown in block 504, several values written to the flash device meet USB specifications. The device serial number is such a value, and the device serial number written to each device changes randomly or continuously as the test operator enters some starting value using the software. Other variables, such as product identification number (ID) also need to be changed for different products or volumetric capacity. Furthermore, the USB registry driver of the existing operating system (OS) does not perform these value and variable writing procedures, thus making the capacity USB test infeasible.

As shown in blocks 505, 506, and 507, the present invention provides several benefits to existing operating system USB registry drivers, namely, the time to format/test a large number of USB devices is reduced because the present invention utilizes specific manufacturing software . Furthermore, partitioning (capacity, driver letter) can be tailored to each different requirement according to known techniques. FIG. 6 is a simplified flowchart illustrating a method of manufacturing format/test for a USB device according to a specific embodiment of the present invention. The method of FIG. 6 can be used for single or multiple devices connected to the panel to achieve a high-speed "pipeline" format/test process, rather than slow individual DUT testing (as shown in FIG. 3(A)).

As shown in block 101, prior to starting the formatting/testing process for a selected DUT (a group of DUTs), a modified USB driver software is installed on the test host system to operate to block existing operating system USB from being recognized as "HCDI,sys" driver section. The software instructions used to prevent the execution of the segment "HCDI,sys" are well known to those skilled in the art. In one embodiment, some small files of the operating system's USB bus driver are replaced for this reason, as will be understood by those skilled in the art.

As shown at block 102, one or more "brandnew" (unformatted and untested) USB devices formed in accordance with the present invention are probed, plugged in, or otherwise coupled to a suitable fixture (such as a 4 (A) and one of the fixtures shown in Figure 4(B)).

As shown in block 110, an initial simple check of the plurality of USB devices is then performed by checking the contents of the controller hard-coded values to identify most common errors. Especially as shown in FIG. 6(A), once the USB device is coupled, the count value is set at "1", and the host test software reads at least some hard-coded data stored in a first device. (e.g., in controller ROM, one or more hard-coded configuration, interface, and endpoint descriptors (block 120)), bulk storage classcode (block 121), vendor identification (vendor identification , VID) and product identification (PID) values (block 122), and compare the hard-coded data with predetermined well-known good values to determine whether an incorrect USB device is coupled to the test host (block 123). If an incorrect device is detected ("No" path at block 123), a colored ( (such as red) displays a flag to generate a warning signal, warning the operator to remove the incorrect device. After a series of brief checks of selected devices ("Yes" path at block 123), a colored (eg, yellow) display flag or other graphic signal is displayed on the host test system (block 103B). Then in block 103C, the device count value is compared to a predetermined maximum number of devices based on the number of devices currently under test (all devices connected to the panel). If the count is less than the maximum number of devices, then the count is incremented (block 102A) and the brief check is repeated on another USB device coupled to the test system (ie, blocks 102-123 and block 103) until each is coupled to The devices of the host test system have been continuously checked briefly ("YES" path at block 103C), at which point the counter value is reset. As shown in block 103D, once all devices under test (DUTs) have been initialized, the program can optionally be paused by the operator and wait for a "continuation" signal (such as pressing the space bar on the host system or using the mouse to press START icon on the monitor). This pause allows the operator time to visually inspect the display flags of all DUTs, replacing any DUTs designated as defective (in this case, the initialization process will repeat for the newly added DUT). The method according to the present invention facilitates efficient and reliable programming on USB devices by briefly checking at least some hard-coded data before testing and/or formatting the flash memory device.

Referring again to Figure 6, once a brief initial check of all USB devices is complete, the test host proceeds to actually test and format the flash memory devices. This testing/formatting process begins at the first block of storage flash memory used to temporarily store predetermined code entry points (FIG. 6, block 130). As shown in FIG. 6B, in one embodiment, the saving process is performed on each DUT, and the count value is continuously set to "1" (block 131), the current DUT (DUT[Count]) is selected, and saved in the current DUT In, the flash memory is used in the first block of the entry point register (block 133), then the counter is incremented (blocks 135, 137), and the process is re-saved for the next DUT until all DUTs have been processed (in "Yes" path of block 135). Finally, the code entry points stored in the storage space include an operating system (OS) entry point, a firmware entry point and a non-volatile register entry point. Note that after the test/format process is complete, the actual code entry point value is written (downloaded) in the relevant field of the first block that is saved.

Next, check the capacity of the flash memory provided in each USB device (FIG. 6, block 140). FIG. 6(C) is a flowchart of the capacity checking process for each DUT according to an embodiment. The process starts by setting the count value to "1" (block 141). Afterwards, memory capacity checks are performed on each DUT by reading the initial bad block data provided in the flash device (i.e. reading flags located at fixed locations in the flash device is regulated by the manufacturer or supplier of the flash device. programmatic; block 142). The bad block data resulting from the scan is then used to determine if a certain percentage of reserved memory exists (blocks 143 and 144), and if insufficient reserved memory is provided, the DUT is rejected. According to test specifications for future bad block data relocation purposes (i.e. when one or more flash memory cells of a good block fail at some point, copy the data from the good block and relocate it in a reserved good memory Locating data in blocks), is a predetermined size (eg 20%) that requires reserve memory (representing a certain percentage of total "good" memory). Note that for USB devices with an even number (two or more) of flash memory chips, when a high proportion of bad blocks is detected, dual-channel operation is not suitable for mass production, so only single-channel operation is recommended. Before formatting the flash memory, the flash memory storage capacity of each USB device is checked, so the present invention helps to identify and reject unsuitable USB devices at an early stage, by reducing the total time required to program multiple USB devices, thereby reducing manufacturing costs. cost. After an acceptable storage capacity is confirmed ("Yes" path at block 144), two or more copies of bad block identification data are stored in the storage area of the flash memory to ensure safety (block 145). In one embodiment, bad block data is stored in memory locations that are located after memory locations reserved for entry point data (eg, 2nd and 3rd memory blocks), and two additional memory areas are reserved blocks (such as the 4th and 5th memory blocks) for future expansion. Storing two copies of bad block data provides redundant copies to ensure reliable long-term operation of the USB device. Once the capacity check and bad block data storage process is completed for the first device, the counter value will be incremented (block 147), and the capacity check and bad block data storage process will be repeated successively for each DUT until all DUTs have been affected Processed ("Yes" path at block 146).

Then, according to another embodiment of the present invention, a burst writing process is used to write at least one handle data and a boot code into a selected memory block of the flash memory (block 150 of FIG. 6 ). The control firmware produced by the manufacturer can be used to facilitate the operation of subsequent controllers. Generally speaking, existing USB devices include two types of ROM-based handles, static handles and dynamic handles. The static handle is composed of an initial reset jump address (jumpaddress) and mechanical information used to specify the basic flash erase/write/read operation state conforming to a wide range of flash memory types (for example, the static handle contains a relatively long Write time delay, which helps write operations to the "worst case" (slowest type of flash memory). According to the present invention, the static handle stored in ROM is obtained by the controller at start-up. The dynamic handle includes time adjustment control information to be used by the DUT to utilize a specific flash type (eg optimal number of write operations), which not only helps in the most appropriate operation of the flash memory, but also helps in maintaining domain adaptability. According to another embodiment of the present invention, the dynamic control firmware is stored in selected blocks of the flash memory to reduce the controller die size and facilitate domain adaptability. After the dynamic control firmware is written into the flash memory, a control bit of the DUT is reset to move the control of the DUT processor from the static handle to the dynamic firmware code. To facilitate the move to dynamic firmware, a static "jumpstart" firmware is provided in ROM that includes a dynamic handle to the address of the entry point for further execution use.

FIG. 6D is a simple flow chart showing a "pipeline" approach to write control firmware into each DUT using a burst write process to reduce processing time. The count value for the current DUT is initialized (block 151 ), and then a page (or block) of commands and/or data is written into the SRAM (volatile) buffer of the first DUT (block 152 ). As shown on the right side of block 152, a page of instructions and/or data includes writing control firmware into the block immediately following the bad block. After writing the page, the host system commands the DUT to write commands/data from the SRAM buffer into the flash memory unit (block 153). Note that at this stage of the format/test process, the dynamic handle has not yet been written to flash, so the write process used by the DUT is based on the slower static handle. According to the present invention, in order to help the writing process to be carried out in a time-sensitive manner, once a page of instructions/data is written into the SRAM and the DUT is commanded to perform the writing action, the host system proceeds to the next DUT (i.e. at block 157 , the count value increases, and then the host system writes the same command/data to the next DUT). Finally, a page of instructions/data is written to each DUT ("YES" path at block 155). Here, the host system determines whether all necessary command data has been written into each DUT. If not, the counter value is re-initialized (block 151), and the write process is repeated to write the instructions/data of the next page into the DUT. When the command/data of the second page is written into the first DUT (ie DUT[1]), the first DUT has completed the process of writing the command/data of the first page from the SRAM buffer to the designated block of the flash memory. Using this "pipeline" method, the process of writing dynamic handles to each DUT is performed in a highly efficient manner, avoiding long delays caused by the host system waiting for each DUT to write information/data to the flash memory .

In addition to the control firmware, in one embodiment of the present invention, one or more blocks of the flash memory are designated as non-volatile registers, and these non-volatile registers are used to store write-protected information, such as storing Values that will not be lost once the power is turned off immediately after use, such as the number of capacity divisions and user passwords. Information is written into each DUT, either during the burst write process described above, or in a subsequent (eg, second) burst write process after the dynamic handle is written to each DUT. Note that dynamic handles can then be used to speed up the write process if a subsequent burst write process is utilized.

Next, as shown in block 160 (FIG. 6), low-level formatting of the flash memory is performed, wherein the low-level formatting is based on the provided user specification. In one embodiment, low-level formatting includes writing main boot region (MBR), file allocation table (FAT), and initial root directory data into selected memory blocks of the flash memory. Without this data, the USB device cannot be used by the end user. Note that if an end user obtains a USB device that has not been low-level formatted, the USB device will not be usable, and the end user cannot use the operating system provided by the formatting software to perform this step. However, after completing the low-level formatting, end users can change the FAT format they want. During any of the burst write processes described above or during a subsequent burst write process after a dynamic handle is written to each DUT, low-level formatting information is written into each DUT (eg, the block in FIG. 6D ). 160A).

After low-level formatting, refresh serial number, date code, and product version code values are written to non-volatile registers (block 170 of FIG. 6 ), during any of the burst write processes described above or during dynamic handle During the burst write process after each DUT (such as shown in block 170A of FIG. 6 ), the descriptor information is written into each DUT.

Next, the test host reads all the information written to the flash memory (block 180), which is then compared with the values previously stored in the host system's buffer to confirm that the USB device is properly formatted. According to an embodiment of the present invention, the verification process is shown in Figure 6(E). The count value is set to "1" (block 181), and then the host system instructs the current DUT to reread the predetermined information from the flash memory. Note that the reread process is performed using a dynamic handle previously written to the DUT. Thereafter, the information read from the DUT is compared with previously stored data in the host system (block 183). If any data read from the USB device is incorrect ("No" path at block 184), a corresponding flag (such as a red flag) is displayed on the host test system monitor to instruct the operator The USB device fails the test/format process (block 185A). Conversely, if the data read from the current USB device is correct, a corresponding flag (such as a green flag) is displayed on the host test system monitor to indicate that the test/format process was successful (block 185B ). Thereafter, at block 187, the device calculation is compared to a predetermined maximum number of devices (eg, all devices connected to the panel) based on the number of devices currently being tested. If the calculated value is less than the maximum number of devices, the device count is increased one by one, and the test process is repeated for another USB device coupled to the test host until every device coupled to the host test system has been checked (in the box 187's "yes" path). Then, the test host program terminates.

FIG. 7 is a simplified block diagram showing an example USB device 10B in accordance with a particular embodiment of the present invention. As mentioned above, the USB device includes a flash card controller 214 and one or more flash memory devices 215 .

Referring to the left half of FIG. 7, flash memory 215 is described in FIG. 7 in simplified form, and further described below, wherein flash memory 215 includes entry point buffer 420 and bad block data 413, a control selection bit 415A, control Firmware 415B, and non-volatile register 421 . As shown, the communication between the controller 214 and the flash memory 215 is directly through the entry point register 420, which is related to the function to be executed, wherein the entry point register 420 indicates to the controller that the control firmware 415B and the non-volatile register are required. 420.

Referring to the right half of Fig. 7, controller 214 includes a microprocessor 450, a control end point register (control end point register) 451 and address decoder 452, a static random access memory (RAM), a read-only Memory (ROM), an input/output interface circuit 470 . The control endpoint register 451 provides the system default address required by each controller. The control endpoint register is used to communicate with this device, even if the address changes later. The static ROM 453 includes a RAM buffer (buffer) 453A and a flash access timing register (flash access timing register) 453B. Buffer 453A includes a sufficient amount of memory to store at least one block of flash memory 215, and may be used to facilitate, for example, when performing a block copy operation (such as reading data from flash memory 215 and writing to RAM 453). execution speed. During communication with the flash memory 215, the flash access time register 453B stores command codes utilized by the controller 214. The ROM 454 includes hard-wired data (that is, data that cannot be modified), wherein the hard-wired data includes jump start firmware 454A and different descriptors 454B. The jump boot firmware 454A includes a reset address vector that causes the microprocessor 450 to perform a large jump operation to the entry point register 420 of the flash memory device 215 . The jump-boot firmware 454A also includes most of the basic read/write/erase timing state machine data and block copy instructions since no code changes are required. In addition, the jump-boot firmware includes static scripts written into the flash access timing register 453B, and the static scripts are used as system default timing, for example, during initial read/write commands from flash memory 215 or during the initial read/write command to flash memory 215. Note, however, that the dynamic handle used to support different types of flash memory is stored in the control firmware register 415B of the flash device 215 to facilitate refresh. A different descriptor value 454B is also hardcoded in ROM 454 and is used when the test host requires specific information from USB device 10B. When the error value cannot be responded, it will cause the USB device 10B to be rejected by the test host, and be considered as a controller failure. For more detailed descriptor values, please refer to the specification of USB Mass Storage Class (USB Mass Storage Class). The controller 214 includes a bulk-only-transport (BOT) command decoder 456 to facilitate communication with the flash memory 215 using BOT commands. The logical block address-to-physical block address (LBA-to-PBA) converter/decoder 452 is used to decode the logical address generated by the BOT command decoder 456 . The input/output interface circuit 470 includes a physical layer USB transceiver 470A for transmitting and receiving NRZI signals different from USB, and a serial interface engine 470B for performing serial-to-parallel (receiving end) operation and Parallel-to-serial (parallel-to-serial) (transmitter) operation, a data buffer 470C is used to buffer the data frame of input/output (incoming/outgoing), and because the speed matching is not the same, so utilize serial interface engine 470B, Different registers and interrupt handling logic 470C are used to handle the USB protocol.

FIG. 8 is a simplified block diagram illustrating the different address structures and partitioning of flash memory 215 after the test/format process (described earlier) is complete. As shown in the left half of FIG. 8 , the flash memory 215 is mainly divided into a read-only area 405 and a read/write area 406 .

The read-only area 405 includes an entry point register 420 , a bad block list 413 , a reserve block 414 , a control firmware 415B, a master boot block (MasterBootBlock) 416 and a non-volatile register 421 . As shown in the right half of FIG. 8 , the entry point register 420 includes a control firmware entry point address 420A to store the location of the control firmware 415B, and a non-volatile register entry point address 420A to store the non-volatile cache Depending on the location of the different values of register 421, an operating system (OS) accesses address 420C to store the location of the main boot block 416. The ROM 405 can only be updated by the manufacturing test software, but cannot be changed by the general user host PC system. The control firmware 415B is executed by the microprocessor 450 of the controller 214 (refer to FIG. 7 ), and the control firmware 415B can only be read (that is, cannot be updated by the end user). Likewise, the non-volatile register 421 stores some values (such as product serial number or ID number) that can be refreshed during the testing/formatting process, but these values cannot be changed by the end user.

The read/write area 406 includes memory blocks for use by end users. In one embodiment, the read/write area 406 includes a basic file structure, so the file can be read/written by the host operating system, and can be divided into several partitions (partitions 1, 2, 3, 4). The first partition (partition 1) includes a file allocation table (FAT) 1417A and a file allocation table (FAT) 2417B, a directory 418, and a file cluster.

According to an embodiment of the present invention, when the USB device 10B starts to boot, the static handle is read from the jump boot firmware 454A to the flash access time register 453B. During an initial step (block 110 of FIG. 6 ), the controller 214 uses the flash memory 215 using the system default timing provided by the static handle, eg, reads the product identification data of the flash memory 215 . The product identification data is sent to the host system, which then compares the product identification data to a stored table to identify the time parameters that have been reset (alternatively, before the initial formatting process, the operator can first provide the product identification of the flash memory to the host system). Then, the host system writes the updated time parameters into the controller, and the controller stores the updated time parameters in the flash access time register. Once this process is complete, the controller utilizes the refresh time parameter to write the formatted information into the flash memory in an efficient manner, thereby reducing manufacturing time. Note that once the formatting is complete, the control selection bit 415A is set in the flash memory 215. When the USB device 10B is started up, the control selection bit 415A enables the controller 214 to write the dynamic handle to the flash memory access time from the control firmware 415B. Buffer 453B.

FIG. 9 is an exemplary bad block list stored in the flash memory 215 according to an embodiment of the present invention. In this embodiment, a binary value of “1” indicates a good memory block 402 , and a binary value of “0” indicates a bad memory block 401 . Two copies of the bad block data 413A and 413B are stored to ensure that even if one copy is later corrupted, the bad block data is still available. The other two blocks (refer to FIG. 8 ) are temporarily reserved for future use once one of the bad block lists 413A, 413B is broken. During manufacturing test, the manufacturing test software controls the renewal of all bad blocks. According to the process defined by the handle firmware 415B, when a bad block occurs during normal operation, the bad block list 413A, 413B will be activated to be updated. And, because whenever another bad block is found, another bit will be reset to "0", so in the list of bad blocks 413A and 413B, if you need to refresh other flash data blocks Before, it is never necessary to erase all bits to "1". Therefore, the blocks used to store bad block data have higher reliability.

FIG. 10(A) is a flowchart of manufacturing software algorithm algorithm for testing/formatting a USB device under test (DUT) according to another embodiment of the present invention. Testing begins when the DUT is coupled to the test host and all parameters are entered by the operator and immediately read by the test host (block 601 ). The software executes the Get_descriptor (reading) process to read the internal hard descriptor value (block 602) with the transmission instruction, and then, the software executes a Set_descriptor instruction to set the correct value (correct value) and increase or change the descriptor instead of adding Or change those descriptors stored in the controller's RAM buffer (block 603). Then, when executing a Get_configuration command, the software reads the initial configuration value (block 4), and then the Set_configuration software downloads each different configuration value (block 605). Then, the software reads an interface descriptor value, responds to a Get_interface command (block 606), and then the software uses the Get_interface command to download the correct value (block 607). Afterwards, the download device fixes the address to the USB device in response to the software's Set_address command. When successful, an associated colored flag changes in response to the plug-instatus (block 608). Then, reset the device register value (device register value) to respond to a Clear_feature command (block 609), and some special features, such as remote_wake up or endpoint_halt capabilities, are controlled by software set_feature (block 610). The USB device can be of many different types, such as a large storage capacity type, and can be executed by different types of specific instructions, such as like_max_lun (block 611), to read the number of divisions supported by the software. For unformatted devices, The software will command to set a system default value (default), wherein the system default value is based on the partition number of the flash device. Afterwards, a Get_status command is used to check whether the programming is successful (block 612). If successful, the color of each pattern on the test host monitor will change to indicate a successful programming status (block 613).

FIG. 10B is a flow chart of manufacturing software calculation rules for enumeration of a USB device under test (DUT) according to another embodiment of the present invention. This calculation process starts when the DUT is plugged into a test hub (testhub), which in turn is connected to a test host (such as a general PC). Since the DUT is not tested, either the D+ or D- pin should be identified with a 1.5K ohm pullup resistor connected at full speed or low speed (block 702). If the resistor value is incorrect or not connected, a colored flag will indicate a defective device and should be rejected as stated. Once the test host PC recognizes the DUT, the test host drives a Reset command to the DUT for at least 10 seconds (block 703 ). If the DUT responds appropriately to the reset command and indicates a successful reset status, the test host issues to the DUT using the system default control endpoint 0 (block 704). The test host PC then sends Get_descriptor to the DUT controller hard code value to get the Max Packet Size parameter (block 705), and the DUT responds by sending its transfer packet size (block 706). The test host PC then sends Set_Address to the DUT to assign a unique address. Assuming all communication between the test host PC and the DUT is successful here ("Yes" path of block 707A), then a short version of the mass storage driver is sent to the DUT for later communication (block 708 ). Afterwards, the test host sends a Get_descriptor command to the DUT to compare the device descriptor value with the system default value set by the system, and any inconsistency will be reflected on the test host PC to warn the operator to reject the DUT (block 709). If the device descriptor value is correct, the test host PC sends a set_configuration command to set the configuration number (block 710), and writes all necessary values into the DUT flash memory, thus completing the calculation (block 711).

FIG. 11 is an operation flowchart according to another embodiment of the present invention, showing all operation modes of the test host system on the USB device.

Referring to the upper part of FIG. 11, the operator starts the test plan (block 801), and downloads all configurations and all possible types of flash memory characteristic values into the program (block 802). These files are stored in the hard disk before being downloaded to the program. The program then waits for the operator to enter the correct parameters for the desired test, for example, the starting serial number of the selected device under test (DUT) or even a password to activate the program. As shown below block 804, there are two main instruction paths that will be decoded and executed: low level formatting (right branch under block 804) and flash software configuration (left branch under block 804).

Referring to the lower right part of Figure 11, low-level formatting includes a flash erase/read/write check for all flash memory blocks, because the flash memory may be used by other management providers first, and generally there will be differences Algorithm to mark bad blocks, so a test read/write (R/W) pattern is written to the flash memory of all flash blocks (block 810A). Afterwards, each R/W pattern is read and compared to the expected result. Then, although some blocks have been marked as bad, it is up to all blocks to be erased. Thereafter, low-level formatting is performed (block 811 ) during which only good blocks are erased to all binary "1" values. However, since the flash memory may be contaminated by previous use, it is possible to perform a complete scan for bad blocks through the parameter scan types selection entry.

Afterwards, the individual information of each memory card is written to the flash memory card to restore the individual memory card information (block 812). In one embodiment, the information includes serial number, product ID, supplier ID and LED light mode (block 817). Then the control firmware is written to the flash memory (block 813), for example, a binary (image) file is copied to the flash memory (block 818). In addition, the firmware entry point address is recorded in the non-volatile register of the flash memory. Afterwards, the FAT of the flash memory will be refreshed by software loading the pre-programmed file of the OS entry point address stored in the non-volatile register according to the customer's request. Then, when requested by the client, all initial files are copied to flash memory (block 815). These files may include auto-executable images or executable files for use in a precopy directory stored on the test host (block 819). Afterwards, the stored data is read back from the DUT and stored in the hard disk device of the test host for testing and future reference (block 816).

The left part of Fig. 11 includes an optional procedure for refreshing, such as the flash time stored in the dynamic handle. Initially, some parameters will be changed, for example, due to the change of the flash memory type in the test program, it may be necessary to confirm whether the test operator password is entered correctly, and confirm whether the new flash time is entered. However, if the process of FIG. 11 is used continuously to test DUTs with the same flash device, the optional process on the left of FIG. 11 does not need to be performed because the program retains the correct parameters for testing. Referring to the left part of FIG. 11 , after the low-level format is performed, the flash memory software configuration is used, and the flash memory configuration starts to check the pre-stored password input by the operator (block 805 ). Flash software configuration is limited to authorized personnel (such as device manufacturers), while unauthorized personnel without passwords will be rejected by the system and cannot use it. Once the correct password is confirmed, the software will wait for operator input (block 805A). Flash memory is produced by many different suppliers with many different parameter settings, as memory capacity continues to increase from each supplier. The first step in software configuration is to identify the specific flash memory used on the target DUT (block 806). In order to make the configuration process sound, the sequence of flash memory types is programmed in advance to achieve flexibility (block 807), and the user can update the sequence, and for easy modification, all update information is displayed on the device monitor (block 808), and then change or save in the file for future reference.

FIG. 12(A) and FIG. 12(B) are simplified schematic diagrams showing the operation of defective flash memory chips in dual channel and single channel, respectively. FIG. 13(A) and FIG. 13(B) are block diagrams describing related flash memory configurations. When there is a double number of flash memory chips integrated into the device, two options can be applied: single route or dual route operation.

In the dual route operation shown in Figure 12(A), the slave controller 214 divides the data bus into two parts: the data line data [7:0] is connected to the flash memory chipset 215-1, and the data line data [15:8] It is connected to the flash memory chipset 215-2, and both memories share the same controller address and control bus 90. The advantage of the dual route operation as shown in 12(A) is that it is fast because the data bus becomes doubled. As shown in Figure 13(A), the disadvantage of single-route operation is that the bad block (BB) area on either side of the flash memory chip is generally asymmetrical, but because the address and control bus are connected together, symmetric operation results in Generate bad blocks and reduce the available good block capacity. The addresses of the two groups of flash chips are also staggered, in order to reflect the connection of the data bus.

FIG. 12(B) shows a single-way operation where two memory banks 215-1A and 215-1B are connected to the data line data[7:0]. In single-way operation, the physical address range is continuous, as shown in FIG. 13(B), and there is no bad block situation caused by double-way operation as described in FIG. 13(A). Accordingly, the usable capacity of the single-way operation is more than that of the dual-way operation, and the area is prepared and expanded to erase the gap caused by bad area reservation purposes. However, the disadvantage of single-way operation is that the operation is slower because only 8 bus ways Data[7:0] are used instead of the 16 data bus ways used by dual-way operation. However, because of the increase of flash chips with a high proportion of bad blocks, such as the recent production of a large number of flash chips, it is best to use a single route operation.

14 is a block diagram showing information and parameter settings stored in different memory areas of each USB device according to the present invention. All parameters can be changed by the operator and are divided into two categories: device information and configuration information.

The device information is stored in each device 10B in a block (field) located in the upper area of FIG. 10 . Block 905 includes a maximum device size (eg, 256MB). Block 901 includes the device size established by the device manufacturer (eg, for a device with a maximum size of 256MB, the effective device size can be set at 250MB, and the remaining 6MB is reserved for bad block management). Block 902 includes the use of flash parts, for example, the manufacturer's part number is established by Samsung or Infineon (eg Samsung's K9K8G08U0M 1Gbyte flash device). Block 903 includes a flash memory ID information, which is read through the flash initial command address 90H and used to determine whether the flash memory device is correct, because some flash memories have different time properties but share the same ID code. In order to allow end customers to easily access different NAND flash time specifications, this feature is provided to help in flash ID adjustment. Block 904 includes the number of flash chips used in the particular device 10B. Blocks 905A, 905B and 905C store the different passwords used during formatting/testing and subsequent modification of the USB device. Because operator passwords are very important for controlling the manufacturing process, and to maintain test quality, password modification (block 905B) and validation (block 905C) are critical for formal access to the MIS control test program.

The configuration information of the device 10B is disclosed in the block diagram below the device information in FIG. 10 . Block 906 includes production line number information, an operator ID number used in production control messages. Block 907 includes pre-scanning flash type information, which includes different methods of scanning flash memory (erase/read/write), a skip back block value (skip back block value) (block 907A), a Full scan values of all blocks (block 907B), one scans good blocks and skips bad block flag values implanted by the manufacturer (block 907C). For those devices using flash components, a full scan is recommended to rebuild the bad_block_list (block 907B). Block 908 includes the main serial number (serial number, S/N), and block 908A includes the initial S/N of this particular device, with the updated serial number information of block 908B, regardless of whether the serial number is generated using a predetermined sequence or randomly (that is, the serial number can be increased or decreased, or can be arbitrarily generated by the operator's input (such as software calling a random number generator and a sub-parameter (such as the host tester time/date)) to ensure its randomness), the main principle is The serial number needs to be different for each device according to the USB specification. Block 909 includes current specifications and limits for the device (eg, the maximum current draw of the device), where a device exceeding this amount is an indication of device failure (eg, 500ma is the maximum specified current listed for a USB device). Block 910 includes a time interval and brightness value of the LED lights of the device under different conditions, and used to inform the operator of the operational status (eg, when the test is aborted or successful or the device is idle or in use). Block 917 includes the vendor/product ID number of the correct controller used to allow the test/format process (i.e. devices with mismatched vendor/product numbers in this category will initially be subject to the test/format system reject). Block 911 includes supplier name and product content decoding information, and block 912A includes product serial name (string name) and version information. Block 913 stores a statistical value representing the pass/fail test number of products tested on the test product line (block 913A is used to reset this value), and block 915 includes a maximum test number of test product lines, because the test is performed by Initially set by an operator, this information is used to provide useful statistical information to the operator. Block 919 includes the maximum reserved ratio of flash memory (ie, the amount of reserved memory required for bad block allocation for future operation purposes). Block 921 includes a write protection switch (on or off), and block 920A includes a capacity allocation number, which is used to record that the flash memory can be allocated to multiple different areas during storage, so as to achieve the purpose of data classification. Block 920 stores an initial volume label, such as D: (E:, F:, and so on). Finally, block 920 contains the BIN number of each device corresponding to each slot, and this information is used to disclose an error code when the device fails the test/format process.

Because the multi-level-cell (MLC) flash memory has higher storage density than the single-level cell flash memory with the same size, the MLC flash memory is becoming more and more popular. According to some embodiments of the present invention, the techniques described above can be applied to mass production of MLC flash memory or production testing of MLC flash memory. More detailed information about MLC flash memory can be referred to above content and US Patent Application No. 11/737,336, wherein US Patent Application No. 11/737,336 is assigned to the same assignee of the present application.

FIG. 15 is a diagram showing multilayer voltage sensing of an MLC memory cell (CELL), according to an embodiment of the present invention. The system shown in FIG. 15 can be used with the techniques described above. A flash memory chip has a flash memory unit (flash cell) array, which is arranged in a row (row) and column (column) mode, and the flash memory cell array is selected according to the row part of the address and the column part of the address. The address can be generated by a sequencer according to the area address or page address put into the flash memory chip. A third part of the address effectively selects bits within the MLC memory cell.

Referring to FIG. 15, the control engine 1052 receives the address and selects one or more flash memory cells at the intersection of the selected row and column. The MLC address is sent to translation logic 1060 to generate multiple bits per memory cell. According to the MLC address of the control logic 1052, one or more bits are selected from the bits of each memory cell output by the decoding logic 1060. Typically, 8 or more flash memory cells are read and sensed by 8 or more bit lines in parallel, or by 8 or more copies of the interpreter logic 1060. sensing, but only the bit division is displayed.

The bit line 1058 is first charged by the pull-up (pull up) 1056, the selected flash memory cell 1054 is at the intersection of the selected row and column, and the flash memory cell 1054 has a gate voltage VG, its is applied when the channel is open, depending on the state of the flash memory unit 1054. Different states may be programmed into the flash memory cell 1054, and each state stores a different amount of charge on the floating gate of the flash memory cell 1054, so each state causes a different amount of channel current to flow through the flash memory Cell 1054, from bit line 1058 to ground. The adjustable current flows through the flash memory unit 1054 , combined with the pull-up current from the pull-up 1056 to form a voltage divider. The voltage on bit line 1058 thus changes as the state is programmed into flash memory cell 1054 .

The bit line 1058 is used as the inverting input terminal (inverting input) of the comparator 1030-1040, and the non-inverting input terminal is a reference voltage for the comparator 1030-1040, and this reference voltage is provided by the reference-current generator 1041-1051 produced. The voltages generated by the reference-current generators 1041-1051 are controlled by the control engine 1052 and respond to these reference state voltages, upper state voltages, and lower state voltages for sensing the states of the four memory cells.

The voltages generated by the reference voltage generators 1041-1051 are continuous high voltages, so the bit line voltage exceeds the lower reference voltage, clearing the output of the lower state comparator, and when the bit line voltage cannot exceed the upper reference voltage , so that the higher state reference voltage output is maintained at the original setting. The location of the transition from comparators 30 - 40 outputting 0 to comparators 1030 - 1040 outputting 1 is indicative of the induced voltage on bit line 1058 . For example, when the comparator outputs 0 and the comparator outputs 1, a 0-to-1 transition occurs in comparators 1037 and 1038 . The voltage IU2 is applied to the comparator 1037 , and the voltage IR3 is applied to the comparator 1038 . The voltage on bit line 1038 is between IU2 and IR3, which is read as state 3 (01).

Decode logic 1060 receives the 11 comparator outputs from comparators 1030-1040 and detects the position of the transition from 0 to 1. The decoding logic 1060 generates several outputs, such as read data bits (read data bits) D1, D0, which are 2 bits, and are used to decode the states read from the memory cells. A 4-bit MLC will have an interpreter logic that outputs four read data bits D3, D2, D1, D0.

Other outputs from interpret logic 1060 are useful during memory cell programming. During programming, the memory cell is slowly charged or discharged, so the voltage on the bit line 1058 changes. Once the required data is read from the data-read output D1, D0, the operation stops. However, to ensure a sufficient noise margin, the bit line voltage should be stated between the upper and lower state voltages, such as between VL2 and VU2, rather than between adjacent read-reference voltage, such as between VR2 and VR3. When the bit line voltage is between VR2 and VL2, the under-program output is enabled, and when the bit line voltage is between VU2 and VR3, the over-program output is enabled. When the bit line voltage is between VL2 and VU3, neither the under-program output nor the over-program output is enabled.

The less than or equal to output can also be enabled when a desired memory cell value has been reached. A bit select output less than or may supply write data to interpret logic 1060 to allow a less than or equal output to the target logic state. The interpretation logic 1060 can be used as a truth table. Because the reference current flows through the resistor to generate a reference voltage, so when the comparators 1030-1040 are current comparators, the reference-current generators 1041-1051 can generate the reference current or the reference voltage.

Figure 16 shows a programmable continuous reference generator and operational amplifier. The voltage reference generator 1120 generates a higher reference voltage to be applied to the upper operational amplifier 1161 and the resistor 1101 . The calibration register 1122 can be programmed to different values to adjust the highest reference voltage value generated by the voltage reference generator 1120 .

Applying the higher reference voltage to a series of resistors 1101-1111 forms a voltage divider to ground. The resistance value of each resistor 1101-1111 can be the same, so the voltage difference between the higher reference voltage and the ground terminal can be divided into 11 equal voltage segments, resulting in 11 partial voltages. Alternatively, each resistor 1101-1111 can have a different programmable value to provide even more voltage control.

Each divided voltage from resistors 1101-1111 is applied to the non-inverting input (+) of one of operational amplifiers 1161-1171, the output and inverting input of each operational amplifier 1161-1171 are connected together to achieve high efficiency. The inverting output terminal is connected to the ground terminal via ground resistors 1181-1191, wherein the ground resistors 1181-1191 have the same resistance value. Each operational amplifier 1161-1171 generates a reference voltage equal to the divided voltage applied to the non-inverting input. Eleven reference voltages are thus generated, which have steadily increasing voltage values. These reference currents correspond to the reference currents generated by the reference-voltage generators 1041-1051 of FIG. 15 .

When a data error occurs during the read of the flash memory cell, the reference voltage compared to the bit line voltage is adjusted in an attempt to recover the data in the flash memory cell. For example, leakage may reduce the charge stored in the floating gate of the flash memory cell, causing too much current to flow through the selected channel of the flash memory cell 1054 (FIG. 15). Therefore, the bit line voltage drops. The calibration register 1122 can be reprogrammed to reduce the highest reference voltage generated by the voltage reference generator, reducing all reference voltages applied to the operational amplifiers 1161-1171. The bit line voltage may now fall within the correct reference value, allowing data to be read without exceeding the maximum allowable number of ECC errors.

The correction buffer 1122 can be changed gradually until all the read data is correct. The ECC byte can be used to detect errors, so when the ECC checker reports few or no errors, the reference-voltage adjustment can be stopped and the data read. Blocks can be redistributed.

FIG. 17 is a flow chart of downgrading of an MLC during a write or erase operation. When an error occurs during a write or erase operation, step 1202, the ECC checker flags too many errors during a read or low activity, then the downgrade process is initiated. The bits-per-cell indicator is read from the block or the spare area of a particular block, step 1204 . When the memory bit indicator is already 1 bit per memory cell, step 1206, the memory cell is downgraded to the minimum density first, and the error is still occurring, the downgrade is unsuccessful. Step 1208, mark the block as a bad block by clearing the bit in the bad block byte (Byte) of the redundant area, so this block is now removed from future use. Step 1210, if necessary, another block can be selected for operation.

When a block has its memory bit indicators to set 2 or more bits per memory cell, the block can then be degraded. Step 1214, the number of bits/memory cells read from the memory bit indicator of the redundant area of the block is reduced to the next lower level, for example, from 4 bits per memory cell (4 bits/memory cell) to 3 bits per memory cell (3 bits/memory cell). The size of the blocks may be reduced, or the arrangement of the blocks may be changed to accommodate the reduced number of bits per memory cell. For example, from 4 bits/memory cell to 3 bits/memory cell, the block size can be halved. After demoting, the pages of a chunk can have half the number of logical dividers.

Step 1216, write the reduced bits/memory units to the memory bit indicator to downgrade the block. Write or erase operations can then be re-executed on the degraded block. When the downgrade process is triggered by a read error exceedance, the block can be erased once the data has been read and relocated to another block.

FIG. 18 is a flow chart of reading error correction using ECC bytes and adjusting voltage references. Read errors can be detected by checking the read data to ECC bytes. For example, non-zero symptoms generated from data and ECC bytes can signal error generation, as well as signal erroneous bit positions and error corrections.

Step 1220, activate the process when a read error is detected. Step 1222 , when the number and location of errors allow the use of ECC bytes to correct errors, then the ECC bytes can be used to correct read errors, step 1242 . In step 1230, the data can be relocated in another block, using memory bit pointers to enable block erasure and optionally downgrade.

The number of correctable errors is a fixed number, such as an ECC limit, or varies with error location, such as any 3 bits in a byte, or any string of 4 bad bits. The ECC limit can also be set arbitrarily, or set to a lower correctable value, but still there are unpleasant, degraded blocks that should be described, even though their errors are correctable.

In step 1222, when the number of errors exceeds the ECC limit, the ECC mechanism cannot correct all errors, so data may be lost. Therefore, by adjusting the reference voltage level compared with the bit line voltage, an attempt is made to recover the lost data. In step 1224, the calibration register 1122 is written with new value data so that the voltage reference generator 1120 generates a higher reference voltage. This causes all reference voltages to gradually increase in series. At step 1226, the data in the block is read using these higher reference voltages. After that, and check the data for errors using ECC bytes. At step 1228, raising the reference voltage is successful when the number of errors is reduced below the ECC limit. At step 1232, the ECC bytes can be used to correct any remaining errors. At step 1230, the data is then relocated to other blocks. This block can be downgraded through the call downgrade process in Figure 17.

Increasing the reference voltage is sometimes successful when the amount of negative charge stored in the flash memory cell increases. Also, the increase in negative charge is due to memory cell disturbances resulting from reading or programming adjacent memory cells. The excess negative charge requires a higher gate voltage to compensate, so increasing the reference voltage is effective.

In step 1228, when the number of errors still exceeds the ECC limit, then increasing the reference voltage is not successful. Wherein, the reference voltage can be increased by repeating steps 1224-1228 (not shown in the figure) several times.

When increasing the reference voltage but unable to recover the data, the reference voltage can be lowered. In step 1234, the calibration register 1122 of FIG. 16 is written with new value data so that the voltage reference generator 1120 generates a lower reference voltage. This causes all reference voltages to decrease in series. At step 1236, the data in the block is read using these lower reference voltages. After that, and check the data for errors using ECC bytes. At step 1238, lowering the reference voltage is successful when the number of errors is reduced below the ECC limit. At step 1242, the ECC bytes can be used to correct any remaining errors. At step 1230, the data is then relocated to other blocks. This block can be downgraded through the call downgrade process in Figure 17.

Lowering the reference voltage is sometimes successful when the amount of negative charge stored in the flash memory cell decreases. Also, leakage can cause negative charges to decrease. The reduced negative charge causes excess channel current to flow through the selected memory cell in response to a fixed gate voltage. The excess channel current causes the bit line voltage to be lower than usual, so the reference voltage must be lowered to compensate for memory cell leakage.

In step 1238, when the number of errors still exceeds the ECC limit, then lowering the reference voltage is not successful. Wherein, the reference voltage can be lowered by repeating steps 1234-1238 (not shown) several times. However, when the number of data errors does not fall below the ECC limit, the table data is lost. At step 1240, an unrecoverable data error is signaled. Further detailed information on the above process can also be referred to US Patent Application No. 11/737,336.

According to some embodiments, MLC flash memory can be used on USB devices with dual USB plugs, which can support multiple communication interfaces, ie dual.

19A-19C are perspective views showing a USB extension plug with multiple properties according to an embodiment of the present invention. Referring to FIG. 19A , the USB expansion plug is shown in a full view 1301 and an exploded view 1302 . In one embodiment, the USB extension plug 1300 includes a housing or shell 1303 and a USB connector substrate 1304, wherein the USB connector substrate 1304 can be inserted into the housing 1303, and the housing 1303 is made of metal, that is, a metal case. The connector substrate 1304 includes a first terminal and a second terminal, wherein the first terminal has a plurality of metal fingers or tabs 1305 , and the second terminal includes a plurality of electrical contact pins 1307 . In a specific embodiment, pin 1307 has 9 pins. The connector substrate 1304 also includes one or more springs 1306 for providing pressure to another USB connector to make substantial contact with the contact fingers 1305 when the other USB connector is inserted into the opening of the USB expansion plug.

In one embodiment, the contact fingers 1305 can be located on an upper surface of the connector substrate 1304 , and other contact fingers (not shown in the figure) can be located on the lower surface of the connector substrate 1304 . For example, the contact finger 1305 conforms to the standard USB specification, and other contact fingers can be designed to conform to other interfaces, such as PCIExpress or IEEE1349 specification interface. Therefore, the USB extension plug 1300 can be used for a plurality of different communication interfaces, that is, duality. Further detailed information on dual-purpose USB extension plugs can be found in the aforementioned applications or patents, such as US Patent No. 7,021,971 and US Patent Application No. 11/864,696, which are hereby incorporated by reference.

Referring now to FIG. 19B, the USB expansion plug 1300 can be connected to a PCBA, wherein the PCBA has a memory device and a memory controller for controlling the memory device. As shown in the top view 1308 , side view 1309 , and bottom view 1310 of FIG. 19B , the USB extension plug 1300 is connected to the PCB substrate 1311 , for example, by soldering pins 1307 on the PCB substrate 1311 . In addition, a memory device, such as a flash memory device, may be located on one surface of the PCB substrate 1311, and a memory controller, such as a flash controller, may be located on the other surface. In this example, the memory device 1315 is located on the bottom surface 1313 of the PCB substrate 1311 , and the memory controller 1314 is located on the upper surface 1312 of the PCB substrate 1311 . In one embodiment, the memory device 1315 may be an MLC compatible memory, and the memory controller 1314 may be an MLC compatible memory control IC.

According to another embodiment, the techniques described for FIGS. 19(A)-19(B) can also be applied when the flash memory and the flash controller are integrated on a single package, such as the board shown in FIG. 19(C). Chip on board (COB) package. Referring to FIG. 19C, a COB package 1316 can be a kind of MLC package, which can be located on the upper surface 1312 of the PCB substrate 1311, wherein the COB package 1316 can pass one or more contact fingers (contact finger) 1317 on the surface of the COB package 1316. connection (e.g. soldering).

20A and 20B are perspective views showing a USB extension plug with multiple properties according to an embodiment of the present invention. Referring to FIG. 20A , the USB extension plug is shown in full view 1401 and exploded view 1402 . In one embodiment, the USB extension plug 1400 includes a housing or shell 1403 and a USB connector substrate 1404, wherein the USB connector substrate 1404 can be inserted into the housing 1403, and the housing 1403 is made of metal, that is, a metal case. The connector substrate 1404 includes a first terminal and a second terminal, wherein the first terminal has a plurality of electrical contact fingers or tabs, and the second terminal includes a plurality of electrical contact pins 1407 . In a specific embodiment, the pins 1407 have a first column and a second column, wherein the first column has 5 pins, and the second column has 4 pins. The connector substrate 1404 also includes one or more springs 1406 for providing pressure to another USB connector to make substantial contact with the contact fingers 1405 when the other USB connector is inserted into the opening of the USB expansion plug.

In one embodiment, similar to the USB extension plug 1300 , the contact fingers 1405 can be located on an upper surface of the connector substrate 1404 , and other contact fingers (not shown) can be located on the lower surface of the connector substrate 1404 . For example, the contact finger 1405 conforms to the standard USB specification, and other contact fingers can be designed to conform to other interfaces, such as PCI Express or IEEE1349 interface specifications. Therefore, the USB extension plug 1400 can be used for a plurality of different communication interfaces, that is, duality.

Referring now to FIG. 20B, the USB expansion plug 1400 can be connected to a PCBA, wherein the PCBA has a memory device and a memory controller for controlling the memory device. As shown in the top view 1408 , side view 1409 , and bottom view 1410 of FIG. 20B , the USB extension plug 1400 is connected to the PCB substrate, for example, by soldering pins 1407 on the PCB substrate. As in the example shown in side view 1409, a first row of pins 1407 may be soldered on an upper surface of the PCB substrate and a second row may be soldered on a lower surface of the PCB substrate, or vice versa. In addition, a memory device, such as a flash memory device, can be located on one surface of the PCB substrate, and a memory controller, such as a flash controller, can be located on the other surface of the PCB substrate. In this example, similar to that shown in FIGS. 19A-19B , a memory device is located on the bottom surface of the PCB substrate, and a memory controller is located on the upper surface of the PCB substrate. Moreover, the memory device can be an MLC compatible memory, and the memory controller can be an MLC compatible memory control IC.

Likewise, according to yet another embodiment, the techniques described in FIGS. 20A-20B can also be applied to a flash memory and a flash controller integrated in a single package, such as a COB package as shown in FIG. 20C . Other types of packaging are also available.

21A-21I show an embodiment of a USB expansion connector and a socket with metal contact pins, wherein the metal contact pins are located on the upper surface and the lower surface of the pin substrate. Please note that the embodiment shown in Figures 21A-21I can be combined with any of the previous embodiments. Referring to FIG. 21A, the expansion connector has a plastic housing 2176 for the user to hold when inserting the connector plug into the socket. The pin substrate 2170 has four metal contact pins 2188 located on its upper surface, wherein the substrate 2170 is made of insulating material, such as ceramic, plastic or other materials. Metal leads or wires may pass through the lead substrate 2170 to connect the metal contact pins 2188 to wires inside the plastic housing 2176 for connecting to peripheral devices.

Five back metal contact pins 2172 are located on the bottom of the pin substrate 2170, near the end of the connector plug. The metal contact pins 2172 on the back are extra pins used for expansion signals, such as PCIExpress signals. Metal leads or wires may pass through the lead substrate 2170 to connect the metal contact pins 2172 to wires located in the plastic housing 2176 for connecting peripheral devices.

In some embodiments, the metal cover 2173 is a rectangular tube surrounding the pin substrate 2170 and has an open end. An opening in the metal cover 2173 at the bottom of the pin substrate 2170 allows the rear metal contact pins 2172 to be exposed.

FIG. 21B shows a USB expansion slot with 4 metal contact pins on the upper surface of the pin substrate and 5 metal contact pins on the lower surface of the pin substrate. The contact substrate 2184 has four metal contact pins 2186 formed on a bottom surface facing the groove for inserting the pin substrate 2170 of the connector. The pin base 2184 also has a lower base extension 2185 with an L-shaped pin base, which is not present in existing USB sockets.

Five metal contact pins 2180 are located on a lower substrate extension 2185 near the open end of the recess. A bump or spring can be formed on the metal contact pin 2180, such as by bending a flat metal pin. This bump allows the metal contact pin 2180 to contact the metal contact pin 2172 on the backside, which is located on the pin substrate 2170 of the connector.

The groove is formed by connecting the bottom surface of the pin substrate 2184 , the upper surface of the lower pin substrate 2185 and the back surface of the pin substrate 2184 to the lower substrate extension 2185 . The metal cover 2178 is a metal tube covering the pin substrate 2184 and the lower substrate extension 2185 . The metal cover 2173 of the USB connector fills the gap between the metal cover 2175 and the top and sides of the pin substrate 2184 . Mounting pins 2182 can be formed on the metal cover 2178 to mount the USB socket to the PCB or chassis.

FIG. 21C shows the bottom surface of pin substrate 2184 for metal contact pins 2186 to be located thereon. These four pins carry different signal, power, and ground of the existing USB, and are in contact with the metal contact pins 2188 of the USB connector on the upper surface of the pin substrate 2170, as shown in FIG. 21D .

The USB contact has five back metal contact pins 2172 located on the bottom surface of the pin substrate 2170, arranged as shown in FIG. 21D. These pins 2172 are in contact with extended metal contact pins 2180 arranged on the lower substrate extension 2185 as shown in FIG. 21C. These 5 expansion pins carry expansion signals, such as PCI Express signals.

Figure 21E shows a 9-pin USB connector plug inserted into a 9-pin USB receptacle. When fully inserted, the ends of the contact substrate 2170 fit between the pin substrate 2184 and the lower substrate extension 2185 of the USB receptacle. On the upper surface of the pin base plate 2170 of the connector, metal contact pins 2188 make contact with four metal contact pins 2186 of the socket pin base plate 2184 . The backside metal contact pins 2172 on the bottom surface of the pin substrate 2170 are in contact with the extended metal contact pins 2810 on the upper surface of the lower substrate extension 2185 .

Because the back metal contact pin 2172 is recessed, it will not contact with the metal cover 2138 of the existing USB slot. FIG. 21F is a schematic diagram of a standard 4-pin USB connector and an extended 9-pin USB connector before the connector is inserted into a USB slot. When fully inserted, as shown in FIG. 21G , the ends of the connector pin substrate 2134 are inserted under the socket contact substrate 2134 . At the upper surface of the connector pin substrate 2134 , metal contact pins 2132 make contact with four metal contact pins 2186 of the socket pin substrate 2184 . Because the standard 4-pin USB connector has only four pins 2132, the contact pins on the upper surface of the socket pin substrate 2185 are not in electrical contact with the USB connector.

22A-22I are diagrams showing a second embodiment of a USB connector and socket, with metal contact pins on one of the contact substrate surfaces. FIG. 22A shows an extended 9-pin USB connector plug with four metal pins and five extended metal pins on the upper surface of the pin substrate. In Figure 22A, the connector has a plastic housing 2196 for the user to hold when inserting the connector plug into the socket. The pin base plate 2190 has the metal contact pins 2200 , 2201 located on its upper surface, wherein the base plate 2190 is made of insulating material, such as ceramic, plastic or other materials. Metal leads or wires may pass through the lead substrate 2190 to connect the metal contact pins 2200 , 2201 to wires inside the plastic housing 2196 for connecting to peripheral devices.

The length of the pin substrate 2190 is longer than the length L2 of the pin substrate 2134 . The increased length may be 2-5mm, and the end metal pin 2201 is mostly located in the extended area beyond L2. The metal cover 2193 is a rectangular tube surrounding the pin substrate 2190 and has an open end.

FIG. 22B shows an expansion socket with four metal contact pins and five expansion metal contact pins on one of the pin substrate surfaces. The pin base 2204 has metal contact pins 2206, 2207 formed on a surface facing the recess into which the pin base 2190 of the connector is inserted. The pin base plate 2204 does not require the lower base plate extension of FIG. 21B, but may have an L shape as shown.

The metal cover 2198 is a metal tube covering the pin substrate 2204 and has an opening below. The metal cover 2193 of the USB connector is inserted into the gap between the metal cover 2198 and the top and side of the pin substrate 2204 . Mounting pins 2202 can be formed on the metal cover 2198 to mount the USB extension slot to a PCB or chassis.

FIG. 22(C) shows an expansion 9-pin USB connector plug inserted into the 9-pin socket. The metal contact pins 2207 and 2206 formed on the bottom surface of the pin base plate 2204 of the socket respectively contact the metal pins 2201 and 2202 on the pin base plate 2190 .

FIG. 22(D) shows the bottom surface of the socket pin substrate 2204 upon which metal contact pins 2206, 2207 may be located. The primary metal contact pins 2206 are the five pins in the first row, closest to the slot opening. Secondary metal contact pins 2207 are the four pins in the second row, the secondary metal contact pins 2207 furthest from the slot opening include four USB pins. The main metal contact pins 2206 include expansion pins for supporting other interface specifications, such as PCI-Express.

When the USB connector is fully inserted into the USB socket, the ends of the pin substrate 2190 fit into the grooves below the contact substrate 2204 of the USB socket. At the upper surface of the connector pin substrate 2190, the metal contact pins 2200 are in contact with the six main metal contact pins 2206 of the socket pin substrate 2204, and the metal contact pins 2201 at the end of the upper surface of the pin substrate 2190 are in contact with Secondary expansion metal contact pins 2207 on the bottom surface of pin substrate 2204 make contact.

FIG. 22(F) shows a schematic view of an expanded 9-pin connector before it is plugged into a standard 4-pin USB slot. When fully inserted, as shown in FIG. 22(G), the ends of the pin base plate 2190 are inserted under the slot pin base plate 2142. On the upper surface of the connector pin substrate 2190 , the first, third, fourth and sixth of the end metal contact pins 2201 are in contact with the four USB metal contact pins 2144 of the socket pin substrate 2142 . The last row of metal pins 2200 on the upper surface of the pin base 2190 do not make contact with the socket metal cover 2138 or any metal contact pins because they are located too far behind the connector pin base 2190 . Therefore, only four standard USB pins (metal contact pins 2144, 2201) can be electrically contacted.

FIG. 22H shows a schematic view of a standard 4-pin USB connector before being inserted into an expanded 9-pin USB slot. When fully inserted, the ends of the connector pin substrate 2134 are inserted below the socket pin substrate 2204 as shown in FIG. 22(I). On the upper surface of the connector pin base 2134 , the metal contact pins 2132 are in contact with the first, third, fourth and sixth four primary metal contact pins 2206 of the socket pin base 2204 . The secondary metal contact pins 2207 on the substrate 2204 are not in contact with the contactor metal cover 2133 because the depth of the extended USB slot is greater than the length of the prior art USB connector. Therefore, only four standard USB pins (metal contact pins 2132, 2206) can be electrically contacted. As shown in Figures 22(F)-22(I), the expanded 9-pin USB connector plug and socket are electrically and mechanically connected to the standard existing 4-pin USB socket and USB connector plug.

The above descriptions are only preferred embodiments of the present invention, and are only illustrative rather than restrictive to the present invention. Those skilled in the art understand that many changes, modifications, and even equivalents can be made within the spirit and scope defined by the claims of the present invention, but all will fall within the protection scope of the present invention.

Claims (10)

1. the method for a format/testing general sequence bus unit is characterized in that: it is to utilize a Test Host that contains computing system to realize that described method is to comprise:

Couple plural USB device to described Test Host, each described USB device comprises a quickflashing controller and at least one flash memory device, wherein each described USB device comprises a USB connector plug that expands, couple a printed circuit board device or couple a chip on board, it has at least one flash memory device and quickflashing controller, and wherein said expansion USB connector plug comprises:

One expands the pin substrate, has one and expands length, and it is more than or equal to the standard length of the pin substrate of standard USB connector plug;

The standard metal contact pin of plural number plug, be positioned on the described pin substrate, the standard pin substrate of described expansion USB connector plug inserts in the groove of standard USB slot, and standard metal contact pin electrically contacts with described plug standards Metal Contact pin essence; With

The plural number plug expands the Metal Contact pin and is positioned on the described expansion pin substrate, the described expansion pin substrate of described expansion USB connector plug inserts in the groove that expands the USB slot, and the slot expansion Metal Contact pin essence that is positioned at the described plug expansion Metal Contact pin on the described expansion pin substrate and is positioned on the described expansion USB slot is electrically contacted;

Read at least one controller endpoint descriptor value from each described USB device, the described controller endpoint descriptor value of checking each described USB device is to match with the descriptor value that is stored in described Test Host; With

To having each described USB device format/test of an effective end points descriptor value, by tentation data being write in the flash memory device with pipelined fashion, in described flash memory device, read described tentation data afterwards, relatively with described tentation data that is read and the known good data value that has described Test Host.

2. the method for format according to claim 1/testing general sequence bus unit, it is characterized in that: also comprise and a usb driver is installed, indicate described computer system in a single day to detect the USB register flow path that described USB device just stops standard to described Test Host.

3. the method for format according to claim 1/testing general sequence bus unit is characterized in that: also comprise described USB device is set, make described USB device be connected to a panel.

4. the method for format according to claim 3/testing general sequence bus unit, it is characterized in that: before described USB device is connected to described panel, also comprise the described panel of simplification, or behind all described USB devices of continuous formsization/test, the described panel of simplification.

5. the method for format according to claim 1/testing general sequence bus unit, it is characterized in that: read the step of described controller endpoint descriptor value from each described USB device, it is drawn together and reads at least one configuration descriptor value, a large amount of storage class code values, supplier's identifier and a product identifier.

6. the method for format according to claim 1/testing general sequence bus unit, it is characterized in that: also comprising showing a corresponding coloured flag on a monitor of described Test Host, is that descriptor value with described storage matches to check the described controller endpoint descriptor value that has each described USB device.

7. the method for format according to claim 1/testing general sequence bus unit, it is characterized in that: in described format/testing procedure, it comprises and scans the faulty blocks data that are stored in described flash memory device, and the deposit storage volume of checking each flash memory device is to equal a pre-sizing.

8. the method for format according to claim 1/testing general sequence bus unit, it is characterized in that: in described format/testing procedure, it comprises and writes at least neither good area data copy to the predetermined block of described flash memory device that wherein said defective region data are identification faulty blocks on described flash memory device.

9. the method for format according to claim 1/testing general sequence bus unit is characterized in that: described flash memory device comprises a plurality of nonvolatile memory units, and it is a simple layer cell type or a multilevel-cell type.

10. the method for format according to claim 1/testing general sequence bus unit, it is characterized in that: described test/format comprises and writes at least one handle data and start code data, or write the data that the user provides, or write also new sequence number, date code, product version yardage value to the predetermined block of described flash memory device.

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