CN101395795B - MEMS resonator and manufacturing method thereof, and MEMS oscillator - Google Patents

Abstract

The invention relates to a MEMS resonator comprising a first electrode and a movable element (48) comprising a second electrode, the movable element (48) being movable at least towards the first electrode, the first electrode and the movable element (48) being separated by a space (46, 47) having sidewalls. According to the invention, the MEMS resonator is characterized in that a dielectric layer (60) is provided on at least one side wall of the spacer (46, 47).

Description

MEMS resonator and manufacturing method thereof, and MEMS oscillator

technical field

The invention relates to a MEMS resonator comprising a first electrode and a movable element comprising a second electrode, the movable element being movable at least towards the first electrode, the first electrode and the movable element being spaced by a side wall separate.

The invention also relates to a method of manufacturing such a MEMS resonator.

The invention also relates to a MEMS oscillator comprising a MEMS resonator, and to an integrated circuit comprising such a MEMS oscillator.

Background technique

A MEMS resonator is known from WO 2004/027796A2. This document discloses a planar beam resonator with fixed supports at both ends. The two-terminal clamped beam resonator includes a single crystal silicon (SCS) beam arranged between two clamped regions. The SCS beam has a defined width and height and is used as the resonating element of the clamped beam resonator 200 . The drive and sense electrodes face each other, separated from the SCS beam by a sub-micron spacing. The electrodes preferably comprise polysilicon. Therefore, the fixed-terminal beam resonator consists essentially or completely of silicon.

A disadvantage of known MEMS resonators is that they are difficult to manufacture.

Contents of the invention

It is an object of the present invention to provide an alternative MEMS resonator of the kind proposed in the opening paragraph which is relatively easy to manufacture. The independent claims define the invention. The dependent claims define advantageous embodiments.

According to the invention, this object is achieved by providing the spacer with a dielectric layer on at least one side wall. Silicon MEMS resonators are excited and sensed using capacitive switching. The efficiency of this conversion depends largely on the distance (gap width) between the resonator and its excitation and/or sensing electrodes. Typically, this distance is required to be much less than 1 μm in most applications such as oscillators and accelerometers. These narrow spaces cannot be fabricated using conventional photolithography techniques. For the devices in WO 2004/027796A2, many processing steps are required, including the use of sacrificial layers and additional etching steps. However, the invention enables the space width to be reduced in a simple manner, ie by employing only one additional processing step.

The invention is also based on the realization that the dielectric material provided on the side walls has a dielectric constant greater than 1 and that this fact can be exploited. Since the dielectric constant is greater than 1, the effective space width is smaller than the distance between the electrodes, which has been recognized by the inventors. The term "effective interval width" is further explained in the description of the drawings in this specification.

In an advantageous embodiment of the MEMS resonator according to the invention, a dielectric layer is provided on at least two side walls. The advantage of this measure is that the physical gap width and the effective gap width can be further reduced.

In another embodiment of the MEMS resonator according to the invention, the MEMS resonator further comprises a further electrode, towards which the moving element is movable, the further electrode and the movable element are formed by another electrode having a further side wall. Separated by a spacer, said further spacer is provided with a further dielectric layer on at least one further side wall. The additional electrodes enable the designer, for example, to implement a first electrode as an excitation electrode (e.g., for capacitively exciting a movable element), and a second electrode as a sense electrode (e.g., for measuring a varying width due to another spacing). resulting in capacitive modulation).

Advantageously, a further dielectric layer is provided on at least two further side walls.

Preferably, the dielectric or further dielectric comprises at least one of the following materials: silicon dioxide, silicon nitride or a ferroelectric material such as PZT or PLZT. The greater the dielectric constant of the dielectric, the more the effective space width is reduced.

The invention also relates to a method of manufacturing a MEMS resonator. The method according to the invention comprises the following steps:

providing a semiconductor body comprising a substrate layer, a sacrificial layer provided on the substrate layer, and a top layer provided on the sacrificial layer;

forming a top layer pattern for forming a spacer, the spacer partially exposing the sacrificial layer, the spacer further used to define the movable element;

selectively removing the sacrificial layer to partially release the movable element from the substrate layer; and

A dielectric layer is provided on at least one sidewall of the space associated with the top layer around the movable element.

WO 2004/027796A2 discloses a method of forming spaces with a width smaller than that achievable with photolithographic techniques. In this method, an additional sacrificial oxide layer is deposited in the space immediately adjacent to the resonator and immediately thereafter partially removed, so that a nanoscale oxide layer remains on the resonator. The remaining spaces are then filled with polysilicon to form electrodes. Releasing the resonator structure is done as the last step of the method, where the thin sacrificial oxide and oxide layers are selectively etched away. This document therefore discloses a rather complicated method of forming spaces with a width smaller than that achievable with photolithographic techniques.

The method according to the invention differs significantly from the methods described above. In the method according to the invention, the movable element is released before the dielectric layer is provided on at least one side wall. Also, the dielectric is not removed, consistent with the inventor's earlier stated understanding. Consequently, fewer process steps are required in the method according to the invention.

US 2005/0124135 A1 discloses three alternative methods of forming spaces with a width smaller than that achievable with photolithographic techniques. In a first method disclosed by US 2005/0124135 A1, an oxide layer is thermally grown or deposited on a silicon substrate and patterned to form trenches there. Then, a thin polysilicon layer is deposited on the oxide layer. The trench is then refilled with oxide and back etched to expose the sacrificial oxide layer on the sidewalls of the trench. Finally, the sacrificial sidewall polysilicon is etched to create nano-trenches.

In a second method disclosed by US 2005/0124135 A1, a nitride layer is formed on the substrate. A polysilicon layer is then deposited and patterned using a mask with openings that are reduced in size to sub-micron dimensions. The mask is then used to form submicron dimensions by etching.

In a third method disclosed by US 2005/0124135 A1, an SOI wafer is provided, the wafer comprising a first silicon layer, an oxide layer and a second silicon layer. Then, a thin nitride layer is deposited on the SOI wafer, which prevents oxidation of the second silicon layer in later process steps. A thin film polysilicon layer is deposited and patterned to create openings. The patterned polysilicon layer is oxidized to form an oxide mask. The openings are reduced in size during oxidation. An anisotropic dry etch of the thin nitride layer is then performed followed by an ion etch step to etch the second polysilicon layer down to the oxide layer. Finally, the oxide layer is locally removed in order to partially release part of the resulting microstructure.

Common to all three approaches is the use of a reduced-size mask to etch trenches with sub-micron dimensions. This differs substantially from the method according to the invention, which does not include the step of etching trenches with sub-micrometer widths. Instead, the trenches to be formed may have conventional dimensions achievable by conventional photolithographic techniques. In the method according to the invention, after the trenches have been formed, the dimensions of the trenches are reduced, which considerably simplifies the manufacturing process.

Please note that the order of the steps in the method according to the invention can be changed. For example, a second material may be provided to the movable element prior to selectively removing the sacrificial layer. For this, conventional steps such as etching, deposition and CMP can be used.

An advantageous embodiment of the method according to the invention is characterized in that in the step of providing the semiconductor body, a top layer comprising silicon is provided on the sacrificial layer. Using silicon has the advantage that it is compatible with most process technologies and thus allows for simple integration with integrated circuits.

Another refinement of the previous embodiment is characterized in that the step of providing the dielectric layer comprises an oxidation step whereby at least silicon of at least one sidewall of the space associated with the top layer is converted into silicon oxide. Oxidation of silicon is a well-controlled technique that is also available in most MEMS manufacturing environments. Silicon dioxide is a dielectric material with a dielectric constant of 3.9, which is advantageous for significantly reducing the effective space width.

An alternative embodiment is characterized in that the step of providing a dielectric layer comprises depositing a dielectric layer, which dielectric layer is provided on at least one sidewall of the space associated with the top layer. The deposition technique also provides a high degree of control over the deposited dielectric layer.

Preferably, the step of depositing a dielectric layer comprises the deposition of at least one of the following materials: silicon dioxide and silicon nitride.

Furthermore, the step of depositing the dielectric layer is preferably performed using one of the following techniques: atomic layer deposition (ALD) and low pressure chemical vapor deposition (LPCVD).

The invention also relates to a MEMS oscillator comprising a MEMS resonator. Smaller spacing helps to reduce the motional impedance of the MEMS resonator. Low motional impedance (eg <10 kOhm) is required at resonance to obtain low oscillator phase noise.

The invention also relates to an integrated circuit comprising such a MEMS oscillator. Forming a silicon oxide layer on a silicon resonator is compatible with the process flow of an integrated circuit. Thus, MEMS resonators according to the present invention allow relatively straightforward integration of monolithically integrated MEMS oscillators.

Any additional features may be combined and combined with any aspect. Other advantages will be apparent to those skilled in the art. Various changes and modifications are possible without departing from the claims of the present invention. Therefore, it should be clearly understood that the description is illustrative only and not intended to limit the scope of the present invention.

Description of drawings

How the present invention is implemented will be described by way of example with reference to the accompanying drawings, in which:

Figures 1a to 1e illustrate a method of manufacturing a MEMS resonator according to one embodiment of the method of the present invention;

Fig. 2 illustrates the principle of reducing the spacer width in the case of forming a dielectric on the sidewall of the spacer by oxidation; and

FIG. 3 illustrates the principle of reducing the spacer width in case the dielectric is formed by deposition on the sidewalls of the spacer.

Detailed ways

The present invention will be described in terms of particular embodiments with reference to certain drawings but the invention is not limited thereto, its scope being limited only by the appended claims. Any reference signs in the claims should not be construed as limiting the scope. The drawings described are only schematic and non-limiting. In the drawings, the size of some of the elements is exaggerated and not drawn on scale for illustrative purposes. Where the terms "comprising" or "comprises" are used in the present description and claims, other elements or steps are not excluded. Where a singular noun is referred to (eg "a" or "an", "the"), where an indefinite or definite article is used, this includes a plural of such noun unless expressly stated otherwise.

Moreover, in the description and claims, the terms first, second, third, etc. are used to distinguish similar elements, not to describe sequential and chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Figures 1a to 1e illustrate a MEMS resonator at various stages of a MEMS fabrication process according to one embodiment of the method of the present invention.

Figure 1a refers to a stage of the manufacturing process in which a semiconductor body 100 is provided. The semiconductor body 100 includes a substrate layer 20 , a sacrificial layer 30 provided on the substrate layer 20 and a top layer 40 provided on the sacrificial layer 30 . In one embodiment of the invention, the top layer 40 may comprise silicon, but other materials are also possible, for example, germanium (Ge), III-V semiconductor compounds like gallium arsenide (GaAs), II-V semiconductor compounds like indium phosphide VI semiconductor compounds and other materials. For the sacrificial layer 30 material, silicon dioxide (SiO ₂ ) can be used, but other materials are also feasible. In cases where silicon is used as the material of the top layer 40 and silicon oxide (or other insulating material) is used as the material of the sacrificial layer 30, the term silicon-on-insulator (SOI) may be used. In the market, silicon-on-insulator substrates/wafers are widely available and can be fabricated in a simple and easy manner. In the example shown in Figures 1a to 1e, an SOI substrate is used, wherein the top layer 40 comprises silicon, and wherein the insulating (sacrificial) layer 30 comprises silicon dioxide.

Figures 1b and 1c illustrate other stages of the manufacturing process. In FIG. 1 b, a patterned masking layer 55 having openings 50 is provided. For example, patterning mask layer 50 can be accomplished using conventional optical lithography techniques, although other lithography techniques such as electron beam lithography, ion beam lithography, and x-ray lithography can also be used. In these techniques, the pattern is written directly on the mask layer 50 . In this particular example, photolithography is employed. The masking layer 50 may then comprise a photoresist layer, but may also be a hard mask, eg made of silicon oxide or silicon nitride. In FIG. 1c the top layer 40 is patterned through the opening 55 of the mask layer 50 . Thus, an opening 45 is formed in the top layer 40, which corresponds to the opening 55 in the mask layer. This can be done by using, for example, a dry etch step (eg DRIE etch). Etching techniques are known to those skilled in the art. Openings 45 are formed so as to expose the sacrificial layer 30 under the top layer 40 . Spaces 46, 47 are also formed which define the movable element 48 of the MEMS resonator to be manufactured.

In FIG. 1d , a further stage of the manufacturing process is shown, the sacrificial layer 30 is partially removed (at least the sacrificial layer under the movable element) in order to partially release the movable element 48 . This can be done by using, for example, a selective wet etch step. Selective etch techniques are also known to those skilled in the art. A movable element is placed between the clamping areas (not shown in the figure). In this particular example, the movable element 48 is movable (at least) in a direction perpendicular to the side walls of the spaces 46 , 47 .

Silicon MEMS resonators are excited and sensed using capacitive switching. The efficiency of this conversion largely depends on the distance (gap width) between the resonator and its excitation and/or sensing electrodes. Typically, this distance is required to be much less than 1 μm in most applications such as oscillators and accelerometers. These narrow spaces cannot be fabricated using conventional photolithography techniques. Figure 1e illustrates further stages of the fabrication process of a MEMS resonator according to an embodiment of the method of the present invention. In this embodiment, a thermal oxidation step is used to reduce the width of the spaces 46, 47 in the top layer 40. Thermal oxidation is a known process to those skilled in the art. In the case of thermal oxidation of silicon, as is the case in the illustrated example, the oxidation step is typically carried out at a temperature of about 1000° C. in an environment comprising O ₂ or H ₂ O. More information on thermal oxidation can be found in S. Wolf, "Silicon processing", Vol. 1, pp. 198-241.

In FIG. 1 e , silicon dioxide SiO ₂ (dielectric) is grown everywhere where the silicon is uncovered, especially on the sidewalls of the spacers 46 , 47 . However, by providing a capping layer locally or in the trenches, the growth of silicon dioxide can be prevented. Alternatively, a different material may be used in the top layer 40 next to the silicon so that only the silicon is oxidized. A known isolation technique employing this principle is called LOCOS (Local Oxidation of Silicon). In LOCOS, silicon nitride (Si ₃ N ₄ ) is used to avoid oxidation. Thus, this technique allows the dielectric to be provided on only one sidewall of the spaces 46,47.

Alternatively, a dielectric (eg silicon oxide, and silicon nitride) may be deposited on the sidewalls of the spacers 46, 47 in addition to oxidation. There are several techniques for deposition such as atomic layer deposition (ALD) and low pressure vapor deposition (LPCVD). To ensure that the dielectric is deposited on the sidewalls of the spacers, oblique/shaded deposition techniques may be used. More information on shadow deposition can be found in S. Wolf, "Siliconprocessing", Vol.1, pp.374.

Before or after the stage shown in Figure 1e, various other steps may be performed to complete the product, such as:

Partial removal of grown/deposited oxides;

forming electrodes;

forming bond pads;

form other circuits; and so on.

The steps mentioned above are well known to those skilled in the art.

As shown in FIGS. 2 and 3, the effectiveness of the present invention can be determined by comparing the effective space width before and after providing the dielectric. In FIG. 2 the reduction in space width is illustrated in the case of silicon oxidation, and in FIG. 3 the reduction in space width in the case of silicon oxide deposition is illustrated.

Referring to Figure 2, the physical width decreases from _g0 to _g1 . This is a result of the oxidation of the sidewalls of the spacer, which forms an oxide layer 60 of thickness d. The parameter _g0 represents the original spacer width, measured from the original sidewalls S1, S2 of the spaces 46, 47 before oxidation. The parameter _g1 represents the physical gap width after oxidation.

The equivalent spacing width (g _eff ) of a capacitor formed between two silicon bodies (ε _r =3.9) is given by:

${\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}}{{\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; 3.9</span>}}$

It is known that in the case of silicon oxide grown with 44% of the oxide thickness below the original surface, the physical gap width _g can be represented by the original gap width g as _follows :

${\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.44</span>}<span\; class="notranslate">\; )</span>$

$<span\; class="notranslate">\; \&DoubleRightArrow;</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.44</span>}<span\; class="notranslate">\; )</span>$

After substituting the formula for g ₁ into the formula for g _eff , the following relationship is obtained:

$<span\; class="notranslate">\; \&DoubleRightArrow;</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.44</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 3.9</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.61</span>}\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; \&Greater\; Equal;</span>\mathrm{<span\; class="notranslate">\; 0.46</span>}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}$

It can be seen from the formula that the effective interval width g _eff is smaller than the original interval width g ₀ . The minimum effective spacer width after oxidation is 0.46 g ₀ , which occurs at the following oxide thicknesses:

$\mathrm{<span\; class="notranslate">\; 0.56</span>}{\mathrm{<span\; class="notranslate">\; d</span>}}_{\mathrm{<span\; class="notranslate">\; max</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0.5</span>}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}$

$<span\; class="notranslate">\; \&DoubleRightArrow;</span>{\mathrm{<span\; class="notranslate">\; d</span>}}_{\mathrm{<span\; class="notranslate">\; max</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 0.5</span>}}{\mathrm{<span\; class="notranslate">\; 0.56</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0.893</span>}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}$

For a MEMS resonator using capacitive switching, this results in a reduction factor of its impedance at resonance of 0.46 ⁻⁴ =22.3.

Referring to Figure 3, the situation is different because in the case of dielectric deposition, the silicon (or other material) on the sidewalls is not consumed. The equivalent spacing width (g _eff ) of a capacitor formed between two silicon bodies (ε _r =3.9) is given by (similar to Fig. 2):

${\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}}{{\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; 3.9</span>}}$

However, the physical gap width g ₁ can be represented by the raw gap width g ₀ as follows:

${\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}$

$<span\; class="notranslate">\; \&DoubleRightArrow;</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}$

After substituting the formula for g ₁ into the formula for g _eff , the following relationship is obtained:

$<span\; class="notranslate">\; \&DoubleRightArrow;</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 3.9</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1.487</span>}\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; \&Greater\; Equal;</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; .</span>\mathrm{<span\; class="notranslate">\; 256</span>}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}$

It can be seen from the formula that the effective spacer width g _eff is again smaller than the original spacer width g ₀ , and even smaller in the case of oxidation. The minimum effective spacer width after oxidation is 0.256g ₀ , which occurs when the oxide thickness d is:

_dmax = 0.5g ₀

For a MEMS resonator, this results in a reduction factor of its resistance at resonance of 0.256 ⁻⁴ =231.3.

The present invention thus provides an attractive MEMS resonator which has good performance and which is easier to manufacture than MEMS resonators known from the prior art. The invention also provides a method of manufacturing such a MEMS resonator which is simpler than the methods known from the prior art.

Claims (8)

1. MEMS resonator, it comprises second electrode of first electrode and displaceable element (48) form, displaceable element (48) is movably towards first electrode at least, first electrode and displaceable element (48) are had the interval (46 of sidewall, 47) separately, wherein, first electrode and second electrode are as the part of the top layer (40) of semiconductor body (10) and form, wherein semiconductor body comprises substrate layer (20), sacrifice layer (30) and top layer (40), wherein under first electrode, there is sacrifice layer, and under second electrode (48), do not have sacrifice layer, and wherein at least one sidewall at interval (46,47), provide dielectric layer (60).

2. MEMS resonator as claimed in claim 1 is characterized in that providing dielectric layer (60) at least two sidewalls.

3. method of making the MEMS resonator, it may further comprise the steps:

Semiconductor body (10) is provided, and substrate layer (20), the sacrifice layer (30) that is provided on substrate layer (20) and the top layer (40) that is provided on sacrifice layer (30) are provided for it;

Form top layer (40) pattern, to form (46,47) at interval, (46,47) expose sacrifice layer (30) partly at interval, and (46,47) also are used to limit displaceable element (48) at interval;

Optionally remove sacrifice layer (30), so that moving meter (48) is partly discharged from substrate layer (20); And

On at least one sidewall at the interval (46,47) relevant, provide dielectric layer (60) with displaceable element (48) top layer (40) on every side.

4. method as claimed in claim 3 is characterized in that in the step that semiconductor body (10) are provided, and the top layer (40) that comprises silicon is provided on sacrifice layer (30).

5. method as claimed in claim 4 is characterized in that providing the step of dielectric layer (60) to comprise oxidation step, and thus, the silicon at least at least one sidewall at the interval (46,47) relevant with top layer (40) is converted into silica.

6. as claim 3 or 4 described methods, it is characterized in that providing the step of dielectric layer (60) to comprise dielectric layer deposition, at least one sidewall at the interval (46,47) relevant, provide this dielectric layer (60) with top layer (40).

7. MEMS oscillator, it comprises MEMS resonator as claimed in claim 1 or 2.

8. integrated circuit, it comprises MEMS oscillator as claimed in claim 7.

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