CN101312153A - Fuse-wires structure and forming method thereof - Google Patents
Fuse-wires structure and forming method thereof Download PDFInfo
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- CN101312153A CN101312153A CNA2007100410951A CN200710041095A CN101312153A CN 101312153 A CN101312153 A CN 101312153A CN A2007100410951 A CNA2007100410951 A CN A2007100410951A CN 200710041095 A CN200710041095 A CN 200710041095A CN 101312153 A CN101312153 A CN 101312153A
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Abstract
A fuse forming method includes sequentially forming a first medium layer and a polysilicon layer, forming at least two adjacent doped areas with opposite conduction types, sequentially forming a silicide layer and a second medium layer, forming a through hole filled with conductive material on the second medium layer, and forming a metal gasket on the through hole. The invention accordingly provides a fuse structure, which forms different doped areas of the fuse structure by utilizing the polysilicon layer which forms a transistor as the polysilicon layer of the fuse structure, and using source /drain ion implantation and ion implantation forming a source /drain extending area. Before and after programming, the fuse structure has large resistance difference, which is favorable for status detection before and after programming, and simultaneously completely compatible with the existing standard CMOS technology, does not increase extra masks and doping process and technological cost.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly fuse-wires structure and forming method thereof.
Background technology
Along with semiconductor technology gets microminiaturization and complexity must improve, semiconductor element easier various defective or the impurity of being subjected to that also becomes must influence, and the inefficacy of plain conductor, diode or transistor etc. often promptly constitutes the defective of entire chip.Therefore in order to address this problem, prior art just can form some fuses in integrated circuit, to guarantee the utilizability of integrated circuit.
In general, fuse connects the redundant circuit (redundancy circuit) in the integrated circuit, in case detect when finding that circuit has defective, these redundant circuits just can be used for repairing or replacing defective circuit.With the memory construction is example, prior art can get the superiors in structure and make some fuse-wires structures, its role is to when internal memory is finished, if when wherein having the function of partial memory cell, word line or lead that problem is arranged, just can utilize memory cell, word line or the lead of other redundancies of fuse jumper connection (redundant cells) to replace.
Fuse expands the function that sequencing (programming elements) can be provided at present, so that the different function of various client Ke Yi is come programmed circuit.For example, in order to save research and development and cost of manufacture, wafer factory can utilize lead to be connected with each transistor in the storage array, and in lead, increase a fuse, after treating that semiconductor chip fabrication is finished, carry out the data input by the outside again, become various product chips with each standard chips of uniquenessization.(Programmable ROM when PROM) carrying out the data input, burns fuse as using high voltage, opens circuit (off-state) and produce, and promptly finishes the input of " 1 " when programmble read only memory PROM; Otherwise without the fuse that burns, the transistor wire line still exists and forms conducting state (on-state), promptly is equivalent to deposit in " 0 ".The process that this kind utilizes high voltage to burn (blowing) fuse is sequencing (programming), in case and the fuse of sequencing will forever form off state and exist.Therefore fuse demonstrates binary arithmetic operation, allows programming information is encoded after the manufacturing of integrated circuit and encapsulation.
The making flow process of the fuse-wires structure on the silicon-on-insulator of prior art (SOI) is with reference to shown in the accompanying drawing 1, and at first execution in step 100, and silicon-on-insulator (SOI) is provided, and described SOI has first insulating barrier and monocrystalline silicon layer; Execution in step 102 is patterned into band with monocrystalline silicon layer; Execution in step 104 with one or more doping impurity monocrystalline silicon layers, comprises the multiple mask from dissimilar impurity to the zones of different of each monocrystalline silicon zone and the doping process that inject, also comprises the unadulterated technology of one or more parts that keeps monocrystalline silicon zone; Execution in step 106 is with the formation of the top at least silicide strip of silication monocrystalline silicon layer; Execution in step 108 is forming one or more second insulating barriers on the silicide strip so that silicide strip is isolated with surrounding structure electricity or heat on three-dimensional; Execution in step 110 before forming second insulating barrier or afterwards, forms and passes second insulating barrier to the electrically contacting of the end of silicide strip, thereby finish fuse-wires structure.
The fuse-wires structure that adopts this flow process to form utilizes the silicide strip on the SOI, and top silicide material allows fuse to be used as conductor under programming state.When programming, silicide is moved or disconnects.Yet adopt above-mentioned flow process compatible mutually with existing standard CMOS process, simultaneously, in manufacturing process, need extra increase mask and carry out doping process, this has increased the technology cost.
In being 200610106431 Chinese patent application, application number can also find more information relevant with technique scheme.
Summary of the invention
The problem that the present invention solves is that existing formation fuse-wires structure technology is compatible mutually with standard CMOS process, in manufacturing process, needs extra increase mask and carries out doping process, has increased the technology cost.
For addressing the above problem, the invention provides a kind of formation method of fuse, comprising: Semiconductor substrate is provided; Form first dielectric layer and polysilicon layer successively on Semiconductor substrate, described polysilicon layer adopts and forms transistorized polysilicon layer; In polysilicon layer, form at least two doped regions, the conductivity type opposite of described adjacent two doped regions; Form silicide layer having on the polysilicon layer of at least two doped regions; On silicide layer, form second dielectric layer; Form through hole in second dielectric layer, described through hole exposes silicide layer; Adopt the electric conducting material filling vias and contact with silicide layer; On second dielectric layer, form metal gasket facing to the lead to the hole site that is filled with electric conducting material.
The doped region that forms in the described polysilicon layer is two, is respectively in carrying out source/leakage ion implantation technology or is carrying out in source/drain extension region ion implantation technology forming simultaneously.
The doped region that forms in the described polysilicon layer is three, in carrying out source/leakage ion implantation technology or carrying out in source/drain extension region ion implantation technology forming simultaneously.
Electric conducting material of filling in the described through hole and metal gasket are metallic aluminium.
Described silicide is the silicide of tungsten, titanium, nickel, cobalt, tantalum or platinum.
Accordingly, the invention provides a kind of fuse-wires structure, comprising: Semiconductor substrate; Be positioned at first dielectric layer and polysilicon layer on the Semiconductor substrate successively, described polysilicon layer adopts and forms transistorized polysilicon layer; Be arranged at least two doped regions of polysilicon layer, the conductivity type opposite of described adjacent two doped regions; Be positioned at the silicide layer on the polysilicon layer with at least two doped regions; Be positioned at second dielectric layer on the silicide layer; The electric conducting material that is arranged in the second dielectric layer through hole and is filled in through hole; Be positioned at the metal gasket that forms facing to the lead to the hole site that is filled with electric conducting material on second dielectric layer.
The doped region that forms in the described polysilicon layer is followed successively by two, is respectively in carrying out source/leakage ion implantation technology or is carrying out in source/drain extension region ion implantation technology forming simultaneously.
The doped region that forms in the described polysilicon layer is three, is respectively in carrying out source/leakage ion implantation technology or is carrying out in source/drain extension region ion implantation technology forming simultaneously.
Electric conducting material of filling in the described through hole and metal gasket are metallic aluminium.
Described silicide is the silicide of tungsten, titanium, nickel, tantalum or platinum.
Compared with prior art, technique scheme has the following advantages: form the polysilicon layer of the polysilicon layer of transistorized polysilicon gate as fuse by employing, before and after programming, the resistance value of fuse-wires structure differs bigger, be beneficial to programming front and back status detection, compatible fully with existing standard CMOS technology simultaneously, do not increase the technology cost.
Technique scheme is injected the different doped regions that inject the formation fuse-wires structure with the ion of formation source/drain extension region by the polysilicon layer that adopts the transistorized polysilicon gate of formation as the polysilicon layer of fuse, the ion that employing forms transistorized source/drain electrode, before and after programming, the resistance value of fuse-wires structure differs bigger, be beneficial to programming front and back status detection, compatible fully with existing standard CMOS technology simultaneously, do not increase extra mask and doping process, do not increase the technology cost.
Description of drawings
Fig. 1 is the schematic flow sheet of the formation fuse-wires structure of prior art;
Fig. 2 to Fig. 9 is the structural representation of the formation fuse of the first embodiment of the present invention;
Figure 10 to Figure 12 is the structural representation of the formation fuse of the second embodiment of the present invention;
Figure 13 is the structural representation of the formation fuse of the third embodiment of the present invention;
Figure 14 A is a kind of fuse-wires structure testing circuit;
Figure 14 B is the differential detection circuit of another kind of fuse-wires structure.
Embodiment
The invention provides a kind of formation method and structure thereof of fuse; the structure of three kinds of fuses is disclosed in an embodiment of the present invention; in polysilicon layer, form two doped regions with PN junction and three doped regions respectively with positive-negative-positive structure and NPN structure; can also form such as a plurality of doped region structures such as PNPN..., should too not limit protection scope of the present invention at this.
The present invention at first provides a kind of first embodiment of formation method of fuse, comprising: Semiconductor substrate is provided; Form first dielectric layer and polysilicon layer successively on Semiconductor substrate, described polysilicon layer adopts and forms transistorized polysilicon layer; In polysilicon layer, form at least two doped regions, the conductivity type opposite of described adjacent two doped regions; Form silicide layer having on the polysilicon layer of at least two doped regions; On silicide layer, form second dielectric layer; Form through hole in second dielectric layer, described through hole exposes silicide layer; Adopt the electric conducting material filling vias and contact with silicide layer; On second dielectric layer, form metal gasket facing to the lead to the hole site that is filled with electric conducting material.
At first with reference to Fig. 2, provide Semiconductor substrate 201, described Semiconductor substrate is silicon substrate, III-V compounds of group substrate or the II-VI compounds of group substrate etc. with semiconductor device of multilayer conductive layer, dielectric layer formation.
On Semiconductor substrate 201, form first dielectric layer 202, described first dielectric layer 202 for a kind of in silica, silicon nitride, the silicon oxynitride or its constitute, also can be low dielectric coefficient medium layers such as carbon containing silica.
With reference to Fig. 3, on first dielectric layer 202, form polysilicon layer 203, described polysilicon layer is for adopting the polysilicon layer that forms transistorized polysilicon gate.Form described polysilicon layer 203 and be present technique field personnel's known technology,, form described polysilicon layer 203 and adopt the chemical vapor deposition (CVD) devices to form as an optimization execution mode of the present invention.
With reference to Fig. 4, on polysilicon layer 203, form first photoresist layer 204, on first photoresist layer 204, define the shape of two doped regions in first polysilicon layer 203, the mask of the shape of two doped regions in described definition first polysilicon layer 203 can additionally not increase mask like this for adopting the mask of formation of the prior art source/drain electrode or source/drain extension region (LDD).In the present embodiment, at first define the shape of the first doped region 203a, carry out ion then and inject the formation first doped region 203a that mixes, the remainder of polysilicon layer 203 constitutes 203b.The conduction type of the first doped region 203a is the p type.
With reference to Fig. 5, on polysilicon layer 203, form second photoresist layer 205, on second photoresist layer 205, define the shape of the second doped region 203c, carry out ion then and inject the formation second doped region 203c that mixes.The conduction type of the second doped region 203c is the n type.
P type first doped region 203a that forms in the described polysilicon layer and the n type second doped region 203c district are for forming simultaneously in carrying out source/leakage ion implantation technology, inject the formation first doped region 203a such as in forming the transistorized source of PMOS/drain electrode, carrying out ion simultaneously, in the source/drain electrode that forms nmos pass transistor, carry out the ion injection simultaneously and form the second doped region 203c.The described first doped region 203a and the second doped region 203c constitute PN junction.
With reference to Fig. 6, on polysilicon layer 203, form silicide layer 206 with at least two doped regions.Described silicide layer 206 is the silicide of tungsten, titanium, nickel, tantalum or platinum.Relatively the execution mode of You Huaing is for adopting titanium silicide.Form described silicide layer 206 and be present technique field personnel's known technology.
With reference to Fig. 7, on silicide layer 206, form second dielectric layer 207 on three-dimensional so that polysilicon layer 203 and silicide layer 206 are isolated with surrounding structure electricity or heat.Described second dielectric layer 207 can be that one deck or multilayer constitute, described second dielectric layer 207 can for a kind of in silica, silicon nitride, the silicon oxynitride or its constitute.
With reference to Fig. 8, form through hole 208 at the two ends of second dielectric layer 207, described through hole exposes silicide layer 206; Adopt electric conducting material filling vias 208 then, electric conducting material is contacted with silicide layer 206.The electric conducting material of filling in the described through hole 208 can be doped polycrystalline silicon, metal material etc., and as an optimization execution mode of the present invention, described electric conducting material is metal A l.
With reference to Fig. 9, the two ends on second dielectric layer 207 form metal gasket 209 respectively facing to through hole 208 positions that are filled with electric conducting material.
Behind above-mentioned process implementing, form fuse-wires structure of the present invention, comprising: Semiconductor substrate 201; Be positioned at first dielectric layer 202 and polysilicon layer 203 on the Semiconductor substrate 201 successively, described polysilicon layer 203 adopts and forms transistorized polysilicon layer; Be arranged in the first doped region 203a and the second doped region 203c of polysilicon layer 203, the conduction type of the described first doped region 203a and the second doped region 203c is respectively p type and n type; Be positioned at the silicide layer 206 on the polysilicon layer 203 with two doped regions; Be positioned at second dielectric layer 207 on the silicide layer 206; Be arranged in the through hole 208 of second dielectric layer 207 and the electric conducting material that is filled in through hole; Be positioned at the metal gasket 209 that forms facing to through hole 208 positions that are filled with electric conducting material on second dielectric layer 207.
Figure 10 to Figure 12 is the structural representation of the formation fuse of the second embodiment of the present invention, is to form three doped regions with different among first embodiment.At first, on polysilicon layer 203, form the 3rd photoresist layer 210, on the 3rd photoresist layer 210, define the shape of the second doped region 203f then, inject the formation second doped region 203f by ion then with reference to Figure 10.The conduction type of the described second doped region 203f is the p type, and the ion that then forms the second doped region 203f injects and can adopt the ion that forms PMOS transistorized source/leakage diffusion region (LDD) or formation source/drain electrode to inject formation simultaneously.
With reference to Figure 11, on polysilicon layer 203, form the 4th photoresist layer 211 then, on the 4th photoresist layer 211, define the shape of the first doped region 203e and the 3rd doped region 203g then, inject formation first doped region 203e and the 3rd doped region 203g by ion then.The conduction type of described first doped region 203e and the 3rd doped region 203g is the n type, and the ion that then forms the first doped region 203e and the 3rd doped region 203f is injected to the ion implantation technology of source/drain electrode of adopting the formation nmos pass transistor or the ion implantation technology of formation source/drain electrode forms simultaneously.
With reference to Figure 12, on the polysilicon layer 203 that has three doped regions, form silicide layer 212 then, described silicide layer 212 is the silicide of tungsten, titanium, nickel, tantalum or platinum.
Technology subsequently is identical with technology among first embodiment, be included on the silicide layer 212 form second dielectric layer and in second dielectric layer, form through hole, filled conductive material and on second dielectric layer, form technology such as metal gasket in through hole facing to the lead to the hole site that is filled with electric conducting material, specifically can not give unnecessary details at this with reference to Fig. 7 to Fig. 9.
Figure 13 is the structural representation of the formation fuse of the third embodiment of the present invention.Be that with the difference among second embodiment conduction type that forms the first doped region 203h, the second doped region 203i and the 3rd doped region 203j respectively is p type, n type and p type.Then form the first doped region 203h, the second doped region 203i and the 3rd doped region 203j in the ion implantation technology of the source/drain electrode that forms nmos pass transistor or in source/leakage diffusion region (LDD) technology, forming simultaneously.
The present invention is by forming at least two doped regions in polysilicon layer, the conductivity type opposite of described adjacent two doped regions, on crystal silicon layer, form silicide layer then and constitute fuse-wires structure, because the conductivity type opposite of adjacent two doped regions in the polysilicon, before and after programming, the resistance value of fuse-wires structure differs bigger, is beneficial to programming front and back status detection.
The present invention forms the polysilicon layer of the polysilicon layer of transistorized polysilicon gate as fuse by employing, before and after programming, the resistance value of fuse-wires structure differs bigger, is beneficial to programming front and back status detection, compatible fully with existing standard CMOS technology simultaneously, do not increase the technology cost;
The present invention injects the different doped regions that inject the formation fuse-wires structure with the ion of formation source/drain extension region by the polysilicon layer that adopts the transistorized polysilicon gate of formation as the polysilicon layer of fuse, the ion that employing forms transistorized source/drain electrode, before and after programming, the resistance value of fuse-wires structure differs bigger, be beneficial to programming front and back status detection, compatible fully with existing standard CMOS technology simultaneously, do not increase extra mask and doping process, do not increase the technology cost.
Figure 14 A provides the circuit that the fuse of prior art detects.The circuit of testing circuit 100 for adopting a fuse to form comprises: resistance R PU, be used for dividing potential drop, and its first end links to each other with power input, described power input input voltage VDD; Fuse RFUS, its first end links to each other with second end of resistance R PU, links to each other with an input A of detector 30 simultaneously; Detector 30 is used for comparing according to the voltage and the reference voltage of input A input, and its comparative result exports output Y to; Transistor T RAN is used to select fuse RFUS to be detected, and its drain terminal links to each other with second end of fuse RFUS, its source end ground connection, and its grid links to each other with selecting signal.First end of described fuse RFUS, second end are the metal gasket 209 at the fuse-wires structure two ends among above-mentioned first embodiment.
Between the resistance of the resistance value of RPU among Figure 14 A before and after fuse RFUS is programmed.Such as, fuse RFUS resistance value before programming is X, and resistance value is 100X after programming, and the value of relatively optimizing of resistance R PU is 10X.The reference voltage of detector 30 is relatively optimized and is set at 0.5VDD among Figure 14 A.When selecting signal to choose fuse RFUS among Figure 14 A by transistor T RAN, described testing circuit 100 forms path, when fuse RFUS be not programmed out-of-date, the current potential that A is ordered is 0.1VDD, and for the fuse RFUS that programmed, the current potential that A is ordered is about 0.9VDD, and the voltage phase difference that A is ordered before and after the programming is greater than 0.5VDD, and detector 30 can be told.
But in the prior art, not obvious if fuse RFUS resistance value increases after programming, will cause the judged result of detector 30 unreliable.Such as, fuse RFUS resistance value before programming is X, and resistance value is 4X after programming, and the value of relatively optimizing of resistance R PU is 2X.In this case, the reference voltage of detector 30 is relatively optimized and is set at 0.5VDD among Figure 14 A.When selecting signal to choose fuse RFUS among Figure 14 A by transistor T RAN, described testing circuit 100 forms path, when fuse RFUS be not programmed out-of-date, the current potential that A is ordered is 0.33VDD, and for the fuse RFUS that programmed, the current potential that A is ordered is about 0.67VDD, and the voltage phase difference that A is ordered before and after the programming is 0.34VDD, and at this time detector 30 can be told this two current potentials in theory.But in reality was made, the resistance value of resistance R PU may have bigger deviation, and reference voltage also may be forbidden, and is not just to be 0.5VDD.Such as, when the resistance value of resistance R PU reduces 50%, be that the resistance value of resistance value RPU is when being X, if FUSE was not programmed, the current potential that A is ordered will be 0.5VDD, if at this moment reference voltage is lower slightly, be lower than 0.5VDD, detector will think that fuse has been blown, and obtains opposite error result.
Take place for fear of the insecure situation of above-mentioned testing result, in side circuit, adopt more complicated differential detection circuit usually, concrete structure as shown in Figure 14B.The difference channel of testing circuit 200 for adopting two fuses to form, comprise first testing circuit, described first testing circuit further comprises: the first resistance R PU1 is used for dividing potential drop, its first end links to each other with first power input, the described first power input input voltage VDD1; The first fuse RFUS1, its first end link to each other with second end of resistance R PU and the B point; Transistor T RAN is used to select fuse RFUS to be detected, and its drain terminal links to each other with second end of fuse RFUS, its source end ground connection, and its grid links to each other with selecting signal.
Described testing circuit 200 also comprises second testing circuit, and described second testing circuit further comprises: the second resistance R PU2, be used for dividing potential drop, and its first end links to each other with the second source input, described second source input input voltage VDD2; The second fuse RFUS2, second end of its first end and the second resistance R PU2 is connected in the C point, its second end ground connection.
Described testing circuit 200 further comprises detector 30, an one input input B point current potential, and its another input input C point current potential is used for the current potential and the C point current potential of the input of B point are compared, and its comparative result exports output Z to.
In differential detection circuit 200, the second fuse RFUS2 is used for reference rather than programming.The second fuse RFUS2 is identical with the manufacture craft of the first fuse RFUS1, but resistance value differs two times before programming, adopt testing circuit 200, as long as the resistance value of the second fuse RFUS2 after programming greater than 2X, described differential detection circuit 200 can accurately pick out the current potential that B point and C are ordered, can detect the first fuse RFUS1 and whether be programmed, but above-mentioned differential detection circuit 200 structure more complicated can increase the technology cost.
Fuse-wires structure of the present invention is owing to be formed with the doped region of at least two conductivity type opposite in polysilicon layer; Whether before and after programming, the resistance value of fuse-wires structure differs bigger, adopt the simple root testing circuit promptly just can accurately judge fuse as the testing circuit 100 of Figure 14 A and be programmed.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the formation method of a fuse is characterized in that, comprising:
Semiconductor substrate is provided;
Form first dielectric layer and polysilicon layer successively on Semiconductor substrate, described polysilicon layer adopts and forms transistorized polysilicon layer;
In polysilicon layer, form at least two doped regions, the conductivity type opposite of described adjacent two doped regions;
Form silicide layer having on the polysilicon layer of at least two doped regions;
On silicide layer, form second dielectric layer;
Form through hole in second dielectric layer, described through hole exposes silicide layer;
Adopt the electric conducting material filling vias and contact with silicide layer;
On second dielectric layer, form metal gasket facing to the lead to the hole site that is filled with electric conducting material.
2. the formation method of fuse according to claim 1 is characterized in that, the doped region that forms in the described polysilicon layer is two, is respectively in carrying out source/leakage ion implantation technology or is carrying out in source/drain extension region ion implantation technology forming simultaneously.
3. the formation method of fuse according to claim 1 is characterized in that, the doped region that forms in the described polysilicon layer is three, in carrying out source/leakage ion implantation technology or carrying out in source/drain extension region ion implantation technology forming simultaneously.
4. the formation method of fuse according to claim 1 is characterized in that, electric conducting material of filling in the described through hole and metal gasket are metallic aluminium.
5. the formation method of fuse according to claim 1 is characterized in that, described silicide is the silicide of tungsten, titanium, nickel, cobalt, tantalum or platinum.
6. a fuse-wires structure is characterized in that, comprising:
Semiconductor substrate;
Be positioned at first dielectric layer and polysilicon layer on the Semiconductor substrate successively, described polysilicon layer adopts and forms transistorized polysilicon layer;
Be arranged at least two doped regions of polysilicon layer, the conductivity type opposite of described adjacent two doped regions;
Be positioned at the silicide layer on the polysilicon layer with at least two doped regions;
Be positioned at second dielectric layer on the silicide layer;
The electric conducting material that is arranged in the through hole of second dielectric layer and is filled in through hole;
Be positioned at the metal gasket that forms facing to the lead to the hole site that is filled with electric conducting material on second dielectric layer.
7. fuse-wires structure according to claim 6 is characterized in that the doped region that forms in the described polysilicon layer is followed successively by two, is respectively in carrying out source/leakage ion implantation technology or is carrying out in source/drain extension region ion implantation technology forming simultaneously.
8. fuse-wires structure according to claim 6 is characterized in that the doped region that forms in the described polysilicon layer is three, is respectively in carrying out source/leakage ion implantation technology or is carrying out in source/drain extension region ion implantation technology forming simultaneously.
9. fuse-wires structure according to claim 6 is characterized in that, electric conducting material of filling in the described through hole and metal gasket are metallic aluminium.
10. fuse-wires structure according to claim 6 is characterized in that, described silicide is the silicide of tungsten, titanium, nickel, tantalum or platinum.
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| CN200710041095A CN100576500C (en) | 2007-05-23 | 2007-05-23 | Fuse-wires structure and forming method thereof |
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| CN200710041095A CN100576500C (en) | 2007-05-23 | 2007-05-23 | Fuse-wires structure and forming method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425446A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Fuse structure and using method thereof |
| CN105097047A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Detection circuit and method for memory and storage array |
| WO2022041270A1 (en) * | 2020-08-31 | 2022-03-03 | 深圳市大疆创新科技有限公司 | Semiconductor element, and testing method and device therefor |
-
2007
- 2007-05-23 CN CN200710041095A patent/CN100576500C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425446A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Fuse structure and using method thereof |
| CN104425446B (en) * | 2013-08-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and its application method |
| CN105097047A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Detection circuit and method for memory and storage array |
| CN105097047B (en) * | 2014-05-04 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Memory, the detection circuit of storage array and method |
| WO2022041270A1 (en) * | 2020-08-31 | 2022-03-03 | 深圳市大疆创新科技有限公司 | Semiconductor element, and testing method and device therefor |
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|---|---|
| CN100576500C (en) | 2009-12-30 |
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| PB01 | Publication | ||
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| C14 | Grant of patent or utility model | ||
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20111117 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |