CN101303889B - Memory cell and method for manufacturing nonvolatile device thereof - Google Patents
Memory cell and method for manufacturing nonvolatile device thereof Download PDFInfo
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Abstract
The invention provides a memory cell and a method for manufacturing a nonvolatile device thereof. By employing a nonvolatile device having a split gate structure, the logic state of the memory cell is stored in the nonvolatile device. Therefore, the nonvolatile device can still retain the stored data even when the power is turned off. The SRAM has the advantage of fast operation, and has the function of storing data in the nonvolatile memory.
Description
Technical field
The invention relates to a kind of memory cell, and particularly relevant for a kind of Nonvolatile memery unit.
Background technology
Random access memory mainly can be divided into dynamic RAM (DynamicRandom Access Memory is called for short DRAM) and static RAM (Static RandomAccess Memory is called for short SRAM).The advantage of static RAM is operation and low power consumption fast, and compared to dynamic RAM, static RAM must not carry out the periodicity charging to be upgraded, comparatively simple on designing and making.Therefore, static RAM is widely used in the information electronic product.
Because static RAM is a kind of volatibility (Volatile) storer, it is to store data with the electric crystal conduction state in the storage unit.Therefore, after the electric power that is supplied to storer is eliminated, data stored in static RAM will disappear completely.
On the other hand, can erase and programmable read only storage (Electrically ErasableProgrammable Read Only Memory by electricity, be called for short EEPROM) can repeatedly carry out the actions such as depositing in, read, erase of data owing to having, and the advantage that the data that deposits in also can not disappear after outage, thus become PC and electronic equipment a kind of non-volatile memory device of extensively adopting.
Yet along with science and technology is constantly progressive, integrated circuit technique is at a tremendous pace, and the information electronic product is also very universal, for example computer, mobile phone, digital camera or personal digital assistant (PersonalDigital Assistant is called for short PDA) ... or the like.The data that the information required by electronic product will be handled, store also increases thereupon day by day, also must take into account again simultaneously compact, characteristic such as be convenient for carrying.Therefore, during for fear of power-off, the shortcoming that data can disappear in the static RAM develops the semiconductor element of advantage that stores data both of a kind of quick operation that can have static RAM concurrently and flash memory, quite is necessary.
Summary of the invention
The invention provides a kind of memory cell, in non-volatile apparatus, the data in the memory cell can not disappeared because of power-off the data storage in the memory cell.
The invention provides a kind of manufacture method of non-volatile apparatus, this non-volatile apparatus is applicable to memory cell, uses the data of avoiding in the memory cell and disappears because of power-off.
The present invention proposes a kind of memory cell and comprises first metal-oxide-semiconductor (MOS), second metal-oxide-semiconductor (MOS), first non-volatile apparatus and second non-volatile apparatus.First end of first metal-oxide-semiconductor (MOS) couples first contact, and this first contact is coupled to first voltage.Second end of first metal-oxide-semiconductor (MOS) couples second voltage.The gate terminal of first metal-oxide-semiconductor (MOS) couples second contact.First end of second metal-oxide-semiconductor (MOS) couples second contact, and this second contact is coupled to first voltage.Second end of second metal-oxide-semiconductor (MOS) couples tertiary voltage.The gate terminal of second metal-oxide-semiconductor (MOS) couples first contact.First non-volatile apparatus has separated grid structure.The control gate of first non-volatile apparatus extremely couples the first control bias voltage.The selection gate terminal of first non-volatile apparatus couples first and selects bias voltage.First end of first non-volatile apparatus couples first contact.Second end of first non-volatile apparatus couples the first bit line.Second non-volatile apparatus has separated grid structure.The control gate of second non-volatile apparatus extremely couples the second control bias voltage.The selection gate terminal of second non-volatile apparatus couples second and selects bias voltage.First end of second non-volatile apparatus couples second contact.Second end of second non-volatile apparatus couples the second bit line.
In one embodiment of this invention, above-mentioned memory cell, wherein first non-volatile apparatus and second non-volatile apparatus comprise substrate, electric charge storage layer, control grid respectively, select grid and gate dielectric layer.Substrate has source area and drain region.Electric charge storage layer is disposed on the part block of substrate.The control grid is disposed on the electric charge storage layer.Select grid to be overlying on the part block of substrate on the part block with the control grid.Gate dielectric layer is disposed to be selected between grid and the substrate, selects between grid and the electric charge storage layer and select grid and control between the grid.
In one embodiment of this invention, above-mentioned memory cell, wherein first non-volatile apparatus and this second non-volatile apparatus comprise substrate, floating grid, control grid respectively, select grid and gate dielectric layer.Substrate has source area and drain region.Floating grid is disposed on the part block of substrate.The control grid is disposed on the part block of floating grid.Select grid to be overlying on the part block of substrate on the part block with floating grid.Gate dielectric layer is disposed at and selects between grid and the substrate, selects between grid and the floating grid, between substrate and the floating grid and between floating grid and the control grid.
In one embodiment of this invention, above-mentioned memory cell more comprises first load unit and second load unit.First load unit is coupled between first voltage and first contact.Second load unit is coupled between this first voltage and this second contact.
From another angle, the present invention proposes a kind of manufacture method of non-volatile apparatus, and this non-volatile apparatus is applicable to memory cell, and this memory cell comprises load unit and metal-oxide-semiconductor (MOS).The manufacture method of non-volatile apparatus comprises provides the substrate with source area and drain region, and forms electric charge storage layer on the part block of substrate.Then, form the control grid on electric charge storage layer.In addition, form on the part block that gate dielectric layer is overlying on substrate on the part block with the control grid, and form and select grid on this grid electricity layer.In addition, electrically connect source area to the bit line, and electrically connect this drain region to one contact, this contact electrically connects a voltage by load unit, and this contact electrically connects metal-oxide-semiconductor (MOS).Non-volatile apparatus then has separated grid structure.
From another angle, the present invention proposes a kind of manufacture method of non-volatile apparatus again, and this non-volatile apparatus is applicable to memory cell, and this memory cell comprises load unit and metal-oxide-semiconductor (MOS).The manufacture method of non-volatile apparatus comprises provides the substrate with source area and drain region, and forms first grid dielectric layer on the part block of substrate.Then, form floating grid on first grid dielectric layer.In addition, form second gate dielectric layer on the part block of floating grid, and form the control grid on second gate dielectric layer.Moreover, form on the part block that the 3rd gate dielectric layer is overlying on substrate on the part block with floating grid, and form and select grid on the 3rd gate dielectric layer.In addition, electrically connect source area to the bit line, and electrically connect this drain region to one contact, this contact electrically connects a voltage by load unit, and this contact electrically connects metal-oxide-semiconductor (MOS).Non-volatile apparatus then has separated grid structure.
Memory cell of the present invention is because of adopting non-volatile apparatus, and this non-volatile apparatus has separated grid structure, therefore the logic state of memory cell can be stored in the non-volatile apparatus.Even so when power-off, still can keep the data that originally was stored in the storer.It not only has static RAM and operates advantage fast, can have the function of non-volatile memory storage data simultaneously again concurrently.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the equivalent circuit diagram according to a kind of memory cell of the first embodiment of the present invention.
Fig. 2 A is the section of structure according to a kind of non-volatile apparatus of the first embodiment of the present invention.
Fig. 2 B is the section of structure according to the another kind of non-volatile apparatus of the first embodiment of the present invention.
Fig. 3 A is the circuit diagram of a kind of memory cell when writing the data of logical one according to the first embodiment of the present invention.
Fig. 3 B is the circuit diagram of a kind of memory cell when writing the data of logical zero according to the first embodiment of the present invention.
Fig. 4 is according to a kind of memory cell of first embodiment of the present invention circuit diagram when the hold mode.
Fig. 5 A is the circuit diagram when reading the data that is stored in the logical one in the memory cell according to the first embodiment of the present invention a kind of.
Fig. 5 B is the circuit diagram when reading the data that is stored in the logical zero in the memory cell according to the first embodiment of the present invention a kind of.
Fig. 6 A is the circuit diagram of the data according to a kind of logical one with memory cell of the first embodiment of the present invention when writing non-volatile apparatus.
Fig. 6 B is the circuit diagram of the data according to a kind of logical zero with memory cell of the first embodiment of the present invention when writing non-volatile apparatus.
Fig. 7 A is a kind of circuit diagram when non-volatile apparatus recovers the data of logical one according to the first embodiment of the present invention.
Fig. 7 B is a kind of circuit diagram when non-volatile apparatus recovers the data of logical zero according to the first embodiment of the present invention.
Fig. 8 is the circuit diagram according to the sequencing state of a kind of non-volatile apparatus of erasing of the first embodiment of the present invention.
100: memory cell 10,12: load unit
20,22: metal-oxide-semiconductor (MOS) 30,32: non-volatile apparatus
40,42: bit line A～E, CG1, CG2, SG1, SG2: end points
200: substrate 202: source area
204: drain region 210: electric charge storage layer
212,216: oxide layer 214: nitration case
220: control grid 230: select grid
240: gate dielectric layer 250: floating grid
I1, I2, Δ I1, Δ I2: electric current
Embodiment
Fig. 1 is the equivalent circuit diagram of a kind of memory cell (Memory Cell) according to the first embodiment of the present invention.Memory cell 100 for example comprises load unit 10 and 12, metal-oxide-semiconductor's (MetalOxide Semiconductor is called for short MOS) 20 and 22, non-volatile apparatus 30 and 32.First end of load unit 10 couples terminal A, and second end then couples terminal B, and wherein terminal A receives one first voltage.Similarly, first end of load unit 12 couples terminal A, and second end then couples end points C.In the present embodiment, load unit 10 and 12 can be a resistance, but the present invention is not as limit.In other selection embodiment, load unit 10 and 12 can also use vague and general type electric crystal (Depletion Mode Transistor), (the P-type Metal OxideSemiconductor of P type metal-oxide-semiconductor (MOS), abbreviation PMOS), membrane transistor (Thin Film Transistor is called for short TFT) ... or the like.
Please continue with reference to Fig. 1, first end of metal-oxide-semiconductor (MOS) 20 couples terminal B, and its second end couples end points D, and its gate terminal couples end points C.In addition, first end of metal-oxide-semiconductor (MOS) 22 couples end points C, and its second end couples end points E, and its gate terminal couples terminal B.In the present embodiment, metal-oxide-semiconductor (MOS) 20 and 22 for example is a N type metal-oxide-semiconductor (MOS).
In addition, in the present embodiment, the control gate of non-volatile apparatus 30 extremely couples end points CG1, and it selects gate terminal to couple end points SG1, and its first end couples terminal B, and its second end couples bit line 40.Similarly, the control gate of non-volatile apparatus 32 extremely couples end points CG2, and it selects gate terminal to couple end points SG2, and its first end couples end points C, and its second end then couples bit line 42.In preferred embodiment, non-volatile apparatus 30 and 32 can have the structure of separable grid (Split Gate).
Fig. 2 A is the section of structure according to a kind of non-volatile apparatus of the first embodiment of the present invention.Please refer to Fig. 2 A, non-volatile apparatus 30 is identical haply with 32 structural profile, therefore only describes with non-volatile apparatus 30.Non-volatile apparatus 30 for example is semiconductor-oxide-nitride thing-oxide-semiconductor (the being called for short SONOS) structure with separable grid.Non-volatile apparatus 30 comprises substrate (Substrate) 200, electric charge storage layer (Charge Trapping Layer) 210, control grid (Control Gate) 220, selects grid (Select Gate) 230 and gate dielectric layer 240.
In substrate 200 (for example being the substrate of P type), have source area 202 and drain region 204.Electric charge storage layer 210 is disposed on the part block of substrate 200.Control grid 220 is disposed on the electric charge storage layer 210.Select grid 230 to be overlying on the part block of substrate 200 on the part block with control grid 220 in addition, gate dielectric layer 240 can be disposed to be selected between grid 230 and the substrate 200, selects between grid 230 and the electric charge storage layer 210 and selection grid 230 and controlling between the grid 220.
Wherein, control grid 220 and the material of selecting grid 230 for example are doped polycrystalline silicon (Poly) or other suitable conductive materials.Electric charge storage layer 210 is made of with oxide layer 216 oxide layer (Oxide) 212, nitration case (Nitride) 214.The material of oxide layer 212,216 for example is monox (SiO) or silicon dioxide (SiO
2).The material of nitration case 214 for example is silicon nitride (SiN).The material of gate dielectric layer 240 for example is a monox.Because electric charge storage layer 210 can be used for store charge, so non-volatile apparatus 30 and non-volatile apparatus 32 be able to the data in the storing memory unit 100, and data can not disappeared because of the interruption of power supply supply.
In the foregoing description, though non-volatile apparatus 30,32 is an example with the SONOS structure with separable grid, but in other embodiments, non-volatile apparatus 30,32 also can be energy gap engineering SONOS (Bandgap Engineered SONOS the is called for short BE-SONOS) structure with separable grid.For instance, haveing the knack of this area skill person can change electric charge storage layer 210 in regular turn into and being made of oxide layer, nitration case, oxide layer, nitration case, oxide layer.The material of oxide layer for example is silicon dioxide (SiO
2).The material of nitration case for example is silicon nitride (SiN).Also can change control grid 220 and the material of selecting grid 230 into P type Poly in addition.30,32 of non-volatile apparatus become the BE-SONOS structure with separable grid thus.
The present technique field has knows also visual its demand of the knowledgeable usually, and changes the structure of non-volatile apparatus according to the teaching of spirit of the present invention and aforementioned all embodiment.For example, Fig. 2 B is the section of structure according to the another kind of non-volatile apparatus of the first embodiment of the present invention.Please refer to Fig. 2 B, non-volatile apparatus 30 and 32 section of structure are roughly the same, only describe with non-volatile apparatus 30 at this.Non-volatile apparatus 30 comprises substrate 200, floating grid (Floating Gate) 250, control grid 220, selects grid 230 and gate dielectric layer 240.
Hold above-mentionedly, substrate 200 for example is the substrate of P type, and it has source area 202 and drain region 204.Floating grid 250 is disposed on the part block of substrate 200.Because floating grid 250 can be used for store charge, so non-volatile apparatus 30 and non-volatile apparatus 32 be able to the data in the storing memory unit 100, and data can not disappeared because of the interruption of power supply supply.Control grid 220 is disposed on the part block of floating grid 250.Select grid 230 to be overlying on the part block of substrate 200 on the part block with floating grid 250.The material of control grid 220, selection grid 230 and floating grid 250 for example is doped polycrystalline silicon (Poly) or other suitable conductive materials.
In the present embodiment, gate dielectric layer 240 can be disposed at select between grid 230 and the substrate 200, select between grid 230 and the floating grid 250, between substrate 200 and the floating grid 250 and floating grid 250 and controlling between the grid 220.Wherein, the material of gate dielectric layer 240 for example is a monox.
In addition, this area has and knows that usually the knowledgeable should produce above-mentioned non-volatile apparatus 30,32 easily according to the section of structure of Fig. 2 A and Fig. 2 B, then will not give unnecessary details at this.Then, be described in more detail with next operations method at memory cell 100.
In the present embodiment, the terminal B of supposing memory cell 100 is logic high potential and end points C when being logic low potential, and then memory cell 100 stored data are logical one.Anti-, when the terminal B of memory cell 100 is logic low potential and end points C when being logic high potential, then memory cell 100 stored data are logical zero.
Fig. 3 A is the circuit diagram of a kind of memory cell when writing the data of logical one according to the first embodiment of the present invention.Please refer to Fig. 3 A, suppose that memory cell 100 will write the data of logical one.At first, with the voltage signal of a logic high potential, its current potential for example between 1～6V, offers terminal A and bit line 40, and with the voltage signal of a logic low potential, its current potential for example is 0V, offers end points D and E, and bit line 42.In addition, with a control bias voltage, its current potential for example is to offer end points CG1 and CG2 between 3～5V, and with a selection bias voltage, its current potential for example is between 3～5V, offers end points SG1 and SG2.By this, make non-volatile apparatus 30 and 32 be conducting state.Thus, the logic high potential of bit line 40 then is stored in terminal B, and the logic low potential of bit line 42 then is stored in end points C.
Fig. 3 B is the circuit diagram of a kind of memory cell when writing the data of logical zero according to the first embodiment of the present invention.Please refer to Fig. 3 B, suppose that memory cell 100 will write the data of logical zero.At first, with the voltage signal of a logic high potential, its current potential for example is between 1～6V, offers terminal A and bit line 42, and with the voltage signal of a logic low potential, its current potential for example is 0V, offers end points D and E, and bit line 40.In addition, with a control bias voltage, its current potential for example is between 3～5V, offers end points CG1 and CG2, and with a selection bias voltage, its current potential for example is between 3～5V, offers end points SG1 and SG2.By this, make non-volatile apparatus 30 and 32 be conducting state.Thus, the logic low potential of bit line 40 then is stored in terminal B, and the logic high potential of bit line 42 then is stored in end points C.
Fig. 4 is the circuit diagram of a kind of memory cell when keeping (Maintain) state according to the first embodiment of the present invention.Please refer to Fig. 4, suppose that the data of memory cell 100 will be in hold mode.At first, with the voltage signal of a logic high potential, its current potential for example is between 1～6V, offers terminal A, and with the voltage signal of a logic low potential, its current potential for example is 0V, offers end points D and E, bit line 40 and 42.By this, make non-volatile apparatus 30 and non-volatile apparatus 32 be off state.Thus, the logic current potential of terminal B and C then can be in hold mode.
Fig. 5 A is the circuit diagram when reading the data that is stored in the logical one in the memory cell according to the first embodiment of the present invention a kind of.Please refer to Fig. 5 A, in an embodiment, suppose that memory cell 100 has stored the data of a logical one.In the time will reading the stored data of memory cell 100, can be earlier with the voltage signal of logic high potential, its current potential for example is between 1～6V, offer first end of terminal A, bit line 40 and 42, and voltage signal with a logic low potential, its current potential for example is 0V, offers end points D and end points E.In addition, with a control bias voltage, its current potential for example is between 3～5V, offer end points CG1 and CG2, and with a selection bias voltage, its current potential for example is between 3～5V, offer end points SG1 and SG2, make non-volatile apparatus 30 and non-volatile apparatus 32 be conducting state.
Hold above-mentionedly,,, so can treat as and do not have the electric current non-volatile apparatus 30 of flowing through because the current potential of terminal B is identical with the current potential of bit line 40 though non-volatile apparatus 30 is a conducting state.That is to say that if first end of bit line 40 provides electric current I 1, second end of bit line 40 then can receive electric current I 1.On the other hand, because the current potential of end points C is lower than the current potential of bit line 42.Therefore, if first end of bit line 42 provides electric current I 2, the electric current Δ I2 that then has a part flow to end points E at last from flow through in regular turn non-volatile apparatus 32, end points C, metal-oxide-semiconductor (MOS) 22 of bit line 42, and second end of bit line 42 then can receive electric current I 2 one Δ I2.
Have in the present technique field and to know that usually the knowledgeable should know, by the difference of the output current of second end of second end of sensing amplifier (not illustrating) sensing bit line 40 and bit line 42, then can read the logic state of the stored data of memory cell 100.For example, the output current of second end of bit line 40 is greater than the output current of second end of bit line 42, and the original state of then representing memory cell 100 is a logical one.
Fig. 5 B is the circuit diagram when reading the data that is stored in the logical zero in the memory cell according to the first embodiment of the present invention a kind of.Please refer to Fig. 5 B, suppose to have stored in the memory cell 100 data of logical zero.In the time will reading the data that is stored in the logical zero in the mnemon 100, can be earlier with the voltage signal of a logic high potential, its current potential for example is between 1～6V, offer first end of terminal A, bit line 40 and 42, and voltage signal with logic low potential, its current potential for example is 0V, offers end points D and E.In addition, with a control bias voltage, its current potential for example is between 3～5V, offer end points CG1 and CG2, and provide one to select bias voltage, its current potential for example is between 3～5V, offer end points SG1 and SG2, make non-volatile apparatus 30 and non-volatile apparatus 32 be conducting state.And remaining reads principle and can no longer add to give unnecessary details at this with reference to the explanation of Fig. 5 A.
Fig. 6 A is the circuit diagram of the data according to a kind of logical one with memory cell of the first embodiment of the present invention when writing non-volatile apparatus.Please refer to Fig. 6 A, suppose that the stored data of original state of memory cell 100 is a logical one.When the data that will write a logical one is to non-volatile apparatus 32, at first can be with the voltage signal of a logic high potential, its current potential for example is between 1～6V, offer terminal A, bit line 40 and 42, and voltage signal with a logic low potential, its current potential for example is 0V, gives end points D and E.In addition, with a control bias voltage, its current potential for example is between 5～12V, offers end points CG1 and CG2, and with a selection bias voltage, its current potential for example is between 0.5～3V, offers end points SG1 and SG2.
Because end points C and bit line 42 have the pressure reduction of certain degree, therefore have electric charge (Electron) and be injected into the electric charge storage layer 210 or the floating grid 250 of non-volatile apparatus 32 through the source terminal of non-volatile apparatus 32, make non-volatile apparatus 32 by sequencing (Programmed) from end points C.The pressure reduction of terminal B and bit line 40 then deficiency so that non-volatile apparatus 30 by sequencing.Thus, the data of promptly finishing a logical one writes non-volatile apparatus 32.In other words, even when power-off, non-volatile apparatus 32 is still possessed by the sequencing state.
Fig. 6 B is the circuit diagram of the data according to a kind of logical zero with memory cell of the first embodiment of the present invention when writing non-volatile apparatus.Please refer to Fig. 6 B, suppose that the stored data of original state of memory cell 100 is a logical zero.When the data that will write logical zero is to non-volatile apparatus 30, at first can be with the voltage signal of a logic high potential, its current potential for example is between 1～6V, offer terminal A, bit line 40 and bit line 42, and voltage signal with a logic low potential, its current potential for example is 0V, gives end points D and E.In addition, with a control bias voltage, its current potential for example is between 5～12V, offers end points CG1 and CG2, for example is between 0.5～3V and select its current potential of bias voltage with one, offers end points SG1 and SG2.
Because terminal B and bit line 40 have the pressure reduction of certain degree, so have electric charge and be injected into the electric charge storage layer or the floating grid of non-volatile apparatus 30 through the source terminal of non-volatile apparatus 30, make non-volatile apparatus 30 by sequencing from terminal B.The pressure reduction of end points C and bit line 42 then deficiency so that non-volatile apparatus 32 by sequencing.Thus, soon the data of a logical zero writes non-volatile apparatus 30.In other words, even when power-off, non-volatile apparatus 30 is still possessed by the sequencing state.
Fig. 7 A is a kind of circuit diagram when non-volatile apparatus recovers the data of logical one according to the first embodiment of the present invention.Please refer to Fig. 7 A, in the present embodiment, suppose that non-volatile apparatus 32 is by sequencing at the beginning.At first, the present invention can be with the voltage signal of a logic high potential, and its current potential for example is between 1～6V, offers bit line 40 and 42, and with the voltage signal of a logic low potential, its current potential for example is 0V, gives terminal A, D and E.In addition, can be with a control bias voltage, its current potential for example is between 2～3V, offers end points CG1 and CG2, and with a selection bias voltage, its current potential for example is between 2～3V, offers end points SG1 and SG2.
Hold above-mentionedly, because non-volatile apparatus 30 is by sequencing, so non-volatile apparatus 30 can be in conducting state.That is to say that the logic high potential of bit line 40 can be stored in terminal B.On the other hand, because non-volatile apparatus 32 is by sequencing, so non-volatile apparatus 32 can be in off state.In addition, the logic high potential of terminal B can make metal-oxide-semiconductor's 22 conductings.In other words, end points C then can be in logic low potential.Thus, promptly finish from the datum recover of non-volatile apparatus 32 logical one.
Fig. 7 B is a kind of circuit diagram when non-volatile apparatus recovers the data of logical zero according to the first embodiment of the present invention.Please refer to Fig. 7 B, suppose that non-volatile apparatus 30 is by sequencing at the beginning.At first, can be with the voltage signal of a logic high potential, its current potential for example is between 1～6V, offers bit line 40 and 42, and with the voltage signal of a logic low potential, its current potential for example is 0V, offers terminal A, D and E.In addition, can be with a control bias voltage, its current potential for example is between 2～3V, offers end points CG1 and CG2, for example is between 2～3V and select bias with one, offers end points SG1 and SG2.
Hold above-mentionedly, because non-volatile apparatus 32 is by sequencing, so non-volatile apparatus 32 can be in conducting state.That is to say that the logic high potential of bit line 42 can be stored in end points C.On the other hand, because non-volatile apparatus 30 is by sequencing, so non-volatile apparatus 30 can be in off state.In addition, the logic high potential of end points C can make metal-oxide-semiconductor's 20 conductings.In other words, terminal B then can be in logic low potential.Thus, promptly finish from the datum recover of non-volatile apparatus 30 logical zero.
Fig. 8 is the circuit diagram according to the sequencing state of a kind of non-volatile apparatus of erasing of the first embodiment of the present invention.Please refer to Fig. 8, suppose that non-volatile apparatus 30 or 32 is by sequencing at the beginning.At first, provide a voltage signal, its current potential for example is between 0～4.5V, offers bit line 40 and 42, and with a voltage signal, its current potential for example is between 1～3V, offers terminal A, to keep the logic state of terminal B and C.In addition, with the voltage signal of a logic low potential, its current potential for example is 0V, offers end points D and E, in addition with a control bias voltage, its current potential for example be between-8～-12V between, offer end points CG1 and CG2, and with a selection bias voltage, its current potential for example is 0V, offers end points SG1 and SG2.Can force the control grid of non-volatile apparatus 30 and 32 to discharge electric charge.In other words, promptly utilize interband hot hole (Band To Band Hot Hole is called for short BTBHH) or floating grid to wear the sequencing state that (Floating Gate Tunneling) eliminates non-volatile apparatus 30 or non-volatile apparatus 32 then.Thus, can repeat again non-volatile apparatus 30 or non-volatile apparatus 32 sequencing.
In sum, embodiments of the invention have following advantage at least:
1. because memory cell has adopted the non-volatile apparatus of separable grid, the logic state of memory cell can be stored in the non-volatile apparatus.Even so when power-off, still can keep the data that originally was stored in the storer, and behind electric power starting, data can be read from non-volatile apparatus.
2. not only have static RAM and operate advantage fast, can have the function of non-volatile memory storage data simultaneously again concurrently.
3. utilize the electric crystal in the traditional memory cell of non-volatile apparatus replacement, therefore can't increase the size of memory cell, and can in the storer of same size size, increase the effect of data storage in non-volatile apparatus, also help the integration of element.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
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| US6687162B1 (en) * | 2002-04-19 | 2004-02-03 | Winbond Electronics Corporation | Dual reference cell for split-gate nonvolatile semiconductor memory |
| CN1538524A (en) * | 2003-04-16 | 2004-10-20 | ����뵼��ɷ�����˾ | Split-gate flash memory unit and manufacturing method thereof |
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| CN1538524A (en) * | 2003-04-16 | 2004-10-20 | ����뵼��ɷ�����˾ | Split-gate flash memory unit and manufacturing method thereof |
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