CN101286452A - Method for manufacturing metal oxide semiconductor transistor element - Google Patents

Abstract

The invention provides a method for manufacturing a metal oxide semiconductor transistor element. First, a semiconductor substrate and a gate structure are provided on the semiconductor substrate. The semiconductor substrate is provided with a source electrode area and a drain electrode area which are respectively positioned in the semiconductor substrate at two sides of the grid structure. Then, a stress covering layer is formed on the semiconductor substrate and covers the grid structure, the source region and the drain region. After that, inert gas treatment is carried out to change the stress value of the stress covering layer. Since the invention can easily adjust the stress value of the stress covering layer, the single stress covering layer can satisfy the requirements of both the N-type and the P-type metal oxide semiconductor transistors.

Description

Method for making a metal oxide semiconductor transistor element

technical field

The present invention relates to a method for manufacturing metal-oxide-semiconductor (metal-oxide-semiconductor, MOS) transistor elements, in particular to a method for making N-type and P-type metal oxides by utilizing a stress covering layer with binary-stress. method for semiconductor transistor devices. The present invention is characterized in that the stress value of the stress covering layer is changed by inert gas treatment, so that the N-type or P-type metal oxide semiconductor transistor element can have a higher saturation drain current at the same time, thereby improving the operation of the semiconductor transistor element efficacy.

Background technique

As the semiconductor technology enters the deep sub-micron era, the demand for the performance and stability of the transistor device is increasing, and the metal oxide semiconductor transistor device with strained silicon (strained silicon) has also emerged. When the band structure of silicon is changed, the mobility of carriers can be increased. Therefore, devices with strained silicon structure in the channel region can obtain a speed gain of 1.5 times or even up to 8 times. Currently, methods for forming strained silicon metal oxide semiconductor transistors can be mainly divided into two methods. One is to use the principle that the lattice constant of the silicon germanium layer is different from that of silicon to cause structural strain when silicon is epitaxy on silicon germanium. The second is to form a stress covering layer with stress on the transistor structure, and use the stress of the stress covering layer to change the lattice structure of the channel region of the transistor element.

Please refer to FIG. 1 to FIG. 3 , which illustrate schematic cross-sectional views of conventional methods for fabricating the NMOS transistor device 10 and the PMOS transistor device 110 . First, as shown in FIG. 1 , firstly, a semiconductor substrate 16 is provided, and a first transistor region 1 and a second transistor region 2 are defined on the semiconductor substrate 16 . The first and second transistor regions 1, 2 respectively include a gate dielectric layer 14, 114 on the semiconductor substrate 16, and a gate 12, 112 on the gate dielectric layer 14, 114, wherein the gate 12, 112 generally includes polysilicon, and the corresponding gates 12, 112 and gate dielectric layers 14, 114 are collectively referred to as gate structures. The semiconductor substrate 16 has a source region 18 and a drain region 20 in the first transistor region 1 , respectively located in the semiconductor substrate 16 on two sides of the gate 12 . The semiconductor substrate 16 has a source region 118 and a drain region 120 in the second transistor region 2 , respectively located in the semiconductor substrate 16 on two sides of the gate 112 . The source region 18 and the drain region 20 are separated from each other by the channel region 22 , and the source region 118 and the drain region 120 are separated from each other by the channel region 122 . According to conventional techniques, the semiconductor substrate 16 generally further includes shallow junction source extensions 17 , 117 and shallow junction drain extensions 19 , 119 .

In FIG. 1, the source region 18 and the drain region 20 of the NMOS transistor element 10 are N+ doped regions implanted with arsenic, antimony or phosphorus, and the channel region of the NMOS transistor element 10 22 is a P-type doped region. The source region 118 and the drain region 120 of the PMOS transistor device 110 are P+ doped regions, and the channel region 122 of the PMOS transistor device 110 is an N-type doped region.

Sidewalls 32 , 132 made of silicon nitride are formed on the sidewalls of the gate electrodes 12 , 112 . Between the sidewalls 32, 132 and the sidewalls of the gates 12, 112 is a liner layer 30, 130, which is usually made of silicon dioxide. The exposed silicon surfaces of the NMOS transistor device 10 and the PMOS transistor device 110, including gates 12, 112, source regions 18, 118 and drain regions 20, 120, are all formed with metal silicide layer (silicide layer) 42 to be in contact with the subsequently formed contact plugs. Since the process of fabricating the semiconductor structure as shown in FIG. 1 is common knowledge of those skilled in the art, its detailed fabrication procedures are not repeated here.

As shown in FIG. 2, after the NMOS transistor element 10 and the PMOS transistor element 110 in FIG. , wherein the stress covering layer 46 covers the metal silicide layer 42 and the sidewalls 32, 132, and its thickness is usually about 200 to 400 angstroms. The purpose of depositing the stress covering layer 46 is, on the one hand, to change the lattice structure of the channel region 22 of the NMOS transistor device 10, and on the other hand, to enable the subsequent etching of the contact hole to have an obvious etching end point, that is, Used as a contact etch stop layer (CESL). After depositing the stress covering layer 46 , an anneal process is performed to strengthen the stress of the stress covering layer 46 .

As shown in FIG. 3 , a dielectric layer 48 is then deposited, such as a silicon oxide layer. Usually, the dielectric layer 48 is much thicker than the stress capping layer 46 . Then, contact holes 52 are formed in the dielectric layer 48 and the stress capping layer 46 by conventional photolithography and etching processes.

However, the aforementioned conventional techniques still have disadvantages to be overcome. The stress covering layer 46 is deposited on the entire chip, thus increasing the tensile stress of the NMOS transistor device 10 and the PMOS transistor device 110 at the same time. Although the performance of the N-MOS transistor device 10 will be improved accordingly, the performance of the P-MOS transistor device 110 will be reduced instead.

In order to improve the operating performance of the NMOS transistor and the PMOS transistor at the same time, the process of the stress covering layer 46 also adopts another selective stress system (selective strain scheme, SSS). known technology. In the known technology, a stress covering layer with tensile stress is firstly deposited on the semiconductor substrate to cover the NMOS transistor element and the PMOS transistor element. Next, a patterning process is used to remove the tensile stress capping layer above the PMOS transistor element. Afterwards, a stress covering layer with compressive stress is fully deposited on the semiconductor substrate, covering the tensile stress covering layer and the PMOS transistor element. Next, another patterning process is used to remove the compressive stress covering layer above the NMOS transistor device.

Although the known technology of this SSS can simultaneously improve the operating performance of N-type metal-oxide-semiconductor transistors and P-type metal-oxide-semiconductor transistors, its manufacturing process is very complicated, which not only takes a long time, but also requires a lot of effort. relatively large cost. In addition, its complicated manufacturing process may also increase product defects.

Contents of the invention

Therefore, the main objective of the present invention is to provide a method for fabricating N-type and P-type MOS transistors with a stress capping layer having dual stresses, which has better operating performance.

According to a preferred embodiment of the present invention, the present invention provides a method for fabricating a metal oxide semiconductor transistor device. First, a semiconductor substrate is provided, a gate dielectric layer is located on the semiconductor substrate, and a gate is located on the gate dielectric layer. The semiconductor substrate has a source region and a drain region, and the source region and the drain region are respectively located in the semiconductor substrate on both sides of the gate. Afterwards, a stress covering layer is formed on the semiconductor substrate and covers the gate, the source region and the drain region. Next, an inert gas treatment is performed to change the stress value of the stress covering layer.

According to another preferred embodiment of the present invention, the present invention further provides a method for manufacturing a metal oxide semiconductor transistor device. First, a semiconductor substrate is provided, and a first transistor region and a second transistor region are defined on the semiconductor substrate. The first and second transistor regions respectively include a gate structure, and the semiconductor substrate on opposite sides of each gate structure has a source region and a drain region. Afterwards, a stress covering layer is formed on the semiconductor substrate in the first and second transistor regions, and the stress covering layer covers the gate structure, the source region and the drain region. Next, a patterned hard mask is formed on the stress covering layer, the patterned hard mask covers the stress covering layer in the second transistor region, and exposes the stress covering layer in the first transistor region, and then an inert gas treatment is performed , to change the stress value of the stress capping layer not covered by the patterned hard mask. Then, the patterned hard mask is removed.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the drawings are only for reference and auxiliary description, and are not intended to limit the present invention.

Description of drawings

1 to 3 are schematic cross-sectional views of conventional methods for fabricating N-type MOS transistors and P-type MOS transistors.

4 to 11 are schematic cross-sectional diagrams illustrating the method of the NMOS transistor device and the PMOS transistor device according to the first preferred embodiment of the present invention.

FIG. 12 to FIG. 17 are schematic cross-sectional views showing the methods of the NMOS transistor device and the PMOS transistor device according to the second preferred embodiment of the present invention.

FIG. 18 is a bar diagram showing the tensile stress values of the stress covering layer of the present invention.

Explanation of reference signs

1 first transistor region 2 second transistor region

10 NMOS transistor element 12 gate

14 Gate Dielectric Layer 16 Semiconductor Substrate

17 shallow junction source extension 18 source region

19 shallow junction drain extension 20 drain region

22 channel area 30 liner layer

32 sidewalls 42 metal silicide layer

46 Stress covering layer 48 Dielectric layer

52 Contact hole 68 Mask layer

78 mask layer 98 photoresist

110 PMOS transistor element 112 gate

114 Gate dielectric layer 117 Shallow junction source extension

118 source region 119 shallow junction drain extension

120 Drain Region 122 Channel Region

130 Cushion layer 132 Side wall

188 patterned hardmask 212 value

214 Value 216 Value

222 Value 224 Value

226 Value 232 Value

234 Value 236 Value

242 Value 244 Value

246 Value 252 Value

254 Value 256 Value

262 Value 264 Value

266 Value 301 First Transistor Area

302 second transistor region 310 NMOS transistor element

312 Gate 314 Gate Dielectric Layer

316 Semiconductor substrate 317 Shallow junction source extension

318 Source Region 319 Shallow Junction Drain Extension

320 Drain Region 322 Channel Region

330 Cushion layer 332 Side wall

342 Silicide metal layer 346 Stress covering layer

348 dielectric layer 352 contact hole

410 PMOS transistor element 412 gate

414 Gate Dielectric Layer 417 Shallow Junction Source Extension

418 Source Region 419 Shallow Junction Drain Extension

420 Drain Region 422 Channel Region

430 Cushion layer 432 Side wall

Detailed ways

Please refer to FIG. 4 to FIG. 11 , which are schematic cross-sectional diagrams illustrating the method of the N-type metal-oxide-semiconductor transistor device 310 and the P-type metal-oxide-semiconductor transistor device 410 according to the first preferred embodiment of the present invention, wherein the same device or Parts are still represented by the same symbols. It should be noted that the drawings are for illustration purposes only and are not drawn to original scale. In addition, in FIGS. 4 to 11 , the photolithography and etching processes for the parts related to the present invention are well known to those skilled in the art, so they are not explicitly shown in the figures.

The present invention relates to a method of fabricating metal-oxide-semiconductor transistor elements or complementary metal-oxide-semiconductor (CMOS) transistor elements with strained silicon in integrated circuits. To simplify the description, in FIG. 4 to FIG. 11 , the CMOS transistor technology is used for illustration. As shown in FIG. 4 , a semiconductor substrate 316 is provided first. A first transistor region 301 and a second transistor region 302 are defined on the semiconductor substrate 316, wherein the first transistor region 301 is used to manufacture N-type metal oxide semiconductor transistor elements, and the second transistor region 302 is used to manufacture P type metal-oxide-semiconductor transistor devices. The semiconductor substrate 316 may be a silicon substrate or a silicon-on-insulator (SOI) substrate or the like. Firstly, a gate dielectric layer 314 and a gate 312 on the gate dielectric layer 314 are simultaneously formed on the semiconductor substrate 316 in the first transistor region 301 . On the other hand, a gate dielectric layer 414 and a gate 412 on the gate dielectric layer 414 are formed on the semiconductor substrate 316 in the second transistor region 302 at the same time. The corresponding gate 312 and gate dielectric layer 314 are collectively referred to as a gate structure, and the corresponding gate 412 and gate dielectric layer 414 are collectively referred to as a gate structure. The gates 312 and 412 generally comprise conductive materials such as polysilicon or metal silicide. In this embodiment, the gate dielectric layers 314 and 414 may be made of silicon dioxide. However, in another embodiment of the present invention, the gate dielectric layers 314 and 414 may also be made of insulating materials such as high dielectric constant (high-k).

After that, using the gate structure as an implantation mask, a shallow junction source extension 317 and a shallow junction drain extension 319 are simultaneously formed in the semiconductor substrate 316 in the first transistor region 301, and the shallow junction source extension 317 and the shallow junction drain Between extensions 319 is channel region 322 . Next, a shallow junction source extension 417 and a shallow junction drain extension 419 are formed in the semiconductor substrate 316 in the second transistor region 302 , and a channel region 422 is formed between the shallow junction source extension 417 and the shallow junction drain extension 419 .

Next, using deposition and etch-back processes, sidewalls 332 and 432 made of silicon nitride are formed on the sidewalls of the gates 312 and 412, and a liner between the gates and the sidewalls is formed at the same time. Layers 330 and 430 . The liner layers 330 and 430 are generally L-shaped with a thickness of about 30 to 120 angstroms, and may be made of silicon oxide. Besides, in another embodiment of the present invention, the liner layers 330 and 430 can also be offset spacers.

As shown in FIG. 5 , after forming the sidewalls 332 and 432 , the second transistor region 302 is covered by a mask layer 68 made of a material such as photoresist. Next, an ion implantation process is performed to implant N-type dopant species, such as arsenic, antimony or phosphorus, into the semiconductor substrate 316 in the first transistor region 301, thereby forming the source region 318 of the N-type metal oxide semiconductor transistor element. and drain region 320 . After the aforementioned ion implantation process is completed, the mask layer 68 is stripped off immediately.

As shown in FIG. 6 , the first transistor region 301 is then covered with a mask layer 78 . Then another ion implantation process is performed to implant P-type dopant species, such as boron, into the semiconductor substrate 316 in the second transistor region 302, thereby forming the source region 418 and the drain of the P-type metal oxide semiconductor transistor element. polar region 420 . After the aforementioned ion implantation process is completed, the mask layer 78 is removed immediately. Those skilled in the art will understand that the aforementioned injection sequence shown in FIGS. 5 and 6 can be reversed. In other words, the P-type doping in the second transistor region 302 can be performed first, and then the N-type doping in the first transistor region 301 can be performed. In addition, after the doping of the drain and source is completed, the semiconductor substrate 316 can generally be subjected to a thermal process of annealing or activating the dopant. This step is also common knowledge of those skilled in the art and will not be repeated here. statement.

In addition, those who know this field should understand that the present invention can also be combined with a selective epitaxial growth (SEG) process to fill the semiconductor substrate with a silicon germanium (SiGe) epitaxial layer or a silicon carbide (SiC) epitaxial layer. layer as the source and drain regions.

As shown in FIG. 7 , according to a preferred embodiment of the present invention, a stress covering layer 346 is uniformly deposited on the semiconductor substrate 316 as a polysilicon stressor. The stress capping layer 346 covers the source regions 318 , 418 , the drain regions 320 , 420 and the gates 312 , 412 , and has a thickness between about 30 to 2000 angstroms. According to the present invention, the stress covering layer 346 is in a state of tensile strain (tensile-stressed) during deposition, and the stress of the initial deposition (as-deposition) is between about 500 million Pa (0.5 Giga pascals, 0.5 GPa) and 2.5 GPa. between. Thereafter, the present invention can also carry out surface treatment to the stress covering layer 346, such as UV curing (UV curing) process, high temperature peak annealing (thermal spike anneal) process, laser annealing (laser anneal) process or electron beam (e-beam) processing etc. to increase the stress of the stress covering layer 346 .

As shown in FIG. 8 , then, a mask layer is uniformly deposited on the semiconductor substrate 316 to cover the stress covering layer 346 . In this embodiment, the material of the mask layer may be oxide or a substance that simultaneously includes oxide, photoresist, etc., and has a better etching selectivity ratio to the stress covering layer 346 . A patterning process is then performed, using the photoresist 98 as an etching mask to remove the mask layer in the second transistor region 302 to form a patterned hard mask 188 . The patterned hard mask 188 covers the stress capping layer 346 in the first transistor region 301 and exposes the stress capping layer 346 in the second transistor region 302 . In addition, in another embodiment of the present invention, a photoresist material with an appropriate thickness can also be directly used as the patterned hard mask 188 . If the patterned hard mask 188 is a photoresist material, the step of forming the photoresist 98 can be omitted.

Next, as shown in FIG. 9 , the photoresist 98 is subsequently removed and an inert gas treatment is performed to change the stress value of the stress capping layer 346 not covered by the patterned hard mask 188 . Inert gas treatment can be carried out in chemical vapor deposition (chemical vapor deposition, CVD) equipment or in physical vapor deposition (physical vapor deposition, PVD) equipment. Inert gas treatment uses argon and other inert gases, and the processing power ( treatment power) between 0.1 kilowatts (kilo-watts, KW) and 10 kilowatts. In addition, one or more types of helium, krypton, nitrogen, oxygen or other inert gases are also selected for inert gas treatment.

The inert gas treatment can substantially reduce the tensile stress of the stress cap layer 346 not covered by the patterned hard mask 188 . Through the control of process parameters such as processing power and processing time, the present invention can adjust the stress value of the stress covering layer 346 . In other words, after the inert gas treatment, the stress covering layer 346 covering the semiconductor substrate 316 has a double stress structure, that is, the stress covering layer 346 above the NMOS transistor element 310 has a larger The tensile stress of the stress covering layer 346 above the PMOS transistor device 410 is relatively small. With the longer treatment time of the inert gas and the control of process parameters such as greater processing power, the decrease in the tensile stress value is greater, and even the stress covering layer above the PMOS transistor element 410 can be directly eliminated. 346 tensile stress.

Next, as shown in FIG. 10 , the patterned hard mask 188 is first removed, and then a rapid thermal processing (rapid thermal processing, RTP) is performed to store the stress state of the stress capping layer 346 into the NMOS transistor element 310. and the PMOS transistor element 410 . Afterwards, as shown in FIG. 11 , the stress capping layer 346 is removed to form a CMOS transistor device with strained silicon.

After the aforementioned CMOS transistor device is completed, processes such as salicide, dielectric layer deposition, and contact hole etching can be performed, which will not be repeated here.

Please refer to FIG. 12 to FIG. 17 , which are schematic cross-sectional diagrams showing the method of the N-type metal oxide semiconductor transistor device 310 and the P-type metal oxide semiconductor transistor device 410 according to the second preferred embodiment of the present invention, wherein the same device or Parts are still represented by the same symbols. As shown in FIG. 12 , a semiconductor substrate 316 is provided first. A first transistor region 301 and a second transistor region 302 are defined on the semiconductor substrate 316 . In the first transistor region 301, the gate dielectric layer 314 is located on the semiconductor substrate 316, the gate 312 is located on the gate dielectric layer 314, and the source region 318 and the drain region 320 are respectively located on both sides of the gate 312. In the semiconductor substrate 316 . An N-type channel region 322 is located between the source region 318 and the drain region 320 . On the other hand, in the second transistor region 302, the gate dielectric layer 414 is located on the semiconductor substrate 316, the gate 412 is located on the gate dielectric layer 414, and the source region 418 and the drain region 420 are respectively located on the gate In the semiconductor substrate 316 on both sides of the electrode 412 . Between the source region 418 and the drain region 420 is a P-type channel region 422 . The gate 312 has a sidewall 332 and a liner 330 on its sidewall, and the gate 412 has a sidewall 432 and a liner 430 on its sidewall.

Similarly, this embodiment can also be combined with the selective epitaxial growth process, and the silicon germanium epitaxial layer or the silicon carbide epitaxial layer is filled in the semiconductor substrate as the source region and the drain region.

As shown in FIG. 13 , a metal silicide process is then performed to form a silicide metal layer 342 such as nickel silicide on the source regions 318 , 418 , drain regions 320 , 420 and gates 312 , 412 . As shown in FIG. 14 , a stress covering layer 346 is uniformly deposited on the semiconductor substrate 316 , and the stress covering layer 346 covers the source regions 318 , 418 , the drain regions 320 , 420 and the gates 312 , 412 . The stress capping layer 346 is in a state of tensile strain when deposited, and its initial deposition stress is approximately between 0.5 GPa and 2.5 GPa. Afterwards, the present invention can also carry out surface treatment on the stress covering layer 346 , such as ultraviolet curing process, high temperature peak annealing process, laser annealing process or electron beam treatment, etc., so as to increase the stress of the stress covering layer 346 .

As shown in FIG. 15 , next, a mask layer is uniformly deposited on the semiconductor substrate 316 to cover the stress covering layer 346 . The material of the mask layer can be oxide, photoresist, or a substance including oxide and photoresist, etc., which has a better etching selectivity ratio to the stress covering layer 346 . A patterning process is then performed, using the photoresist 98 as an etching mask to remove the mask layer in the second transistor region 302 to form a patterned hard mask 188 . The patterned hard mask 188 covers the stress capping layer 346 in the first transistor region 301 and exposes the stress capping layer 346 in the second transistor region 302 .

Next, as shown in FIG. 16 , the photoresist 98 is subsequently removed, and an inert gas treatment is performed to change the stress value of the stress capping layer 346 not covered by the patterned hard mask 188 . Inert gas treatment can be performed in chemical vapor deposition equipment or in physical vapor deposition equipment, which utilizes argon and other inert gases, and the processing power is between 0.1 kW and 10 kW. The inert gas treatment can substantially reduce the tensile stress of the stress cap layer 346 not covered by the patterned hard mask 188 . In other words, after the inert gas treatment, the stress capping layer 346 above the NMOS transistor element 310 has a larger tensile stress, while the stress capping layer 346 above the PMOS transistor element 410 The tensile stress of 346 is small, even in the state of no tensile stress.

Next, as shown in FIG. 17 , the patterned hard mask 188 is first removed, and then a dielectric layer 348 is deposited on the semiconductor substrate to cover the stress covering layer 346 in the first transistor region 301 and the second transistor region 302 . The dielectric layer 348 can be silicon oxide, doped silicon oxide and other low dielectric constant materials. Photolithography and etching processes are then performed to form contact holes 352 in the dielectric layer 348 and the stress capping layer 346 , respectively reaching the source regions 318 , 418 , the drain regions 320 , 420 and the gates 312 , 412 . In other embodiments, only contact holes leading to the source regions 318 , 418 and the drain regions 320 , 420 may also be formed, but this is not explicitly shown in the drawings. According to the spirit of the present invention, the stress capping layer 346 can be used as a contact etch stop layer during the contact hole dry etching process.

Please refer to FIG. 18 , which is a schematic diagram showing the tensile stress values of the stress covering layer 346 of the present invention, wherein the vertical axis shows the tensile stress values. The figure shows the stress values of six sets of stress covering layers. Each set of stress covering layers has been measured at least three times, and the values 212, 222, 232, 242, 252, and 262 are measured after the stress covering layers are deposited. Stress values, the values 214, 224, 234, 244, 254, 264 are the stress values measured after the stress covering layer has undergone the ultraviolet curing process, and the values 216, 226, 236, 246, 256, 266 are the stress covering layers after the inert Stress values measured after gas treatment. The difference between the six sets of stress covering layers in the figure lies in the processing power of the inert gas treatment. The processing power from left to right is 2 kW, 3 kW, 4 kW, 5 kW, 6 kW and 7 kW. The treatment time of the aforementioned six groups of inert gas treatment is 10 seconds, but the present invention is not limited thereto. As shown in Fig. 18, as the processing power increases, the decrease of the tensile stress value also increases. When the processing power is greater than 5 kW, the stress value of the stress covering layer after the inert gas treatment is even lower than that of the deposited stress covering layer.

The present invention is characterized in that the stress value of the stress covering layer is changed by inert gas treatment, so that the stress covering layer becomes a structure with double stress. In view of this, the stress covering layer of the high tensile stress part can change the lattice structure of the channel region of the NMOS transistor element, so that the NMOS transistor element can have a higher saturation drain current, Further, the operating efficiency of the semiconductor transistor device is improved. On the other hand, the stress covering layer covering the PMOS transistor device has only low tensile stress, which can prevent the stress covering layer from degrading the operation performance of the PMOS transistor device. In view of this, the present invention enables the N-type or P-type MOS transistor device to have a higher saturation drain current, thereby improving the operating performance of the semiconductor transistor device.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the patent of the present invention.

Claims (32)

1. method of making metal-oxide semiconductor transistor component includes:

Provide the semiconductor-based end, gate dielectric to be positioned on this semiconductor-based end, and grid is positioned on this gate dielectric, this semiconductor-based end, have source region and drain region, and this source region and this drain region laid respectively in this semiconductor-based end of these grid both sides;

On this semiconductor-based end, form the stress cover layer and cover this grid, this source region and this drain region; And

Carry out inert gas and handle, to change the tectal stress value of this stress.

2. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this metal-oxide semiconductor transistor component is a N type metal oxide semiconductor transistor unit.

3. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this metal-oxide semiconductor transistor component is the P-type mos transistor unit.

4. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this stress cover layer includes silicon nitride.

5. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein before this inert gas was handled, this stress cover layer had stretching stress.

6. the method for making metal-oxide semiconductor transistor component as claimed in claim 5, wherein this inert gas processing is to be used for reducing tectal this stretching stress of this stress.

7. the method for making metal-oxide semiconductor transistor component as claimed in claim 5, the stress value scope of this stretching stress before wherein this inert gas is handled is between 0.5GPa and 2.5GPa.

8. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this inert gas is handled and is carried out among chemical vapor depsotition equipment.

9. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this inert gas is handled and is carried out among Pvd equipment.

10. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this inert gas includes argon gas and other inert gases in handling.

11. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein the processing power of this inert gas processing is between 0.1 kilowatt and 10 kilowatts.

12. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein after forming this stress cover layer, this method includes UV cured technology, high temperature peak annealing process, laser annealing technique or electron beam treatment in addition.

13. the method for making metal-oxide semiconductor transistor component as claimed in claim 1 wherein includes quick thermal treatment process in addition after this inert gas treatment step.

14. the method for making metal-oxide semiconductor transistor component as claimed in claim 13 wherein includes in addition after this quick thermal treatment process step and removes the tectal step of this stress.

15. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this method includes the step at this drain region and this source region formation metal silicide layer in addition.

16. the method for making metal-oxide semiconductor transistor component as claimed in claim 15, wherein this stress cover layer when etching contact hole as contact etch stop layer.

17. the method for making metal-oxide semiconductor transistor component as claimed in claim 1 wherein has laying on the two lateral walls of this grid.

18. the method for making metal-oxide semiconductor transistor component as claimed in claim 17 wherein has sidewall on this laying.

19. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this method has the step that forms extension of shallow junction source electrode and shallow junction drain electrode extension in this semiconductor-based end in addition.

20. a method of making metal-oxide semiconductor transistor component includes:

The semiconductor-based end, be provided, definition has the first transistor zone and transistor seconds zone on this semiconductor-based end, this first with this transistor seconds zone on include grid structure respectively, respectively this of these relative both sides of grid structure has source region and drain region in semiconductor-based end;

This first with this transistor seconds zone in this semiconductor-based end on formation stress cover layer, this stress cover layer covers on these grid structures, these source regions and these drain regions; And

Carry out inert gas and handle, to change the tectal stress value of this stress in this transistor seconds zone.

21. the method for making metal-oxide semiconductor transistor component as claimed in claim 20, wherein before this inert gas is handled, this method includes the step that forms hard mask on this stress cover layer in addition, this hard mask covers on this stress cover layer in this first transistor zone, and exposes this stress cover layer in this transistor seconds zone.

22. the method for making metal-oxide semiconductor transistor component as claimed in claim 20, wherein this method forms N type metal oxide semiconductor transistor unit in this first transistor zone, and forms the P-type mos transistor unit in this transistor seconds zone.

23. the method for making metal-oxide semiconductor transistor component as claimed in claim 20, wherein this stress cover layer includes silicon nitride.

24. the method for making metal-oxide semiconductor transistor component as claimed in claim 21, wherein this hard mask includes oxide.

25. the method for making metal-oxide semiconductor transistor component as claimed in claim 20, wherein before this inert gas was handled, the stress value of the tectal stretching stress of this stress was between 0.5GPa and 2.5GPa.

26. the method for making metal-oxide semiconductor transistor component as claimed in claim 25, wherein this inert gas is handled in order to reduce tectal this stretching stress of this stress.

27. the method for making metal-oxide semiconductor transistor component as claimed in claim 20, wherein this inert gas includes argon gas and other inert gases in handling.

28. the method for making metal-oxide semiconductor transistor component as claimed in claim 20, wherein after forming this stress cover layer, this method includes UV cured technology, high temperature peak annealing process, laser annealing technique or electron beam treatment in addition.

29. the method for making metal-oxide semiconductor transistor component as claimed in claim 20 wherein includes quick thermal treatment process in addition after this inert gas treatment step.

30. the method for making metal-oxide semiconductor transistor component as claimed in claim 29 wherein includes in addition after this quick thermal treatment process step and removes the tectal step of this stress.

31. the method for making metal-oxide semiconductor transistor component as claimed in claim 20, wherein this method includes the step at this drain region and this source region formation metal silicide layer in addition.

32. the method for making metal-oxide semiconductor transistor component as claimed in claim 31, wherein this stress cover layer when etching contact hole as contact etch stop layer.

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