CN101253628B - Two-terminal nanotube devices and systems and methods of making the same - Google Patents

Abstract

A two-terminal switching device includes first and second conductive terminals and a nanotube article. The nanotube article has a plurality of nanotubes and is in permanent direct physical contact with both the first and second conductive terminals. The two-terminal switching device also includes a stimulation circuit in electrical communication with at least one of the first and second conductive terminals. The stimulation circuit is configured to create a first voltage difference between the first conductive terminal and the second conductive terminal, thereby causing the resistance of the nanotube article between the first and second conductive terminals to change from a relatively lower resistance to a relatively higher resistance. The stimulation circuit is configured to create a second voltage difference between the first conductive terminal and the second conductive terminal, thereby causing the resistance of the nanotube article between the first and second conductive terminals to change from a relatively higher resistance to a relatively lower resistance. The relatively higher resistance of the nanotube article between the first and second conductive terminals corresponds to a first state of the two-terminal switching device, and the relatively lower resistance of the nanotube article between the first and second conductive terminals corresponds to a second state of the two-terminal switching device. The first and second states of the two-terminal switching device are non-volatile.

Description

Double-ended nanotube devices and systems and fabrication methods thereof

Cross References to Related Applications

This application claims priority under 35 U.S.C. §119(e) to the following applications, the contents of which are hereby incorporated by reference in their entirety:

U.S. Provisional Patent Application No. 60/679,029, entitled "Reversible Nanoswitch," filed May 9, 2005;

U.S. Provisional Patent Application No. 60/692,891, entitled "Reversible Nanoswitch," filed June 22, 2005;

U.S. Provisional Patent Application No. 60/692,918, entitled "NRAM Nonsuspended Reversible Nanoswitch Nanotube Array," filed June 22, 2005; and

U.S. Provisional Patent Application No. 60/692,765, entitled "Embedded CNT Switch Applications For Logic," filed June 22, 2005. the

This application is related to the following applications, the contents of which are hereby incorporated by reference in their entirety:

U.S. Patent Application No. (to be published (TBA)) entitled "Memory Arrays Using Nanotube Articles With Reprogrammable Resistance" filed on the same date as this application; and

U.S. Patent Application No. (to be published) entitled "Non-Volatile Shadow Latch Using A Nanotube Switch" filed on the same date as this application. the

background

technical field

The present invention relates generally to the field of switching devices, and more particularly to two-terminal nanotube devices useful in fabricating nonvolatile and other memory circuits. the

Description of related fields

Digital logic circuits are used in personal computers, portable electronic devices such as personal organizers and calculators, electronic entertainment equipment, and in control circuits for home appliances, telephone switching systems, automobiles, airplanes, and other manufactured goods. Early digital logic was built with discrete switching elements consisting of individual bipolar transistors. Through the invention of bipolar integrated circuits, a large number of individual switching elements can be combined on a single silicon substrate to create complete digital logic circuits such as inverters, NAND gates, NOR gates, flip-flops, adders, etc. However, the density of bipolar digital ICs is limited by their high power dissipation and the packaging technology's ability to dissipate the heat generated by the circuit's operation. Metal-oxide-semiconductor ("MOS") integrated circuits using field effect transistor ("FET") switching elements greatly reduce the power consumption of digital logic, enabling the formation of high-density complex digital circuits used in current technology. The density and speed of operation of MOS digital circuits are still limited by the need to dissipate the heat generated by the operation of the device. the

Digital logic integrated circuits built from bipolar or MOS devices cannot function properly under conditions of high heat or extreme environments. Current digital integrated circuits are typically designed to operate at temperatures less than 100 degrees Celsius, and very few circuits operate at temperatures exceeding 200 degrees Celsius. In conventional integrated circuits, the leakage current of individual switching elements in the "off" state increases rapidly with temperature. As the leakage current increases, the operating temperature of the device rises, the power dissipated by the circuit increases, and the difficulty of distinguishing the off state from the on state reduces the reliability of the circuit. Conventional digital logic circuits are also subject to internal short circuits in extreme environments because they can generate currents inside the semiconductor material. It is possible to fabricate integrated circuits with special devices and insulation techniques that allow them to remain operational when exposed to extreme environments, but the high cost of these devices limits their availability and practicality. Furthermore, such digital circuits exhibit timing differences relative to their conventional counterparts, requiring additional design verification to add protection to existing designs. the

Integrated circuits built with either bipolar or FET switching elements are volatile. They only maintain their internal logic state while power is applied to the device. When power is removed, the internal state is lost unless some type of non-volatile memory circuitry such as EEPROM (Electrically Erasable Programmable Read Only Memory) is added internally or externally to the device to maintain the logic state. Even with non-volatile memory to retain logic states, additional circuitry is required to transfer the logic states to the memory before power is lost, and to restore the state of individual logic circuits when power to the device is restored. Alternative solutions to prevent loss of information in volatile digital circuits, such as battery backup, also add cost and complexity to digital designs. the

Important characteristics of logic circuits in electronic equipment are low cost, high density, low power, and high speed. Conventional logic solutions are limited to silicon substrates, but logic circuits built on other substrates may allow direct integration of logic devices into many manufactured products in a single step, further reducing costs. the

Devices have been proposed that use nanoscale wires such as single-walled carbon nanotubes to form cross junctions to function as memory cells. (Refer to WO 01/03208, "Nanoscopic Wire-Based Devices, Arrays, and Methods of Their Manufacture (device, array and its manufacturing method based on nanoscale wires)"; and "Carbon Nanotube-Based Nonvolatile Random Access by Thomas Rueckes et al. Memory for Molecular Computing (non-volatile random access memory based on carbon nanotubes for molecular computing), Science (science), volume 289, pages 94-97, July 7, 2000.) Hereinafter these The device is called a nanotube wire interleaved memory (NTWCM). In these proposals, individual single-walled nanotube wires suspended over other wires define the memory cell. Writing electrical signals into one or two wires causes them to physically attract or repel each other. Each physical state (ie, a line of attraction or repulsion) corresponds to an electrical state. The repulsive line is an open junction. The attracting line is the closed state that forms the rectifying junction. When electrical power is removed from the junction, the wires retain their physical state (and therefore electrical state), forming a non-volatile memory cell. the

U.S. Patent No. 6,919,592 entitled "Electromechanical Memory Array Using Nanotube Ribbons and Method for Making Same" discloses an electromechanical circuit such as a memory cell, wherein the circuit includes a circuit having conductive traces structure and supports extending from the substrate surface. An electromechanically deformable nanotube ribbon or switch is suspended by supports spanning the conductive traces. Each ribbon includes one or more nanotubes. These ribbons are typically formed by the selective removal of material from a layer of nanotubes or entangled structures of nanotubes. the

For example, as disclosed in US Patent No. 6,919,592, nanofabric can be patterned into ribbons, and these ribbons can be used as components to create non-volatile electromechanical memory cells. The ribbon is electromechanically deflectable in response to control traces and/or electrical stimulation of the ribbon. The deflected physical state of the tape can represent the corresponding informational state. The deflected physical state has a non-volatile character, meaning that the strip remains in its physical state (and thus information state) even if power is removed from the memory cell. As disclosed in U.S. Patent No. 6,911,682, entitled "Electromechanical Three-Trace Junction Devices," a three-trace architecture can be used in electromechanical memory cells, where two of the traces are controlled with deflection electrode. the

The use of electromechanical bistable devices for digital information storage has also been proposed (see U.S. Patent No. 4,979,149 entitled "Nonvolatile Memory Device Including a Micro-Mechanical Storage Element") ). the

The creation and operation of bistable, nanoelectromechanical switches based on carbon nanotubes (including their monolayer construction) and metal electrodes has been described in detail in an earlier patent application having a common assignee with the present invention, U.S. Patent No. 6,784,028、6,835,591、6,574,130、6,643,165、6,706,402、6,919,592、6,911,682、和6,924,538；美国专利申请No.2005-0062035、2005-0035367、2005-0036365、2004-0181630；以及美国专利申请No.10/341005、10/ 341055, 10/341054, 10/341130, the contents of which are hereby incorporated by reference in their entirety (hereinafter and above "Incorporated Patent References"). the

overview

The present invention provides structures and methods for fabricating two-terminal nanotube switches, memory cell arrays based on these switches, fuse/antifuse devices based on these switches, and reprogrammable wiring based on these switches. the

In one aspect, a double-terminal switching device includes a first conductive terminal and a second conductive terminal spaced apart from the first conductive terminal. The device also includes a nanotube article having at least one nanotube. The nanotube article is disposed in permanent direct physical contact with both said first and second conductive terminals. The device also includes a stimulation circuit in electrical communication with at least one of the first and second conductive terminals. The stimulation circuit is configured to create a first voltage difference between the first and second conductive terminals such that the resistance of the nanotube article between the first and second conductive terminals changes from a relatively low The resistance changes to a relatively high resistance. The stimulation circuit is configured to create a second voltage difference between the first conductive terminal and the second conductive terminal such that the resistance of the nanotube article between the first and second conductive terminals is relatively low. High resistance changes to relatively low resistance. A relatively high resistance between the first and second conductive terminals corresponds to a first state of the device, and a relatively low resistance between the first and second conductive terminals corresponds to a second state of the device. The first and second states of the device may be non-volatile. The resistance of the first state may be at least about ten times greater than the resistance of the second state. the

In another aspect, the nanotube article overlaps at least a portion of the first terminal in a controlled geometric relationship. The controlled geometry may allow relatively good flow of electrical current between the first terminal and the article of nanotubes and relatively poor flow of heat between the first terminal and the article of nanotubes. The controlled geometric relationship may be a predetermined degree of overlap. In another aspect, at least one of the first and second terminations has a vertically oriented feature, and the nanotube article substantially conforms to at least a portion of the vertically oriented feature. In another aspect, a nanotube article includes regions of nanotube structures that define orientation. the

In another aspect, the first electrical stimulus is an erase operation. In another aspect, the second electrical stimulus is a programming operation. In another aspect, the stimulation circuit is capable of applying a third electrical stimulus to at least one of the first and second conductive terminals to determine the state of the device. The third electrical stimulus may be a non-destructive read operation. the

In another aspect, a two-terminal memory device includes a first conductive terminal and a second conductive terminal spaced from the first conductive terminal. The device also includes a nanotube article having at least one nanotube. The nanotube article is configured to be in permanent direct physical contact with the first and second conductive terminals. The device also includes a stimulation circuit in electrical communication with at least one of the first and second conductive terminals. The stimulation circuit is configured to create a first voltage difference between the first and second conductive terminals, thereby opening one or more gaps between the one or more nanotubes and the one or more conductors in the device. Opening of the one or more gaps changes the resistance of the nanotube article between the first and second conductive terminals from a relatively low resistance to a relatively high resistance. The stimulation circuit is configured to create a second voltage difference between the first conductive terminal and the second conductive terminal, thereby closing one or more bridges between the one or more nanotubes and the one or more conductors in the device. gaps, and the closure of the one or more gaps changes the resistance of the nanotube article between the first and second conductive terminals from a relatively high resistance to a relatively low resistance. The conductors in the device include one or more of a first conductive terminal, a second conductive terminal, nanotubes, and nanotube segments. A relatively high resistance between the first and second conductive terminals corresponds to a first state of the device, and a relatively low resistance between the first and second conductive terminals corresponds to a second state of the device. The first and second states of the device may be non-volatile. the

In another aspect, the first electrical stimulus heats at least a portion of the nanotube article to open the one or more gaps. In another aspect, one or more thermal features of the device are selected to minimize heat flow out of the nanotube element. Heat flow out of the nanotube element can be minimized by arranging the nanotube article and the first conductive terminal in a controlled geometric relationship that restricts heat flow from the nanotube article and into the first conductive terminal. The controlled geometric relationship may be a predetermined degree of overlap. Heat flow out of the nanotube element can be minimized by selecting a first conductive terminal material that is relatively well conductive and relatively poorly conductive. This material has relatively high electrical conductivity and relatively low thermal conductivity. the

In another aspect, the first electrical stimulus opens the one or more gaps by forming a gap between the one or more nanotubes and one or more of the first and second conductive terminals. In another aspect, the first electrical stimulus opens the one or more gaps by separating one or more nanotubes from one or more other nanotubes in the electrical network of nanotubes. In another aspect, the first electrical stimulus opens the one or more gaps by breaking the one or more nanotubes into two or more nanotube fragments. In another aspect, the first electrical stimulus opens the one or more gaps by exciting one or more phonon modes of one or more nanotubes in the nanotube article. One or more phonon modes can represent a thermal bottleneck. One or more phonon modes may be optical phonon modes. One or more nanotubes in a nanotube article can be selected to have a particular strong radial breathing mode or defect mode. In another aspect, the second electrical stimulus closes the one or more gaps by attracting the one or more nanotubes toward the one or more conductors. The second electrical stimulus can attract the one or more nanotubes toward the one or more conductors by generating an electrostatic attraction. the

In another aspect, a selectable memory cell includes a cell select transistor having a gate, a source, and a drain, wherein the gate is in electrical contact with one of a word line and a bit line, and the drain is in electrical contact with the other of the word line and a bit line. an electrical contact. The unit also includes a double-terminal switching device including a first conductive terminal, a second conductive terminal, and a nanotube article having at least one nanotube in permanent direct physical contact with each of the first and second conductive terminals. The first conductive terminal is in electrical contact with the source of the cell select transistor, and the second conductive terminal is in electrical contact with the program/erase/read line. The cell also includes memory operating circuitry in electrical communication with word lines, bit lines, and lines for performing program functions, erase functions, or read functions. The memory operating circuit is capable of applying a select signal on a word line to select the cell and an erase signal on a line for performing a program function, an erase function or a read function to switch the device between the first and second conductive terminals. The resistance changes from relatively low resistance to relatively high resistance. The memory operation circuit is also capable of applying a select signal on a word line to select the cell and a program signal on a line for performing a program function, an erase function or a read function to switch the device between the first and second conductive terminals. The resistance changes from relatively high resistance to relatively low resistance. A relatively high resistance between the first and second conductive terminals corresponds to a first information state of the memory cell, and a relatively high resistance between the first and second conductive elements corresponds to a second information state of the memory cell. The first and second information states may be non-volatile. the

In another aspect, the memory operating circuitry applies a select signal on a word line to select the cell and a read signal on a program/erase/read line to determine the information state of the memory cell. Determining the information state of a memory cell may not change the state of the memory cell. In another aspect, multiple selectable memory cells can be connected to lines for performing program functions, erase functions, or read functions. the

In another aspect, a reprogrammable two-terminal fuse/antifuse device includes a first conductor, a second conductor spaced apart from the first conductor, and a second conductor having a plurality of nanotubes connected to the first conductor. The nanotube element is in permanent direct physical contact with each of the second conductors. The nanotube element includes a nanotube density selected to open an electrical connection between the first and second conductors and create the A high resistance state of the nanotube article to form a first device state. The nanotube element is also capable of closing an electrical connection between the first and second conductors and producing a low resistance state of the nanotube article in response to a second threshold voltage across the first and second conductors to form a first Second device status. The device can be a crosspoint switch. The first and second device states may be non-volatile. the

In another aspect, a reprogrammable interconnect between the plurality of wiring layers includes a first conductive terminal and a plurality of wiring layers, each wiring layer including a wiring layer conductive terminal. The interconnect also includes a stimulus circuit in electrical communication with the first conductive terminal and each wiring layer conductive terminal. The interconnect also includes a nanotube article having a plurality of nanotubes. The nanotube article is arranged in permanent direct physical contact with the first conductive terminal and in permanent direct physical contact with each wiring layer conductive terminal. The stimulation circuit is configured to create a first voltage difference between the first conductive terminal and a wiring layer conductive terminal of the plurality of wiring layer conductive terminals, thereby causing the nanotube article to move between the plurality of wiring layer conductive terminals. Interconnections are formed between each wiring layer, and the nanotube article has a relatively low resistance state. The stimulation circuit is configured to create a second voltage difference between the first conductive terminal and a wiring layer conductive terminal of the plurality of wiring layer conductive terminals, thereby causing the nanotube article to disconnect from the plurality of wiring layer conductive terminals. The interconnection between the two wiring layers, the nanotube article has a relatively high resistance state. In another aspect, the stimulus circuit disconnects all interconnections in response to safety concerns. the

In another aspect, a method of fabricating a two-terminal memory device includes providing a first conductive terminal and providing a second conductive terminal spaced apart from the first conductive terminal. The method also includes providing a stimulation circuit in electrical communication with at least one of the first and second conductive terminals. The method also includes providing a nanotube article comprising at least one nanotube. The nanotube article overlaps at least a portion of at least one of the first and second conductive terminals to a predetermined extent. The device response is related to a predetermined degree of overlap between the nanotube article and at least one of the first and second conductive terminals. the

The predetermined degree of overlap may be determined by a timed isotropic etch process. The predetermined degree of overlap can be determined by a directional etching process. The predetermined degree of overlap may be determined by the thickness of the sacrificial film. The predetermined degree of overlap may be determined by the thickness of at least one of the first and second conductive terminals. the

In another aspect, the method includes fabricating a second memory device whose structure is a mirror image of the two-terminal memory device structure. the

Brief description of the drawings

In the attached picture,

Figure 1A shows a cross-sectional view of an exemplary embodiment of the invention;

Figure 1B shows a cross-sectional view of an exemplary embodiment of the invention;

2A-I are SEM micrographs of structures according to certain embodiments of the invention;

3A-E show cross-sectional views of structures according to some embodiments of the invention;

Figure 4 is a cross-sectional view of a structure according to some embodiments of the present invention;

Figure 5 is a cross-sectional view of a structure according to some embodiments of the present invention;

Figure 6 is a cross-sectional view of a structure according to some embodiments of the present invention;

Figure 7 is a flow chart illustrating a general fabrication process according to some embodiments of the present invention;

8A-F illustrate cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

9A-C illustrate cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

Figures 10A-I illustrate cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

11A-C show cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

12A, B and 13 show cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

14A-J show cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

15A-N illustrate cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

16A-L illustrate cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

17A-M illustrate cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

18 is a flow diagram illustrating switch operability verification using read, erase, and program cycles in accordance with certain embodiments of the invention;

Figure 19 is a flowchart illustrating an erase cycle according to some embodiments of the present invention;

Figure 20 is a graph showing current and voltage erase characteristics of devices according to certain embodiments of the present invention;

Figure 21 is a flowchart illustrating a programming loop according to some embodiments of the present invention;

22A and 22B are graphs showing read, erase and program current versus voltage characteristics and resistance characteristics, respectively, of devices according to certain embodiments of the present invention;

23A-E, 24A-E and 25A-E show cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

Figure 26 is a cross-sectional view of a structure according to some embodiments of the invention;

Figure 27 is a cross-sectional view of a structure according to some embodiments of the invention;

Figure 28 is a cross-sectional view of a structure according to some embodiments of the invention;

Figure 29 is a cross-sectional view of a structure according to an aspect of the present invention;

Figure 30A and 30B show the schematic diagram of prior art structure;

Figure 31 shows a cross-section of a device according to some embodiments of the invention;

32A and 32B show schematic diagrams according to some embodiments of the present invention;

33A-G illustrate cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

34A-E illustrate cross-sectional views of structures created in fabrication steps according to certain embodiments of the invention;

35 and 36 are plan views of structures according to some embodiments of the invention. the

A detailed description

Preferred embodiments of the present invention provide two-terminal nanotube switches and devices using these switches. Generally, the nanotube element or article overlaps at least a portion of each of the two terminals, such as a conductive element. Stimulation circuitry connected to one or both of the terminals applies an appropriate electrical stimulus, to which the nanotube element responds by changing the state of the switch. For example, the resistance of the electrical path between two terminals characterizes the state of the switch. A relatively higher resistance path corresponds to the "open" or OFF state of the switch, while a relatively lower resistance path corresponds to the "closed" or ON state of the switch. Both states are nonvolatile. The stimulus circuit can non-destructively read out (NDRO) the state of the switch and repeatedly change the switch state (eg, resistance). the

The inventors believe that the ability to change a switch between two states is related to the relationship between the thermal and electrical characteristics of the switch. Specifically, the inventors believe that the performance of the switch is related to the relationship between the current passing through the nanotube element and the dissipation of heat out of the nanotube element. Desirably, to turn the switch into the "on" state, a stimulus circuit applies a stimulus in the nanotube element that the inventors believe is sufficient to cause overheating, while the switch is designed to limit the heat induced by the current that can flow out of the nanotube element feature. The inventors believe this overheats the nanotube element, breaking the conductive path in the switch and creating an "on" state. In other words, the inventors believe that the thermal and electrical management of the switch enhances the heat build-up in the nanotube element, allowing the "on" state to form. In certain embodiments, thermal and electrical management can be accomplished by overlapping the nanotube article with at least one of two terminals, such as conductive elements, in a predetermined controlled manner. For example, in certain embodiments, the nanotube element overlaps at least one of the two terminals by a prescribed geometry, such as a controlled overlap length of a preferred length. Then, it is difficult for heat to flow from the nanotube element into the terminal, but the contact length is long enough that current flows well from the terminal into the nanotube element. In some embodiments, thermal and electrical management is achieved by making switches from materials that dissipate heat poorly. For example, the switch could be passivated with a layer of lower thermal conductivity, which helps keep heat out of the nanotube element. Alternatively, the terminals may be made of a material that is relatively good at conducting electricity and relatively poor at conducting heat. Other designs and materials for thermal and electrical management of the switch are contemplated. It should be noted that although switch resistance changes induced by electrical stimulation have been repeatedly observed, the reasons for these resistance changes are still considered from a theoretical and experimental point of view. As of the filing date, the inventors believe that the thermal effects described herein cause or contribute to the observed behavior. Other effects may also cause or contribute to the observed behavior. the

The switch can be fabricated using methods that are easily integrated into existing semiconductor fabrication methods, as described in detail below. Several methods are now described that allow the fabrication of overlaps of specified geometries between nanotube articles or elements and terminals. the

Because the switch can be controllably switched between two non-volatile states, and because the fabrication of the switch can be integrated into existing semiconductor fabrication methods, the switch can be used in many applications. For example, the switch can be implemented in non-volatile random access memory (NRAM) arrays, reprogrammable fuse/antifuse devices, and reprogrammable wiring applications. the

First, an embodiment of a nanotube-based non-volatile memory device/switch is shown and its various components are described. Next, a method of fabricating a switching element is shown. Describes the test method when fabricating switching elements. Finally, embodiments using nanofabric-based non-volatile components, such as memory arrays, fuse/anti-fuse devices, and reprogrammable wiring, and methods of making them are shown. the

2-terminal nanotube switch

FIG. 1A shows a cross-sectional view of a 2-terminal nanotube switch (2-TNS) 10 . The nanotube element 25 is placed on a substrate 35 comprising an insulator layer 30 . The nanotube element 25 at least partially overlaps two terminals, for example the conductive elements 15 and 20 , deposited directly on the nanotube element 25 . the

In this embodiment, nanotube elements 25 may be patterned in defined areas either before or after deposition of conductive elements 15 and 20. the

Conductive elements 15 and 20 are in contact with stimulation circuit 100 . Stimulation circuit 100 electrically stimulates at least one of conductive elements 15 and 20 , which changes the state of switch 10 . Specifically, nanotube element 25 responds to the stimulus by changing the resistance of switch 10 between conductive elements 15 and 20; the relative value of the resistance corresponds to the switch state. For example, if stimulation circuit 100 applies a relatively high voltage and a relatively high current across conductive elements 15 and 20, nanotube element 25 responds by changing the switch resistance between conductive elements 15 and 20 to a relatively high resistance. respond. This corresponds to the "erased" state of the device, where conduction between conductive elements 15 and 20 is relatively poor. For example, if stimulation circuit 100 applies a relatively low voltage and a relatively low current across conductive elements 15 and 20, nanotube element 25 changes the resistance of the switch between conductive elements 15 and 20 to a relatively low resistance to respond. This corresponds to a "programmed" state of the device in which conduction between conductive elements 15 and 20 is relatively good, even close to ohmic. In general, the high and low resistance values are preferably separated by at least an order of magnitude. Example voltages, currents, and resistances for the "program" and "erase" switch states of certain embodiments of two-terminal nanotube switches are described in more detail below. the

Conductive elements 15 and 20 are preferably made of a conductive material and may be made of the same or different materials depending on the desired performance characteristics of switch 10 . For example, conductive elements 15 and 20 may be made of metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and other suitable metals and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And TiSi _x conductive nitride, oxide or silicide. Other types of conductive or semiconducting materials may also be used. Conductive elements 15 and 20 typically have a thickness in the range of, for example, 5-500 nm. In this embodiment, conductive elements 15 and 20 are preferably spaced about 160 nm apart. The spacing can be as small or as large as the process design allows, eg from 5 nm to 1 micron, depending on the desired characteristics of the switch 10 . Preferably, the spacing is less than about 250nm.

A preferred method of making a complete overlap between the nanotube element and the terminal or conductive element follows that described in the patent publications and issued patents listed above and commonly assigned to the assignee of the present application, or in current electronics industry practice Known techniques used. A preferred method of making partial overlap of a controlled overlap length between nanotube elements and terminals or conductive elements is described in detail below. the

The insulator 30 can be made of SiO ₂ , SiN, Al ₂ O ₃ , BeO, polyimide or other suitable insulating materials, and has a thickness in the range of 2-500 nm, for example. The insulator 30 is supported by a substrate 35 made of, for example, silicon. Substrate 35 may also be a composite of semiconductors, insulators, and/or metals connected to conductive elements 15 and 20 to provide electrical signals to nonvolatile 2-terminal nanotube switch (2-NTS) 10 . In some embodiments, substrate 35 may be the same material as insulator 30, such as quartz. In general, substrate 35 may be any material that accepts nanotube deposition by spin coating, but is preferably a material selected from the group consisting of thermal oxides or nitrides, including but not limited to Silicon oxide, silicon nitride, aluminum oxide on silicon; or any combination of the following on silicon or silicon dioxide: aluminum, molybdenum, iron, titanium, platinum, and aluminum oxide; or any other substrate used in the semiconductor industry end.

In certain embodiments, nanotube element 25 is a structure of entangled carbon nanotubes (also referred to as a nanofabric). Methods of making nanotube elements and nanostructures are well known and described in the incorporated patent references. In certain embodiments, the nanotube element or structure is porous, and material from conductive elements 15 and/or 20 fills at least some of the pores in the nanotube element. In certain embodiments, nanotube elements 25 include single-walled nanotubes (SWNTs) and/or multi-walled nanotubes (MWNTs). In certain preferred embodiments, nanotube elements 25 comprise double-walled nanotubes (DWNTs). In certain preferred embodiments, nanotube element 25 includes one or more nanotube bundles. In certain preferred embodiments, nanotube element 25 comprises one or more DWNT bundles. In certain embodiments, nanotube elements 25 include SWNTs, MWNTs, nanotube bundles, and mostly DWNTs. In certain embodiments, nanotube element 25 comprises a single nanotube. the

Certain nanotubes made by certain methods are preferred for use with 2-TNS 10. For example, nanotubes made by CVD processes are preferred, and they tend to consistently exhibit the switching behavior described herein. the

FIG. 2A shows a SEM image of an example SWNT nanostructure 50 made by a spin-on method of substantially single-layer entangled nanotubes. Although Figure 2A shows a single-layer nanofabric, other suitable techniques can be used to fabricate multi-layer nanofabric. That is, preferred embodiments do not require that the nanostructures have to be single-walled nanotubes. For example, nanostructures can include nanotube bundles and/or single nanotubes. Although FIG. 2A shows a nanofabric with randomly oriented nanotubes, aligned or near-aligned nanotubes can also be used. Furthermore, the nanotubes may be metallic and/or semiconducting, as described in the incorporated patent references. In general, nanostructures need not include carbon nanotubes at all, but are simply made of one material and have a form that exhibits non-volatile switching behavior as described herein, such as silicon nanowire-based structures, Other nanowires or quantum dots. the

The nanostructures shown in Figure 2A are preferably fabricated on horizontal surfaces. In general, structures are conformal or can be oriented at various angles without limitation. Figure 2C is an SEM image of structure 90 with nanostructures 95 following an underlying step after deposition. These conformal properties of nanostructures can be used to fabricate vertically oriented 2-TNSs with enhanced size control and requiring smaller areas (eg, can be fabricated in greater density), as described further below. the

In certain embodiments, nanotube element 25 in FIG. 1A is a SWNT nanostructure having a thickness between 0.5-5 nm. In other embodiments, nanotube elements 25 in FIG. 1A are MWNT nanostructures with a thickness of 5-20 nm. SWNT diameters may be in the range of, for example, 0.5-1.5 nm. A single nanotube may have a length of 0.3-4 μm and thus may be long enough to span the spacing between conductive elements 15 and 20 . Nanotubes may also be smaller than the distance between conductive elements 15 and 20, but contact (or "form a network") with other nanotubes to span the spacing between these elements. Reference is made to US Patent No. 6,706,402 entitled "Nanotube Films and Articles" for details on conductive articles and networks formed from nanotubes. In general, the nanotube density should be high enough to ensure that at least one nanotube or network of nanotubes spans the entire distance between conductive elements 15 and 20 . Other preferred features of the nanotubes are described herein. the

The two-terminal nanotube switch 10 shown in FIG. 1A has a path between conductive elements 15 and 20 that can be in one of two states. One state may be characterized by a path having a relatively high resistance, R _HIGH , between conductive elements 15 and 20 . In this "on", "erased" or OFF state, it is generally more difficult for current to flow between conductive elements 15 and 20 . Another state may be characterized by a path having a relatively low resistance, R _LOW , between conductive elements 15 and 20 . In this "closed", "programmed" or ON state, current generally readily flows between conductive elements 15 and 20 .

Switch 10 is usually made in a low resistance state. The resistance of this state depends on the properties of the nanotube element 25 and the properties of the conductive elements 15 and 20 . In general, the intrinsic resistance of nanotube elements 25 and nanostructures can be controlled in the range of 100-100,000 ohms per square, such as measured by four-point probe measurements. Films with a resistance of 1,000-10,000 ohms per square typically have a density of 250-500 nanotubes per square micron. In certain embodiments, nanotube element 25 preferably has, for example, 1-30 nanotubes. In certain embodiments, the nanotube element preferably has 5-20 nanotubes. the

The total resistance of switch 10 between conductive elements 15 and 20 in the "closed" state consists of the contact resistance of each overlapping region in series plus the intrinsic series resistance of the nanotubes divided by the number of nanotube paths between elements 15 and 20 (could be a single nanotube and/or a network of nanotubes). In certain preferred embodiments, the overall fabrication resistance of 2-TNS 10 is typically in the range of 10kΩ-40kΩ. In other preferred embodiments, the switch can be designed to have a resistance less than 100Ω or greater than 100kΩ. A description of the resistance of nanotubes can be found in the following citation: "A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VL SI Technologies" by N. Srivastava and K. Banerjee. Comparative Scaling Analysis of Tube Interconnection), Proceedings of the 21stInternational VLSI Multilevel Interconnect Conference (VMIC) (Proceedings of the 21st International VLSI Multilevel Interconnection Conference), September 29-October 2, 1004, Wikoloa, HI , pp. 393-398. the

In general, the performance of the device does not vary strongly with the nanotube density in the nanotube element. For example, the sheet resistance of the nanostructures can vary by at least a factor of 10 and the device still works well. In preferred embodiments, the sheet resistance of the nanostructures is as low as approximately 1 kΩ. In certain embodiments, the resistance of the nanostructures is estimated after fabrication, and if the resistance is found to be greater than about 1 kΩ, additional nanostructures are deposited at a density sufficient to reduce the resistance below about 1 kΩ. the

Stimulation circuit 100 applies a suitable electrical stimulus to at least one of conductive elements 15 and 20 to switch switch 2 - TNS 10 between a low resistance and a high resistance state. In general, appropriate electrical stimulation of the 2-TNS 10 depends on the particular implementation of the switch. For example, in some embodiments, stimulation circuit 100 may bring switch 10 into a high resistance "open" state by applying a relatively high voltage bias across conductive elements 15 and 20 with an unrestricted current. In certain embodiments, the voltage is about 8-10V, or about 5-8V or 3-5V or lower. Sometimes the electrical stimulation is a voltage pulse, and sometimes a series of pulses is used to switch the 2-TNS 10 into the "on" state, eg a series of one or more pulses between 1-5V. The duration of one or more pulses may also be varied to switch the 2-TNS 10 into an "on" state. It has been found in certain embodiments that allowing a relatively high current, eg, greater than 5 μA, to flow through the switch enhances its ability to switch to the "on" state. In certain embodiments, the stimulation circuit 100 must apply stimulation above a threshold voltage and/or current to switch the 2-TNS 10 into an "on" state. In general, any electrical stimulus sufficient to switch the 2-TNS 10 to a relatively higher resistance state can be used. In certain embodiments, this state may be characterized by a resistance R _HIGH on the order of 1 GΩ or more. In general, this state is also considered to be characterized by a relatively low impedance.

In certain embodiments, stimulation circuit 100 may bring switch 10 into a low-resistance “closed” state by applying a relative voltage bias across conductive elements 15 and 20 . In certain embodiments, a voltage of about 3-5V, or about 1-3V or less switches switch 2-TNS to a low resistance state. In certain embodiments, the electrical stimulation required to switch the 2-TNS 10 to the "closed" state depends in part on the electrical stimulation used to switch the 2-TNS 10 to the "open" state. For example, if a relatively high voltage bias is used to "open" the switch, a relatively high voltage bias is required to "close" the switch. For example, if a pulse of 8-10V is used to "open" the switch, a pulse of 3-5V is required to "close" the switch. If a pulse of 3-5V is used to "open" the switch, a pulse of 1-2V is required to "close" the switch. In general, the stimulus used to "open" and "close" the switch can change each time, although the "close" stimulus depends in part on the "open" stimulus. In other words, even if for example the switch is "opened" with a pulse of 8-10V and then "closed" with a pulse of 3-5V, it can then be "opened" again with a pulse of 3-5V and "closed" with a pulse of 1-2V. switch. Using a larger voltage to open the switch will result in a larger voltage being required to close the switch. Although the examples presented herein use an "open" voltage that is higher than a "closed" voltage, in certain embodiments, the "closed" voltage can be higher than the "open" voltage. The difference between closing and opening operations is more dependent on current control than voltage magnitude. As an example, a 6V erase pulse with no current limitation can be used to open the switch, followed by an 8V program pulse with a current capability (cap) of 1 μΑ used to close the switch. the

Sometimes the electrical stimulation is a voltage pulse, and sometimes a series of pulses is used to switch the 2-TNS 10 to the "closed" state, such as a series of one or more pulses between 1-5V. The duration of one or more pulses can also be varied to switch the 2-TNS 10 to the "closed" state. In some embodiments, the same voltage level may be used to "close" and "open" the switch, but the waveforms of the two stimuli are different. For example, a series of pulses of a given voltage may be used to "open" the switch, and a single pulse of the same or similar voltage may be used to "close" the switch. Or for example, a long pulse of a given voltage may be used to "open" the switch, and a short pulse of the same or similar voltage may be used to "close" the switch. Using these types of waveforms simplifies the design of the 2-TNS 10 because it is no longer necessary to apply multiple voltages to the switch. In a particular embodiment of the invention, this phenomenon occurs when the current is limited during programming but not during erasing. the

In some cases it has also been found that limiting the current flowing through the switch enhances its ability to switch to the "closed" state. For example, adding a 1 MΩ inline resistor between the stimulation circuit 100 and one of the conductive elements 15 and 20 to limit the current in the switch to less than 1000 nA increases the ability to switch the 2-TNS 10 to the "closed" state About 40%. Another example is an active circuit that can limit current during a programming loop. In general, any electrical stimulus sufficient to switch the 2-TNS 10 to a relatively lower resistance state can be used. In certain embodiments, this state is characterized by a resistance _RLOW on the order of about 100 kΩ or less. In certain preferred embodiments, the resistance of the relatively higher resistance state is at least 10 times greater than the resistance of the relatively lower resistance state. In general, this state can also be considered to be characterized by a relatively low impedance. In certain preferred embodiments, the impedance of the relatively higher impedance state is at least 10 times greater than the impedance of the relatively lower impedance state.

Both states are non-volatile, ie they do not change until the stimulation circuit 100 applies another appropriate electrical stimulus to at least one of the conductive elements 15 and 20, and the state is maintained despite removal of power from the circuit. The stimulation circuit 100 can also determine the state of the 2-TNS 10 through a non-destructive readout operation (NDRO). For example, stimulation circuit 100 may place a lower measurement voltage across conductive elements 15 and 20 and measure the resistance R between the conductive elements. This resistance can be measured by measuring the current flowing between the conductive elements 15 and 20 and calculating the resistance R therefrom. The stimulus is sufficiently weak that it does not change the state of the device, such as a voltage bias of about 1-2V in certain embodiments. In general, R _HIGH is preferably at least 10 times R _LOW so that the stimulation circuit 100 can more easily detect this state.

The inventors believe that when the switch changes state, the conductive path in the switch undergoes a change that changes its ability to carry current. In other words, the inventors believe that the electrical relationship between one or more conductors along a conductive path changes due to changes in the physical relationship between the conductors. In the higher resistive state of 2-TNS 10, the inventors believe that there is an electrical separation or discontinuity between a sufficient number of conductors that sufficiently limits the path's ability to carry current. This may result from physical gaps formed between these elements in response to electrical stimulation by stimulation circuit 100 . In the lower resistance state of 2-TNS 10, the inventors believe that there is electrical contact or continuity between enough conductors to allow the path to carry current relatively well. This may result from closing a gap between one or more conductors in response to electrical stimulation of stimulation circuit 100 . the

The different conductors on the switch path include one or more individual nanotubes or nanosegments in nanoelement 25 and the two terminals 15 and 20 . Because one or more nanotubes in a nanotube element provide a nanopath between the two terminals, there is a gap between the nanotubes and the terminals and/or between the nanotubes and/or within each individual nanotube itself or between segments. A change in the physical relationship of the switch may cause a change in the state of the switch. For example, a nanotube may be in contact with one or more of the terminals in a low resistance state, while losing physical contact with one or more of the terminals in a high resistance state. Or for example, an electrical network of nanotubes within a nanotube element may contact each other in a low resistance state, but be separated by a gap in a high resistance state. Or for example, individual nanotubes may be physically continuous in a low resistance state, while a physical gap is formed between the nanotubes in a high resistance state. The two resulting nanotube sheets or fragments can each be considered a (shorter) nanotube. In general, the physical relationship between a nanotube and one or more conductors in a double-ended nanotube switch can vary. The inventors believe that, depending on the particular implementation, changes in one or more particular kinds of physical relationships, such as nanotube-to-terminal, network nanotube-to-network nanotube, or within a nanotube, may control the switching behavior of the switch. This phenomenon can vary for different switch design rules. the

The inventors believe that during "on" stimulation of the stimulation circuit 100, physical changes in the conductive pathways in the 2-TNS 10 may result from thermal effects in the conductors. Specifically, the inventors believe that overheating caused by a threshold voltage and/or current density occurring in at least a portion of the nanotubes of nanotube element 25 can cause the nanotubes in the element to contact one or more conductors in the path. Physically separated to form a gap. For example, it has been observed that a threshold current of about 20 microamperes can physically break an individual nanotube into two distinct segments separated by a gap. In certain embodiments, the gap is about 1-2 nm, and in other embodiments, the gap is less than about 1 nm or greater than about 2 nm. This physical gap prevents current from flowing through the nanotube, providing an "open" path characterized by high resistance. If nanotube element 25 is a nanotube structure, the current in each individual nanotube is generally a function of the total current and the number or density of nanotubes, illustrating that in some cases many nanotubes can be combined to form an electrical current. path facts. The inventors believe that, in certain embodiments, these nanotubes can overheat and rupture by applying a total current sufficient to cause the current in one or more individual nanotubes to exceed about 20 microamperes. Because the nanotubes are no longer carrying electrical current, the current in the unbroken nanotubes increases, causing one or more of the nanotubes to overheat and break. As a result, soon most or all of the nanotubes carrying the current overheat and break, creating an "open" path or "erased" state in the 2-TNS 10 characterized by a relatively high resistance. Figure 2B is a photomicrograph of a nanofabric switch (see, for example, arrows) emerging to show all or most of the break in the conductive nanotube pathway. the

Similarly, the inventors believe that overheating caused by threshold voltage and/or current density applied to the nanotubes can physically break contact between one or more nanotubes within the nanotube electrical network. Although the specific threshold voltage and/or current density required to separate two nanotubes within 2-TNS 10 from each other is not currently identified, it is possible that this voltage and/or current density is comparable to that required to disconnect individual nanotubes. similar or lower. Furthermore, overheating caused by threshold voltage and/or current density may physically break contact between one or more nanotubes in nanotube element 25 and one or more of conductor elements 15 and 20 . the

The inventors believe that, in general, 2-TNS 10 can suffer from physical fracture at locations prone to overheating, such as weak thermal links or thermal bottlenecks along the path of nanotube element 25 disposed between conductive elements 15 and 20. The inventors believe that if a path breaks at a given location, the current density can rise in all remaining paths, which can cause overheating and breaking elsewhere. Consequently, soon most or all of the paths carrying current can overheat and break, creating an "open" path or "erased" state in the 2-TNS 10 characterized by relatively high resistance. the

The inventors believe that "closed" stimulation of the stimulation circuit 100 results in electrostatic attraction, which can create a conductive path in the 2-TNS 10. This attraction can pull or move the nanotube and conductor into contact with each other. As noted above, it has been found that the electrical stimulation required to switch the 2-TNS 10 to the "closed" state is at least in part related to the electrical stimulation previously used to switch the 2-TNS 10 to the "open" state. The inventors believe that this effect may be related to the size of the single gap or gaps in the path between the nanotube and the conductor that result in a specific "opening" stimulus. For example, a relatively low "on" voltage can result in relatively little overheating, creating a relatively small gap between the nanotube and the conductor. A relatively low "turn-on" voltage is then required to sufficiently attract the nanotube and conductor across these small gaps and bring them into contact with each other. Or for example, a relatively high "open" voltage can cause relatively large overheating, creating a relatively large gap between the nanotube and the conductor, and then a relatively high "close" voltage is required to bring the nanotube to the conductor. The conductors are attracted across these larger gaps sufficiently to bring them into contact with each other. A "turn-on" voltage that is not high enough will not attract the nanotube and conductor with sufficient strength to bring them into contact. the

The inventors believe that an undesirably high "closed" voltage, such as 8-10V in some embodiments, may be high enough to attract the nanotubes to the conductor. However, once the nanotubes are in contact with the conductor, current that begins to flow through the connection can cause a localized temperature jump at the connection. This can overheat the connection and cause the nanotubes to separate from the conductor again. This connecting and disconnecting process is repeated until the "closed" voltage is removed. In this case, the switch fails because it cannot be programmed or "closed". However, the switch can be closed by a slightly lower "close" voltage. Undesirably high "turn-on" voltages, such as about 15-16 V in certain embodiments, can lead to overheating, causing extremely large gaps, such as 30-40 nm, between the nanotubes and the conductor. The gap is so large that there is not a high enough "close" voltage to attract the nanotube and conductor sufficiently to bring them into contact with each other. In this case, the switch fails because it is no longer programmable. The switch can suffer irreversible damage because there is no stimulus sufficient to bring the nanotubes into contact with the conductor. the

The inventors believe that an alternative mechanism by which an electrical path may be closed by stimulation circuit 100 is due to an electrical arc that may occur across a gap formed by a previous "open" operation. The electrons and/or the resulting high temperature can pull material (near the gap) into the gap to re-establish a connected electrical path. the

The inventors have found that if 2-TNS 10 is not passivated and stimulated in an inert gas, the intensity of the stimulus required to "close" the switch is related to the stimulus used to "open" the switch. In other words, the size of the gap can be related to a "closed" stimulus in an inert gas. The inventors have also found that if 2-TNS 10 is not passivated and stimulated in a vacuum, the stimulus intensity required to "close" the switch remains roughly constant within about 10%, regardless of the amount of stimulation used to "open" the switch. How exciting. In other words, the size of the gap was independent or weakly correlated with the stimulus in vacuum. The inventors believe that the vacuum allows heat to build up in the nanotube elements more rapidly than it would in a gas, possibly because heat leaks from the nanotube elements into the gas. the

The inventors believe that the overheating resulting from the occurrence of threshold voltages and/or currents in 2-TNS 10 (which can break contact between the nanotube and conductor) may be related to thermally induced lattice vibrations or phonons in the nanotube . Specifically, the inventors believe that overheating excites one or more specific phonon modes in the nanotube, and that this phonon mode breaks the contact between the nanotube and the conductor. In general, heat excites a spectrum of acoustic and optical phonons in materials such as nanotubes. Acoustic phonon modes can transport heat, whereas optical phonon modes generally cannot be used to transport heat. Certain optical phonon modes can couple to acoustic phonon modes, allowing heat to flow from the optical mode into the acoustic mode, where it transports heat. However, if heat does not flow easily from the optical mode into the acoustic mode, for example cannot be transported through the nanotube, then a rapid heat build-up or thermal bottleneck can occur in the nanotube. This can result in overheating sufficient to break contact between the nanotube and conductor. the

The inventors have obtained Raman spectra of the different classes of nanotubes that have been tested in 2-TNS 10, and have observed that preferred nanotubes, such as nanotubes that consistently exhibit the switching behavior described herein, generally have A distinct optical phonon mode corresponding to the nanotube radial breathing mode. The inventors believe that this breathing pattern may be related to the on-off behavior of 2-TNS 10. For example, this mode can act as a thermal bottleneck, trapping heat in the nanotubes. This mode can make nanotubes or contacts between nanotubes and conductors more susceptible to breakdown by threshold voltage and/or current density than other kinds of nanotubes that do not exhibit this mode. The breathing mode can also be coupled to modes associated with fracture of the nanotube or contact between the nanotube and the conductor. In other words, the breathing pattern itself may not be directly related to possible gap formation in the switch, but may be related to the phenomenon of gap formation in the switch. the

Preferred nanotubes may also have other common phonon modes associated with their ability to break contact with a conductor. For example, in certain nanotubes, there may be one or more defect modes or one or more modes that may be strongly coupled to the bonding mode between the nanotube and the conductor. In general, one or more optical or acoustic phonon modes can contribute to breaking paths in 2-TNS 10, e.g. "opening" a switch can be phonon induced. Different kinds of nanotubes, eg, nanotubes made by different methods or using different process conditions and/or nanotubes with different numbers of walls, may have different phonon spectra. Certain species may have phonon modes or other characteristics that may cause or enhance the fragility of the contact between the nanotube and conductor. For example, having more than one wall can enhance the breakability of the contact between the nanotube and the conductor. the

The inventors believe that the switching behavior of 2-TNS 10 can be derived from the key relationship of the thermal and electrical properties of the components of the switch. The inventors believe that the two-terminal nanotube switch preferably can provide a sufficiently high voltage and/or current to the nanotube element while allowing sufficient heat to build up in the nanotube element to disconnect one or more nanotubes from the conductor contact between. Preferably, the opening is small enough that it can be reprogrammably closed. By managing this relationship, better implementations with enhanced performance can be designed and produced. These objectives can be achieved through electrical and/or thermal engineering or management of the device. the

The purpose of providing sufficient electrical stimulation to the nanotube elements can be achieved by techniques well known in the art. In particular, the conductive elements preferably conduct electrical current relatively well into the nanoelements. The conductive element may preferably be a relatively good electrical conductor. For example, the conductive elements may be metal or other types of conductive materials. Preferably, the conductive elements are fabricated by processes and materials that are easily integrated into or already used in existing manufacturing methods. In at least the "closed" state, one or both of the conductive elements are preferably in near-ohmic contact with the nanotube element. It is known to make near-ohmic contacts. the

The goal of potentially allowing sufficient heat to build up in the nanotube element to break contact between the nanotube and conductor in response to an "open" stimulus is more challenging. For example, many materials that can be used for conductive elements that conduct electricity well also conduct heat well. For example, metals generally conduct electricity well and are suitable for making many embodiments of 2-TNS, and generally conduct heat well as well. For example, a thermally well-conducting material that is a good thermal conductor can draw enough heat from the nanotube element that the element does not overheat in response to an "open" stimulus. Alternatively, the nanotube elements only overheat in response to undesired large "open" stimuli. Several embodiments are contemplated in order to make 2-TNS that responds to sufficient (but not undesired) "turn-on" stimuli to enable heat accumulation in nanotube elements. the

In certain preferred embodiments, the nanotubes themselves can be thermally engineered by selecting the nanotubes to have characteristics that are particularly prone to fracture in response to an "open" stimulus. For example, as described above, certain nanotubes can be selected to have certain modes that accumulate heat or couple to other modes that break contact between the nanotube and the conductor. Nanotubes can have defects that are prone to being disconnected by overheating. In certain embodiments, the nanotubes can be pretreated to introduce defects prior to deposition. the

In certain preferred embodiments, conductive elements may be thermally engineered by manufacturing from a material (or materials) that conducts electricity relatively well but conducts heat relatively poorly. For example, the material may have relatively low thermal conductivity, relatively high heat capacity, and/or relatively low thermal diffusion constant. For example, in certain embodiments, a doped semiconductor is capable of providing a sufficiently high "turn-on" stimulus to the nanotube element and absorbing relatively low heat from the nanotube element. Other types of materials with this feature are contemplated, such as conducting polymers. Preferably, the conductive element provides sufficient electrical stimulation to "turn on" the switch without significantly impeding heat buildup in the nanotube element. the

In addition, in some preferred embodiments, the distance between two conductive elements is relatively small, such as less than 250 nm. It has been observed that switches with relatively far apart conductor elements, and thus relatively long nanotube elements spanning the distance between them, tend to require relatively large "erase" stimuli in order to turn the device into "Open" state. Switches with relatively larger spacing between conductive elements tend to have higher resistance between conductive elements, and thus lower current density in the nanotube elements for a given erase voltage. the

In general, nanotube elements can also be in physical contact with other materials in 2-TNS besides conductors, such as the underlying insulator and the upper passivation layer. These materials can draw heat from the nanotube elements. In certain preferred embodiments, the one or more materials in contact with the nanotube elements can be selected to be relatively poor thermal conductors, eg, have sufficiently high heat capacity and/or sufficiently low thermal conductivity. In other words, these materials conduct heat poorly and can be good thermal insulators. This is beneficial because nanotube elements are more prone to overheating if the materials in contact with the element draw little heat from the element. For example, the inventors have discovered that, among other benefits, preferably covering the nanotube elements with a passivation layer can significantly reduce the level of stimulation required to "turn on" 2-TNS. By preferably including a passivation layer on the switch, in one embodiment, the stimulus required to "turn on" the switch is reduced in half. In general, the inventors believe that the material or materials in contact with the nanotube element are preferably relatively poor thermal conductors, which contributes to the accumulation of heat in the nanotube element. the

The inventors believe that a preferred passivation layer is also beneficial for isolating 2-TNS components such as nanotube elements and/or conductive elements from the environment. For example, moisture in the air or water attached to a nanotube element can corrode the element at high temperatures. If an "on" stimulus is applied to bare 2-TNS, overheating can occur in the nanotube element at a temperature high enough that any water on the element is sufficient to damage the element so that it cannot conduct electrical current well. This "opens" the 2-TNS, but then the switch cannot "close" because the conductive path provided by the nanotube elements is irreversibly broken. If instead the 2-TNS is passivated with a better passivation layer, the switch is isolated from damaging water and can be "opened" and "closed" repeatedly. Preferably, any water adhering to the 2-TNS is removed before depositing the passivation layer; otherwise, the layer can easily trap water near the switch. The passivation layer is also preferably non-dehumidifying and impermeable to water. It is also preferred not to use a high power plasma that would damage the nanotube elements to make the passivation layer. The passivation layer can be made of any suitable material known in the CMOS industry, including but not limited to: PVDF (polyvinylidene fluoride), PSG (phosphosilicate glass) oxide, Orion oxide (Orion oxide), LTO ( Planarized Low Temperature Oxide) Oxide, Sputtered Oxide or Nitride, Flowfill Oxide, ALD (Atomic Layer Deposition) Oxide, CVD (Chemical Vapor Deposition) Nitride. These materials can be used in combination with each other, i.e. a layer of PVDF or a blend of PVDF and other copolymers can be placed on top of the CNTs and _an ALD _AL2O3 layer can be used to cover this composite, but any high temperature polymerization without oxygen can be used as a passivation layer. In certain preferred embodiments, passivation materials such as PVDF can be mixed with other organic or dielectric materials and form copolymers such as PC7 to produce specific passivation properties such as extended lifetime and reliability.

Passivation of the NRAM device facilitates operation of the device in air at room temperature and acts as a protective layer in conjunction with the material stack on top of the NRAM device. Operation of unpassivated NRAM devices can typically be performed under an inert gas background such as argon, nitrogen or helium, or at elevated (above 125C) sample temperature to remove absorbed water from exposed nanotubes. Therefore, the requirement for a passivation film is usually twofold. First, passivation should form an effective moisture barrier to prevent the nanotubes from being exposed to moisture. Second, the passivation film should not interfere with the switching mechanism of the NRAM device. the

One method of passivation involves a cavity fabricated around the NRAM device to provide a sealed switching region. Both cavities around individual devices (device-level passivation) and cavities around the entire 22-device die (die-level passivation) have been implemented. However, the fabrication process flow is complex, requiring at least 2 additional photolithography steps and at least 2 additional etching steps. the

Another method of passivation involves depositing a suitable dielectric layer over the NRAM device. An example of this approach is the use of spin-coated polyvinylidene fluoride (PVDF) in direct contact with the NRAM device. PVDF is patterned as die-level (over the active area of the entire die) or device-level sheets (separate sheets covering individual devices). A suitable second dielectric passivation film such as alumina or silicon dioxide is then used to seal the PVDF and provide a robust passivation for NRAM operation. NRAM operation is thought to thermally decompose the upper PVDF, thus requiring a second passivation layer to seal the device. Since the die-level passivation is typically ~100 micron square sheets, this localized decomposition can lead to cracking of the second passivation, exposure of the NRAM device to air, and its subsequent failure. To avoid this failure of the second passivation film, the die-level passivated device was electrically "aged" by pulsing the device with 500 ns pulses typically from 4 V to 8 V in 0.5 V steps. This is believed to be a controlled decomposition of PVDF and prevents cracking of the upper second passivation film. After the burn-in process, the die-level passivated NRAM device works normally. Devices passivated with a device-grade PVDF coating and a second passivation film do not require this aging step and can be operated directly at operating voltage in air at room temperature. Through device-level passivation, PVDF is imaged into precise CNT structure shapes, typically 0.5 microns wide and 1-2 microns long. Such flakes are generally considered to be able to disintegrate without rendering the second passivation film ineffective. For a given defect density in the second passivation, on average, it is possible to have no defects on the footprint of a smaller device-level PVDF sheet than a larger die-level sheet. the

The inventors believe that, in certain preferred embodiments, the "on" stimulus applied by the stimulus circuit can be engineered so as to enhance heat build-up in the nanotube element. In one embodiment, applying a relatively large voltage to a switch is an example of engineering an "on" stimulus. In other embodiments, a series of pulses may be applied to the switch, and the pulses may be separated by timing faster than the time scale for heat transfer out of the nanotube element. The inventors believe that in this case the pulse itself need not be of large amplitude, but the total heat deposited by the pulse in the nanotube element may be sufficient to overheat and disconnect the element. the

The inventors believe that, in certain preferred embodiments, double-ended nanotube switches can be thermally engineered by designing them to have "hot spots" or thermal bottlenecks where one or more nanotubes Very prone to overheating. For example, as described in detail below, nanotube elements can be fabricated to partially overlap at least one conductor in a controlled geometric relationship (eg, a controlled overlap length). For example, by controlling the overlap length to be less than 100 nm or less than 50 nm, the amount of heat that the conductor can draw from the nanotube element can be reduced sufficiently to potentially allow the nanotube element to overheat rapidly at one or more locations. Conversely, increasing the overlap length can prevent overheating by dissipating heat from the nanotube element. the

For example, it has been observed that at least 10% more fabricated switches can be "opened" by limiting the overlap length to less than 50 nm compared to above 100 nm. Also, for embodiments having overlap lengths of less than 50 nm, the time required to "turn on" the switch can be reduced, suggesting or illustrating that the nanotube element can overheat more quickly in response to an "turn on" stimulus. For example, the "on" time of fabricated switches with an overlap length of less than 50 nm can be on the order of 100 ns, and the "on" time of switches with an overlap length of greater than 100 nm can be on the order of 1 millisecond or more. Engineered to provide faster switching speeds such as lns or faster. In general, arranging the nanotube element and one or more conductive elements in a specified geometric relationship is useful for managing the thermal relationship between the nanotubes and the conductive element. This or other arrangement can create a thermal bottleneck or "hot spot" in the 2-NTS, which can enhance the operation of the switch. the

In summary, in one or more embodiments, thermal and/or electrical engineering or management can be used to enhance the performance of two-terminal nanotube switches. One or more of the thermal and/or electrical engineering design techniques described herein can be used simultaneously in the design and fabrication of the preferred two-terminal nanotube switch. For example, switches can be made with controlled overlap lengths to reduce the heat drawn by the conductive elements from the nanotube elements, and can be further enhanced with a preferred passivation layer which in some cases can include a blend of copolymers. switch is passivated. the

It should be noted that although switch resistance changes due to electrical stimulation have been repeatedly observed, the origin of these resistance changes is still considered both theoretically and experimentally. At the time of filing, the inventors believe that thermal effects as described herein may cause or contribute to the observed behavior. Other effects may also cause or contribute to the observed behavior. the

Figure IB shows a cross-sectional view of a non-volatile 2-terminal nanotube switch (2-TNS) 10' in which thermal management is achieved by limiting the overlap between the nanotube element 25' and the conductive element 20'. The nanotube element 25' is disposed on a substrate 35' comprising an insulator layer 30'. The nanotube element 25' is arranged to at least partially overlap to a predetermined extent at least one of, for example, the terminals of the conductive elements 15' and 20', which terminals are deposited directly on the nanotube element 25'. the

In this embodiment, the nanotube elements 25' are patterned in an area that may be defined before or after the deposition of the conductive elements 15' and/or 20'. The conductive element 15' overlaps an entire terminal area of the nanotube element 25', forming a near-ohmic contact. At the opposite end of the nanotube element 25', at an overlap region 45', the conductive element 20' overlaps the nanotube element 25' by a controlled overlap length 40'. The controlled overlap length 40' may be, for example, in the range 1-150 nm, or in the range 15-50 nm. In a preferred embodiment, the controlled overlap length 40' is about 45 nm. The switch can be thermally and electrically managed to enhance heat build-up in the nanotube element by confining the overlapping nanotube element 25' and conductive element 20' making it more difficult for heat to flow from the nanotube element to the conductive element where the contact length is sufficiently long , making it easy for current to flow from the conductive element to the nanotube element. the

In one or more embodiments, one or more electrical characteristics of switch 10' are related to controlled overlap length 40'. For example, the time required to erase and/or program switch 10' is related to controlled overlap length 40' as described in more detail below. the

Figures 2D to 2I show top-view SEM images of several different embodiments of functional two-terminal nanotube switches made using materials, nanotube elements and methods according to certain embodiments described herein. In the embodiment shown in Fig. 2D, 2-TNS 60D is formed on an insulator layer 62D deposited on a silicon substrate (not visible in top view). Insulator 62D is about 20nm _SiO2 and serves as the bottom (back) gate. Conductive elements 70D and 75D corresponding to conductive elements 15' and 20', respectively, in FIG. 1B are palladium and have a thickness of about 100 nm. Conductive elements 70D and 75D each have a width of approximately 400 nm, and have a spacing 85D of approximately 150 nm.

In the image, nanotube element 65D, comprising several nanotubes, appears in the right half of the image as a bright gray line against a background of gray insulator 62D. Conductive element 70D overlaps a larger portion of nanotube element 65D, causing conductive element 70D to have a relatively rough texture in the image compared to the texture of conductive element 75D, which overlaps a limited portion of nanotube element 65C, as follows Describe in more detail. Conductive element 70D has striations indicated by region 55D, which is the area where the element is raised due to the underlying layer having nanotubes. It can also be seen that nanotube element 65D extends beyond the periphery of conductive element 70D. This structure does not affect device performance, but conveniently allows imaging and/or characterization of the exposed portion of nanotube element 65D. the

It can be seen that some of the nanotubes in nanotube element 65D span the distance 85D between conductive elements 70D and 75D. Conductive element 75D overlaps nanotube element 65D in region 80D by a controlled overlap length of about 17.4 nm, which corresponds to controlled overlap length 40' in Figure IB. Conductive elements 70D and 75D can be seen to have a white border, which is a charging artifact in the imaging process. The artifact masks a controlled overlap region 80D having substantially less than the artifact length. However, as further described, certain embodiments have overlapping regions that are large enough to be visible in SEM micrographs. the

The embodiment shown in Figure 2E has a similar structure to that of Figure 2D, with conductive elements 70E and 75E having similar dimensions to the elements in Figure 2D, but separated by a distance 85E of about 250 nm. This image is rotated 90 degrees relative to Figure 2D. Here, conductive element 75E overlaps nanotube element 65E by approximately 38.6 nm in region 80E. Although the differences in distances 80D and 80E and 65D and 65E are larger, the embodiments shown in Figures 2D and 2E operate comparably. The embodiment shown in Figure 2F is similar to the embodiment shown in Figures 2D and 2E, but with conductive elements 70F and 75F separated by a distance of about 250 nm. Here, conductive element 75F overlaps nanotube element 65F by approximately 84.9 nm. The embodiment shown in Figure 2G is similar to that shown in Figures 2D-2F, but with conductive elements 70G and 75G separated by a distance of about 150 nm. Here, conductive element 75G overlaps nanotube element 65G by approximately 90.5 nm. the

The embodiment shown in Figure 2G is similar to the embodiment shown in Figures 2D-2G, except that conductive elements 70H and 75H are separated by a distance of about 150 nm. Here, conductive element 75G overlaps nanotube element 65H by approximately 104 nm. In this figure, conductive element 75H can be seen to have a rather roughened texture in the region 80H where element 75H overlaps nanotube element 65H. This texture is comparable to the region of conductive element 70H that overlaps a larger portion of nanotube element 65H, but region 80H is limited to 104 nm. The embodiment shown in Figure 2I has a similar structure to Figure 2H, but conductive element 75I overlaps nanotube element 65I by about 136 nm in region 80I. Here again, conductive element 75I can be seen to have a significantly roughened texture in region 80I compared to the remainder of the element that does not overlap nanotube element 65I. The roughened texture is due to the nanotubes underlying the element material 75I. the

All of the embodiments shown in Figures 2D-2I are functional switches in which thermal management is achieved by arranging the nanotube elements and conductive elements in a specified geometric relationship, such as a controlled overlap length. In certain embodiments, the controlled overlap length has been found to affect the yield of operational switches produced, eg, the percentage of completed switches that function correctly in a particular embodiment. For example, about 10-20% fewer fabricated switches were found to function correctly for embodiments with overlap lengths greater than 100 nm than for embodiments with overlap lengths less than 50 nm. The method for testing 2-NTS is described in detail below. the

The voltages, currents and resistances listed here are intended as examples of suitable values for a particular implementation; suitable values may be different for one or more other implementations. the

In certain applications, it may be desirable to overlap the nanotube element with the conductive element in a different geometry than the embodiments shown in FIGS. 1A-1B or 2D-2I to facilitate thermal engineering of the switch. For example, it may be desirable to position the nanotube elements on the upper, lower, or even vertical sides of the contact elements. In general, any configuration that provides a given geometry sufficient to achieve the switching behavior in the device may be used. Specifically, the conductive elements should be arranged to provide sufficient electrical stimulation to the nanotube elements, while the switch as a whole has sufficient thermal management to achieve a process of breaking contact between nanotubes and conductors in the nanotube elements on the path of the switch. heating. the

It should be understood that the remainder of the embodiments described herein include a stimulation circuit in contact with a conductive element, such as stimulation circuit 100 of FIGS. 1A and 1B , although it is not shown. It should also be understood that while many of the illustrated embodiments show two-terminal nanotube switches in which thermal management is achieved by limiting overlap between nanotube elements and conductive elements such as terminals, other thermal management methods may be used. For example, in certain embodiments, a nanotube element may partially or fully overlap one or both conductive elements, and the materials in the switch may be selected to ensure sufficient heat build-up in at least a portion of the nanotube element. the

Figure 3A shows a switch 900A which is a variation of the 2-TNS10' shown in Figure 1B and is fabricated using preferred methods. In this embodiment, the conductive element 905 overlaps the top and sides of the nanotube element 920 , forming a near-ohmic contact, and filling the via 910 in the insulator 915 . This connects the nanotube element 920 to an electrode (not shown) under the insulator 915 . The conductive element 970 overlaps the top and sides of the nanotube element 920 over a controlled overlap length 901 . the

Figure 3B shows switch 900B, which is another variation of the 2-TNS 10' shown in Figure 1B, and fabricated using preferred methods. In this embodiment, conductive element 935 overlaps the bottom of nanotube element 945 , forms a near-ohmic contact, and fills via 940 in insulator 915 . This connects nanotube element 945 to an electrode (not shown) under insulator 915 . Conductive element 975 overlaps the top and sides of nanotube element 920 over a controlled overlap length. the

FIG. 3C shows switch 900C, which is another variation of 2-TNS 10' of FIG. 1B and is fabricated using preferred methods. In this embodiment, the upper conductive element 950 and the lower conductive element 955 are in contact with each other and overlap the upper surface, the lower surface and the side surface of the nanotube element 965, forming a near-ohmic contact. Lower contact element 955 fills via hole 960 in insulator 915 . This connects nanotube element 965 to an electrode (not shown) under insulator 915 . Conductive element 980 overlaps the top and sides of nanotube element 965 over controlled overlap length 907 . the

Upper and lower conductive elements 950 and 955 are shown extending beyond one end of nanotube element 965 . Upper and lower conductive elements 950 and 955 are in contact with each other and in near-ohmic contact with nanotube element 965 in a region of nanotube element 965 because nanotube element 965 is porous, typically more than 90% porous. Upper and lower conductive elements 950 and 955 fill at least some of the holes in nanotube element 965 . Thus, in alternative embodiments, upper and lower conductive elements 950 and 955 need not extend beyond one end of nanotube element 965 in order to contact nanotube element 965 and each other. the

FIG. 3D shows a switch 900D which is another variation of the 2-TNS 10' of FIG. 1B and made using preferred methods. In this embodiment, the upper conductive element 950 and the lower conductive element 955 are in contact with each other and overlap the upper surface, the lower surface and the side surface of the nanotube element 965 to form a near-ohmic contact. Lower contact element 955 fills via hole 960 in insulator 915 . This connects nanotube element 965 to an electrode (not shown) under insulator 915 . Upper conductive element 980 and lower conductive element 985 contact each other and overlap the upper, lower, and side surfaces of nanotube element 965 over controlled overlap length 907 . the

FIG. 3E shows a switch 900E, which is another variation of the 2-TNS 10 of FIG. 1A and fabricated using preferred methods. In this embodiment, the upper conductive element 950 and the lower conductive element 955 are in contact with each other and overlap the upper surface, the lower surface and the side surface of the nanotube element 965 to form a near-ohmic contact. The material in elements 950 and 955 fills at least some of the pores in nanotube element 965 . Lower contact element 955 fills via hole 960 in insulator 915 . This connects nanotube element 965 to an electrode (not shown) under insulator 915 . The upper conductive element 951 and the lower conductive element 956 contact each other and overlap the upper and lower surfaces of the nanotube element 965 over a controlled overlap length 907 . Material in elements 951 and 956 fills at least some of the pores in nanotube element 965 . In this embodiment, thermal management is achieved not by a controlled overlap length between the nanotube element and the conductive element, but by one or more of the other thermal management techniques described herein. the

FIG. 4 shows a cross-sectional view of another embodiment of a nonvolatile two-terminal nanotube switch (2-TNS) 2500 . In this embodiment, conductive elements 2515 and 2520 are deposited directly onto the surface of insulator 2530 and patterned. Insulator 2522 fills the area between patterned conductive elements 2515 and 2520 and is planarized. Nanotube elements 2525 are conformally deposited on conductive elements 2515 and 2520 , overlapping at least a portion of the upper surfaces of conductors 2515 and 2520 and the upper surface of insulator 2522 , all of which are supported by substrate 2535 . At one end, nanotube element 2525 overlaps the upper surface of conductive element 2515, forming a near-ohmic contact. At the opposite end, nanotube element 2525 is in contact with the upper surface of contact element 2520 over a controlled overlap length 2540 . the

FIG. 5 shows a cross-sectional view of another embodiment of a nonvolatile 2-terminal nanotube switch (2-TNS) 2200 . In this embodiment, both conductive elements 2215 and 2220 are deposited directly on the surface of insulator 2230 and patterned. Conductive element 2220 has a thickness T1, which is in the range of, for example, 5-500 nm. Nanotube element 2225 is conformally deposited on conductive elements 2215 and 2220 in contact with the upper and side surfaces of these elements and the upper surface of insulator 2230 , which is supported by substrate 2235 . Nanotube element 2225 is then patterned such that it overlaps the entire top and side walls of conductive element 2215, forming a near-ohmic contact, using conventional photolithographic techniques as described in more detail below. Nanotube element 2225 overlaps conductive element 2220 at sidewall junction region 2240, providing a controlled overlap of about T1. Nanotube elements 2225 may also overlap the top of conductive elements 2220 by a controlled overlap length 2245, which length may be photolithographically defined as described in more detail below. The total controlled overlap length 2250 is generally defined by the sum of the length T1 of the sidewall contact region 2240 and the overlap length 2245 . the

Figure 6 shows a cross-sectional view of an embodiment of the invention. The structure shown in FIG. 6 is similar to the structure in the photomicrograph shown in FIG. 2C, and has the same elements: silicon substrate 63C, insulator 62C, nanostructure element 65, first and second conductive elements 70C and 75C, overlapping region 80D, but without passivation layer 64 in FIG. 2C. Insulator 62C is disposed over silicon substrate 63C and under nanotube elements 65 . First and second conductive elements 70C and 75C are partially overlying insulator layer 62C and nanotube elements 65 , respectively. First conductive element 70C overlaps nanotube element 65 in overlapping region 80C, and passivation layer 64 is disposed over conductive elements 70C and 75C and nanotube element 65 . the

The embodiments can be fabricated using the materials and methods shown in Figures 1A-1B and 2A-2I. Further details of fabricating the two-terminal nanotube switching element and devices incorporating the switch are described in more detail below. Several additional embodiments and methods of making them are also described below. the

Many of the embodiments described herein show a two-terminal nanotube switch in which thermal management is achieved by overlapping a nanotube element with a conductive element by a controlled overlap length. However, it should be understood that the embodiments described herein may also be thermally managed by other techniques in addition or in the alternative. Embodiments described herein share the common feature of nanotube articles having at least one nanotube arranged to overlap at least a portion of each of the two terminals. Certain preferred embodiments may be thermally and/or electrically managed or engineered to enhance one or more characteristics of the switch. For example, in certain embodiments, a nanotube overlaps one terminal, forms a near-ohmic contact, and overlaps the other terminal by a controlled overlap length. In certain embodiments, one or more materials in the switch may be selected, such as nanotubes, conductive elements, insulator layers, and/or layers, which in many preferred embodiments may include copolymers or hybrid layers. Passivation layer to enhance heat build-up in nanotube elements. the

A stimulus circuit in electrical communication with at least one of the terminals of a two-terminal nanotube switch embodiment may be used to change the switch from a relatively high resistance "erased" or "open" state to a relatively low resistance "programmed" or "closed" state. "state. The circuit can also be used to measure the resistance between two terminals and determine the switch state in a nondestructive readout (NDRO) operation. the

Fabrication of 2-terminal nanotube switches with controlled overlapping regions

In embodiments of a two-terminal nanotube switch, where thermal management is achieved by arranging the nanotube element and the conductive element in a specified geometric relationship, such as a controlled overlap length, precise control of this relationship can enhance the performance of the switch. Certain properties of a non-volatile 2-terminal nanotube switch (2-NTS) can be a function of a controlled overlap length, such as region 40' of switch 10' shown in Figure IB. Several methods for making controlled overlap lengths for specified geometries will be described. Several additional embodiments and methods of making them will also be described. In certain embodiments, the controlled overlap length is a dimension of the conductive element, such as the width or thickness of the conductive element. In general, overlap lengths between 1-150 nm, preferably 15-50 nm, can be fabricated using the techniques described herein. the

To fabricate controlled overlap lengths between nanotube elements and conductive elements, some methods use a preferred fabrication method with horizontally oriented nanotube elements and timed etching at well-controlled etch density and temperature. The method exposes a controlled length of the nanotube element to be in contact with the conductive element. This length corresponds to the controlled overlap length 40' in Figure IB, although a particular embodiment or embodiments may have a different geometric relationship between the nanotube element and the conductive element than that shown in Figure IB. the

Other methods use a preferred fabrication method with horizontally oriented nanotube elements and sidewall spacers of well-controlled film thickness, where the nanotube element is defined after a controlled length of exposure of the element that will overlap the conductive element. Spacer removed. This length corresponds to the controlled overlap length 40' of Figure IB, although a particular embodiment or embodiments may have a different geometric relationship between the nanotube element and the conductive element than that shown in Figure IB. the

Other methods use photolithography-based preferred fabrication methods in which nanotube elements conform to the horizontal and, in some cases, vertical features of one or more conductive elements. In the case of nanotube elements conforming to horizontal features, the elements are positioned and photolithographically patterned to overlap one conductive element by a controlled overlap length. This length corresponds to the controlled overlap length 40' of Figure IB, although in this embodiment the nanotube elements and conductive elements may have a different geometric relationship. Where the nanotube element also conforms to the vertical feature of the conductive element, the nanotube element can contact the vertical feature of the conductive element over a length defined by the thickness of the feature, and can contact the horizontal feature over a photolithographically defined length . Together, the vertical and horizontal lengths define a controlled overlap length corresponding to length 40' in FIG. 1B , although a particular embodiment or embodiments may have a different geometric relationship between the nanotube element and the conductive element than that shown in FIG. 1B . the

Figure 7 shows the general process for fabricating 2-TNS and 2-TNS based devices. Figure 7 is a high level flowchart of the basic method 800 of making the preferred embodiment of the present invention. 2-TNS can be fabricated by first placing an initial structure (step 802 ) on which nanotube elements and possibly conductive elements will be formed later. In a simple embodiment, the initial structure is the substrate on which all elements of the 2-TNS can subsequently be formed. In certain embodiments, the initial structure is a partially fabricated, planarized semiconductor structure defined at the device level, having metal-filled vias providing a conductive path between transistor terminals and the planarized surface of the resulting partially fabricated semiconductor structure (terminal). In certain embodiments, the initial structure includes two conductive elements. In some embodiments, the initial structure even includes nanostructures that do not form nanotube elements. In general, structures that do not yet have defined nanotube elements can be considered initial structures. "Initial structure" is not intended as a limiting term but as a reference point for 2-TNS fabrication. the

2-TNS can be fabricated by placing intermediate structures afterwards (step 804). In certain embodiments, the intermediate structure is characterized as having defined nanotube elements on the surface of the initial structure (provided in step 802). As described further below, in certain embodiments, the intermediate structure has a nanotube element that overlaps and makes near-ohmic contact with a conductive element. In certain embodiments, the intermediate structure has nanotube elements that overlap the conductive elements by a controlled overlap length. For example, the length may be in the range of 1-150 nm. "Intermediate structure" is not intended as a limiting term but as a reference point for 2-TNS fabrication. the

2-TNS can be fabricated by finally setting the final structure (step 806). In certain embodiments, the final structure is as-fabricated 2-TNS. The 2-TNS can be used in wired non-volatile random access memory arrays as described further below. Certain embodiments of the final structure may include memory array on-pitch circuitry, peripheral and other circuit wiring, chip passivation, input and output pads; these features and their fabrication are not shown because They use known industrial production methods. "Final structure" is not intended as a limiting term but as a reference point for the fabrication of 2-TNS. the

Method for Fabricating 2-TNS Using Controlled Etching

The embodiment shown in Figure 3B can be fabricated using the timed etch approach shown in Figures 8A-8F. Referring to Figure 8A, the preferred method deposits a layer of insulator 1000 on an underlying structure (not shown). The conductive elements 1005 in the vias 1010 form a conductive path between the nanofabric 1015 and a conductor (not shown) beneath the insulator 1000 . Insulator 1000 and conductive element 1005 correspond to insulator 915 and conductive element 935 in Figure 3B, respectively. The insulator 1000 may be _Six Ny, Al ₂ O ₃ or other suitable insulating material, for example with a thickness in the range of 5-200 nm, deposited on a flat surface (not shown) using well known industry techniques. Next, preferred methods deposit and pattern an insulator 1020, such as 5-50 nm thick _SiO2, as shown in FIG. 8A. Insulator 1020 is patterned using well known industry techniques. The resulting assembly can be considered as the initial structure.

Next, preferred methods use insulator 1020 as a mask to form and pattern nanostructures 1015, thereby forming nanotube elements 1025 as shown in FIG. 8B. Methods of forming and patterning nanostructures to form nanotube elements are described in the incorporated patent documents. The preferred method then selectively performs a controlled isotropic etch of the insulator 1020, as shown in FIG. 8C. The lateral and vertical dimensions of the insulator 1020 are reduced by this controlled etch, thereby removing the insulator region 1030 . This depends on the characteristics of the etch, for example reducing the size of the insulator 1020 by 1-150 nm in all directions. This exposes the nanotube element 1025 in the region 1050 for a controlled length 1035, for example in the range of 1-150 nm, which corresponds to the reduced size of the insulator 1040, as shown in Figure 8D. the

Next, preferred methods deposit conductor 1045 as shown in FIG. 8E such that conductor 1045 contacts exposed region 1050 of nanotube element 1025 . Conductor 1045 may have a thickness in the range of 5-500 nm, and may be made of metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and others. Suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And TiSi _x conductive nitride, oxide or silicide. Other types of conductive and semiconducting materials may also be used.

Next, preferred methods pattern the conductor 1045 using well-known industry techniques to provide the conductive element 1055 as shown in FIG. 8F. Conductive element 1055 overlaps nanotube element 1025 at exposed region 1050 . The controlled overlap length 1035 shown in FIG. 8F is in the range of, for example, 1-150 nm, and corresponds to the controlled overlap length 40 shown in FIG. different geometric relationships. The structure shown in Figure 8F can be considered as the final structure. This structure may be included in other devices described in more detail below. the

Different approaches to achieving the intermediate structure shown in FIG. 8D can be taken using the directional etching method shown in FIGS. 9A-9C. Figure 9A shows the initial structure as shown in Figure 8A, which includes nanofabrics 1115 and also includes a conformal sacrificial layer 1122, such as silicon, using well-known industry techniques. The thickness of layer 1122 is well controlled and may be, for example, in the range of 1-150 nm. It is preferable to use thickness control because the film thickness of the conformal sacrificial layer 1122 will determine the controlled overlap length between the nanotube elements and the conductive elements in subsequent steps. The components of Figure 9A can be considered an initial structure. the

Preferred methods then directionally etch the conformal sacrificial layer 1122 using well-known industry techniques such as RIE, leaving sidewall regions 1130, as shown in FIG. 9B. The preferred method then uses the insulator 1120 and the sidewall spacers 1130 together as a mask to pattern the nanofabric 1115. This forms nanotube element 1125 as shown in Figure 9B. Methods of depositing and patterning nanostructures to form nanotube elements are described in the incorporated patent documents. the

Next, preferred methods etch (remove) the remaining sidewall spacers 1130 using known industry techniques, exposing the nanotube elements 1125 in regions 1150, as shown in FIG. 9C. At this point in the process, the intermediate structure shown in Figure 9C corresponds to the intermediate structure shown in Figure 8D. Insulators 1000 and 1100, conductive elements 1005 and 1105, nanotube elements 1025 and 1125, insulators 1040 and 1120, and controlled overlap lengths 1035 and 1135 correspond to each other, respectively. The method continues as described with respect to FIGS. 8E and 8F to form a non-volatile 2-terminal nanotube switch (2-TNS) 1070 as shown in FIG. 8F . the

10A-10I illustrate another embodiment and method of fabricating nanotube elements and conductive elements using a timed etch process to form controlled overlapping regions between them. An initial structure 1600 is created or provided as shown in Figure 10A, which includes a substrate 1602 which may be silicon or any suitable material (or combination of materials). Insulator 1604 deposited on substrate 1602 may be fabricated from silicon nitride or any suitable material. Metal plug 1608 is disposed in substrate 1602 and a portion of insulator 1604 such that its upper surface is approximately flush with insulator 1604 . Nanofabric 1610 is applied to structure 1600 to form intermediate structure 1612, as shown in Figure 10B. Methods of applying nanostructures 1610 are described in the incorporated patent documents and will not be repeated below for the sake of brevity. the

Oxide layer 1614 is applied to intermediate structure 1612 of FIG. 10B, forming intermediate structure 1616 in FIG. 10C. A resist coat 1618 is applied to intermediate structure 1616 and patterned, leaving intermediate structure 1620 as shown in Figure 10D. In structure 1620, region 1619 of nanofabric 1610 is exposed. A dry etch process is then performed on intermediate structure 1620 to remove exposed nanofabric region 1619 to form nanotube element 1650 . Then, the remaining photoresist is removed to form an intermediate structure 1622 as shown in FIG. 10E . A wet etch process is performed on intermediate structure 1622 to remove a portion of oxide layer 1614 (shown in dashed lines in FIG. 10E ), leaving remaining oxide 1624 and exposed nanotube element regions 1626 . Region 1626 has a length of, for example, 1-150 nm. FIG. 10F shows intermediate structure 1628 . the

As shown in FIG. 10G , conductive material 1630 is deposited on intermediate structure 1628 . Photoresist 1632 is deposited over conductive material 1630 and patterned to leave regions of photoresist 1632 over exposed nanotube element regions 1626 , thereby forming intermediate structure 1634 . A suitable etch process is performed on conductive material 1630 and photoresist 1632 leaving remaining conductive elements 1636 . Conductive element 1636 overlaps nanotube element 1650 at region 1638 to form intermediate structure 1640, as shown in Figure 10H. the

A layer 1642, which in some embodiments may be composed of a copolymer or other material mixture, is applied to an intermediate structure 1640, which may be an intermetal dielectric, resulting in a final structure 1644 as shown in FIG. 10G. Note that the insulating layer 1604 may serve as a passivation layer preseal. the

Method for fabricating 2-TNS using photolithography

11A-11C illustrate a method that does not rely on controlled etching but instead uses photolithographic techniques to form controlled contact overlap regions. A method of fabricating the embodiment of FIG. 4 using photolithographic techniques is shown in FIGS. 11A-11C. Referring to FIG. 11A , preferred methods deposit and pattern conductive elements 2605 and 2610 on a substrate 2600 . The substrate 2600 may include semiconductor devices, polysilicon gates and interconnects for contacting other layers, metal wiring layers, and studs. The conductive elements 2605 and 2610 can have a well-controlled thickness in the range of 5-500 nm and can be made of materials such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn metal, other suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used. A preferred method of patterning conductive elements 2605 and 2610 may use well-known photolithographic techniques and/or well-known etching techniques, such as reactive ion etching (RIE).

Then, still referring to FIG. 11A , preferred methods deposit and planarize insulator 2622 using known fabrication techniques. Insulator 2622 fills the area between conductive elements 2605 and 2610 . Then, still referring to FIG. 11A , preferred methods conformally deposit nanofabric 2615 over contact elements 2605 and 2610 and insulator 2622 . Methods of applying nanostructures 2615 are described in the incorporated patent references and will not be repeated here for the sake of brevity. The components in Figure 11A can be considered as the initial structure. the

Next, preferred methods deposit, pattern, and align photoresist layer 2620 on nanofabric 2615 using well-known semiconductor industry fabrication methods, as shown in FIG. 11B . The relative alignment of the patterned photoresist layer 2620 and the conductive elements 2610 defines a controlled overlap length between the nanotube elements and the conductive elements, as described further below. Figure 1 IB can be considered an intermediate structure. the

Next, preferred methods pattern the nanofabric 2615 using the patterned photoresist layer 2620 as a mask. This results in the formation of nanotubes 2625 as shown in FIG. 11C and completes the fabrication of a two-terminal switch 2670 corresponding to switch 2500 shown in FIG. 4 . A preferred method then deposits a protective insulating layer ₍ not shown) using well-known insulators such as _SiO2 , _SixNy , _Al2O3 , and other well-known insulators used in semiconductor _{manufacturing} .

2-TNS 2670 includes nanotube element 2625 overlapping the top of conductive element 2650, forming a near-ohmic contact. Nanotube element 2625 overlaps conductive element 2610 over a controlled overlap length 2640, which is in the range of, for example, 1-150 nm in length. The overlap length 2640 is determined by the alignment of the patterned photoresist layer 2620 relative to the conductive elements 2610 . the

The embodiment of Figure 5 can be fabricated using photolithographic techniques and conformal nanotube elements, as shown in Figures 12A-13. Referring to Figure 12A, preferred methods deposit and pattern conductive elements 2305 and 2310 on a substrate 2300. The substrate 2300 may include semiconductor devices, polysilicon gates and interconnections for contacting other layers, metal wiring layers, and studs. Elements 2305 and 2310 can have a well-controlled thickness in the range of 5-500 nm and can be made of materials such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn metals, and other suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used. A preferred method of patterning conductive elements 2305 and 2310 may use well-known photolithographic techniques and well-known etching techniques, such as reactive ion etching (RIE).

Then, still referring to FIG. 12A , preferred methods conformally deposit nanostructures 2315 on conductive elements 2305 and 2310 so as to overlap the upper and side surfaces of elements 2305 and 2310 and a portion of the upper surface of substrate 2300 . Methods of forming and patterning nanostructures are described in the incorporated patent references. The components shown in Figure 12A can be considered as an initial structure. the

Next, preferred methods deposit, pattern, and align photoresist layer 2320 on nanofabric 2315 using well-known semiconductor industry fabrication methods, as shown in Figure 12B. The relative alignment of the patterned photoresist layer 2320 and the conductive elements 2310 determines the controlled overlap length between the nano-elements and the conductive elements 2310, as described further below. The components shown in Figure 12B can be considered intermediate structures. the

Next, preferred methods pattern the nanofabric 2315 using the patterned photoresist layer 2320 as a mask. This forms nanotube 2325 as shown in FIG. 13 and completes the fabrication of two-terminal nanotube switch 2370 corresponding to switch 2200 shown in FIG. 5 . A preferred method then deposits a protective insulating layer (not shown) using a well-known insulator such as _SiO2 , SiN, _{Al2O3 ,} and other well-known insulators used in semiconductor manufacturing.

As described above in relation to FIG. 5 , the nanotube element 2325 overlaps the conductive element 2310 in a region 2350 defined by a sidewall overlap region 2340 (having approximately the same length as the thickness T1 of the conductive element 2310 ) and a controlled overlap length 2345 . (eg 1-150nm) to define. the

In the embodiment shown in Figures 12A-13, the total length of nanotube element 2325 overlapping both surfaces of conductive element 2310 defines a controlled overlap region. However, in other embodiments, the nanotube element 2325 may actually be in contact with more than two surfaces of the conductive element 2310 to define a controlled overlap region, the length of which may affect one or more of the resulting 2-TNS switches. an electrical characteristic. the

Fabrication of dense 2-terminal nanotube switches with controlled overlapping regions

While the above implementations are relatively dense 2-TNSs (ie, many fabricated on a small area), denser scalable non-volatile nanotube two-terminal switches are possible. Some methods of fabricating dense switches use an optimal fabrication method to fabricate a picture frame structure, which provides dense 2-TNS for many purposes. the

Other described methods of fabricating dense switches use preferred fabrication methods with vertically oriented nanotube elements. In these methods, the spacing between conductive elements is controlled by the film thickness rather than the photolithographic device. The thickness of the removable (or sacrificial) film is used to define the controlled overlap length between the vertically oriented nanotube elements and the conductive elements. Alternatively, the thickness of the conductive element itself defines the controlled overlap length. the

How to make photo frame design 2-TNS

An implementation that provides relatively dense 2-TNS is the picture frame design. The picture frame design has symmetrical features that scale with the metal ground rule that defines each technology generation. The photo frame design technology of the nanotube three-terminal structure was submitted on June 9, 2004 entitled "Non-volatile Electromechanical Field Effect Devices and Circuits using Same and Methods of Manufacturing Same (non-volatile electromechanical field effect devices and using the device U.S. Patent Application No. 10/864,186 for Circuits and Methods of Making the Same) and U.S. Pat. It is described in patent application Ser. No. 10/936,119. An example picture frame design of a non-volatile nanotube two-terminal switch is described further below with respect to FIGS. 14A-14J . the

Referring to Figure 14A, a preferred method deposits an insulator 1800 on an underlying structure (not shown). Conductive elements 1805 in vias 1810 form a conductive path between nanofabric 1815 and a conductor (not shown) beneath insulator 1800 . In this regard, the initial structure is similar to a portion of the structure shown in Figure 3B. For example, insulator 1800 and conductive element 1805 in FIG. 14A correspond to insulator 915 and conductive element 935 in FIG. 3B , respectively. In this embodiment, however, instead of being at one end of the nanotube element, the conductive element 1805 is designed to be at the center of the picture frame switch as further described below. Insulator 1800 may be, for example, SiN, _{Al2O3 ,} or other suitable insulating material deposited on a flat surface (not shown) with a thickness in the range of 5-200 nm using known industry techniques. The assembly shown in Fig. 14A can be considered as an initial structure.

Next, preferred methods deposit and pattern optional conductive elements 1807 as shown in Figure 14B. Optional element 1807 may provide a near-ohmic contact with improved resistance between nanofabric 1815 and conductive element 1805 . Optional element 1807 may be a metal such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and other suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used.

Then, preferred methods deposit and pattern an insulator 1820 such as SiO ₂ with a thickness of 5-50 nm, such as shown in FIG. 14C . The insulator 1820 can be patterned using known industry techniques.

Next, preferred methods deposit and pattern a conformal sacrificial layer 1822, such as silicon, as shown in Figure 14D. Layer 1822 has a well-controlled thickness, such as in the range of 1-150 nm, controlled using known industry techniques. The preferred method of using thickness control is because the thickness of the conformal sacrificial layer 1822 will determine the controlled overlap length between the nanotube elements and the conductive elements in subsequent processes. the

Preferred methods then directionally etch the conformal sacrificial layer 1822 using well-known industry methods such as RIE, leaving sidewall regions 1830 as shown in Figure 14E, for example. the

Next, preferred methods pattern nanofabric 1815 using insulator 1820 and sidewalls 1830 as a mask to form nanotube element 1825 as shown in Figure 14F. Methods of patterning nanostructures to form nanotube elements are described in the incorporated patent documents. the

Preferred methods then use known industry techniques to etch (remove) the remaining sidewall spacers 1830, thereby exposing the nanotube elements 1825 in regions 1835, as shown in Figure 14G. the

Next, preferred methods deposit conductor 1845 as shown in Figure 14H. Conductor 1845 overlaps exposed region 1835 of nanotube element 1825, as shown in Figure 14H. Conductor 1845 may have a thickness in the range of 5-500 nm and may be made of metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and others. Suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used. The components shown in Figures 14B-14H can be considered intermediate structures.

Next, preferred methods pattern the conductor 1845 using well-known industry techniques to form conductive elements 1855 as shown in Figure 14I. Conductive element 1855 overlaps nanotube element 1825 in exposed region 1835 by a controlled overlap length 1860. Overlap length 1860 is, for example, in the range of 1-150 nm. Although this embodiment has a different geometric relationship between the conductive element and the nanotube switch, the controlled overlap length 1860 corresponds to the length 40' shown in FIG. 1B. the

Figure 141 shows a cross-section of a picture frame 2-TNS 1870 including a support insulator 1800 on an underlying substrate (not shown) and a conductive element 1805 in a via 1810. Figure 14J shows a plan view of switch 1870 corresponding to the cross-section shown in Figure 14I. Conductive element 1855 can be seen overlapping the periphery or outer edge of nanotube element 1825 and conductive element 1807 can be seen overlapping the central region of nanotube element 1825 . The embodiment shown in Figures 14I and 14J can be considered the final structure. the

The picture frame 2-TNS structure has many potential uses due to its density, scalability, and symmetry. In addition to being useful in memory (e.g., non-volatile random access memory) cells, photo-frame non-volatile two-terminal nanotube switches can be used, for example, as programmable and reprogrammable fuses/antifuses between metal layers switches and/or wiring for reconfigurability, as described in more detail below. the

Approaches to use thin-film technology to fabricate dense 2-TNS

15A-15N illustrate the fabrication of vertically oriented 2-TNS pairs. Referring to FIG. 15A, a preferred method deposits an insulating layer 1200 such as SiO ₂ on an underlying structure (not shown). Conductive elements 1205A and 1205B are disposed in respective vias 1210A and 1210B.

Then, a preferred method deposits an insulator 1212 as shown in FIG. 15A , which can be, for example, SiN, Al ₂ O ₃ or other suitable insulating materials deposited on the surface of the insulator 1200 using known industry techniques with a thickness in the range of 2-200 nm. The thickness of insulator 1212 is used to define, for example, the spacing between conductive elements 1205A and conductive elements deposited in subsequent process steps. By using controlled deposition layer thicknesses to define the spacing between conductive elements can be more accurate than using photolithography.

Then, preferred methods deposit a sacrificial layer 1215, such as silicon, with a thickness in the range of 1-150 nm as shown in FIG. 15A using well known industry techniques. It is preferable to use thickness control because the thickness of the sacrificial layer 1215 will determine the controlled overlap length between the nanotube elements and the conductive elements in subsequent processes. The assembly shown in Figure 15A can be considered as an initial structure. the

Next, preferred methods use known industry techniques to pattern the sacrificial layer 1215 to form a sacrificial insulator 1220 as shown in FIG. 15B. the

Next, preferred methods deposit additional insulating material and planarize to embed sacrificial insulator 1220 into insulator 1225, as shown in Figure 15C. A non-conformal insulating layer can be deposited and etched back using a directional etch such as RIE, where the sacrificial insulator 1220 surface acts as an etch stop. The resulting surface need not be very flat to keep the thickness of the sacrificial insulator 1220 under control. the

Next, preferred methods pattern and directionally etch the sacrificial insulator 1220, as shown in Figure 15D. These methods form sacrificial insulator 1230 and directionally etch insulator 1225 to selectively stop at the surface of insulator 1200 . These methods expose conductive elements 1205A and 1205B and leave opening 1245 . A directional etch, such as RIE, selected for the underlying insulator 1200 and conductive element 1205, for example, may be used. the

Next, as shown in Figure 15E, preferred methods deposit conformal nanostructures 1235 using methods described in the incorporated patent documents. the

Next, preferred methods deposit a conformal protective insulator 1240 on the nanofabric 1235, as shown in Figure 15F. The protective insulator 1240 can use SiN, Al ₂ O ₃ or other suitable insulating materials.

Next, preferred methods deposit an insulator 1250 using, for example, TEOS, as shown in Figure 15G. TEOS is deposited and fills the opening 1245 using well known industry techniques. _SiO2 is another example of an insulator that can be used for this purpose. Next, preferred methods planarize the insulator 1250 using known industry techniques, as shown in Figure 15H. This exposes an area of the protective insulator 1240 .

Then, preferred methods selectively remove exposed portions of protective insulator 1240 . Directional etching, such as RIE, can be used to obtain the structure shown in Figure 15I. the

Preferred methods are then used to remove exposed areas of nanofabric 1235 using, for example, ashing or other suitable techniques as described in the incorporated patent documents. Figure 15J shows the resulting structure with nanotube elements 1255 in a vertical orientation. the

Next, preferred methods remove the sacrificial insulator region 1230, as shown in Figure 15K. This exposes region 1260 at the end of vertically oriented nanotube element 1255 . The length of this region is defined by the thickness of the removed sacrificial insulator 1230 . the

Next, preferred methods deposit conductor 1265 as shown in Figure 15L. Conductor 1265 overlaps the exposed area of nanotube element 1255 . Conductor 1265 has a thickness in the range of 5-500 nm and may be made of metals such as Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and other suitable metals, and its composition. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiN can be used. the

Next, preferred methods pattern conductor 1265 using known industry techniques to form conductive elements 1270A and 1270B as shown in FIG. 15M. Elements 1270A and 1270B overlap the ends of nanotube element 1255 by respective controlled overlap lengths 1280A and 1280B, respectively. These lengths are for example in the range 1-150 nm. The controlled spacing 1285 between conductive elements 1270A and 1205A is determined by the thickness of insulator 1212, as described with respect to FIG. 15A. The components of Figures 15B-15M can be considered intermediate structures. the

Then, as shown in FIG. 15N , preferred methods perform a directional etch of insulator 1250 selected for insulator 1225 and insulator 1240 using conductive elements 1270A and 1270B as a mask layer. The etch creates opening 1290 and stops at the surface of insulator 1240 . Etching of insulator 1240 selected for insulator 1250 and insulator 1200 is then performed, again using conductive elements 1270A and 1270B as a masking layer. Conductive elements 1270A and 1270B are then again used as a mask for selective etching of exposed regions of nanotube element 1255 . This etch forms two separate vertically oriented nanotube element segments 1255A and 1255B. Conductive elements 1205A and 1205B overlap corresponding nanotube element segments 1255A and 1255B, forming near-ohmic contacts and forming conductive paths between the segments and corresponding contacts (not shown) beneath insulator 1200 . This forms mirror image non-volatile 2-terminal nanotube switches (2-TNS) 1295A and 1295B as shown in Figure 15N. The assembly shown in Figure 15N can be considered the final structure. the

Vertically oriented mirror image nonvolatile 2-terminal nanotube switches (2-TNS) 1295A and 1295B include conductive elements 1270A and 1270B that overlap corresponding nanotube element segments 1255 by corresponding controlled overlap lengths 1280A and 1280B. While the geometry of this embodiment differs in many respects from that shown in FIG. 1B , lengths 1280A and 1280B correspond to controlled overlap length 40' shown in FIG. 1B . the

Another approach to fabricating dense 2-TNS uses a preferred fabrication method employing vertically oriented nanotube elements, where the controlled overlap length between nanotube elements and conductive elements is achieved by selectively masking the sidewall regions of the grooves (also can be called concave) to determine. US Patent No. 5,096,849 to Bertin et al. teaches a method of selectively masking groove sidewall regions and has been employed herein to control a controlled overlap length. Vertically oriented nanotube elements can be used to form potentially denser 2-TNSs, and can be made into pairs as further described below. the

Referring to FIG. 16A , preferred methods deposit and pattern conductor 2805 on substrate 2800 . The substrate 2800 may include semiconductor devices, polysilicon gates, and interconnections described below for contacting other layers, metal wiring layers, and studs. Conductor 2805 can have a well-controlled thickness in the range of 5-500 nm and can be made of metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn , and other suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used. A preferred method of patterning the conductor 2805 may use well-known photolithographic techniques and/or well-known etching techniques, such as reactive ion etching (RIE).

Next, preferred methods deposit and planarize insulator 2810 such that the surfaces of insulator 2810 and conductor 2805 are coplanar, as shown in Figure 16A. Insulator 2810 supported by substrate 2800 may have a _thickness , for example, in the range of 5-500 nm, and one or more dielectric layers of _SiO2 , SiN, _Al2O3 , or other suitable insulating material may be used.

Next, preferred methods deposit an insulator 2815 . Insulator 2815 may have a thickness in the range of 5-500 nm, as shown in Figure 16A, and may be composed of _SiO2 , SiN, _{Al2O3 ,} or other suitable insulating material. The thickness of the insulator 2815 controls the spacing between the upper surface of the conductor 2805 and the lower surface of the second conductor deposited on the upper surface of the insulator 2815, as described further below.

Then, still referring to FIG. 16A , preferred methods deposit a conductor layer 2820 on the insulator 2815 . The conductor layer 2820 has a thickness T1 in the range of, for example, 5-500 nm by using a well-controlled deposition thickness, and can be made of materials such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn metals, other suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used. Figure 28A can be considered an initial structure.

Next, preferred methods deposit and pattern a masking layer 2825 over the conductor 2820, as shown in Figure 16B. Masking layer 2825 may be, for example, a photoresist layer, and may be patterned using methods well known in the semiconductor industry. the

Then, preferred methods remove (etch) the exposed portion of the conductor layer 2820, resulting in the conductor 2830 as shown in FIG. 16C. Well-known etching methods such as RIE can be used to define conductor 2830 . the

Next, preferred methods deposit and planarize insulator 2835 such that the upper surface of insulator 2835 and the upper surface of conductor 2830 are coplanar, as shown in Figure 16D. Insulator 2835 may be composed of SiO ₂ , SiN, Al ₂ O ₃ , or other suitable insulating material. Alternatively, structures may be used that do not introduce insulator 2835 planarization during this step of the process. However, planarization in this step can facilitate subsequent process steps.

Next, preferred methods deposit and pattern a masking layer 2840, forming openings 2845 as shown in FIG. 16E. The opening 2845 corresponds to the location of the vertical groove to be used in subsequent process steps to fabricate a vertical non-volatile nanotube two-terminal switch by depositing the nanotube element directly on the conductive element. the

Next, preferred methods directionally etch conductor 2830, directionally etch insulator 2815, and directly etch conductor 2805, stopping on the surface of substrate 2800 to form recess 2860 as shown in Figure 16F. Recess 2860 may be formed using any suitable directional etching fabrication method, such as reactive ion etching (RIE). The method of forming groove 2860 separates conductor 2830 into two conductive elements 2850A and 2850B. The method of forming groove 2860 also separates conductor 2805 into two conductive elements 2855A and 2855B. The method of forming groove 2860 also forms a corresponding groove opening in insulator 2815 . the

Next, preferred methods use known semiconductor fabrication techniques to remove masking layer 2840, which may be photoresist. Preferred methods then deposit conformal nanostructures 2865 on the bottom and sidewalls of recess 2860, on the upper surfaces of conductive elements 2650A and 2650B, and on the upper surface of insulator 2835, as shown in Figure 16G. Methods of depositing nanostructures are described in the incorporated patent documents. the

Then, preferred methods fill the recess 2860 with an insulator 2870, such as TEOS, to approximately planarize the surface of the insulator 2860, as shown in FIG. 16H, and this structure can be further planarized by, for example, CMP as desired. the

Next, preferred methods etch openings 2875 in the insulator 2870 in the recess region, as shown in Figure 16L. This exposes the bottom region of the nanofabric 2865. The opening 2865 need not be located in the center of the recessed area, but the opening 2875 should not expose (portions of) sidewall regions of the nanofabric 2865. Preferred methods of etching the insulator TEOS or other insulators are well known in the semiconductor industry. the

Preferred methods are then used to selectively remove the exposed bottom region of the bottom of opening 2875 using, for example, ashing or other suitable techniques as described in the incorporated patent documents. This forms vertically oriented nanofabric segments 2865A and 2865B, as shown in Figure 16I. the

A preferred method then fills the opening 2875 with an insulator such as TEOS and performs an approximate planarization to obtain an approximately planarized insulator 2880, as shown in FIG. 16J. This structure can be further planarized by, for example, CMP as desired. the

At this point in the process, a controlled overlap length between vertically oriented nanofabric segments 2865A and 2865B and corresponding conductive elements 2850A and 2850B needs to be defined. A method of selectively masking groove sidewall regions (or recessed regions) with vertically oriented nanofabrics can be used. US Patent No. 5,.096,849 to Bertin et al. describes a prior art process (fabrication method) for the selective removal of material within recesses in a silicon substrate. As described in prior art US Pat. No. 5,096,849, the preferred method of fabrication proceeds as further described below, as described in prior art US Pat. No. 5,096,849. the

A preferred method directionally etches (eg, using RIE) planarized insulator 2880 and removes insulator material to a predetermined depth D1 below the surface of conductive elements 2850A and 2850B, as shown in FIG. 16K . This defines the upper surface of the remaining groove-fill insulator 2885 . Portions of nanofabric segments 2865A and 2865B can also be selectively removed to a depth D1 using preferred methods to form nanotube elements 2890A and 2890B. Depth Dl defines the upper edges of covered (ie, protected) nanotube elements 2890A and 2890B relative to the upper surfaces of conductive elements 2850A and 2850B, respectively. In certain embodiments, RIE removes both the insulating material and portions of the nanostructure fragments in the same step. However, in cases where nanostructure portions are not completely removed by the RIE process, preferred methods may be used to remove exposed nanostructures using, for example, ashing or other suitable techniques as described in the incorporated patent documents. the

Nanofabrics 2890A and 2890B overlap conductive elements 2850A and 2850B by a controlled overlap length defined by difference T1-D1. T1 is, for example, in the range of 5-500 nm, and the overlapping length T1-D1 may be, for example, in the range of 1-150 nm. The components shown in Figures 16B-16K can be considered intermediate structures. the

Next, preferred methods remove the remaining insulator 2885, as shown in Figure 16L. Alternatively, additional insulator material can be added and the structure planarized (not shown). The assembly shown in Figure 16L can be considered the final structure. 2-TNS 2895A and 2895B are mirrored pairs. Switch 2895A includes a nanotube element 2890A that overlaps the entire height of one side of conductive element 2855A to form a near-ohmic contact. Nanotube element 2890A overlaps conductive element 2850A by a controlled overlap length 2892A, which can be, for example, in a length range of 1-150 nm and defined by T1-D1. Switch 2895B includes a nanotube element 2890B that overlaps the entire height of one side of conductive element 2855B to form a near-ohmic contact. Nanotube element 2890B overlaps conductive element 2850B by a controlled overlap length 2892B, which can be, for example, in the length range of 1-150 nm and defined by T1-D1. While the geometry of this embodiment differs in many respects from that shown in FIG. 1B , lengths 2892A and 2892B correspond to controlled overlap length 40' shown in FIG. 1B . the

Another approach to fabricate dense 2-TNS uses a preferred fabrication method in which the controlled overlap length between vertically oriented nanotube elements and conductive elements is determined by the thickness of the conductive elements. This approach results in improved overlap length control and process simplification. The fabrication method uses a conductive element comprising first and second conductors in electrical contact. The first conductor has a controlled sidewall thickness and overlaps the vertically aligned nanotube element over the thickness. This thickness defines the controlled overlap length. The second conductor forms a wiring layer interconnecting the plurality of switches. Vertically oriented nanotube elements can form potentially denser structures and can be made into pairs as described further below. the

Referring to FIG. 17A , preferred methods deposit and pattern a conductor 3005 on a substrate 3000 . Substrate 3000 may include semiconductor devices, polysilicon gates, and interconnects for contacting other layers, metal wiring layers, and studs as described further below. The conductor 3005 can have a thickness in the range of 5-500 nm using well-controlled deposition thickness and can be made of materials such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn metal, and other suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used. A preferred method of patterning conductor 3005 may use well-known photolithographic techniques and/or well-known etching techniques, such as reactive ion etching (RIE).

Next, preferred methods deposit and planarize insulator 3010 such that the surfaces of insulator 3010 and conductor 3005 are coplanar, as shown in Figure 17A. The insulator 3010 supported by the substrate 3000 may have _a thickness, for example, in the range of 5-500 nm, and a dielectric layer of _SiO2 , SiN, _Al2O3 or other suitable insulating material may be used.

Next, preferred methods deposit an insulator 3015, as shown in Figure 17A. Insulator 3015 may have a thickness, for example, in the range of 5-500 nm, and may be composed of SiO ₂ , SiN, Al ₂ O ₃ or other suitable insulating material. The thickness of insulator 3015 controls the spacing between the upper surface of conductor 3005 and the lower surface of another conductor deposited on the upper surface of insulator 3015, as described further below.

Then, still referring to FIG. 17A , preferred methods deposit a conductor layer 3018 on the insulator 3015 . The thickness of the conductor layer 3018 determines the controlled overlap length between the nanotube elements and the first conductor, as described further below. The conductor layer 3018 can have a thickness in the range of, for example, 5-500 nm by using a well-controlled deposition thickness, and can be made of materials such as Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn metal, and other suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, etc. may be used. the

Next, preferred methods deposit a conductor layer 3020 in electrical contact with conductor layer 3018, as shown in Figure 17A. The conductor layer 3020 is used to interconnect the nanotube two-terminal switches described further below. The conductor layer 3020 can have a thickness in the range of, for example, 5-500 nm by using a well-controlled deposition thickness, and can be made of materials such as Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn metal, and other suitable metals and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, TiN, etc. may be used. the

Next, preferred methods deposit an insulator 3022 on the upper surface of the conductor layer 3020 . Insulator 3022 may have a thickness, for example, in the range of 5-500 nm, as shown in Figure 17A, and may be composed of _SiO2 , SiN, _{Al2O3 ,} or other suitable insulating material. Figure 17A can be considered an initial structure.

Next, preferred methods deposit and pattern a masking layer 3025 over the insulator 3022, as shown in Figure 17B. Masking layer 3025 may be, for example, a photoresist layer and is patterned using methods known in the semiconductor industry. the

Next, preferred methods selectively remove the exposed portions of insulator 3022 and conductor layers 3020 and 3018 . Next, preferred methods remove patterned mask layer 3025, leaving patterned insulator 3022', conductor 3030, and conductor 3032, as shown in Figure 17C. These methods expose portions of the insulator 3015 . Portions of the different layers can be removed using better known etching methods such as RIE. the

Next, preferred methods deposit and planarize an insulator 3035 such that the insulator 3035 insulates (covers) the upper surface of the conductor 3030, as shown in Figure 17D. The thickness of the insulator 3035 on the upper surface of the conductor 3030 is not critical and may vary from, for example, 5nm to 500nm. Insulator 3035 may be composed of SiO ₂ , SiN, Al ₂ O ₃ or other suitable insulating materials.

Next, preferred methods deposit and pattern a mask layer 3040 to form openings 3045 as shown in Figure 17E. Openings 3045 correspond to the location of vertical grooves for fabrication of vertical non-volatile nanotube two-terminal switches formed by direct deposition of vertically oriented nanotube elements on conductive elements. the

Next, preferred methods directionally etch conductor 3030, exposing the upper layer of conductor 3032, and forming conductors 3050A and 3050B, as shown in FIG. 17F. A preferred known etching method such as RIE selected for conductor 3032 may be used. This step separates conductor 3030 into two conductors, conductors 3050A and 3050B. the

Next, preferred methods deposit and pattern a conformal sacrificial _layer 3047 such as _SiO2 , SiN, _Al2O3 or other insulator using known industry techniques, as shown in Figure 17F. Layer 3047 has a thickness in the range of, for example, 1-150 nm. Thickness control of the sacrificial layer 3047 is not critical because the sacrificial layer thickness is not used to define the controlled contact overlap length as described further below.

Preferred methods then directionally etch the conformal sacrificial layer 3047 using well-known industry methods such as RIE. This leaves sidewall spacers 3048A and 3048B on the sidewall regions corresponding to conductors 3050A and 3050B. This also exposes a portion of the upper surface of conductor 3032, as shown in Figure 17G. the

Then, preferred methods directionally etch conductor 3032, directionally etch insulator 3015 and directionally etch conductor 3005, and stop at the surface of substrate 3000 to form groove 3060 as shown in FIG. 17H. Grooves 3060 may be formed using known directional etching fabrication methods using reactive ion etching (RIE). The method of forming groove 3060 separates conductor 3032 into two electrical conductors, conductors 3052A and 3052B. The method of forming groove 3060 also separates conductor 3005 into two conductive elements, namely 3055A and 3055B. The method of forming groove 3060 also forms a corresponding groove opening in insulator 3015 . the

Preferred methods then deposit conformal nanostructures 3065 on the bottom and sidewalls of recess 3060, on the upper surface of insulator 3035, and on the upper surfaces of sidewall spacers 3048A and 3048B, as shown in Figure 17I. Nanostructures 3065 can be deposited as described in the incorporated patent documents. the

A preferred method then fills the recess 3060 with an insulator, such as TEOS, to approximately planarize the surface of the insulator 3070, as shown in Figure 17J. the

Next, preferred methods etch openings 3075 in the insulator 3070 in the recess region as shown in FIG. 17K , exposing the bottom region of the nanofabric 3065 . The opening 3075 need not be located in the center of the recess area, however, the opening 3075 should not expose the sidewall area (portion) of the nanofabric 3065 . Preferred methods of etching the insulator TEOS or other insulators are well known in the semiconductor industry. the

Preferred methods then remove (etch) the exposed areas of the nanofabric at the bottom of the opening 3075 using, for example, ashing or other suitable techniques as described in the incorporated patent documents. The resulting structure with vertically oriented nanofabric segments 3065A and 3065B is shown in Figure 17K. the

A preferred method then fills the opening 3075 with an insulator such as TEOS and approximately planarizes to obtain a nearly planarized insulator 3080 as shown in FIG. 17L , the structure can be further planarized as desired by, for example, CMP. The components shown in Figures 17B-17L can be considered intermediate structures. the

Next, preferred methods remove (etch) insulator 3080 and expose the horizontal tops of nanofabric segments 3065A and 3065B. Preferred methods then remove these horizontal tops using, for example, ashing or other suitable techniques as described in the incorporated patent documents, to form nanotube elements 3090A and 3090B. The resulting structure with vertically oriented nanotube elements 3090A and 3090B is shown in Figure 17M. The assembly shown in Figure 17M can be considered the final structure. the

Switches 3095A and 3095B are mirrored pairs, as shown in Figure 17M. The switch 3095A includes a nanotube element 3090A that overlaps the entire height of the conductive element 3055A to form a near-ohmic contact. Nanotube element 3090A overlaps the entire height of the sidewall of conductor 3052A. The height of conductor 3052A defines a controlled overlap length 3092A, which may be in the range of length, eg, 1-150 nm. Switch 3095B includes a nanotube element 3090B that overlaps the entire height of conductive element 3055B to form a near-ohmic contact. Nanotube element 3090B overlaps the entire height of the sidewall of conductor 3052B. The height of conductor 3052B defines a controlled overlap length 3092B, which may be in the range of length, eg, 1-150 nm. While the geometry of this embodiment differs in many respects from that shown in FIG. 1B , lengths 3092A and 3092B correspond to controlled overlap length 40' shown in FIG. 1B . the

Example making steps

The initial structure consisted of a 4" Si wafer with a 30nm thermal _SiO2 layer. A set of gold alignment marks was patterned on the wafer to define an array of 60 7mm2 dies. An _O2 asher was used to pass oxygen plasma The wafer was pretreated for 2 minutes in bulk. 3 ml of an aqueous nanotube solution containing mainly MWNTs (greater than 50%) and SWNTs (and bundles thereof) was distributed onto the oxide layer of the Si wafer. Nanotube structures were applied by a spin-coating process , the process is described more fully in the incorporated reference. After nanotube spin coating, the wafer was baked on a baking tray at 150°C, and the resulting nanostructures were measured by a 4-point probe. Sheet resistance. The nanotube deposition procedure was repeated until the sheet resistance of the nanostructures was below a specified value of about 1-2 kΩ. The wafer was baked at 150° C. on a baking tray between and after nanotube spin coating .

A 400 nm PMMA photoresist was spin-coated on the nanostructures and placed on a baking tray and baked at 180° C. for 5 minutes. The photoresist areas were exposed using electron beam lithography (EBL) and developed in MIBK:IPA solution. This opens a window of controlled length on the nanofabric that will become an overlap region of controlled length between the nanofabric and the conductive element. E-beam-evaporated germanium-on-alumina bilayers (10 nm/100 nm, respectively) were deposited and lifted off. The exfoliation was done in NMP at 70°C. The hard mask pattern was transferred onto the nanostructures by using plasma reactive ion etching (RIE), such that the nanostructures were removed except for the active area. This defines the nanotube article. the

The NT hardmask was stripped (5 min at room temperature using 10:1 DI:peroxide) to remove Ge and a TMAH solution of stripped alumina (Microposit 321 developer, 10 min at room temperature). Deposit PMMA photoresist again. Write the pattern of conductive elements in the photoresist using EBL and develop as above. 100 nm of Pd metal was deposited using electron beam evaporation. (2nm of Ti is used as a binder between Pd and oxide.) NMP completes exfoliation at 70°C. Spin coat Shipley 1805 photoresist onto the wafer. Contact lithography machines are used to pattern larger metal contacts, which include pads and traces that connect to conductive elements. The photoresist was developed in Microposit 321 developer. 200 nm of Au (with 2 nm of Ti as a binder of Au and oxide) was deposited. NMP completes the exfoliation at 70 °C. the

Electrical testing was performed on 10 dies and device yield was measured for devices with overlapping regions of varying lengths ranging from no overlap to 500 nm overlap between nanotube elements and conductive elements. Each device contains two conductive elements (or terminals). The testing was performed at the wafer level using probe cards, and some wafers were diced and packaged by mounting and wire bonding to ceramic DIN chip packages. These devices were tested using a DC source-meter and by using an arbitrary function generator/pulse pattern generator. To read the device state, a 1 volt pulse was applied and the corresponding current was measured. High or infinite resistance corresponds to the "open" state and relatively low resistance corresponds to the "closed" state. the

Typically the "open" state exhibits a resistance across the two conductive elements on the order of GΩ, while the "closed" state exhibits a resistance on the order of 10 kΩ to several MΩ. These states can be switched between two states by voltage pulses. The desired state of the device can be set by introducing a current limit during the PROGRAM pulse (switching the device to a low-resistance state), or by introducing a current limit during the erase (ERASE) pulse (switching the device to a high-resistance state) During this period, no current constraints are introduced to set. The current limit (flexibility) of the programming pulse can be set at 80OnA and the amplitude of the pulse can be set at 5V. The amplitude of the erase pulse can be set at 8V. The programming and erasing pulse widths can be set at 6ms and 1μs, respectively. The resistance of these devices during their "open" and "closed" states can be recorded by switching the device between the "open" and "closed" states hundreds of times. Device failure is defined as a "closed" state with a resistance greater than 10MΩ and an "open" state with a resistance greater than 10MΩ. The typical error percentage was found to be less than 5% for devices with less than 100nm NT-metal overlap. the

Testing as-fabricated two-terminal nanotube switches

FIG. 18 is a flowchart illustrating the steps of an embodiment of an initial device operability test 100 . Test 100 evaluates the operation of a 2-TNS device made such as the embodiments shown herein. First the device under test (DUT) 2-TNS receives a READ operation (step 200) in order to measure the state of the fabricated DUT. The read operation (step 200 ) is typically performed by applying a voltage of 1-3V across two suitable conductive elements of the DUT, such as conductive elements 15 and 20 in FIG. 1A . The current flowing through the two conductive elements and a nanotube element such as nanotube element 25 in FIG. 1A is measured. In certain embodiments, this current is typically in the range of 100 nA-100 μA. From this information, the resistance between the first and second conductive elements of the device can be determined. This in turn allows the state of the device to be determined. In general, the impedance between the first and second conductive elements of the device is a function of the state of the device, and can also be determined by measuring the electrical characteristics of the switch. the

In general, it is preferable to fabricate the finished DUT in a state with a relatively low resistance path R _LOW between the first and second conductive elements. As noted above, the relatively lower resistance path corresponds to a "closed" or "programmed" device state in which current flows relatively easily through the nanotube element between the first and second conductive elements. The relatively higher resistance path R _HIGH corresponds to an "on" or "erased" device state in which it is relatively difficult for current to flow through the nanotube element between the first and second conductive elements. In a preferred embodiment, R _HIGH is at least ten times R _LOW . In a preferred embodiment, R _HIGH is greater than 1 MΩ. Both R _HIGH and R _LOW states are non-volatile, ie these states remain unchanged when power is removed or lost.

If the read operation (step 200) measures resistance R= _RHIGH , then the DUT is discarded. If the resistance measured by the read operation (step 200 ) is R = _RLOW , then an erase cycle is performed on the DUT (step 400 ), as will be described in more detail below.

During an erase cycle (step 400 ), the DUT preferably switches from a low resistance state of R _LOW to a high resistance state of R _HIGH . If the DUT is not erased and remains in the R _LOW state, the DUT is discarded. If the DUT is erased and transitioned to the R _HIGH state, then the DUT is accepted and subjected to a programming cycle (step 600), described in more detail below.

During the programming loop (step 600), the DUT is preferably switched from the R _HIGH state to the R _LOW state. If the DUT is not programmed and remains in the R _HIGH state, the DUT is discarded. If the DUT is programmed and transitioned to the _RLOW state, then the DUT is accepted as an operating switch (step 700). In an alternative embodiment, such as in the case of a high throughput process, the DUT may be assumed to be an operational switch as-fabricated (step 700) and the other steps in the operational test 100 omitted.

FIG. 19 is a flowchart illustrating the steps of the erase cycle (step 400). The erase cycle (step 400) preferably switches the DUT from a relatively lower resistance state to a relatively higher resistance state. FIG. 5 shows a corresponding erase waveform 410 . The erase cycle (step 400) begins with a read operation (step 210). If the read operation (step 210 ) measures the resistance of the device R = R _FIGH , then the device is already in a relatively high resistance state. Thus, the erase loop (step 400) ends. If the read operation (step 210) measures the device resistance R= _RLOW , then apply an erase waveform to the DUT (step 410). These waveforms preferably switch the DUT from a low resistance state to a high resistance state.

A maximum voltage is applied across the conductive elements of the DUT, approximately 8V in one embodiment, as shown in FIG. 20 . Reference is made to conductive elements 15 and 20 in FIG. 1A. This voltage results in a corresponding current with a maximum current indicative of a successful erase operation and in one embodiment is 15 μA. The result of the erase cycle (step 400) is independent of the polarity of the erase voltage and/or the direction of the erase current. The voltage polarity and current direction in FIG. 20 can be reversed without changing the erase process (step 400). the

In some embodiments, the maximum erase voltage is in the range of 8-10V. The erase current varies over a relatively wide range and typically depends on the nanotube density and/or controlled overlap length in the nanotube element. For a DUT with 5-10 nanotubes (or electrical network of nanotubes) spanning the distance between conductive elements, the current may be in the range of 1-30 μA, or may be higher. It is difficult to know what the operating erase current is at the start of the erase pulse because the device reacts to this voltage on an extremely short time scale, making the instantaneous erase current difficult to know. The voltage, current and success of the erase cycle (step 400) do not vary significantly with contact metallurgy such as Al, W, Ti, Pd. the

However, the voltage, current and time required for the erase cycle (step 400) can vary with the controlled overlap length between the nanotube element and the conductive element. See length 40' in Figure 1B. For the waveform 410 shown in FIG. 20, the erase time is approximately 300 ns for an exemplary overlap size between 50-100 nm. In general, shorter controlled overlap lengths generally result in shorter erase times. For example, controlled overlap lengths greater than about 100 nm can result in erase times in the millisecond range, while lengths of less than about 50 nm or less can result in erase times in the nanosecond range. There is a relationship that longer overlap generally requires a larger erase voltage magnitude. the

Waveform 410 in FIG. 20 shows a DUT erased using a single erase pulse. However, in many non-volatile applications, multiple erase pulses can be used to successfully erase the DUT. The counter (step 420) in FIG. 19 is used to count the number of erase cycles applied to the DUT). If the number of cycles reaches the maximum defined number of cycles, N _MAX , the DUT is discarded. The maximum allowable value of N _MAX depends on application requirements, process details and particular implementation, but N _MAX is not expected to exceed 10-12 cycles.

FIG. 21 is a flowchart illustrating the steps of the programming loop (step 600). The programming loop (step 600) preferably switches the DUT from a relatively high resistance state to a relatively low resistance state. A corresponding programming waveform 710 is shown in FIG. 22A . The program loop (step 600) begins with a read operation (step 230). If the read operation (step 230) measures the resistance of the device R= _RLOW , then the device is already in a low resistance state. Thus, the programming loop (step 600) ends. If the read operation (step 230) measures the device resistance R= _RHIGH , then a programming waveform is applied to the DUT (step 610). These waveforms preferably switch the DUT from a high resistance state to a low resistance state.

A maximum voltage, approximately 5V in one embodiment, is applied across the conductive elements of the DUT, as shown in Figure 22A. Reference is made to conductive elements 15 and 20 in FIG. 1A. This voltage results in a corresponding current during programming with a maximum current, which in one embodiment is 30 μA. This indicates a successful program operation. The result of the programming loop (step 600) is independent of the polarity of the programming voltage and/or the direction of the programming current. The voltage polarity and current direction in Figure 22A can be reversed without changing the programming process (step 600). the

In some embodiments, the programming voltage is preferably in the range of 3-5V. For a DUT with 5-20 nanotubes (or electrical network of nanotubes) spanning the distance between conductive elements, the current can be in the range of 1-60 μA. It is difficult to know what the operating erase current is at the start of the erase pulse because the device reacts to this voltage on an extremely short time scale, making the instantaneous erase current difficult to know. The voltage, current and success of the programming cycle (step 600) do not vary significantly with contact metallurgy such as Al, W, Ti, Pd. the

The timing of the programming loop (step 600) does not vary significantly with the controlled overlap length between the nanotube elements and the conductive elements. See length 40' of Figure 1B. the

The success of the program loop can be confirmed by a read operation (step 240). In one embodiment, a current of about 7.5 μA corresponds to a relatively lower resistance state. The current in the off state during a read operation may be in the pA range. the

Waveform 710 in Figure 22A shows a DUT programmed using a single programming pulse. However, in many non-volatile applications, multiple programming pulses can be used to successfully program the DUT. The counter in Figure 21 (step 620) is used to count the number of programming pulses applied to the DUT. If the number of cycles reaches the maximum predetermined number of cycles, M _MAX , the DUT is discarded. The maximum allowable value of M _MAX depends on application requirements, process details and particular implementation, however, M _MAX is not expected to exceed 10 to 12 cycles.

The maximum number of cycles a DUT can withstand between a high-resistance "open" state and a low-resistance "closed" state before failure is an important parameter. Waveform 710 of FIG. 22A shows the voltage and current of a DUT undergoing the following steps: read, program, read, erase. FIG. 22B shows the resistance value 650 of a DUT that was repeatedly cycled using these steps for about 50 million operations before failure. Figure 22B shows values of R _LOW in the range of about 10kΩ to 40Ω, and values of R _HIGH exceeding 10GΩ. The spread of these values reflects the resolution of the measurement equipment. The ratio of the values R _HIGH and R _LOW exceeds 5 orders of magnitude, making the corresponding states easy to detect electrically.

In general, 2-TNS with two easily detectable states can be used as non-volatile random access memory (NRAM). Two states are available as information states for the device. the

NRAM memory array structure using cells having one transistor and one double-terminal nanotube switch and method of making the same

Two-terminal nanotube switches can be used to produce non-volatile random access memory (NRAM) arrays that have many desirable features over prior art memory arrays, as described in a document entitled " Memory Arrays Using Nanotube Articles With Reprogrammable Resistance (using a memory array of nanotube products with reprogrammable resistance)" is detailed in US Patent Application No. (to be published). For example, memory devices incorporating 2-TNS arrays can achieve memory densities at least as dense as memory cells in contemporary technology, providing non-destructive readout (NDRO) operations, non-volatile data when power is lost or removed retention, and fast random access times. the

As in U.S. Patent Application No. (to be published) entitled "Non-Volatile Shadow Latch Using ANanotube Switch" filed on the same date as the present invention and co-assignee Described in more detail, minimization of NRAM cell area is desirable because NRAM arrays composed of multiple cells use less silicon area, have higher performance, and consume less power. Memory performance is enhanced and power consumption is reduced because shorter array lines have less capacitive loading. Also, less NRAM array area results in smaller chip sizes for NRAM functions, resulting in more chips per die and correspondingly lower memory costs. The cell area can be calculated for the minimum feature size F as is known in the industry. In general, for certain embodiments of NRAM cells using two-terminal nanotube switches with one select transistor, the cell density may be similar to that of DRAM cells, such as stacked capacitor DRAM cells. Here, a cell area size of about ^8F is desired, where F is the smallest feature area for a given technology. For other implementations of double-terminal nanotube switches including integrated select transistors as above, the density depends in part on the number of double-terminal switches that can be stacked. Here, a cell area size of about 4 to ^6F is desirable and can achieve similar cell densities as flash memory cells, which are denser than DRAM cells.

To make preferred embodiments of the present invention, preferred methods include one or more of the above-described methods of producing 2-TNS. While the method described above uses 2-TNS with controlled overlap between nanotube elements and conductive elements to thermally engineer the switch, any method can be used to thermally engineer the switch. the

In general, although not shown, it should be understood that the elements in the described embodiments are in electrical communication with memory operating circuitry similar to the stimulation circuitry described above. In the described NRAM array, the memory operation circuitry is in electrical communication with the bit lines, word lines, and program/erase/read lines, which allows the circuitry to select one or more cells in the array and to do so as described above for the stimulus circuitry. Change and/or determine the state of a cell in a similar manner as described above. the

One method of fabricating an NRAM array is shown in Figures 23A-23E. FIG. 23A shows an initial structure 1300 with a planarized upper surface 1355 . The cell selection transistor 1335 includes a source 1315 , a drain 1310 and a channel region 1330 formed in the silicon substrate 1305 . Gates 1320, fabricated with sidewall spacers 1325 and a portion of the array wordlines described further below in the array plan view, control the ON and OFF states of channel region 1330 using well-known methods of MOSFET device operation. Studs 1340 embedded in dielectric 1350 provide a conductive path from source 1315 to planarized surface 1355 of initial structure 1300 . Studs 1345 embedded in dielectric 1350 provide an electrical path from drain 1310 to planarized surface 1355 of initial structure 1300 . the

Preferred methods further described above then form intermediate structures 1070A and 1070B, which are 2-TNS devices in electrical communication with underlying transistors, as shown in Figure 23B. Structure 1070A corresponds to non-volatile two-terminal switch 1070 as shown in Figure 8F. Structure 1070B is a mirror image of structure 1070A with corresponding wiring and interconnections. Conductive element 1005, such as 2-TNS 1070A, overlaps and makes near-ohmic contact with nanotube element 1025 and post 1340. This forms a conductive path between the nanotube element 1025 and the source 1315 of the transistor 1335, enabling erase, program and/or read operations in the 2-TNS 1070A. The 2-TNS 1070B is connected to the source of the transistor below the surface 1355 of the structure 1300 in a similar manner. the

Next, preferred methods deposit and planarize an insulator 1360, as shown in Figure 23C. Insulator 1360 may be, for example, TEOS or another insulator deposited and planarized using known semiconductor fabrication methods. the

Next, preferred methods etch vias in insulator 1360 and insulator 1000 using known semiconductor fabrication methods to expose the top surface of post 1345, as shown in cross-section 1395 of FIG. 23D. the

Next, preferred methods deposit and pattern a conductive layer to form post 1370 and bitline 1375 as shown in cross-section 1395 of Figure 23D and bitline 1375' as shown in corresponding plan view 1395' of Figure 23E. A conductive path is formed between bit line 1375 (1375') and drain 1310 through studs 1370 and 1345. If transistor 1335 is in the OFF state, channel region 1330 is not formed and bit line 1375 (1375') is electrically isolated from nanotube element 1025. However, if transistor 1335 is in the ON state, a conductive channel connecting drain 1310 and source 1315 is formed. This forms a conductive path between bit line 1375 (1375') and nanotube element 1025 through posts 1370 and 1345, drain 1310, channel 1330, source 1315, post 1340, and conductive element 1005. the

Figures 23D and 23E show different views of transistor 1335, which is used to select (or deselect) cell 1390A using gate 1320, which is also part of word line 1320'. Other cells, such as cell 1390B, can be selected by activating other word lines, such as 1325'. Conductive element 1055' overlaps nanotube element 1025 in cell 1390A by a controlled overlap length 1050 of preferably 1-150 nm, and simultaneously overlaps other nanotube elements in other memory cells by about the same controlled overlap length 1050. Thus, conductive element 1055' interconnects multiple cells, and this element is used in erase, program and/or read operations as described in detail above. Nonvolatile memory cells 1390A and 1390B, which include a select transistor and a nonvolatile two-terminal switch layout, are mirror images of each other. Additional preferred methods of accomplishing the fabrication and passivation of the NRAM function (not shown) use well-known semiconductor fabrication techniques. the

Memory cells 1390A and 1390B (FIG. 23E) corresponding to nonvolatile two-terminal switch 1070 shown in FIG. 8F are shown in memory array cross-section 1395 and corresponding memory plan view 1395', and result in a cell area of 10F2. the

The second fabrication method, shown and described in FIG. 24, reduces the cell area of cells 1390A and 1390B by approximately 30% by using vertically oriented SWNT fabric switches 1295A and 1295B as shown in FIG. Tighter source-source spacing between cells is achieved, as described further below. the

FIG. 24A shows an initial structure 1400 with a planarized top structure 1455 . Structure 1400 reduces the spacing between source 1415 diffusions relative to the spacing between source 1315 diffusions shown in FIG. 23A. The closer spacing of the source diffusions requires a different approach to fabricating the non-volatile two-terminal intermediate structure, as described further below. The cell selection transistor 1435 includes a source 1415 , a drain 1410 and a channel region 1430 formed on the silicon substrate 1405 . On gate 1420 fabricated with sidewall spacers 1425 and a portion of the array wordlines described further below in Array Plan View, the ON and OFF states of channel region 1430 are controlled using well known MOSFET device operation methods. Studs 1440 embedded in dielectric 1450 provide a conductive path from source 1415 to planarized surface 1455 of partially fabricated semiconductor structure 1400 . Studs 1445 embedded in dielectric 1450 provide a conductive path from drain 1410 to planarized surface 1455 of initial structure 1400 . the

Preferred methods further described above then form intermediate structures 1295A and 1295B of two-terminal nanotube memory devices interconnected with respective underlying transistors, as shown in Figure 24B. The vertical orientation of intermediate structures 1295A and 1295B is used to position adjacent nonvolatile two-terminal devices at more closely spaced source diffusions 1415 . Structure 1295A is the same as non-volatile two-terminal switch structure 1295A as shown in Figure 15N. Structure 1295B is the same as non-volatile two-terminal switch structure 1295B shown in Figure 15N. Structure 1295B is a mirror image of structure 1295A with corresponding wiring and interconnections. For example, conductive element 1205A of 2-TNS 1295A overlaps and makes near-ohmic contact with nanotube element 1255A and post 1440. This forms a conductive path between nanotube element 1255A and transistor 1435 source 1415, enabling erase, program and/or read operations in 2-TNS 1070A. 2-TNS 1270B is similarly connected to the source of the transistor below surface 1455 of structure 1400. the

Next, preferred methods deposit and planarize an insulator 1460, as shown in Figure 24C. Insulator 1460 may be, for example, TEOS or another insulator deposited and planarized using known semiconductor fabrication methods. the

Next, preferred methods use known semiconductor fabrication methods to etch vias in insulator 1460 and insulator 1200, exposing the upper surface of stud 1445 as shown in cross-sectional view 1495 of FIG. 24D. the

Next, preferred methods deposit and pattern a conductive layer to form conductive posts 1470 and bit line cross-sections 1475 as shown in FIG. 24D and bit line plan 1475' as shown in corresponding plan view 1495' in FIG. 24E. A conductive path is formed between bit line 1475 (1475') and drain 1410 through studs 1470 and 1445. If transistor 1435 is in the OFF state, channel region 1430 is not formed and bit line 1475 (1475') is electrically isolated from nanotube element 1255A. However, if transistor 1435 is in the ON state, a conductive channel connecting drain 1410 and source 1415 is formed in region 1430 . This forms a conductive path between bit line 1475 (1475') and nanotube element 1255A through posts 1470 and 1445, drain 1410, channel 1430, source 1415, post 1440, and conductive element 1205A. the

24D and 24E show different views of transistor 1435 used to select (or deselect) cell 1490A using gate 1420, which is also part of word line 1420'. Conductive element 1270A (1270A') overlaps nanotube element 1255A by a controlled overlap length 1275A of preferably 1-150 nm, while overlapping other nanotube elements in another memory cell by approximately the same controlled overlap length. Thus, conductive element 1270A interconnects multiple cells, and the cell is used in the erase, program, and/or read operations described in detail above. Nonvolatile memory cells 1490A and 1490B, which include a select transistor and a nonvolatile two-terminal switch layout, are mirror images of each other. Additional preferred methods of accomplishing the fabrication and passivation of the NRAM function (not shown) use well-known semiconductor fabrication techniques. the

Memory cells 1490A and 1490B (FIG. 24E) have the same cell area of about ^7E2 , which is about 30% smaller than cells 1390A and 1390B (FIG. 23E), which have a cell area of about ^10F2 .

Another method of fabrication that reduces the cell area of cells 1390A and 1390B shown in FIG. 13E by approximately 30% is described and illustrated in FIGS. 25A-E . This can be accomplished by interchanging cells 1070A and 1070B of FIG. 23D so that the conductive element is adjacent to the stud connecting the bit line to the drain. This enables tighter source-source spacing between adjacent cells, as described further below. An additional insulation step is required on the upper portion of the stud that contacts the bit line to prevent shorts between the bit line and conductive elements due to via misregistration, as described further below. the

FIG. 25A shows an initial structure 1500 with a planarized top structure 1555 . The cell selection transistor 1535 includes a source 1515 , a drain 1510 and a channel region 1530 formed on the silicon substrate 1505 . The ON and OFF states of the channel region 1530 are controlled by using well known methods of MOSFET device operation at the gate 1520 fabricated through sidewall spacers 1525 and a portion of the array wordlines as described further below in Array Plan View. Posts 1540 embedded in dielectric 1550 provide a conductive path from source 1515 to planarized surface 1555 of initial structure 1500 . Studs 1545 embedded in dielectric 1550 provide a conductive path from drain 1510 to planarized surface 1555 of initial structure 1500 . the

The preferred method described further above then forms 2-TNS 1070A and 1070B interconnected with respective underlying transistors, as shown in Figure 25B. Structure 1070A corresponds to non-volatile two-terminal switch structure 1070 shown in FIG. 8F. Structure 1070B is a mirror image of structure 1070A with corresponding wiring and interconnections. Compared to FIG. 23B , the positions of 2-TNS 1070A and 1070B are swapped with respect to corresponding underlying transistors, such as transistor 1535. The conductive element 1005 of the 2-TNS overlaps and makes near-ohmic contact with the nanotube element 1025 and stud 1540 . This forms a conductive path between the nanotube element 1025 and the source 1515 of the transistor 1535, enabling erase, program and/or read operations in the 2-TNS 1070A. the

Next, preferred methods deposit and planarize an insulator 1560, as shown in Figure 25C. Insulator 1560 may be, for example, TEOS or another insulator deposited and planarized using known semiconductor fabrication methods. the

Next, preferred methods use known semiconductor fabrication methods to etch vias in insulator 1560 and insulator 1000, exposing the top surface of stud 1545 as shown in cross section 1595 of FIG. 25D. the

Next, preferred methods deposit a conformal insulating film and coat the via opening sidewalls with an insulator 1580 . If the vias are not properly aligned and expose conductive element 1055 , insulator 1580 will insulate the exposed portion of conductive element 1055 and prevent a short circuit with post 1570 . Insulator 1580 may be, for example, SiO ₂ .

Next, preferred methods deposit and pattern a conductive layer to form conductive posts 1570 and bitline cross-sections 1575 as shown in Figure 25D and bitline plan 1575' as shown in corresponding plan view 1595' in Figure 25E. A conductive path is formed between bit line 1575 (1575') and drain 1510 through studs 1570 and 1545. If transistor 1535 is in the OFF state, channel region 1530 is not formed, and bit line 1575 (1575') is electrically isolated from nanotube element 1025. However, if transistor 1535 is in the ON state, a conductive channel connecting drain 1510 and source 1515 is formed. This forms a conductive path between bit line 1575 (1575') and nanotube element 1025 through posts 1570 and 1545, drain 1510, channel 1530, source 1515, post 1540, and conductive element 1005. the

Figures 25D and 25E show different views of transistor 1535 used to select (or deselect) cell 1590A using gate 1520, which is also part of word line 1520'. Other cells, such as cell 1590B, can be selected by activating other word lines, such as 1525'. Conductive elements 1055 (1055') form and interconnect switch regions 1050 in a plurality of nonvolatile memory cells such as 1590A and 1590B (FIG. 25E), and are used during erasing, programming, and/or reading used in operation. Nonvolatile memory cells 1590A and 1590B, which include a select transistor and a nonvolatile two-terminal switch layout, are mirror images of each other. Additional preferred methods of accomplishing the fabrication and passivation of the NRAM function (not shown) use well-known semiconductor fabrication techniques. the

Cells 1590A and 1590B (FIG. 25E) have the same cell area of about ^7F , which is the same area as cells 1490A and 1490B (FIG. 24E) and 30 less than ^cells 1390A and 1390B (FIG. 23E), which have a cell area of about 10F. %.

Figure 26 shows and describes another method of fabricating an NRAM array with 2-TNS. Non-volatile two-terminal nanotube switch 2370a corresponds to non-volatile two-terminal nanotube switch 2370 shown in FIG. 13 . As shown in memory array structure 2400 shown in cross-section in FIG. 26, nonvolatile memory cell structure 2490A includes a transistor 2435 interconnected to a bit line, a first word line, and a second word line. Non-volatile 2-TNS 2370A, described further below. Non-volatile memory cell structure 2490B is a mirror image of 2490A, and 2-TNS 2370B is a mirror image of 2-TNS 2370A. the

A preferred method is to fabricate an NRAM array cell structure 2400 as shown in FIG. 26 . First, preferred methods fabricate an initial structure 2402 with a planarized surface 2404 . the

Preferred methods then fabricate an intermediate structure comprising mirror images 2-TNS 2370A and 2370B on surface 2404 of initial structure 2402 using preferred methods further described above with respect to FIGS. 12A-13 . the

Then, the preferred method completes the fabrication of non-volatile memory chips on the intermediate structure to complete the NRAM memory array structure 2400 as shown in FIG. 26 . the

In operation, a conductive path is formed between bit line 2475 and drain 2410 through studs 2445 and 2470 in dielectric 2460 . If transistor 2435 is in the OFF state, channel region 2430 is not formed and bit line 2475 is electrically isolated from nanotube element 2325 . However, if transistor 2435 is in the ON state, a conductive channel connecting drain 2410 and source 2415 is formed. This forms a conductive path between bit line 2475 and nanotube element 2325 through posts 2470 and 2445, drain 2410, channel 2430, source 2415, post 2440, and conductive element 2305A. the

Transistor 2435 is used to select (or deselect) cell 2490A using gate 2420, which is also part of a common word line shared with other cells in the corresponding row. Other cells, such as cell 2490B, can be selected by activating other word lines. In NRAM memory array structure 2400, conductive element 2310A overlaps nanotube element 2325 in region 2350 of a controlled overlap length, while overlapping other nanotube elements in other cells by the same controlled overlap length. Accordingly, conductive elements 2310A interconnect corresponding rows of cells similar to 2490A, forming a common electrical connection for use in erase, program, and/or read operations as described above. Nonvolatile memory cells 2490A and 2490B contain a select transistor and a nonvolatile two-terminal switch and have corresponding layouts that are mirror images of each other. Additional preferred methods of accomplishing the fabrication and passivation of the NRAM function (not shown) use well-known semiconductor fabrication techniques. the

Another method of fabricating an NRAM array with 2-TNS is shown and described in FIG. 27 . As shown in memory array structure 2700 shown in cross-section in FIG. 27, nonvolatile memory cell structure 2790A includes a transistor 2735 interconnected to a bit line, a first word line, and a second word line. 2 - TNS2670A, described further below. the

Non-volatile two-terminal nanotube switch 2670A corresponds to non-volatile two-terminal nanotube switch 2670 shown in FIG. 11C . Non-volatile memory cell structure 2790B is a mirror image of 2790A, and 2-TNS 2670B is a mirror image of 2-TNS 2670A. the

A preferred method is to fabricate an NRAM array cell structure 2700 as shown in FIG. 27 . First, preferred methods fabricate an initial structure 2702 with a planarized surface 2704 . the

Preferred methods then fabricate an intermediate structure comprising 2-TNS 2670A and 2670B on surface 2704 of initial structure 2702 using preferred methods further described above with respect to FIGS. 11A-11C . the

Then, the preferred method completes the fabrication of the non-volatile memory chips on the intermediate structure to complete the NRAM memory array structure 2700 as shown in FIG. 27 . the

In operation, a conductive path is formed between bit line 2775 and drain 2710 through studs 2745 and 2770 in dielectric 2760 . If transistor 2735 is in the OFF state, channel region 2730 is not formed and bit line 2775 is electrically isolated from nanotube element 2625 . However, if transistor 2735 is in the ON state, a conductive channel connecting drain 2710 and source 2715 is formed. This forms a conductive path between bit line 2775 and nanotube element 2625 through posts 2770 and 2745, drain 2710, channel 2730, source 2715, post 2740, and conductive element 2605A. the

Transistor 2735 is used to select (or deselect) cell 2790A using gate 2720, which is also part of a common word line shared with other cells in the corresponding row. Other cells, such as cell 2790B, can be selected by activating other word lines. In NRAM memory array structure 2700, conductive element 2610A overlaps nanotube element 2625 in a region 2640 of a controlled overlap length of, for example, 1-150 nm, while overlapping other nanotube elements in other cells by approximately the same controlled overlap length . Accordingly, conductive element 2610A is interconnected in parallel with other cells similar to cell 2790A in a corresponding row, forming a common electrical connection for use in erase, program, and/or read operations as described in detail above. Nonvolatile memory cells 2790A and 2790B each include a select transistor and a nonvolatile two-terminal switch, and have corresponding layouts that are mirror images of each other. Additional preferred methods of accomplishing the fabrication and passivation of the NRAM function (not shown) use well-known semiconductor fabrication techniques. the

Figure 28 describes and illustrates another method of fabricating an NRAM array with 2-TNS. The non-volatile two-terminal nanotube switch 2895A shown in Figure 28 corresponds to the vertically oriented non-volatile two-terminal nanotube switch 2895A shown in Figure 16L. 2-TNS 2895A is interconnected with transistor 2935 as shown in memory array structure 2900 in cross-section in FIG. 28 . Vertically oriented switches are designed to minimize NRAM cell size (area). the

It is desirable to simplify the fabrication method and simultaneously reduce the cell area and the corresponding NRAM array area, because an NRAM array composed of multiple cells uses less silicon area, has higher performance, and consumes less power. Vertically oriented switches are designed to reduce NRAM cell size (area). the

Nonvolatile memory cell structure 2990A includes 2-TNS 2895A interconnected with transistor 2935 and with a bit line, a first word line, and a second word line, as described further below. Non-volatile memory cell structure 2990B is a mirror image of 2990A, and 2-TNS 2895B is a mirror image of 2895A. Insulator 2925 corresponds to insulator 2815 in Figure 16L. the

A preferred method fabricates the NRAM array element structure 2900 shown in FIG. 28 . the

First, preferred methods fabricate an initial structure 2902 with a planarized surface 2904 . the

Preferred methods then fabricate an intermediate structure comprising 2-TNS 2895A and 2895B on surface 2904 of initial structure 2902 using preferred methods further described above with respect to FIGS. 16A-16L . the

Then, the preferred method completes the fabrication of the non-volatile memory chips on the intermediate structure to complete the NRAM memory array structure 2900 as shown in FIG. 28 . the

In operation, a conductive path is formed between bit line 2975 and drain 2910 through studs 2945 and 2970 in dielectric 2960 . If transistor 2935 is in the OFF state, channel region 2930 is not formed and bit line 2975 is electrically isolated from nanotube element 2890A. However, if transistor 2935 is in the ON state, a conductive channel connecting drain 2910 and source 2915 is formed. This forms a conductive path between bit line 2975 and nanotube element 2890A through posts 2970 and 2945, drain 2910, channel 2930, source 2915, post 2940, and conductive element 2855A. the

Transistor 2935 is used to select (or deselect) cell 2895A using gate 2920, which is also part of a common word line shared with other cells in the corresponding row. Other cells, such as cell 2895B, can be selected by activating other word lines. In NRAM memory array structure 2900, conductive element 2850A overlaps nanotube element 2890A by a controlled overlap length 2892A, eg, 1-150 nm, while overlapping other nanotube elements in other cells by approximately the same controlled overlap length. Thus, conductive element 2850A interconnects corresponding rows of cells similar to cell 2895A, forming a common electrical connection used in erase, program, and/or read operations as described above. the

Nonvolatile memory cells 2895A and 2895B of corresponding layouts containing one select transistor and one nonvolatile two-terminal switch are mirror images of each other. Additional preferred methods of accomplishing the fabrication and passivation of the NRAM function (not shown) use well-known semiconductor fabrication techniques. the

Figure 29 describes and illustrates another method of fabricating an NRAM array with 2-TNS. The non-volatile two-terminal nanotube switch 3095A shown in Figure 29 corresponds to the vertically oriented non-volatile two-terminal nanotube switch 3095A shown in Figure 17M. 2- TNS 3095A is interconnected with transistor 3135 as shown in memory array structure 3100 in cross-section in FIG. 29 . Vertically oriented switches are designed to minimize NRAM cell size (area). the

Nonvolatile memory cell structure 3190A includes 2-TNS 3095A interconnected with transistor 3135 and with one bit line, one first word line, and one second word line, as described further below. Non-volatile memory cell structure 3190B is a mirror image of 3190A, and non-volatile two-terminal nanotube switch array cell structure 3095B is a mirror image of 3095A. the

A preferred method is to fabricate an NRAM array cell structure 3100 as shown in FIG. 31 . the

First, preferred methods fabricate an initial structure 3102 with a planarized surface 3104 . the

Preferred methods then fabricate an intermediate structure comprising 2-TNS 3095A and 3095B on surface 3104 of initial structure 3102 using preferred methods further described above with respect to FIGS. 17A-17M . the

Then, the preferred method completes the fabrication of non-volatile memory chips on the intermediate structure to complete the NRAM memory array structure 3100 as shown in FIG. 29 . the

In operation, a conductive path is formed between bit line 3175 and drain 3110 through studs 3145 and 3170 in dielectric 3160 . If transistor 3135 is in the OFF state, channel region 3130 is not formed and bit line 3175 is electrically isolated from nanotube element 3090A. However, if transistor 3135 is in the ON state, a conductive channel connecting drain 3110 and source 3115 is formed. This forms a conductive path between bit line 3175 and nanotube element 3090A through posts 3170 and 3145, drain 3110, channel 3130, source 3115, post 3140, and conductive element 3055A. the

Transistor 3135 is used to select (or deselect) cell 3190A using gate 3120, which is also part of a common word line shared with other cells in the corresponding row. Other cells, such as cell 3190B, can be selected by activating other word lines. In NRAM memory array structure 3100, conductive element 3050A overlaps nanotube element 3090A by a controlled overlap length 3092A, eg, 1-150 nm, while overlapping other nanotube elements in other cells by approximately the same controlled overlap length. Thus, conductive element 3050A interconnects corresponding rows of cells similar to cell 3190A, forming a common electrical connection for use in erase, program, and/or read operations as described above. the

Nonvolatile memory cells 3095A and 3095B, including a select transistor and a nonvolatile two-terminal switch and corresponding layout, are mirror images of each other. Additional preferred methods of accomplishing the fabrication and passivation of the NRAM function (not shown) use well-known semiconductor fabrication techniques. the

Using the methods and embodiments described herein, one skilled in the art can fabricate a non-volatile random access memory using either embodiment of a two-terminal nanotube switch. It is even possible to fabricate certain NRAM arrays that include more than one different implementation of two-terminal nanoswitches. the

For example, the picture frame non-volatile two-terminal switch 1870 shown in Figures 14I and 14J can be replaced by 2-TNS 1070A and 1070B in the NRAM cells shown in Figures 23D and 23E and Figures 25D and 25E. Other NRAM cells (not shown) can be designed to take advantage of the dense picture frame non-volatile two-terminal nanotube switch 1870. the

Nonvolatile two-terminal nanotube switches as high-density crosspoint switches

Data processing, communications, and customer solutions dictate semiconductor design, test, burn-in, and packaging technology selection. Examples of product coverage include: smart cards/games, mobile/handheld devices such as cell phones, personal computers, desktops/workstations, and servers/mainframes. These requirements are driven by miniaturization, performance, power, reliability, quality and time to market. For some applications, such as aviation, components are exposed to harsh environments such as high radiation levels. In some applications, security features such as nearly impossible reverse engineering are also required. the

Time to market, including rapid hardware prototyping and production ramp-up, has resulted in increased use of pre-wired reconfigurable logic such as field programmable gate arrays (FPGAs). For many applications, pre-wired reprogrammable logic such as FPGAs are chosen instead of ASIC chips because the complexity of ASIC logic chips increases to the 15-20 (or more) conductor level, resulting in higher cost and longer time to market. The lower density of pre-wired reprogrammable logic chips than ASIC chips makes it more desirable. Some ASIC designs are beginning to include embedded pre-wired reconfigurable logic regions as well. the

The size and electrical characteristics of the prewired switches essentially determine the reconfigurable logic architecture and potential use. The smallest pre-wired switch currently in use is a prior art non-volatile one-time programmable (OPT) double-terminal anti-fuse switch between logic lines as shown in Figures 30A and 30B. The non-volatile OTP antifuse has the smallest size (area) because it is a crosspoint switch placed between pre-wired logic conductors and can be programmed to selectively interconnect various logic conductors, as shown in Figure 30A and 30B. A prior art non-volatile OTP double-terminal antifuse for designing pre-wired reconfigurable logic functions is described in the following reference: "Programmable Elements and Their Impact on FPGA Architecture, Performance, and Radiation Hardness (Programmable Components and Their Effects on FPGA Architecture, Performance, and Radiation Hardness), Altera, 1995. The referenced PowerPoint presentation "80_McCollum_5_PROGRAMMABLE LOGIC_ALTERA.ppt" can be found at http://klabs.org . The prior art finds the use of a dielectric layer between two metal layers to form an antifuse.

FIG. 30A shows a prior art antifuse 1900 in an ON (closed) or programmed conductive state 1920 . Figure 30A shows a prior art antifuse 1900 in an OFF (open) non-conductive state 1910 prior to programming. When antifuse 1900 is in conductive state 1920, conductors 1930 and 1940 are electrically connected by a resistance of less than 100 ohms. In the non-conductive state, conductors 1930 and 1940 are not electrically connected, and the capacitance added by the antifuse is very small, eg, less than 1 fF per node. the

Advantages of prior art antifuse 1900 include density, low capacitance, relatively low resistance, and non-volatility achieved by using a crosspoint switch configuration. Also, it is difficult to "reverse engineer" chips to trace logic functions, which is important in security applications. The switch is able to withstand harsh environments such as high temperatures and high radiation levels (radiation hardness switch). the

Drawbacks of the prior art antifuse 1900 include high voltage programming (10-12V) at high currents (typically 10mA per antifuse). Also, because antifuses can only be programmed once (OTP), it is not possible to completely weed out defective antifuses from pre-wired reprogrammable logic portions. Because of these and other constraints, programming is relatively complex and is usually done in the socket (test fixture) prior to use in the system. the

What is needed is a way to maintain this density and other advantages of the prior art antifuse 1900 while eliminating or reducing the disadvantages (limitations), especially the elimination of defective switches and Eliminates the need to program switches in receptacles prior to use in a system. the

Non-volatile two-terminal nanotube switches such as the 2-TNS 1870 shown in Figures 14I and 14J and other switches described further above can eliminate or substantially reduce the limitations of the prior art switch 1900 shown in Figures 30A and 30B. For example 2-TNS 1870 can be used in place of prior art antifuse switch 1900. 2-TNS 1870 is easily integrated between metal layers, is a small crosspoint switch, and most importantly, can be repeatedly erased as further described above. division and programming. As a result, a pre-wired reconfigurable logic section can be assembled with an integrated and fully tested 2-TNS ready for programming. the

In certain embodiments, non-volatile two-terminal nanotube switches have an erase voltage of 8-10 V, a program voltage of 4-6 V, and relatively low program and erase currents, typically less than 100 μA per switch. Because these switches are easy to detect and require approximately 100 times less current to program than prior art antifuse 1900, 2-TNS based prewired reconfigurable logic chips can be programmed in a system environment. The harsh environment tolerance and high security of the nanotubes (nearly impossible to "reverse engineer") means that the logic can be used in demanding aerospace applications and can be programmed in space, for example. the

Figure 31 shows a cross-section of a non-volatile nanotube crosspoint switch 2000 resulting from the integration of the 2-TNS 1870 shown in Figures 14I and 14J with conductor layers 2060 and 2055. Conductor 2055 corresponds to conductive element 1855 shown in FIG. 141 and overlaps nanotube element 1825 in region 1850 by a controlled overlap length, eg, 1-150 nm, as further described above. Insulator 2002 corresponds to insulator 1800 shown in Figure 14I. Conductor 2060 is in electrical contact with nanotube element 1825 of 2-TNS 1870 through terminal post 1805. the

Conductors 2055 and 2060 are in relatively good electrical contact when non-volatile nanotube crosspoint switch 2000 is in the relatively low resistance "closed" or ON state. When non-volatile nanotube crosspoint switch 2000 is in the relatively high resistance "open" or ON state, conductors 2055 and 2060 are in relatively poor electrical contact. the

32A and 32B show a schematic diagram 2100 of the non-volatile nanotube crosspoint switch 2000 shown in FIG. 31 . 32A and 32B illustrate the use of a non-volatile nanotube crosspoint switch 2100 in place of the prior art antifuse crosspoint switch 1900 shown in FIGS. 30A and 30B . Conductors 2130 and 2140 in FIGS. 32A and 32B correspond to conductors 1930 and 1940 in FIGS. 30A and 30B , respectively. Figure 32A shows the nanotube crosspoint switch 2100 in the as-fabricated/programmed "closed" state 2110 as described further above. The "closed" state may be characterized by a relatively low resistance between conductors 2130 and 2140, such as less than 100 ohms or less than 1000 ohms in certain embodiments. Figure 32B shows the nanotube crosspoint switch 2100 in the erased "on" state 2120 described further above. State 2120 of nanotube crosspoint switch 2100 corresponds to state 1910 of prior art antifuse 1900 . State 2110 of nanotube crosspoint switch 2100 corresponds to state 1920 of prior art antifuse 1900 . Nanotube crosspoint switch 2100 can be programmed to change from state 2120 to state 2110 and then erased to return to state 2120 . As described further above, millions of such cycles have been observed. Operation of each switch can be verified prior to shipment of products containing pre-wired reconfigurable logic. the

Due to the relatively low programming current of the non-volatile nanotube crosspoint switch 2100, on-chip erase and program functions are also possible in a system environment. The high voltage requirements described further above can be generated on-chip as described in US Patent No. 6,346,846 to Bertin et al. High voltages can be programmed onto the chip as described in US Patent No. 5,818,748 to Bertin et al. the

The above sections describing Figures 14, 31 and 32 describe a two-terminal nanotube switch as a high-density electrically reprogrammable crosspoint switch with a first conductive element and terminal (vertical filled via) on the top surface of the insulator. ) provide a reprogrammable contact between one end. The opposite end of the terminal contacts a second conductor which contacts the lower surface of the same insulator. The above sections describe the application of electrically reprogrammable crosspoint switches. the

Two-terminal nanotube switches as high-density electrically reprogrammable nanotube via interconnects between two or more wiring layers

Other embodiments of electrically reprogrammable via interconnect switches are described below. In these embodiments, nanotube elements replace stud via interconnects that typically use conductive materials such as tungsten, aluminum, copper, and/or other conductors. The nanotube elements provide electrically reprogrammable connections between layers using the non-volatile nanotube two-terminal switches described further above. These embodiments enable electrically reprogrammable wiring interconnects after chip fabrication and packaging. the

Electrically reprogrammable via interconnects based on nanotube elements can withstand harsh environments such as high-temperature operation (e.g., over 200 degrees Celsius) and can withstand high radiation levels. High temperature tolerance and radiation tolerance derive from specific properties of nanotube elements. the

Electrically reprogrammable interconnects based on nanotube elements offer high security. The switch connection may be electrically reprogrammable (eg open so that the ON state of the switch is erased) on the nanosecond or up to microsecond scale, subject to safety considerations. Even using hardware reverse engineering, this interconnection network cannot be determined. the

In general, although not shown, it should be understood that elements of the described embodiments may be in electrical communication with stimulation circuits similar to those described above. In the reprogrammable interconnect, the stimulus circuit is in electrical communication with the conductive terminals and one or more wiring layer conductive terminals, which enables the circuit to operate in the same manner as described above for the stimulus circuit that changes the switch between two states. Reprogrammatically make or break interconnections between one or more wiring layers in a similar manner as described above. the

33A-33G illustrate one method of fabricating a two-terminal nanotube switch as a high-density reprogrammable nanotube via interconnect between two wiring layers. the

First, preferred methods deposit a conductor 3205 of controlled thickness, as shown in Figure 33A. Conductor 3205 may have a thickness in the range of 5-500 nm and may use metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and other suitable metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used.

Preferred methods then use known industry techniques to deposit and pattern conductors 3210 defining conductor lengths, widths (not shown) and openings 3215 to accommodate vertical vias as shown in FIG. 33A. An opening 3215 in conductor 3210 is formed using a known RIE etch selected for conductor 3205, opening 3215 is shown in cross-section in FIG. 33A. Conductor 3210 is wide enough that hole 3215 leaves a sufficiently wide area (not shown) around opening 3215 that conductor 3210 remains a continuous conductor. The width and length of conductor 3205 are patterned using the same masking steps used to define the dimensions of conductor 3210 such that conductors 3205 and 3210 form a composite conductor where the upper surface of conductor 3205 and the lower surface of conductor 3210 are in electrical and mechanical contact , except opening 3215. Conductor 3210 may have a thickness in the range of 5-500 nm and may use metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and other suitable metals. metals, and combinations thereof. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used.

Next, preferred methods deposit and planarize insulator 3220 using known industry methods. An insulator 3220 fills the opening 3215 and provides a planar upper surface 3222, as shown in Figure 33A. The insulator 3220 may be SiO ₂ , SiN, Al ₂ O ₃ , BeO, polyimide, or other suitable insulating material with a thickness in the range of 2-500 nm. The assembly shown in Figure 33A can be considered as an initial structure.

Next, preferred methods use known industry techniques to deposit and pattern conductor 3225 on top surface 3222 of insulator 3220 and planarize the surface to form insulator 3224 as shown in FIG. 33B . The conductor 3225 has a thickness in the range of 5-500 nm, and metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and other suitable metals can be used, and its combination. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors including CNTs themselves (e.g., single-walled, multi-walled, and/or double-walled), or metal alloys such as RuN, RuO, TiN, TaN, CoSi _x And other conductive nitrides, oxides or silicides of TiSi _x . Other types of conductive and semiconducting materials may also be used.

Next, preferred methods deposit, expose and form a mask layer 3230 with openings 3235 as shown in FIG. 33B to define the locations of electrically reprogrammable vias as described further below. the

Next, preferred methods directionally etch conductor 3225, directionally etch insulator 3220, and directionally etch conductor 3205, stopping on the surface of insulator 3200 to form via 3240 as shown in Figure 33C. Known directional etch fabrication methods using reactive ion etching (RIE) may be used to form recesses 3240, for example. the

Next, preferred methods deposit conformal nanofabric layer 3245 on the bottom and sidewalls of recess 3240, on the upper surfaces of conductive elements 3225A and 3225B, and on the upper surface of insulator 3224, as shown in Figure 33D. Deposition of structures 3245 may be accomplished by techniques described in the incorporated patent documents. the

Next, preferred methods fill the recess 3240 with an insulator 3250, such as TEOS, using known industry techniques to planarize the surface of the insulator 3250, as shown in Figure 33E. the

Next, preferred methods use known industry methods to pattern and etch insulator 3250, exposing a portion of nanofabric 3245 as shown in FIG. 33F. Etching using RIE may remove exposed portions of nanofabric 3245. The nanostructures 3245 may be only partially removed by the etching step of the insulator 3250, or may not be removed at all. the

If the nanofabric 3245 is not removed in its entirety, a preferred method may remove the exposed portion of the nanofabric using, for example, ashing or other suitable techniques as described in the incorporated patent references. This results in nanotube element 3267 as shown in Figure 33F. the

Next, preferred methods deposit and planarize an insulator 3260, completing an electrically reprogrammable via interconnect structure 3280 based on non-volatile nanotube elements as shown in FIG. 33G. the

Structure 3280 includes conductive element 3225A overlapping nanotube element 3267 at the sidewalls and upper surface of conductor 3225A and forming a near-ohmic contact. Structure 3280 also includes conductive element 3225B that overlaps and forms near-ohmic contact with nanotube element 3267 at the sidewalls and upper surface of conductor 3225B. Sidewalls 3275 of nanotube element 3267 form vias between conductive element 3225A and conductive element 3205A, and between conductive element 3225B and conductive element 3205B. Conductors 3210A and 3210B in electrical and mechanical contact with corresponding conductive elements 3205A and 3205B may be used for interconnection. the

Nanotube elements 3267 overlap the sidewalls of conductor 3205A for a controlled overlap length determined by the thickness of conductive element 3205A. Nanotube elements 3267 also overlap the sidewalls of conductor 3205B by a controlled overlap length determined by the thickness of conductive element 3205B. Thus, conductive element 3225A, nanotube element 3267, and conductive element 3205A form a first 2-TNS 3270A, and conductive element 3225B, nanotube element 3267, and conductive element 3205B form a second 2-TNS 3270B. the

In operation, if 2-TNS 3170A is in the closed state, a good (eg, relatively low resistance) electrical connection is formed between conductive elements 3225A and 3205A. In certain embodiments, the resistance between elements 3225A and 3205A may be in the range of, for example, 10-1000Ω for the "closed" state. If 2-TNS 3270 is in the "on" state, there is a relatively poor (eg, relatively high resistance) electrical connection between conductive elements 3225A and 3205A. In certain embodiments, the resistance between elements 3225A and 3205A versus the "on" state can be in the range of, for example, greater than 1 MΩ, or greater than 1 GΩ. Switch 3270B has corresponding states and characteristics. This article illustrates the general operation and characteristics of a nonvolatile two-terminal nanotube switch. the

Two-terminal nanotube switches as high-density electrically reprogrammable nanotube via interconnects between more than two wiring layers

In certain applications, it is desirable to have non-volatile electrically reprogrammable nanotube via interconnects between more than two wiring layers. In the example described further below, a non-volatile electrically reprogrammable interconnection between four wiring layers is shown. Four layers are for illustration purposes only; many more levels are possible. the

Figure 34A shows a similar structure to that shown in Figure 33C, but expanded to include four layers of via interconnects. The preferred method used to fabricate the initial structure shown in FIG. 33A can also be used to fabricate multiple wiring layers with stacked conductive elements 3305A-C and 3310A-C as shown in FIG. 34A. the

Preferred methods then deposit and pattern conductive elements 3325A and 3325B using methods similar to those used to define conductor 3225 shown in Figure 33B. the

Preferred methods then etch the recesses 3330 as shown in Figure 34A using the preferred recess formation methods further described above in relation to the formation of recesses 3240 as shown in Figure 33C. the

Preferred methods then use the preferred methods described above and in the incorporated patent documents to deposit nanostructures 3340 as shown in Figure 34B. the

Preferred methods then fill vias 3330 with insulator 3350 and planarize the surface of insulator 3350 using the preferred methods described above with respect to insulator 3250 as shown in FIG. 33E . the

Preferred methods then pattern insulator 3350 and remove exposed portions of the nanostructures to form nanotubes as shown in FIG. 34D using preferred methods further described above with respect to making nanotube element 3267 as shown in FIG. 33F Element 3367. the

Preferred methods then deposit and planarize insulator 3360 as shown in FIG. 34E using methods further described above with respect to insulator 3260 shown in FIG. The via interconnect structure 3380 is programmed. the

Structure 3380 includes conductive element 3325 overlapping nanotube element 3367 at the sidewalls and upper surface of conductive element 3325 and forming a near-ohmic contact. Sidewalls 3375 of nanotube element 3367 form vias between conductive element 3325 and conductors 3305A, 3305B, and 3305C. the

Nanotube element 3367 overlaps the sidewalls of conductive elements 3305A, 3305B, and 3305C by a controlled overlap length determined by the thickness of elements 3305A, 3305B, and 3305C. Thus, conductive element 3325, nanotube element 3367, and conductive element 3305A form a first 2-TNS 3370A; and conductive element 3325, nanotube element 3367, and conductive element 3305B form a second 2-TNS 3370B; and conductive elements 3325, Nanotube element 3367, and conductive element 3305C form a third 2-TNS 3370C. the

In operation, if the corresponding 2-TNS 3370A, 3370B, and/or 3370C is in the "closed" state, a good (e.g., relatively close) gap is formed between the conductive element 3325 and any or all of the conductive elements 3305A, 3305B, 3305C. low resistance) electrical connection. In certain embodiments, the resistance between elements 3225 and 3305A may be in the range of, for example, 10-1000Ω for the "closed" state. If the corresponding 2-TNS 3370A, 3370B, and/or 3370C is in the "on" state, there is a relatively poor (eg, relatively high resistance) electrical connection between the conductive element 3325 and any or all of the conductive elements 3305A, 3305B, 3305C. connect. In certain embodiments, the resistance between elements 3325 and 3305A versus the "on" state can range, for example, from greater than 1 MΩ or greater than 1 GΩ. Other switches in structure 3380 have corresponding states and characteristics. This article illustrates the general operation and characteristics of a nonvolatile two-terminal nanotube switch. the

All combinations of single or multiple connections can be activated between conductor 3325 and any of conductors 3305A, B, and C. Also, connection between any combination or combinations of conductors 3305A, B, and C is permitted. the

As an example, referring to the non-volatile nanotube element based electrically reprogrammable via interconnect 3380 structure as shown in FIG. 34E, if switch A is "closed", switch B is "open", and switch C is "closed", then Since conductive element 3325A is connected in near-ohmic contact with nanotube sidewall 3375, conductive element 3325 is also connected to elements 3305C and 3310C and 3305A and 3310A. This also connects conductive elements 3305C and 3305A to each other because switch C is in the "closed" state and switch A is in the "closed" state. the

Two-terminal nanotube switches as high-density electrically reprogrammable nanotube via interconnects between two or more wiring layers with greater density

The cross-sections shown in FIGS. 33 and 34 and described further above assume that the via is surrounded by a conductive layer around the entire perimeter of the via opening. Landing pads are provided on various stages due to alignment considerations and the requirement for sufficient conductor boundary area around the vias. Such landing pads require increased spacing between conductors on each level and reduced wiring density. Via connections can also be placed close to metal lines without the need for landing pads, thereby increasing conductor routing density by reducing the spacing between conductors. the

FIG. 35 shows a plan view 3400 of conductors 3430 on a top level and one or more lower conductive wiring levels 3450 . The top conductor line 3430 on the insulator 3410 includes a landing pad 3440 where the vias are provided. The spacing between conductors on all wiring levels is increased in order to meet minimum spacing requirements 3420 . One or more wiring layers 3450 are interconnected by vias 3445 and connected to conductors 3430 . Vias 3445 contain nanotube elements. Top view 3400 corresponds to the cross-section shown in FIGS. 33 and 34 described above, where via 3445 corresponds to nonvolatile nanotube element-based electrically reprogrammable via interconnect 3280 shown in FIG. 33G and FIG. 34E 3380 shown. the

FIG. 36 shows a plan view 3500 of conductors 3530 on a top level and one or more lower conductor wiring levels 3550 . The landing pads have been removed allowing for reduced spacing between conductors and increased wiring density. Via 3545 is located at the corner defined by the intersection of the top-level and lower-level conductors. Electrically reprogrammable via interconnects based on nonvolatile nanotube elements similar to 3280 of FIG. 32G and 3380 in FIG. 34E can be fabricated using the methods described further above in relation to FIGS. The cross-sectional area of the component-to-conductor spacing is smaller because only a portion of the via perimeter will be in contact with each conductor level. Conductor 3530 is imaged onto the upper surface of insulator 3510. Conductor 3650 is located on the upper surface of a lower insulator (not shown) and contacts the lower surface of insulator 3510 . the

Alternate implementation

In certain embodiments, single-walled carbon nanotubes are preferred, while in other embodiments, multi-walled (eg, double-walled) carbon nanotubes are preferred. Also nanotubes can be used in combination with nanowires. Nanowires as used herein refer to individual nanowires, non-woven nanowire aggregates, nanoclusters, nanowires entwined with nanotubes including nanostructures, nanowire clusters, and the like. the

As mentioned above, the interconnection wires used to interconnect the nanotube device terminals may be conventional wires such as AlCu, W or Cu wires with appropriate insulating layers such as _SiO2 , polyimide, and the like. Interconnects can also be single- or multi-walled nanotubes for wiring.

The present invention can also be embodied in other specific forms without departing from its spirit and essential characteristics. Accordingly, the embodiments of the present invention are to be regarded as illustrative rather than restrictive. the

related application

This application refers to the following references, which are assigned to the assignee of the present invention and are hereby incorporated by reference in their entirety:

"Electromechanical Memory Array Using Nanotube Ribbons and Method for Making Same" U.S. Patent Application No. 09/915,093, filed July 25, 2001, now U.S. Patent No. 6,919,592;

"Electromechanical Memory Having Cell Selection Circuitry Constructed With NT Technology," U.S. Patent Application No. 09/915,173, filed July 25, 2001, now U.S. Patent No. 6,643,165 ;

"Hybrid Circuit Having NT Electromechanical Memory," U.S. Patent Application No. 09/915,095, filed July 25, 2001, now U.S. Patent No. 6,574,130;

"Electromechanical Three-Trace Junction Devices," U.S. Patent Application No. 10/033,323, filed December 28, 2001, now U.S. Patent No. 6,911,682;

"Methods of Making Electromechanical Three-Trace Junction Devices," U.S. Patent Application No. 10/033,032, filed December 28, 2001, now U.S. Patent No. 6,784,028;

"Nanotube Films and Articles," U.S. Patent Application No. 10/128,118, filed April 23, 2002, now U.S. Patent No. 6,706,402;

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The present invention can also be embodied in other specific forms without departing from its spirit and essential characteristics. Accordingly, the embodiments of the present invention are to be regarded as illustrative rather than restrictive. the

Claims (129)

1. two-terminal switch device comprises:

First conducting terminal;

With isolated second conducting terminal of described first conducting terminal;

Nanotube articles with a plurality of nanotubes, described nanotube articles be configured to described first and second conducting terminals all permanently direct physical contact; And

With the stimulation circuit of at least one electric connection of described first and second conducting terminals,

Described stimulation circuit is configured to form first voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relative high electrical resistance from relatively low resistance,

Described stimulation circuit is configured to form second voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relatively low resistance from relative high electrical resistance,

The described relative high electrical resistance of the nanotube articles between wherein said first and second conducting terminals is corresponding to first state of described two-terminal switch device, and the described relatively low resistance of the nanotube articles between described first and second conducting terminals is corresponding to second state of described two-terminal switch device, and

Described first and second states of wherein said two-terminal switch device are non-volatile.

2. two-terminal switch device as claimed in claim 1 is characterized in that, selects one or more thermal characteristicss of described two-terminal switch device to minimize the heat that flows out described nanotube articles.

3. two-terminal switch device as claimed in claim 1 is characterized in that, described nanotube articles is permanent overlapping with at least a portion of controlled geometrical relationship and described first conducting terminal.

4. two-terminal switch device as claimed in claim 3, it is characterized in that, described controlled geometrical relationship allows electric current to flow between described first conducting terminal and described nanotube articles, and caloric restriction flows between described first conducting terminal and described nanotube articles.

5. two-terminal switch device as claimed in claim 3 is characterized in that, described controlled geometrical relationship is the overlapping of predetermined extent.

6. two-terminal switch device as claimed in claim 5 is characterized in that, in the scope that overlaps 1-150nm of described predetermined extent.

7. two-terminal switch device as claimed in claim 5 is characterized in that, in the scope that overlaps 15-50nm of described predetermined extent.

8. two-terminal switch device as claimed in claim 5 is characterized in that, the overlapping size by described first conducting terminal of described predetermined extent defines.

9. two-terminal switch device as claimed in claim 1 is characterized in that, described first conducting terminal comprises the material that can conduct electricity and can not heat conduction.

10. two-terminal switch device as claimed in claim 1 is characterized in that, also comprises the passivation layer that is arranged on the described nanotube articles.

11. two-terminal switch device as claimed in claim 10 is characterized in that, described passivation layer comprise can not heat conduction material.

12. two-terminal switch device as claimed in claim 11 is characterized in that described passivation layer is limited in heat in the described nanotube articles.

13. two-terminal switch device as claimed in claim 1 is characterized in that, the resistance of described first state is ten times of resistance of described second state at least.

14. two-terminal switch device as claimed in claim 1 is characterized in that, the impedance of described first state is ten times of impedance of described second state at least.

15. two-terminal switch device as claimed in claim 1 is characterized in that, described first state is by the resistance characterization more than 1 megohm.

16. two-terminal switch device as claimed in claim 1 is characterized in that, described second state is by the resistance characterization below 100 kilohms.

17. two-terminal switch device as claimed in claim 1 is characterized in that, described first voltage difference comprises the electrostimulation that is chosen to provide erase operation.

18. two-terminal switch device as claimed in claim 17 is characterized in that, described erase operation comprises: described stimulation circuit is crossed over described first and second conducting terminals and is applied high voltage.

19. two-terminal switch device as claimed in claim 18 is characterized in that described high voltage is in the 3-10V scope.

20. two-terminal switch device as claimed in claim 17, it is characterized in that, described erase operation comprises: described stimulation circuit applies one or more potential pulses to form voltage difference between described first and second conducting terminals, the number of the amplitude of wherein said potential pulse, the waveform of described potential pulse and described potential pulse is enough to described two-terminal switch device is become described first state together.

21. two-terminal switch device as claimed in claim 1 is characterized in that, described second voltage difference comprises the electrostimulation that is chosen to provide programming operation.

22. two-terminal switch device as claimed in claim 21 is characterized in that, described programming operation comprises: described stimulation circuit is crossed over described first and second conducting terminals and is applied low-voltage and low current.

23. two-terminal switch device as claimed in claim 22 is characterized in that, described low-voltage is in the 1-5V scope, and low current is in the 100nA-100uA scope.

24. two-terminal switch device as claimed in claim 21, it is characterized in that, described programming operation comprises: described stimulation circuit applies one or more potential pulses to form voltage difference at described first and second conducting terminals, and the number of the amplitude of wherein said potential pulse, the waveform of described potential pulse and described potential pulse is enough to described two-terminal switch device is become described second state together.

25. two-terminal switch device as claimed in claim 1, it is characterized in that, it is poor that described stimulation circuit is configured to form tertiary voltage between described first and second conducting terminals, described the 3rd waveform has at least one wave character, and this wave character is selected as determining the state of described two-terminal switch device.

26. two-terminal switch device as claimed in claim 25 is characterized in that, described tertiary voltage difference comprises the electrostimulation that is chosen to provide nondestructive read operation.

27. two-terminal switch device as claimed in claim 26, it is characterized in that, described nondestructive read operation comprises: described stimulation circuit is crossed over described first and second conducting terminals and is applied resistance between voltage and described first and second conducting terminals of sensing, and described voltage is enough low to make it not change the state of described two-terminal switch device.

28. two-terminal switch device as claimed in claim 27 is characterized in that described voltage is less than 2V.

29. two-terminal switch device as claimed in claim 1 is characterized in that, the edge of at least one and described nanotube articles is permanent overlapping in described first and second conducting terminals.

30. two-terminal switch device as claimed in claim 1 is characterized in that, the opposing ends of described nanotube articles is permanent overlapping with each at least a portion of described first and second conducting terminals respectively.

31. two-terminal switch device as claimed in claim 1 is characterized in that, one of described first and second conducting terminals be with the peripheral permanent overlapping of described nanotube articles and with the nonoverlapping photo frame structure in the central area of described nanotube articles.

32. two-terminal switch device as claimed in claim 31 is characterized in that the central area of another of described first and second conducting terminals and described nanotube articles is permanent overlapping.

33. two-terminal switch device as claimed in claim 1 is characterized in that, described first conducting terminal has a plurality of surfaces, and wherein said nanotube articles contacts with at least a portion with upper surface and be permanent overlapping with it.

34. two-terminal switch device as claimed in claim 1 is characterized in that at least one of described first and second conducting terminals has vertical orientated feature, wherein said nanotube articles contacts with at least a portion of described vertical orientated feature.

35. two-terminal switch device as claimed in claim 1 is characterized in that, described nanotube articles comprises the nano tube structure object area that defines orientation.

36. two-terminal switch device as claimed in claim 1 is characterized in that described nanotube articles comprises double-walled nanotubes.

37. two-terminal switch device as claimed in claim 1 is characterized in that described nanotube articles comprises single-walled nanotube.

38. two-terminal switch device as claimed in claim 1 is characterized in that described nanotube articles comprises many walls nanotube.

39. two-terminal switch device as claimed in claim 1 is characterized in that described nanotube articles comprises nanotube bundle.

40. two-terminal switch device as claimed in claim 1 is characterized in that, the one or more nanotubes in the described nanotube articles are selected to has specific breathing pattern radially by force.

41. two-terminal switch device as claimed in claim 40 is characterized in that, described specific by force radially breathing pattern show as hot bottleneck.

42. two-terminal switch device as claimed in claim 40, it is characterized in that, described specific strong radially breathing pattern is corresponding to the pattern that disconnects that is connected between the nanotube and the conductor that cause in the described device, and the conductor in the wherein said two-terminal switch device comprises one or more in described first conducting terminal, described second conducting terminal, nanotube and the nanotube fragment.

43. two-terminal switch device as claimed in claim 1 is characterized in that, described first and second conducting terminals are metals.

44. two-terminal switch device as claimed in claim 43 is characterized in that, described metal comprises among Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb and the Sn at least one.

45. a double-end storage spare comprises:

First conducting terminal;

With isolated second conducting terminal of described first conducting terminal;

Nanotube articles with a plurality of nanotubes, described nanotube articles be configured to described first and second conducting terminals permanently direct physical contact; And

With the stimulation circuit of at least one electric connection in described first and second conducting terminals,

Described stimulation circuit is configured to form first voltage difference between described first conducting terminal and second conducting terminal, thereby make and open one or more gaps between the one or more nanotubes and one or more conductor in the described device, and the resistance of opening the nanotube articles between described first and second conducting terminals in described one or more gaps becomes relative high electrical resistance from relatively low resistance

Described stimulation circuit is configured to form second voltage difference between described first conducting terminal and second conducting terminal, thereby the one or more gaps in the closed described device between one or more nanotubes and the one or more conductor, and the closure in described one or more gaps makes the resistance of the nanotube articles between described first and second conducting terminals become relatively low resistance from relative high electrical resistance

Wherein, the conductor in the described device comprises one or more in described first conducting terminal, described second conducting terminal, nanotube and the nanotube fragment,

Wherein, the relative high electrical resistance of the nanotube articles between described first and second conducting terminals is corresponding to first state of described device, and the relatively low resistance of the nanotube articles between described first and second conducting terminals is corresponding to second state of described device, and

Described first and second states of wherein said double-end storage spare are non-volatile.

46. double-end storage spare as claimed in claim 45, it is characterized in that, described first voltage difference is selected as at least a portion of described nanotube articles was carried out heating to open the one or more gaps in the described conductor, so that first state of described double-end storage spare to be provided.

47. double-end storage spare as claimed in claim 46 is characterized in that, described first voltage difference is selected as by the joule heating at least a portion of described nanotube articles being carried out heating.

48. double-end storage spare as claimed in claim 45 is characterized in that, one or more thermal characteristicss of selecting described double-end storage spare are to minimize the heat that flows out described nanotube articles.

49. double-end storage spare as claimed in claim 48, it is characterized in that, thereby by arrange described nanotube articles and described first conducting terminal to minimize the heat that flows out described nanotube articles with controlled geometrical relationship, described controlled geometrical relationship caloric restriction flows out described nanotube articles and flows into described first conducting terminal.

50. double-end storage spare as claimed in claim 49 is characterized in that, described controlled geometrical relationship is the overlapping of predetermined extent.

51. double-end storage spare as claimed in claim 50 is characterized in that, described predetermined extent overlapping less than 50nm.

52. double-end storage spare as claimed in claim 48 is characterized in that, can conduct electricity and material that can not heat conduction is used for the heat that first conducting terminal minimizes the described nanotube articles of described outflow by selecting one.

53. double-end storage spare as claimed in claim 52 is characterized in that, described material has high conductivity and lower thermal conductivity.

54. double-end storage spare as claimed in claim 52 is characterized in that, selects described material from the group of conducting polymer and doped semiconductor.

55. double-end storage spare as claimed in claim 45, it is characterized in that described first waveform is selected as opening described one or more gap by forming the gap between one or more in described one or more nanotubes and described first and second conducting terminals.

56. double-end storage spare as claimed in claim 45 is characterized in that, described first voltage difference is selected as opening described one or more gap by one or more nanotubes are separated with one or more other nanotubes.

57. double-end storage spare as claimed in claim 45 is characterized in that, described first voltage difference is selected as opening described one or more gap by one or more nanotubes being broken into two or more nanotube fragments.

58. double-end storage spare as claimed in claim 45 is characterized in that, described first voltage difference is selected as comprising the threshold voltage according that surpasses described nanotube articles.

59. double-end storage spare as claimed in claim 45 is characterized in that, described first voltage difference is selected as by exciting in the described nanotube articles one or more phonon modes of one or more nanotubes to open described one or more gap.

60. double-end storage spare as claimed in claim 59 is characterized in that, described one or more phonon modes show as hot bottleneck.

61. double-end storage spare as claimed in claim 59 is characterized in that, described one or more phonon modes are optical phonon patterns.

62. double-end storage spare as claimed in claim 59 is characterized in that, the one or more nanotubes in the described nanotube articles are selected to has specific breathing pattern radially by force.

63. double-end storage spare as claimed in claim 59 is characterized in that, the one or more nanotubes in the described nanotube articles are selected to has defect mode.

64. double-end storage spare as claimed in claim 45 is characterized in that, described second voltage difference is selected as by one or more nanotubes are attracted and closed described one or more gaps to one or more conductors.

65., it is characterized in that described second voltage difference is selected as by producing electrostatic attraction one or more nanotubes being attracted to one or more conductors as the described double-end storage spare of claim 64.

66. double-end storage spare as claimed in claim 45, it is characterized in that, described first voltage difference is selected as opening the one or more gaps that characterized by gap size, and described second waveform is selected as having the next closed one or more gaps by this characterization of size of enough big amplitude.

67. double-end storage spare as claimed in claim 45 is characterized in that, also comprises the passivation layer that is arranged on the described nanotube articles.

68., it is characterized in that described passivation layer is limited in heat in the described nanotube articles as the described double-end storage spare of claim 67.

69. double-end storage spare as claimed in claim 45 is characterized in that, described double-end storage spare can switch above 1,000,000 times between described first and second states repeatedly.

70. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises the nano tube structure object area that defines orientation.

71. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises double-walled nanotubes.

72. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises single-walled nanotube.

73. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises many walls nanotube.

74. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises nanotube bundle.

75. double-end storage spare as claimed in claim 45 is characterized in that, described first and second conducting terminals are metals.

76. a selectable memory cell comprises:

Unit selecting transistor comprises grid, source electrode and drain electrode, and wherein said grid and word line electrically contact, and described drain electrode and bit line electrically contact;

The two-terminal switch device, comprise first conducting terminal, second conducting terminal and nanotube articles with a plurality of nanotubes, described nanotube articles and described first and second conducting terminals all permanently direct physical contact, the source electrode of wherein said first conducting terminal and described unit selecting transistor electrically contacts, and described second conducting terminal electrically contacts with the line that is used to carry out programing function, erase feature or read functions; And

With described word line, bit line be used to carry out the storage operation circuit of the line electric connection of programing function, erase feature or read functions,

Described storage operation circuit comprises a circuit, and this circuit is configured to generate and on described word line

Apply and select signal selecting the described memory cell of selecting, and, generate and carry out in described being used for

Apply erase signal on the line of programing function, erase feature or read functions, described erase signal has at least one waveform characteristic, this waveform characteristic is selected as making that the resistance of the nanotube articles between described first and second conducting terminals becomes relative high electrical resistance from relatively low resistance

Described storage operation circuit comprises a circuit; This circuit is configured to generate and applies the selection signal to select the described memory cell of selecting at described word line; And; Generate and apply programming signal at described line for carrying out programing function, erase feature or read functions; Described programming signal has at least one waveform characteristic; This waveform characteristic is selected as so that the resistance of the nanotube articles between described first and second conducting terminals becomes relatively low resistance from high resistance relatively

The described relative high electrical resistance of the nanotube articles between wherein said first and second conducting terminals is corresponding to the first information state of described memory cell, and the described relative high electrical resistance of the nanotube articles between described first and second conducting elements is corresponding to second information state of described memory cell, and described first and second information states are non-volatile.

77. the memory cell of selecting as claimed in claim 16, it is characterized in that, described storage operation circuit comprises a circuit, being used for generating and applying on described word line selects signal to select the described memory cell of selecting, and, generate and apply on the described line that is used to carry out programing function, erase feature or read functions and read signal, the described signal that reads has at least one waveform characteristic, and this waveform characteristic is selected as determining the information state of described memory cell.

78. as the described memory cell of selecting of claim 77, it is characterized in that, determine that the information state of described memory cell does not change the information state of described memory cell.

79. as the described memory cell of selecting of claim 76, it is characterized in that, also comprise being connected to the described a plurality of memory cells of selecting that are used to carry out programing function, erase feature or read functions line.

80., it is characterized in that one or more thermal characteristicss of described device are selected to and minimize the heat that flows out described nanotube articles as the described memory cell of selecting of claim 76.

81., it is characterized in that described nanotube articles is permanent overlapping with at least a portion of controlled geometrical relationship and described second conducting terminal as the described memory cell of selecting of claim 76.

82. as the described memory cell of selecting of claim 81, it is characterized in that, described controlled geometrical relationship allows electric current to flow between described second conducting terminal and described nanotube articles, and caloric restriction flows between described second conducting terminal and described nanotube articles.

83., it is characterized in that described controlled geometrical relationship is the overlapping of predetermined extent as the described memory cell of selecting of claim 81.

84., it is characterized in that the overlapping size by described first conducting terminal of described predetermined extent defines as the described memory cell of selecting of claim 83.

85. as the described memory cell of selecting of claim 83, it is characterized in that, in the scope that overlaps 1-150nm of described predetermined extent.

86. as the described memory cell of selecting of claim 76, it is characterized in that, one in described first and second conducting terminals is and peripheral permanent overlapping and not overlapping with the central area of the described nanotube articles photo frame structure of described nanotube articles that the central area of another in described first and second conducting terminals and described nanotube articles is permanent overlapping.

87., it is characterized in that described second conducting terminal has a plurality of surfaces as the described memory cell of selecting of claim 76, and described nanotube articles contacts with at least a portion more than a surface and permanent overlapping with it.

88., it is characterized in that described second conducting terminal has vertical orientated feature as the described memory cell of selecting of claim 76, and described nanotube articles contacts with at least a portion of described vertical orientated profile.

89., it is characterized in that the described memory cell of selecting has less than 10F as the described memory cell of selecting of claim 76 ²The definition area, wherein F comprises minimum feature size, 22nm≤F≤180nm.

90., it is characterized in that described nanotube articles comprises the nano tube structure object area that defines orientation as the described memory cell of selecting of claim 76.

91., it is characterized in that described nanotube articles comprises double-walled nanotubes as the described memory cell of selecting of claim 76.

92., it is characterized in that described nanotube articles comprises many walls nanotube as the described memory cell of selecting of claim 76.

93., it is characterized in that described nanotube articles comprises nanotube bundle as the described memory cell of selecting of claim 76.

94., it is characterized in that described first and second conducting terminals are metals as the described memory cell of selecting of claim 76.

95. a re-programmable both-end fuse-antifuse device comprises:

First conductor;

Second conductor of opening with first conductor separation;

Nanotube articles has a plurality of nanotubes, described nanotube articles and described first and second conductors all permanently direct physical contact,

The nanotube density that described nanotube articles comprises is selected as making that described device can be in response to striding

Be connected on the first threshold voltage on described first and second conductors and open the electrical connection between described first and second conductors and produce the high resistance state of described nanotube articles, to form first device state, and can be in response to being connected across second threshold voltage on described first and second conductors electrical connection between closed described first and second conductors and produce the low resistance state of described nanotube articles, to form second device state

Wherein said first and second device states are non-volatile.

96., it is characterized in that described Reprogrammable both-end fuse-antifuse device can switch at least one 1,000,000 times repeatedly as the described Reprogrammable both-end of claim 95 fuse-antifuse device between described first and second device states.

97., it is characterized in that described Reprogrammable both-end fuse-antifuse device is a cross point switches as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

98., it is characterized in that described nanotube articles is permanent overlapping with at least a portion of controlled geometrical relationship and described first conductor as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

99. as the described Reprogrammable both-end of claim 95 fuse-antifuse device, it is characterized in that, described controlled geometrical relationship allows electric current to flow between described first conductor and described nanotube articles, and caloric restriction flows between described first conductor and described nanotube articles.

100., it is characterized in that described controlled geometrical relationship is the overlapping of predetermined extent as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

101. as the described Reprogrammable both-end of claim 95 fuse-antifuse device, it is characterized in that, in described first and second conductors one is peripheral permanent overlapping and not overlapping with the central area of the described nanotube articles photo frame structure with described nanotube articles, and the second area of another and described nanotube articles in described first and second conductors is permanent overlapping.

102., it is characterized in that described nanotube articles comprises the nano tube structure object area that defines orientation as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

103., it is characterized in that described nanotube articles comprises single-walled nanotube as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

104., it is characterized in that described nanotube articles comprises many walls nanotube as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

105., it is characterized in that described nanotube articles comprises double-walled nanotubes as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

106., it is characterized in that described nanotube articles comprises nanotube bundle as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

107., it is characterized in that described first and second conductors are metals as the described Reprogrammable both-end of claim 95 fuse-antifuse device.

108. the interconnection of the Reprogrammable between a plurality of wiring layers, described interconnection comprises:

First conducting terminal;

A plurality of wiring layers, each described wiring layer comprises the wiring layer conducting terminal;

Stimulation circuit is with described first conducting terminal and each wiring layer conducting terminal electric connection;

Nanotube articles with a plurality of nanotubes, described nanotube articles be aligned to described first conducting terminal permanently direct physical contact, and with each wiring layer conducting terminal permanently direct physical contact,

Described stimulation circuit is configured to form between the wiring layer conducting terminal in described first conducting terminal and a plurality of wiring layer conducting terminal first voltage difference, thereby make described nanotube articles in described a plurality of wiring layers, form interconnection between two wiring layers, described nanotube articles has relatively low resistance states

Described stimulation circuit is configured to form between the wiring layer conducting terminal in described first conducting terminal and a plurality of wiring layer conducting terminal second voltage difference, thereby make described nanotube articles disconnect in described a plurality of wiring layer the interconnection between two wiring layers, described nanotube articles has higher relatively resistance states.

109. as the interconnection of the described Reprogrammable of claim 108, it is characterized in that described stimulation circuit comprises a circuit, be used for disconnecting all interconnection in response to safety factor.

110., it is characterized in that one or more thermal characteristicss of described Reprogrammable interconnection are selected to and minimize the heat that flows out described nanotube articles as the described Reprogrammable interconnection of claim 108.

111., it is characterized in that described nanotube articles is permanent overlapping with at least a portion of controlled geometrical relationship and each described wiring layer conducting terminal as the described Reprogrammable interconnection of claim 108.

112. as the described Reprogrammable interconnection of claim 111, it is characterized in that, described controlled geometrical relationship allows electric current to flow between each described wiring layer conducting terminal and described nanotube articles, and caloric restriction flows between each described wiring layer conducting terminal and described nanotube articles.

113., it is characterized in that described controlled geometrical relationship is the overlapping of predetermined extent as the described Reprogrammable interconnection of claim 111.

114., it is characterized in that the size of overlapping each by described wiring layer conducting terminal of described predetermined extent is defined as the interconnection of the described Reprogrammable of claim 113.

115., it is characterized in that, in the scope that overlaps 1-150nm of described predetermined extent as the described Reprogrammable interconnection of claim 113.

116., it is characterized in that described nanotube articles comprises the nano tube structure object area that defines orientation as the described Reprogrammable interconnection of claim 108.

117., it is characterized in that described nanotube articles comprises double-walled nanotubes as the described Reprogrammable interconnection of claim 108.

118., it is characterized in that described nanotube articles comprises many walls nanotube as the described Reprogrammable interconnection of claim 108.

119., it is characterized in that described nanotube articles comprises nanotube bundle as the described Reprogrammable interconnection of claim 108.

120., it is characterized in that described wiring layer conducting terminal comprises metal as the described Reprogrammable interconnection of claim 108.

121. a method of making double-end storage spare, described method comprises:

First conducting terminal is set;

Be provided with and isolated second conducting terminal of described first conducting terminal;

The stimulation circuit of at least one electric connection of setting and described first and second conducting terminals, described stimulation circuit is configured to form voltage difference between described first conducting terminal and second conducting terminal;

Setting comprises the nanotube articles of a plurality of nanotubes, described nanotube articles and described first and second conducting terminals all permanently direct physical contact, each of described nanotube articles and described first and second conducting terminals is permanently overlapping, described nanotube articles is made response to the electrostimulation from described stimulation circuit, thereby described electrostimulation is applied on described first and second conducting terminals and forms voltage difference between described first conducting terminal and second conducting terminal, first voltage difference between described first conducting terminal and second conducting terminal makes described nanotube articles have relatively low resistance states, and second voltage difference between described first conducting terminal and second conducting terminal makes described nanotube articles have higher relatively resistance states.

122., it is characterized in that the isotropic etching process by regularly is placed to described nanotube with described first and second conducting terminals and contacts as the described method of claim 121.

123. as the described method of claim 121, it is characterized in that, by the directional etch process described nanotube be placed to described first and second conducting terminals and contact.

124., it is characterized in that the thickness of the overlapping and expendable film of described predetermined extent is relevant as the described method of claim 121.

125., it is characterized in that the thickness of at least one is relevant in overlapping and described first and second conducting terminals of described predetermined extent as the described method of claim 121.

126., it is characterized in that also comprise and make second memory spare, described second memory spare has the structure as the mirror image of described double-end storage spare structure as the described method of claim 121.

127., it is characterized in that as the described method of claim 121, described nanotube articles is set comprises and select one or more nanotubes to be used to form described nanotube articles, wherein said nanotube presents specific breathing pattern radially by force.

128., it is characterized in that the described memory cell of selecting has less than 6F as the described memory cell of selecting of claim 76 ²The definition area, wherein F comprises minimum feature size, 22nm≤F≤180nm.

129. a two-terminal switch device comprises:

First conducting terminal;

With isolated second conducting terminal of described first conducting terminal;

Nanotube articles with a plurality of nanotubes, described nanotube articles be configured to described first and second conducting terminals all permanently direct physical contact; And

With the stimulation circuit of at least one electric connection of described first and second conducting terminals,

Described stimulation circuit is configured to form first voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relative high electrical resistance from relatively low resistance,

Described stimulation circuit is configured to form second voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relatively low resistance from relative high electrical resistance.

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