CN101227291B - Ethernet MAC layer cross-connection system, transmission method and chip for its application - Google Patents
Ethernet MAC layer cross-connection system, transmission method and chip for its application Download PDFInfo
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Abstract
一种以太网MAC层的交叉级联系统、传输方法及其应用的芯片，该系统包括：多级MAC层交叉芯片层，且每级MAC层交叉芯片层至少包含一个MAC层交叉芯片；其中，下级MAC层交叉芯片和/或物理层芯片的上行数字接口分别通过复用传输接口与其上级MAC层交叉芯片的下行数字接口相连。在上行方向，下级MAC层交叉芯片从其下行数字接口接收经复用传输转换后的数据，并经MAC层交叉处理后，将需要进行转发的流量通过上行数字接口，发送到上级MAC层交叉芯片的下行数字接口；在下行方向，上级MAC层交叉芯片从其下行端口输出的本芯片交叉后的数据和/或从其上级芯片下行的数据，经复用传输转换后，发送到下级MAC层交叉芯片和/或物理层芯片的上行数字接口。
An Ethernet MAC layer cross-connection system, a transmission method and a chip for its application, the system comprising: a multi-level MAC layer cross-chip layer, and each MAC layer cross-chip layer includes at least one MAC layer cross-chip; wherein, The uplink digital interface of the lower MAC layer cross chip and/or the physical layer chip is respectively connected to the downlink digital interface of the upper MAC layer cross chip through a multiplexing transmission interface. In the upstream direction, the lower-level MAC layer cross chip receives the data after multiplexing and transmission conversion from its downlink digital interface, and after the MAC layer cross processing, sends the traffic that needs to be forwarded to the upper level MAC layer cross chip through the uplink digital interface In the downlink direction, the cross-connected data of the chip output by the upper-level MAC layer cross-connect chip from its downlink port and/or the downlink data from its upper-level chip are sent to the lower-level MAC layer cross-connect after multiplexing and transmission Uplink digital interface of chip and/or physical layer chip.
Description
Technical field
The present invention relates to communications network system, relate in particular to a kind of Ethernet MAC layer (MAC, Medium Access Contro1) cascade system and transmission method thereof, more particularly, the present invention relates to the MAC layer cross chips that use in a kind of crossed cascading system, this cascade system of ethernet mac layer and in this crossed cascading system the method for transmission data.
Background technology
Along with the high speed development of network technology, broadband industry was very fast in China's development in recent years.In China, the technology maturity of chip and equipment, interoperability and cost problem become the key of industry development and marketing.When constantly promoting the satisfied more demands of performance, reducing cost also is current main developing direction.One of major measure that reduces cost is a raising scheme degree of integration, the simplified system design.
In order to adapt to low-cost network insertion demand, for chip manufacturer and equipment vendors, generally start with from two aspects, the one, adopt multiplex technique, its objective is the interface number of saving physical chip and medium access control system (Media Access Control is called for short MAC) layer chip, the 2nd, adopt the intersection concatenation technology, make MAC layer chip and IP layer not need to handle all flows, thereby reduced the flow that MAC layer chip need be handled from downstream interface output.
Physical layer multiplex chip (PHY-MUX, Physical layer-Multiplexer) is exactly the product that adopts the physical layer multiplex technology.As shown in Figure 1, comprise a multiplexing converting unit in the physical layer multiplex chip, it is multiplexing by what the multichannel physical layer was imported, in the up direction physical port input that multichannel is descending, is multiplexed into the upstream digital interface of a high speed; At down direction, will send to the corresponding downstream physical port by demultiplexing from the business of the upstream digital interface of a high speed; Thereby reach one or a few high speed uplink digital interface in the physical chip, the purpose of corresponding a plurality of low speed downlink physical interfaces; Reach the ply-yarn drill of simplifying rack-mount unit in actual applications and design, reduce purposes such as network insertion cost.
Because above-mentioned multiplexing converting unit is just worked in physical chip, though can reduce the ascending physical signal port number of physical chip, has alleviated the problem of low-cost network insertion to a certain extent.Handle but all input interface flows all need be delivered to MAC layer chip, do not reduce the flow size that MAC layer chip need be handled at up direction.To down direction, need MAC layer chip to handle the flow that all output to downstream interface equally.
See also Fig. 2, Fig. 2 constitutes the cascaded system structured flowchart for the physical chip that uses above-mentioned multiplex technique and interleaving techniques.As shown in Figure 2, the cascade system of this ethernet physical layer comprises three level physical layer cross chips layers, first order physical layer cross chips layer comprise 16 8 ports 10M physical layer cross chips (1PHY chip #1,1PHY chip #2 ... 1PHY chip #16), second level physical layer cross chips layer comprises two 100M physical layer cross chips (2PHY chip #1,2PHY chip #2), and third level physical layer cross chips layer comprises 1 1000M physical layer cross chips (3PHY chip); The PHY chip #1 of first order physical layer cross chips layer～PHY chip #8 forms one group, 2PHY chip #1 with second level physical layer cross chips layer links to each other by D/A converter module, equally, the PHY chip #9 of first order physical layer cross chips layer～PHY chip #16 forms another group, and the 2PHY chip #2 with second level physical layer cross chips layer links to each other by D/A converter module; Two second level physical layer cross chips link to each other with third level physical layer cross chips layer (3PHY chip) by D/A converter module.
Above-mentioned use has the physical layer crossed cascading system that cross chips is set up of cross processing function, and the port of having realized finishing in the physical layer cross chips between this chip internal, physical layer cross chips at the same level and the different level physical layer cross chips intersects.At up direction, subordinate's physical layer cross chips after the multiplexing process, respectively by upstream Interface, sends to the descending analog interface of higher level's physical chip from the data that analog port receives after digital-to-analogue conversion.At down direction, after higher level's physical intersection chip is finished cross processing,, after digital-to-analogue conversion, send to the upstream Interface of subordinate's physical intersection chip from the data of analog port output.
Above-mentioned physical layer crossed cascading system and physical chip, in the inventor's the file of Chinese patent application formerly " chip of the crossed cascading system of ethernet physical layer, transmission method and application thereof ", be described in detail, its application number is 200610142814.4, therefore, repeats no more.
If the cross processing function in the multiplexing cascade system of above-mentioned intersection is by realizing at MAC layer cross chips, the flow of the cross processing that in the MAC of low-level layer chip, can carry out, just need not send in the MAC layer chip of level or highest level and handle, like this, can reduce more high-rise processing flows such as MAC layer chip and IP layer equally, adapt to the demand of low-cost network insertion.Yet up to the present, also nobody proposed to adopt MAC layer cross chips realization ethernet mac layer to intersect the technology of multiplexing cascade.
Summary of the invention
Purpose of the present invention is, can link to each other by providing a kind of MAC layer intersection multiplexing cascade system, use this system to make the MAC layer cross chips that is in each level.
Another object of the present invention is, provides a kind of MAC layer intersection multiplexing cascade transmission method, and this method is applied in the said system, can be implemented in the port interleaving function of finishing different physical chips in the MAC chip.
Another object of the present invention is, a kind of MAC layer cross chips is provided, and is applied in the above-mentioned cascade system, and described chip comprises multiplexing transmission interface, can directly link to each other with the MAC of level up and down layer cross chips in the cascade system with physical chip.
In order to realize the foregoing invention purpose, the invention provides a kind of crossed cascading system of ethernet mac layer, described system comprises: multistage MAC layer cross chips layer, and every grade of MAC layer cross chips layer comprises a MAC layer cross chips at least; Wherein, the upstream digital interface of the MAC of subordinate layer cross chips and/or physical chip links to each other by the descending digital interface of multiplexing transmission interface with its higher level MAC layer cross chips respectively.
Crossed cascading system for above-mentioned ethernet mac layer, also comprise: the port arrangement module, in order to the port of all physical chips and MAC layer cross chips is encoded, and to port configured port attribute, and set up the port attribute table, and the port arrangement corresponding ports crosstab or the port crossed array that intersect at need; Wherein, described port attribute comprises cross-port and transmits port.
For the crossed cascading system of above-mentioned ethernet mac layer, described MAC layer cross chips comprises: Cross module, it is plugged between the descending digital interface and MAC layer access control module of this MAC layer chip, and links to each other with its upstream digital interface at up direction.
For the crossed cascading system of above-mentioned ethernet mac layer, described MAC layer cross chips also comprises processing module, and described processing module links to each other respectively with the up-downgoing digital port of described Cross module and this chip; Described processing module comprises port processing module, cross processing module and transmits processing module; Described port processing module is delivered to the forwarding port in order to will according to the port attribute table, the data that this chip of need intersects being delivered to cross-port from the data of descending digital port reception with the data that this chip of need is transmitted; Described cross processing module in order to the port crosstab according to this chip, with the data that cross-port need be intersected, offers the MAC layer that described Cross module carries out between port and directly intersects; And described forwarding processing module sends to the upstream digital interface of this chip in order to will transmit the data that port need be transmitted.
For the crossed cascading system of above-mentioned ethernet mac layer, described multiplexing transmission interface comprises:
The first multiplexing converting unit, link to each other with the upstream digital interface of described physical chip and/or the MAC of subordinate layer cross chips, the upstream data that is used for the output of multiplexing described physical chip and/or the MAC of subordinate layer cross chips, and demultiplexing is input to the downlink data of described physical chip and/or the MAC of subordinate layer cross chips;
The second multiplexing converting unit links to each other with the descending digital interface of higher level MAC layer chip, be used for the downlink data of multiplexing higher level MAC layer cross chips output, and demultiplexing is input to the upstream data of higher level MAC layer cross chips;
Wherein, the described first multiplexing converting unit links to each other with the described second multiplexing converting unit, is used to set up the multiplexing transmission passage between the descending digital interface of the upstream digital interface of described physical chip and/or the MAC of subordinate layer cross chips and higher level MAC layer cross chips.
For the crossed cascading system of above-mentioned ethernet mac layer, the described first multiplexing converting unit and the described second multiplexing converting unit link to each other by media independent interface.
For the crossed cascading system of above-mentioned ethernet mac layer, described multiplexing transmission interface also includes the auto-negotiation module, and described auto-negotiation module links to each other with the described first and second multiplexing converting units respectively; In order to the mark of the port number of determining the described first and second multiplexing converting units, multiplexing transmission port correspondence, transmission rate between the first and second multiplexing converting units and the mode of described multiplexing and demultiplexing.
The transmission method that the present invention also provides a kind of ethernet mac layer to intersect cascade, at up direction, the MAC of subordinate layer cross chips is from the data of its descending digital interface reception after the multiplexing transmission conversion, and after the cross processing of MAC layer, the flow that needs are transmitted passes through the upstream digital interface, sends to the descending digital interface of higher level MAC layer cross chips; At down direction, after higher level MAC layer cross chips finished cross processing, data after intersecting from this chip of its downlink port output and/or descending data of level chip from it after the multiplexing transmission conversion, send to the upstream digital interface of the MAC of subordinate layer cross chips and/or physical chip.
For above-mentioned transmission method, also comprise: the port in all chip interfaces in the described cascade system is unified and/or local code, and, set up the port attribute table, and the port arrangement corresponding ports crosstab or the port crossed array that intersect at need to port configured port attribute; Wherein, described port attribute comprises cross-port and transmits port.
For the transmission method of above-mentioned ethernet mac layer, described cross processing comprises:
Step 11: the data that will receive from port, according to the port attribute table, the data that this chip of need intersects are delivered to cross-port, the data that this chip of need is transmitted are delivered to the forwarding port;
Step 12: at all cross-port, according to the port crosstab of this chip, with the data that cross-port need be intersected, the MAC layer that carries out between port directly intersects, after described multiplexing transmission conversion process, send to the upstream digital interface of physical chip and/or the MAC of subordinate layer chip;
Step 13: at all forwarding ports, will transmit the data that port need be transmitted, send to the forwarded upstream port of this chip, after described multiplexing transmission conversion process, send to the downstream interface of higher level MAC layer chip.
For the transmission method of above-mentioned ethernet mac layer, described multiplexing transmission conversion comprises:
Step 21: between described physical chip port and/or the MAC of subordinate layer chip port and higher level MAC layer chip port, set up the multiplexing transmission passage;
Step 22: the data of multiplexing described physical chip port and/or the output of described MAC layer chip port, and send it to this multiplexing transmission passage;
Step 23: the data of this multiplexing transmission passage output of demultiplexing, and send it to described physical chip port and/or MAC layer chip port.
For the transmission method of above-mentioned ethernet mac layer, the described multiplexing transmission passage of setting up includes the following step:
Step 211: determine the number of described transmission FPDP, and the mark of each described transmission FPDP correspondence;
Step 212: determine the transmission rate of described transmission FPDP, the transmission rate of described reception FPDP, and the transmission rate of described multiplexing transmission passage;
Step 213: mode that determine to carry out described multiplexing and described demultiplexing.
For the transmission method of above-mentioned ethernet mac layer, the described step of setting up the multiplexing transmission passage is to finish by the mode of auto-negotiation.
For the transmission method of above-mentioned ethernet mac layer, described multiplex mode is a time division multiplexing or multiplexing based on the mark of ethernet data frame.
For the transmission method of above-mentioned ethernet mac layer, described ethernet data frame is labeled as privately owned port label or VLAN mark.
The present invention also provides a kind of cross chips of ethernet mac layer, comprising: uplink and downlink digital interface and MAC layer access control module; Described MAC layer cross chips also comprises: Cross module, it is plugged between the descending digital interface and MAC layer access control module of described MAC layer chip, in order to the data that receive from its descending digital interface are carried out the port cross processing of MAC layer.
For the cross chips of above-mentioned ethernet mac layer, also comprise chip internal configuration module and processing module; Described chip internal configuration module in order to the port of all MAC layer cross chips is encoded, and to each port arrangement port attribute, forms the port attribute table, and the port arrangement corresponding ports crosstab or the port crossed array that intersect at need; Wherein, described port attribute comprises cross-port and transmits port.Described processing module links to each other respectively with the uplink and downlink digital interface of described Cross module and described chip; Described processing module comprises port processing module, cross processing module and transmits processing module; The port processing module according to the port attribute table, is delivered to cross-port with the data that the described chip of need intersects, and the data that the described chip of need is transmitted are delivered to the forwarding port; The cross processing module in order to the port crosstab according to described chip, with the data that described port need intersect, offers the MAC layer that described Cross module carries out between port and directly intersects; And the forwarding processing module, in order to will transmit the data that port need be transmitted, send to the upstream digital interface of described chip.
Cross chips for above-mentioned ethernet mac layer also comprises:
The first multiplex/demultiplex unit, it is plugged between the descending digital interface of described chip and the Cross module and with described processing module and links to each other, be used for the data that the described descending digital interface of demultiplexing receives, and the multiplexing downlink data that will be input to described descending digital interface; And
The second multiplex/demultiplex unit, it is plugged between described Cross module and the descending digital interface and with described processing module and links to each other, and be used for the upstream data of multiplexing described Cross module output, and demultiplexing is input to the downlink data of described Cross module.
For the cross chips of above-mentioned ethernet mac layer, described descending digital interface is first media independent interface, and described upstream digital interface is second media independent interface.
For the cross chips of above-mentioned ethernet mac layer, also comprise the first auto-negotiation module and the second auto-negotiation module; The first auto-negotiation module links to each other respectively with first media independent interface with the described first multiplex/demultiplex unit; Mode in order to the port number of determining the first multiplex/demultiplex unit in the second multiplex/demultiplex unit and this chip in the MAC of the subordinate layer cross chips, mark that the multiplexing transmission port is corresponding, the second multiplex/demultiplex unit in the MAC of the subordinate layer cross chips and the transmission rate between the first multiplex/demultiplex unit in this chip and described multiplexing and demultiplexing; The second auto-negotiation module links to each other respectively with second media independent interface with the described second multiplex/demultiplex unit; Mode in order to the port number of determining the first multiplex/demultiplex unit in the second multiplex/demultiplex unit and the higher level MAC layer cross chips in this chip, mark that the multiplexing transmission port is corresponding, the second multiplex/demultiplex unit in this chip and the transmission rate between the first multiplex/demultiplex unit in the higher level MAC layer cross chips and described multiplexing and demultiplexing.
From technique scheme as can be seen, the present invention finishes the port interleaving function of various level physical chip in the MAC chip; On the basis of the crossed cascading system of forming by MAC layer cross chips with interleaving function, increased multiplexing transmission interface, at up direction, the MAC of subordinate layer cross chips is from the data of descending digital interface reception after the multiplexing transmission conversion, in this MAC layer cross chips inside, corresponding cross matrix is set, and the flow that needs are intersected intersects; The flow that needs are transmitted sends to the upstream digital interface, after the multiplexing transmission conversion, sends to the descending digital interface of higher level MAC layer cross chips; At down direction, after higher level MAC layer cross chips finished cross processing, data after intersecting from this chip of downlink port output and/or descending data of level chip from it after the multiplexing transmission conversion, send to the upstream digital interface of the MAC of subordinate layer cross chips and/or physical chip.
Use multiplexing transmission interface provided by the invention, make and can dock the descending upstream digital port of physical chip and/or MAC layer chip, the data of transmission each other can be discerned mutually with the high-speed port of MAC layer chip; Thereby save the chip pin number of two ends chip correspondence, also reduced the cost of chip and equipment.And when this multiplexing transmission interface comprised media independent interface, technical solution of the present invention had maximum versatility.
In addition, when this multiplexing transmission interface also includes the auto-negotiation module, make this multiplexing transmission interface have the auto-negotiation function, and then make the multiplex transmission method that is applied on this device can satisfy more different types of application demands.
Description of drawings
Fig. 1 is the functional block diagram of physical layer multiplex chip in the prior art;
The structured flowchart of the cascade system that Fig. 2 physical chip multiplexing for use and interleaving techniques constitutes;
Fig. 3 is the structural representation of MAC layer crossed cascading system of the present invention;
Fig. 4 is the structural representation that is applied to the ethernet mac layer cross chips in the cascade system shown in Figure 3 provided by the invention;
The cross processing flow chart that Fig. 5 is carried out for MAC layer cross chips in the MAC layer crossed cascading system of the present invention;
The multiplexing transmission conversion process flow process of Fig. 6 for being carried out in the MAC layer crossed cascading system of the present invention;
Fig. 7 is the structural representation of one of specific implementation of multiplexing transmission interface of the present invention;
Fig. 8 is two a structural representation of the specific implementation of multiplexing transmission interface of the present invention;
Fig. 9 is three a structural representation of the specific implementation of multiplexing transmission interface of the present invention;
Figure 10 is the structural representation of a kind of ethernet mac layer cross chips provided by the invention.
Embodiment
As previously mentioned, technical scheme provided by the invention has realized the function of ethernet mac layer intersection cascade, describe the internal structure of the MAC layer cross chips that uses in the structure, this cascade system of the crossed cascading system of ethernet mac layer of the present invention in detail below in conjunction with accompanying drawing, and in this crossed cascading system the steps flow chart of transmission data method.Need to prove, among Fig. 3 with Fig. 2 in the meaning of identical number designation representative different.S among Fig. 5 and Fig. 6 represents step.
See also Fig. 3, Fig. 3 is the structural representation of ethernet mac layer crossed cascading system embodiment provided by the invention.The crossed cascading system of this ethernet mac layer, described system comprises two-stage MAC layer cross chips layer, first order MAC layer cross chips layer comprises the MAC layer cross chips (MAC layer chip #1, MAC layer chip #2) of two 100M, and second level MAC layer cross chips layer comprises the MAC layer cross chips (MAC layer chip #3) of 1 1000M.
In actual applications, this cascade system can comprise multistage MAC layer cross chips layer, and every grade of MAC layer cross chips layer comprises a MAC layer cross chips at least; And the descending digital interface of MAC layer cross chips is with the upstream digital interface of physical chip links to each other by multiplexing transmission interface in the first order, and the descending digital interface of MAC layer cross chips can link to each other by multiplexing transmission interface respectively with the upstream digital interface of the MAC of subordinate layer cross chips and/or physical chip during all the other were at different levels.
As shown in Figure 3, the 10M physical layer cross chips of 88 ports (PHY chip #1, PHY chip #2 ... PHY chip #8) upstream Interface links to each other by the downstream interface of the MAC layer cross chips #1 in multiplexing transmission interface and the first order, the 10M physical layer cross chips of 88 ports (PHY chip #9, PHY chip #10 ... PHY chip #16) upstream Interface also links to each other by the downstream interface of the MAC layer cross chips #2 in multiplexing transmission interface and the first order; The upstream Interface of the MAC layer cross chips (#1, #2) in the first order links to each other by the descending digital interface of the MAC layer cross chips (#3) in multiplexing transmission interface and the second level respectively; And the upstream Interface of the 100M physical layer cross chips of two 8 ports (PHY chip #20, PHY chip #21) links to each other by the descending digital interface of the MAC layer cross chips (#3) in multiplexing transmission interface and the second level.
Before cascade system work, by the port arrangement module in the system to the port of all physical chips and MAC layer cross chips encode (local code or Unified coding), and to each port arrangement port attribute, form the port attribute table, described port attribute comprises cross-port and transmits port that the property store of these ports is in the port attribute table.For example, suppose to have 5 chips, each chip has 4 ports, so, is numbered 1,2 when using Unified coding ... 20, when using local code, can adopt the form of local chip port coding+chip number, be i.e. during each local chip internal chiasma operation, can encode 1,2 with port ... 4, and when carrying out intersection between the different chips, just use port coding 11,12 ... 14 (are example with No. 1 chip).Preferably, can carry out Unified coding to the port of all physical chips in the system and MAC layer cross chips by the CPU of system, this port coding also can be reset according to the instruction of CPU in system works.And, to each port arrangement port attribute.
In the present embodiment, employed MAC layer cross chips can be the MAC layer cross chips with interleaving function shown in Figure 4 in the cascade system, this MAC layer cross chips is except that comprising original downlink and uplink interfaces, MAC layer access control module, MAC layer logical link layer module and IP layer interface module, the Cross module of also between the descending digital interface of MAC layer chip and MAC layer access control module, having pegged graft, the data of this Cross module in order to physical chip at the corresponding levels or next stage MAC layer cross chips are uploaded are carried out cross processing.
For above-mentioned MAC layer cross chips, can support the local code or the overall situation coding of its port.And, in MAC layer cross chips at different levels inside, the downlink port that needs are intersected is provided with the corresponding ports crosstab by the CPU of MAC layer cross chips (promptly by as the chip internal configuration module among Fig. 4) or the CPU of system, and the flow that realization intersects to needs intersects.In the ordinary course of things, owing to comprised Multiplexing module in MAC layer cross chips or the physical chip, therefore, described port crosstab can also be the port crossed array.
For convenience, we with the port crosstab to being elaborated in the interlace operation of MAC layer chip internal.
Suppose, the port one 00 of 10M physical chip (PHY chip #1) needs to intersect with the port one 09 of 10M physical chip (PHY chip #8), the port one 16 of 10M physical chip (PHY chip #8) needs to intersect with the port one 25 of 10M physical chip (PHY chip #16), all the other ports do not intersect, at this moment, the port crosstab that is disposed in this MAC layer cross chips (#1) is as shown in table 1, the port crosstab that is disposed in this MAC layer cross chips (#2) is as shown in table 2, the port crosstab that is disposed in this MAC layer cross chips (#3) is as shown in table 3, and it comprises following message: port numbers, port attribute (port crossing condition), the mutual peer port number that intersects.
Port crosstab in the table 1:MAC layer cross chips (#1)
| Port numbers | Port attribute | Mutual cross-port number |
| Port numbers 100 | Intersect | 109 |
| Port numbers 101 | Transmit | X |
| ... | ... | ... |
| Port numbers 109 | Intersect | 100 |
| ... | ... | ... |
| Port numbers 116 | Transmit | X |
Port crosstab in the table 2:MAC layer cross chips (#2)
| Port numbers | Port attribute | Mutual cross-port number |
| Port numbers 117 | Transmit | X |
| Port numbers 118 | Transmit | X |
| ... | ... | ... |
| Port numbers 125 | Transmit | X |
| ... | ... | ... |
| Port numbers 132 | Transmit | X |
Port crosstab in the table 3:MAC layer cross chips (#3)
| Port numbers | Port attribute | Mutual cross-port number |
| ... | ... | ... |
| Port numbers 101 | Transmit | X |
| ... | ... | ... |
| Port numbers | Port attribute | Mutual cross-port number |
| Port numbers 116 | Intersect | 125 |
| ... | ... | ... |
| Port numbers 125 | Intersect | 116 |
Configure after the above-mentioned MAC level contact system, in MAC layer chip at different levels, just can carry out the cross processing of MAC layer.Promptly at up direction, the MAC of subordinate layer cross chips is from the data of its descending digital interface reception after the multiplexing transmission conversion, in this MAC layer cross chips inside, to the port of needs intersection, according to the port crosstab or the port crossed array that are provided with, the flow that needs are intersected intersects; At transmitting the flow that port is transmitted needs,,, send to the descending digital interface of higher level MAC layer cross chips through the multiplexing transmission conversion by the upstream digital interface; At down direction, after higher level MAC layer cross chips finished cross processing, data after intersecting from this chip of downlink port output and/or descending data of level chip from it after the multiplexing transmission conversion, send to the upstream digital interface of the MAC of subordinate layer cross chips and/or physical chip.
In the embodiments of the invention, the CPU in the MAC layer cross chips also finishes the function of processing module, and this processing module comprises port processing module, cross processing module and transmits processing module.The port processing module in order to will according to the port attribute table, the data that the described chip of need intersects being delivered to cross-port from the data of descending digital port reception, is delivered to the forwarding port with the data that the described chip of need is transmitted; The cross processing module in order to port crosstab or the port crossed array according to described chip, with the data that cross-port need be intersected, offers the MAC layer that described Cross module carries out between port and directly intersects; And described forwarding processing module sends to the upstream digital interface of this chip in order to will transmit the data that port need be transmitted.
See also Fig. 5, the cross processing flow process that Fig. 5 is carried out for MAC layer cross chips in the MAC layer crossed cascading system of the present invention, it comprises the steps:
Step 11: the data that will receive from port, according to the port attribute table, the data that this chip of need intersects are delivered to cross-port, the data that this chip of need is transmitted are delivered to the forwarding port;
Step 12: at all cross-port, according to the port crosstab of this chip, with the data that cross-port need be intersected, the MAC layer that carries out between port directly intersects, after described multiplexing transmission conversion process, send to the upstream digital interface of physical chip and/or the MAC of subordinate layer chip;
Step 13: at all forwarding ports, will transmit the data that port need be transmitted, send to the forwarded upstream port of this chip, after described multiplexing transmission conversion process, send to the downstream interface of higher level MAC layer chip.
Specifically, if intersecting of the port one 09 of the port one 00 that only need realize 10M physical chip (PHY chip #1) and 10M physical chip (PHY chip #8) so, just can be finished in the Cross module of MAC layer cross chips (#1).As shown in table 1, the port crosstab in the MAC layer cross chips (#1) is provided with port one 00 and 109 and has cross reference, and other ports do not intersect.The cross processing module is finished two MAC layers between the port and is directly intersected, be i.e. direct interconnection according to the configuring condition of crosstab 1 in the MAC layer cross chips (#1).After the port cross processing, the MAC layer interface flow of port one 00 and 109 data is no longer delivered to the IP layer interface processing module of MAC layer cross chips (#1).
If the port one 16 of need realization 10M physical chips (PHY chip #8) intersects with the port one 25 of 10M physical chip (PHY chip #16), so, this intersection must be finished in the Cross module of MAC layer cross chips (#3).At this moment, as shown in table 1 and 2, port one 16 and port one 25 pairing port attributes are forwarding, be the data that port one 16 and port one 25 need the intersection transmission, by the Cross module of MAC layer cross chips (#1) and MAC layer cross chips (#2), be forwarded in the downstream interface of MAC layer cross chips (#3) respectively, then by the Cross module of MAC layer cross chips (#3) configuring condition according to crosstab 3, finish two MAC layers between the port and directly intersect, be i.e. direct interconnection.After the port cross processing, the MAC layer interface flow of port one 16 and 125 data is no longer delivered to the IP layer interface processing module of MAC layer cross chips (#3).
See also Fig. 3 again, in this cascade system, all link to each other between physical chip and the MAC layer chip and between next stage MAC layer cross chips and the upper level MAC layer cross chips, thereby finish the multiplexing transmission conversion process by multiplexing transmission interface.
See also Fig. 6, the multiplexing transmission conversion process flow process of Fig. 6 for being carried out in the MAC layer crossed cascading system of the present invention, it comprises the steps:
Step 21: between described physical chip port and/or the MAC of subordinate layer chip port and higher level MAC layer chip port, set up the multiplexing transmission passage;
Step 22: the data of multiplexing described physical chip port and/or the output of described MAC layer chip port, and send it to this multiplexing transmission passage;
Step 23: the data of this multiplexing transmission passage output of demultiplexing, and send it to described physical chip port and/or MAC layer chip port.
In addition, as shown in Figure 6, the above-mentioned multiplexing transmission passage of setting up can be subdivided into the following step again:
Step 211: determine the number of described transmission FPDP, and the mark of each described transmission FPDP correspondence;
Step 212: determine the transmission rate of described transmission FPDP, the transmission rate of described reception FPDP, and the transmission rate of described multiplexing transmission passage;
Step 213: mode that determine to carry out described multiplexing and described demultiplexing.
The structure of the multiplexing transmission interface shown in Fig. 3 can have as Fig. 7, Fig. 8 and form shown in Figure 9 successively from simple to complexity.
As shown in Figure 7, multiplexing transmission interface provided by the invention comprises the first multiplexing converting unit and the second multiplexing converting unit; The first multiplexing converting unit links to each other with the upstream digital interface of described physical chip and/or the MAC of subordinate layer cross chips, the upstream data that is used for the output of multiplexing described physical chip and/or the MAC of subordinate layer cross chips, and demultiplexing is input to the downlink data of described physical chip and/or the MAC of subordinate layer cross chips; The second multiplexing converting unit links to each other with the descending digital interface of higher level MAC layer chip, be used for the downlink data of multiplexing higher level MAC layer cross chips output, and demultiplexing is input to the upstream data of higher level MAC layer cross chips; Wherein, the described first multiplexing converting unit links to each other with the described second multiplexing converting unit, is used to set up the multiplexing transmission passage between the descending digital interface of the upstream digital interface of described physical chip and/or the MAC of subordinate layer cross chips and higher level MAC layer cross chips.This multiplexing transmission interface structure two multiplexing converting units of just having pegged graft between the descending digital interface of described physical chip and/or MAC layer cross chips upstream digital interface and MAC layer cross chips need not existing physical chip and MAC layer chip are changed.
As shown in Figure 8, multiplexing transmission interface provided by the invention just between the described first multiplexing converting unit and the described second multiplexing converting unit, similar to shown in Fig. 7 of the media independent interface of having pegged graft, remainder.This multiplexing transmission interface structure is because of the introducing of media independent interface, can at utmost compatible existing MAC layer chip, and make technical solution of the present invention have maximum versatility.
As shown in Figure 9, multiplexing transmission interface provided by the invention except that including the first multiplexing converting unit, the second multiplexing converting unit and the media independent interface of forming above-mentioned multiplexing transmission interface, also includes the auto-negotiation module; This auto-negotiation module links to each other with the described first and second multiplexing converting units respectively; In order to the mark of the port number of determining the described first and second multiplexing converting units, multiplexing transmission port correspondence, transmission rate between the first and second multiplexing converting units and the mode of described multiplexing and demultiplexing.
By increasing described auto-negotiation module, make this multiplexing transmission interface have the auto-negotiation function; That is to say, this multiplexing transmission interface by respectively with described physical chip and/or the MAC of subordinate layer cross chips downlink port and higher level MAC layer cross chips uplink port auto-negotiation, can set the concrete multiplexing transmission pattern of the multiplexing transmission passage of setting up by this multiplexing transmission interface, such as: the transmission rate of setting described physical chip and/or the MAC of subordinate layer cross chips downlink port, the transmission rate of described higher level MAC layer cross chips uplink port, and the transmission rate of described multiplexing transmission passage; The physical chip that setting is docked with higher level MAC layer cross chips uplink port and/or the number of the MAC of subordinate layer cross chips downlink port; And, set the multiplex mode that adopts when this multiplexing transmission interface is carried out described multiplexing and described demultiplexing.Wherein, described multiplex mode is a time division multiplexing or multiplexing based on the mark of ethernet data frame.Described ethernet data frame is labeled as privately owned port label, VLAN mark, perhaps is certain existing known multiplex mode.
Need to prove, above-mentioned multiplexing transmission interface and multiplexing transmission conversion regime, in the inventor's the file of Chinese patent application formerly " multiplexing transmission apparatus between physical layer and the MAC layer and method ", be described in detail, its application number is 200610151773.5, therefore, repeat no more.When linking to each other between the MAC of the subordinate layer cross chips in the cascade system of the present invention and the higher level MAC layer cross chips, also can use multiplexing transmission interface identical and multiplexing transmission conversion regime with patent application formerly.
Cascade system of the present invention does not have special requirement to the physical chip that uses, if comprise the physical chip of Multiplexing module, so, the upstream digital port of this physical chip also can be the port after multiplexing; If comprise the physical chip of Cross module, so, a part of port interleaving function in the system is finished earlier in this physical chip.
Realize the function of intersection for convenience at the ethernet mac layer, the present invention also provides a kind of cross chips of ethernet mac layer as shown in figure 10.Comprised the multiplexing transmission interface described in Fig. 3 in this cross chips, chips that comprise at different levels in the crossed cascading system are directly linked to each other by their up-downgoing digital interface.
As shown in figure 10, the cross chips of this MAC layer is on architecture basics shown in Figure 4, except that including up-downgoing digital interface, internal configurations module, processing module MAC layer Cross module and the MAC layer access control module etc. of forming above-mentioned cross chips, also comprise the first multiplex/demultiplex unit and the second multiplex/demultiplex unit.
The first multiplex/demultiplex unit, it is plugged between the descending digital interface of described chip and the Cross module and with described processing module and links to each other, be used for the data that the described descending digital interface of demultiplexing receives, and the multiplexing downlink data that will be input to described descending digital interface; And, the second multiplex/demultiplex unit, it is plugged between described Cross module and the descending digital interface and with described processing module and links to each other, and is used for the upstream data of the described Cross module output of demultiplexing, and the multiplexing downlink data that is input to described Cross module.
For the cross chips that makes above-mentioned ethernet mac layer has maximum versatility, can in described descending digital interface, increase the function of media independent interface, promptly become first media independent interface shown in the figure; Equally, also can in described upstream digital interface, increase the function of media independent interface, promptly become second media independent interface shown in the figure.
In addition, in order to satisfy more different types of application demands,, also comprise the first auto-negotiation module and the second auto-negotiation module for the cross chips of above-mentioned ethernet mac layer.The first auto-negotiation module links to each other respectively with first media independent interface with the described first multiplex/demultiplex unit; Mode in order to the port number of determining the first multiplex/demultiplex unit in the second multiplex/demultiplex unit and this chip in the MAC of the subordinate layer cross chips, mark that the multiplexing transmission port is corresponding, the second multiplex/demultiplex unit in the MAC of the subordinate layer cross chips and the transmission rate between the first multiplex/demultiplex unit in this chip and described multiplexing and demultiplexing; And the second auto-negotiation module links to each other respectively with second media independent interface with the described second multiplex/demultiplex unit; Mode in order to the port number of determining the first multiplex/demultiplex unit in the second multiplex/demultiplex unit and the higher level MAC layer cross chips in this chip, mark that the multiplexing transmission port is corresponding, the second multiplex/demultiplex unit in this chip and the transmission rate between the first multiplex/demultiplex unit in the higher level MAC layer cross chips and described multiplexing and demultiplexing.
In sum, the cascade system of the present invention by adopting MAC layer cross chips to be linked to be realized the method that MAC level connection transmits, and the interleaving function of the port of different physical chips is finished in the MAC chip.And service port that will intersect and the service port that needs the MAC layer to handle separate at up direction, thereby make things convenient for the different business processing module of back that business is carried out different processing.
What need statement is that foregoing invention content and embodiment are intended to prove the practical application of technical scheme provided by the present invention, should not be construed as the qualification to protection range of the present invention.Those skilled in the art are in spirit of the present invention and principle, when doing various modifications, being equal to and replacing or improve.Protection scope of the present invention is as the criterion with appended claims.
Claims (17)
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007100020946A CN101227291B (en) | 2007-01-18 | 2007-01-18 | Ethernet MAC layer cross-connection system, transmission method and chip for its application |
| PCT/CN2007/070077 WO2007143944A1 (en) | 2006-06-02 | 2007-06-01 | Method and apparatus for forwarding data in ethernet |
| US12/323,053 US8149870B2 (en) | 2006-06-02 | 2008-11-25 | Method and apparatus for forwarding data in ethernet |
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| CN2007100020946A CN101227291B (en) | 2007-01-18 | 2007-01-18 | Ethernet MAC layer cross-connection system, transmission method and chip for its application |
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| CN101227291B true CN101227291B (en) | 2010-09-22 |
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| CN101442563A (en) * | 2008-12-17 | 2009-05-27 | 杭州华三通信技术有限公司 | Data communication method and Ethernet equipment |
| TWI466519B (en) * | 2010-11-29 | 2014-12-21 | Realtek Semiconductor Corp | Network device and network connection method |
| CN110737627B (en) * | 2019-10-11 | 2023-10-03 | 苏州盛科通信股份有限公司 | Data processing method, device and storage medium |
| CN115714637A (en) * | 2022-09-13 | 2023-02-24 | 南京濠暻通讯科技有限公司 | Message transmission device and method based on SRIO time division multiplexing and demultiplexing |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1356806A (en) * | 2001-12-31 | 2002-07-03 | 刘军民 | Data forwarding method for implementing virtual channel transmission in LAN |
| CN1472928A (en) * | 2002-07-31 | 2004-02-04 | 华为技术有限公司 | Method and device for realizing virtual local area network transparent transmission on Ethernet switch |
-
2007
- 2007-01-18 CN CN2007100020946A patent/CN101227291B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1356806A (en) * | 2001-12-31 | 2002-07-03 | 刘军民 | Data forwarding method for implementing virtual channel transmission in LAN |
| CN1472928A (en) * | 2002-07-31 | 2004-02-04 | 华为技术有限公司 | Method and device for realizing virtual local area network transparent transmission on Ethernet switch |
Non-Patent Citations (2)
| Title |
|---|
| 潘小林，李生红.以太网MAC-MAC互连的分析及实现.国外电子元器件 第6期.2005,(第6期),第15-18页. |
| 潘小林,李生红.以太网MAC-MAC互连的分析及实现.国外电子元器件 第6期.2005,(第6期),第15-18页. * |
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