CN101226906A - Chip carrier with dam - Google Patents

Abstract

The invention discloses a chip carrier with a blocking dam, which mainly comprises a base material, a protective layer and the blocking dam. The substrate is provided with a plurality of first connecting pads and a plurality of second connecting pads, the protective layer is formed on the surface of the substrate, the protective layer is provided with a groove, a plurality of first openings and a plurality of second openings, the groove is formed between the first openings and the second openings, the groove is provided with a first side wall and a second side wall, the first openings and the second openings respectively expose the first connecting pads and the second connecting pads, and the dam is formed between the first side wall and the second side wall of the groove and protrudes out of the protective layer. The dam has the function of preventing the chip carrier from being polluted by the overflow of the underfill, and the width and the height of the dam can be controlled because the dam is formed in the groove of the protective layer, and the contact area and the bonding strength between the dam and the protective layer can be increased to prevent the dam and the protective layer from being peeled off. The invention also discloses a semiconductor structure.

Description

Chip carrier with dams

technical field

The invention relates to a chip carrier, in particular to a chip carrier capable of preventing overflow glue from polluting connection pads.

Background technique

A known substrate has a plurality of bump connection pads and a plurality of solder ball connection pads, usually the bump connection pads and the solder ball connection pads are located on the same plane of the substrate and the bump connection pads and the solder ball connection pads are in phase Adjacent, due to the current requirements for electronic products to be light, thin and short, the distance between the bump connection pad and the solder ball connection pad is quite small. When the chip is electrically connected to the substrate with bumps and filled with underfill When sealing the bump between the substrate and the chip, the underfill is likely to overflow to the solder ball connection pad and contaminate the adjacent solder ball connection pad, causing the solder ball connection pad to be damaged in subsequent processes. Unable to smoothly bond with solder balls.

Contents of the invention

The main purpose of the present invention is to provide a chip carrier with a dam, a protective layer is formed on the substrate surface of a substrate having a plurality of first connection pads and a plurality of second connection pads, the protection layer has grooves, A plurality of first openings and a plurality of second openings, wherein the groove is formed between the first opening and the second opening, the groove has a first side wall and a second side wall, and a dam is formed in the groove The groove is between the first sidewall and the second sidewall and protrudes from the protective layer. The dam has the effect of preventing the overflow of underfill glue from polluting the chip carrier, and the dam is formed in the groove of the protective layer, so the width and height of the dam can be controlled, and the dam can be increased The contact area and bonding strength between the dam and the protective layer are used to prevent the dam from being peeled off from the protective layer.

A chip carrier with a dam according to the present invention mainly includes a substrate, a protective layer and a dam, the substrate has a surface of the substrate, a plurality of first connection pads and a plurality of second connection pads, the protection layer forms On the substrate surface of the substrate, the protective layer has a groove, a plurality of first openings and a plurality of second openings, wherein the groove is formed between the first opening and the second opening, and the groove It has a first side wall and a second side wall, the first opening and the second opening reveal the first connection pad and the second connection pad respectively, and the dam is formed on the first side wall and the second connection pad of the groove. between the second sidewalls and protrude from the protective layer.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a chip carrier with dams according to a first embodiment of the present invention.

FIG. 2 is a top view of the chip carrier with dams according to the first embodiment of the present invention.

FIG. 3 is a top view of another chip carrier with dams according to the second embodiment of the present invention.

FIG. 4 is a top view of another chip carrier with dams according to a third embodiment of the present invention.

FIG. 5 is a top view of another chip carrier with dams according to a fourth embodiment of the present invention.

6 is a schematic cross-sectional view of the application of the chip carrier with dams to a semiconductor structure according to the first embodiment of the present invention.

Explanation of reference signs

100 chip carrier 110 substrate

111 substrate surface 112 first connection pad

113 second connection pad 120 protective layer

121 groove 121a first side wall

121b second side wall 122 first opening

123 second opening 124 protective layer surface

130 Barrage 140 Line layer

200 semiconductor structure 210 chip carrier

211 base material 212 protective layer

213 Barrage 214 First connection pad

215 second connection pad 216 groove

216a first side wall 216b second side wall

217 First opening 218 Second opening

219 protective layer surface 220 chip

221 Bump 230 Underfill

Detailed ways

Please refer to FIG. 1 , according to a specific embodiment of the present invention, a chip carrier 100 with a dam is disclosed, which mainly includes a substrate 110, a protective layer 120 and a dam 130. The substrate 110 can be selected from a chip , chip or circuit board, the substrate 110 has a substrate surface 111, a plurality of first connection pads 112 and a plurality of second connection pads 113, the first connection pads 112 and the second connection pads 113 are formed on the substrate Surface 111, in addition, the chip carrier 100 further includes a circuit layer 140, the circuit layer 140, the first connection pad 112 and the second connection pad 113 can be formed by a metal layer after a patterning step, in this embodiment , the base material 110 is a printed circuit board, the protective layer 120 is a solder mask, such as green paint, the first connection pad 112 is a bump connection pad, and the second connection pad 113 is a solder ball connection pad. The protective layer 120 is formed on the substrate surface 111 of the substrate 110, and the protective layer 120 covers the circuit layer 140, the protective layer 120 has a groove 121, a plurality of first openings 122 and a plurality of second openings 123, wherein the groove 121 is formed between the first opening 122 and the second opening 123, the groove 121 has a first side wall 121a and a second side wall 121b, the groove 121 can reveal the circuit layer 140, or, in other embodiments, the groove 121 does not expose the circuit layer 140, and the shape of the groove 121 can be selected from a "mouth" shape, a "ㄇ" shape, an "I" shape or an "L" shape, Please refer to Figures 2 and 3, the groove 121 can be a continuous "mouth" shape, "ㄇ" shape, "I" shape or "L" shape, or, please refer to Figures 4 and 5, the groove 121 It can also be a discontinuous "mouth" shape, "ㄇ" shape, "I" shape or "L" shape, please refer to Figure 1 again, the first opening 122 and the second opening 123 reveal the first connection pad respectively 112 and the second connection pad 113, the dam 130 is formed between the first side wall 121a and the second side wall 121b of the groove 121, and the dam 130 protrudes from the protective layer 120, the The material of the dam 130 is selected from metal or resin, and the forming method of the dam 130 is selected from electroplating, printing or coating methods. In this embodiment, the dam 130 contacts the first side of the groove 121 wall 121a and the second side wall 121b, and the dam 130 protrudes from the protective layer surface 124 of the protective layer 120, or in another embodiment, the dam 130 can extend to contact the protective layer of the protective layer 120. layer surface 124 . Since the dam 130 is formed in the groove 121 of the protective layer 120, the width and height of the dam 130 can be controlled, and since the dam 130 contacts the first side wall 121a of the groove 121 and the The second side wall 121b can therefore increase the contact area and bonding strength between the dam 130 and the protective layer 120, so as to avoid peeling off the dam 130 and the protective layer 120. The chip carrier 100 of the present invention can be applied to semiconductors structure, such as a chip stack structure or a semiconductor package structure, to prevent the underfill glue from overflowing and contaminating the chip carrier 100 .

Please refer to FIG. 6 , a semiconductor structure 200 using the above-mentioned chip carrier, the semiconductor structure 200 may be a chip stack structure or a semiconductor package structure, which includes a chip carrier 210 , a chip 220 and an underfill 230 . The chip carrier 210 includes a substrate 211, a protective layer 212 and a dam 213. In this embodiment, the substrate 211 is a circuit board, and the protective layer 212 is a solder mask, such as green paint. The substrate 211 has A plurality of first connection pads 214 and a plurality of second connection pads 215, the protection layer 212 is formed on the substrate 211 and has a groove 216, a plurality of first openings 217 and a plurality of second openings 218, wherein the concave The groove 216 is formed between the first opening 217 and the second opening 218. The groove 216 has a first sidewall 216a and a second sidewall 216b. The first opening 217 and the second opening 218 respectively expose the first A connection pad 214 and the second connection pad 215, the dam 213 is formed between the first side wall 216a and the second side wall 216b of the groove 216, and the dam 213 protrudes from the protective layer 212 of the protective layer surface 219, in this embodiment, the dam 213 contacts the first side wall 216a and the second side wall 216b of the groove 216, the chip 220 has a plurality of bumps 221, the chip 220 The chip carrier 210 is flip-chip soldered and the bump 221 of the chip 220 is electrically connected to the first connection pad 214 of the chip carrier 210. In this embodiment, the first connection pad 214 is a bump connection pad, the second connection pad 215 is a solder ball connection pad, the underfill 230 is formed between the chip 220 and the chip carrier 210 to seal the bump 221, in this embodiment, the dam 213 Formed in the groove 216 and protruding from the protective layer 212, the height of the dam 213 is smaller than the height of the protrusion 221, or, in another embodiment, the height of the dam 213 can be equal to or greater than the The height of the bump 221 . Before the chip carrier 210 disposes a plurality of solder balls (not shown) on the second connection pad 215, the underfill 230 is first formed between the chip carrier 210 and the chip 220 to seal and protect the bumps. Block 221, the underfill 230 can be limited between the bump 221 and the dam 213 by the dam 213, so as to prevent the underfill 230 from overflowing to the second connection pad 215 and contaminating the second pad 215. The connection pad 215, in addition, because the dam 213 is formed in the groove 216 of the protective layer 212, the width and height of the dam 213 can be controlled, so as to avoid spreading and contaminating the first dam 213 when forming the dam 213. The connection pad 214 and the second connection pad 215, and since the dam 213 contacts the first side wall 216a and the second side wall 216b of the groove 216, the distance between the dam 213 and the protective layer 212 can be increased. contact area and bonding strength, or, in another embodiment, the dam 213 does not contact the first sidewall 216 a and the second sidewall 216 b of the groove 216 .

The scope of protection of the present invention shall be defined by the appended claims. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall all belong to the scope of protection of the present invention.

Claims (11)

1. A chip carrier with a dam comprising: a substrate having a substrate surface, a plurality of first connection pads and a plurality of second connection pads, the first connection pads and the second connection pads are formed on the substrate surface; A protective layer formed on the substrate surface of the substrate, the protective layer has a groove, a plurality of first openings and a plurality of second openings, wherein the groove is formed between the first opening and the second opening and the groove has a first sidewall and a second sidewall, the first opening and the second opening expose the first connection pad and the second connection pad respectively; and The dam is formed between the first sidewall and the second sidewall of the groove and protrudes from the protection layer. 2. The chip carrier of claim 1, wherein the dam contacts the first sidewall and the second sidewall of the groove. 3. The chip carrier as claimed in claim 1, wherein the groove is in a continuous "mouth" shape, "ㄇ" shape, "I" shape or "L" shape. 4. The chip carrier as claimed in claim 1, wherein the groove is in a discontinuous "mouth", "ㄇ" shape, "I" shape or "L" shape. 5. The chip carrier as claimed in claim 1, wherein the passivation layer has a passivation layer surface, and the dam extends to contact the passivation layer surface of the passivation layer. 6. The chip carrier as claimed in claim 1, further comprising a circuit layer, the protective layer covering the circuit layer. 7. The chip carrier as claimed in claim 6, wherein the groove exposes the circuit layer. 8. The chip carrier as claimed in claim 1, wherein the first connection pad is a bump connection pad, and the second connection pad is a solder ball connection pad. 9. The chip carrier as claimed in claim 8, wherein the bump pad is used to electrically connect a flip chip. 10. The chip carrier as claimed in claim 9, further comprising an underfill filling between the flip chip and the chip carrier. 11. The chip carrier as claimed in claim 1, wherein the forming method of the dam is selected from electroplating, printing or coating methods.

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