CN101201517A - Driving circuit for active matrix type display device - Google Patents

Abstract

The invention provides an active matrix display device for saving the number of shift registers in a gate driver. In the active matrix display device of the present invention, the active matrix display device comprises a pixel matrix configured by a plurality of pixels in a matrix shape of N segments × P rows and Y columns, a source driver for driving a data line connected to a source terminal of a pixel TFT in each pixel, and a gate driver for driving a scan line connected to a gate terminal of the pixel TFT, wherein the gate driver comprises at least one shift register in each segment and N × P gate control elements, and an output line of the shift register of each segment is connected to input terminals of P gate control elements in each segment to output a plurality of gate control pulses.

Description

Driving circuit for active matrix type display device

technical field

The present invention relates to a driving circuit for an active matrix display device, in particular to an active matrix display device capable of reducing the size of the driving circuit for driving each pixel and enlarging the effective display area.

Background technique

Two parallel transparent substrates are arranged in the liquid crystal display device, pixel electrodes are arranged on the opposite surfaces, and a liquid crystal layer is arranged between the two transparent substrates. In the liquid crystal display device, the active matrix liquid crystal display device is that the pixel electrodes are arranged in a matrix to represent the pixels. (off) switching element.

FIG. 3 is a structural diagram of a known active matrix liquid crystal display device. The structure and operation of the known liquid crystal display device are described below according to this figure, wherein the liquid crystal panel 1 is an active matrix liquid crystal panel, and has pixel electrodes 30, scanning signal lines 31, data signal lines 32, switching elements 33 and counter electrodes 34 .

The pixel electrodes 30 are electrodes arranged in a matrix shape in the row direction and the column direction. The scanning signal lines 31 are scanning signal lines for selecting pixels in the same direction, and p scanning signal lines are arranged along the row direction of the liquid crystal panel. The data signal line 32 is a data signal line for transmitting an applied voltage to pixels in the same column direction according to display data, and q data signal lines are arranged along the column direction of the liquid crystal panel. The switch element 33 is a switch element for transmitting the data of the data signal line to the pixels of the liquid crystal unit according to the scanning signal, and is composed of, for example, a thin film transistor (Thin Film Transistor, TFT). The opposite electrode 34 is an electrode for providing a common voltage to each liquid crystal cell. The liquid crystal cell is sandwiched between the pixel electrode 30 and the counter electrode 34 . A liquid crystal cell is sandwiched between a group of pixel electrodes 30 and the counter electrode 34 . A liquid crystal cell sandwiched by a set of pixel electrodes 30 and counter electrodes 34 is called a pixel.

In the liquid crystal cell, the function of adjusting the optical shutter is achieved by applying a voltage between the pixel electrode 30 and the counter electrode 34 . The pixels are regularly divided into RGB, and an RGB color filter is set on the opposite electrode 34 side, and the RGB light is synthesized in the human eye to recognize a color image. According to the configuration of RGB pixels, the data line 32 can be divided into RGB data lines.

The gate driver 2 is a circuit for sequentially applying p scanning signals X1, X2, . . . , Xp to the scanning signal lines 31 in the liquid crystal panel 1 . The source driver 3 is a circuit that generates voltages corresponding to display data on the data signal lines 32 in the liquid crystal panel 1 and outputs these voltages as pixel signals Y1, Y2, . . . , Yq. The signal processing circuit 4 receives image signals from the outside, outputs display data to the source driver 3 , and outputs control signals to the gate driver 2 and the source driver 3 .

Next, an operation for displaying an image on the liquid crystal panel 1 will be described. The signal processing circuit 4 controls the gate driver 2 with the control signal, and applies a scanning signal to the scanning signal line 31 of any row of the liquid crystal panel 1 . Therefore, the switching elements 33 in this row are in an on state, and the data lines 32 in each column are connected to the pixel electrodes 30 . The signal processing circuit 4 supplies to the source driver 3 in advance the data required by the pixels of each column on the row for which the scanning signal is supplied. Therefore, the source driver 3 converts the display data into a voltage applied to each pixel electrode 30 and outputs it while the switching element 33 is in the on state. Therefore, the signal processing circuit 4 scans according to the sequence from the uppermost row (i=1) to the lowermost row (i=p) of the liquid crystal panel 1 , and provides display data for all the pixel electrodes 30 .

Next, the configuration of the gate driver 2 will be described with reference to FIG. 2 . The output lines of the one-stage shift registers 22a, 22b, 22c, and 22d are respectively connected to input terminals of AND gates (AND) 25a, 25b, 25c, and 25d. The other input terminal of each AND gate is individually connected to enable signal lines 24a, 24b, 24c, 24d. Output terminals of the respective AND gates 25a, 25b, 25c, 25d are connected to buffers 26a, 26b, 26c, 26d, respectively. Therefore, since the shift registers 22a, 22b, 22c, and 22d are provided corresponding to the AND gates 25a, 25b, 25c, and 25d, the area of the shift register is relatively large, so the use area of the gate driver is also relatively large. It will cause the ratio of the image area to decrease.

Contents of the invention

In view of this, the object of the present invention is to reduce the usage area of the shift register in the gate driver of the active matrix display device, thereby reducing the proportion of the usage area of the gate driver in the device. Thereby, the objectives of device miniaturization, enlarged image display area and cost reduction can be achieved.

In the gate driver of an active matrix display device, the shift register configured to each gate control element is set collectively for each segment (all with N segments) composed of a plurality of gate control elements, so the shift register The sum of will be reduced to 1/P.

Concrete structure of the present invention is as follows:

(1) In the active matrix display device of the present invention, a pixel matrix configured by a plurality of pixels in a matrix shape of N sections×P rows and Y columns is used to drive the TFT sources connected to the pixels in each pixel. A source driver for extreme data lines, and a gate driver for driving a scan line connected to the gate terminal of the pixel TFT, wherein the gate driver includes at least one shift register in each segment, and includes N×P A gate control element, the output lines of the shift registers of each segment are connected to the input terminals of the P gate control elements in each segment, so as to output a plurality of gate control pulses.

(2) In the active matrix type display device as in item (1), the gate driver may drive each pixel row in a descending order or in a reverse order.

(3) In the active matrix type display device as in (1) or (2), driving may be performed in any order.

(4) In the active matrix type display device as in any one of (1) to (3), the gate control element is an AND gate (AND).

Invention effect

The gate driver of the present invention can reduce the number of redundant shift registers in the gate driver in the past, and can reduce the small layout area, so as to achieve the purpose of miniaturization of active matrix display devices and reduction of display frame.

In addition, not only the general normal or reverse driving mode, but also the purpose of arbitrary scanning can be achieved by changing the selection sequence of the enabling lines.

Description of drawings

FIG. 1 shows a schematic diagram of an embodiment of a gate driver for an active matrix display device of the present invention.

FIG. 2 is a schematic diagram of an example of a gate driver of a conventional active matrix display device.

FIG. 3 is a structural diagram of a known active matrix type liquid crystal display device.

Description of main component symbols

1-LCD panel;

2- gate driver;

3 - source driver;

4- Signal processing circuit;

11 - shift register;

12-carry input line;

13 - shift register output line;

14a - enable line;

14b - enable line;

14c - enable line;

14d - enable line;

15a - AND gate;

15b-AND gate;

15c - AND gate;

15d-AND gate;

16a - buffer;

16b - buffer;

16c-buffer;

16d - gate buffer;

17a-gate output line;

17b-gate output line;

17c-gate output line;

17d-gate output line;

22a - shift register;

22b - shift register;

22c - shift register;

22d - shift register;

25a-25d-AND gate;

26a-26d - buffers;

30-pixel electrode;

31-scan signal line;

32-data signal line;

33 - switching element;

34 - Counter electrode.

Detailed ways

The present invention is described in detail based on the examples shown below. However, this is only an example, and is not intended to limit the scope of the present invention to this embodiment.

As shown in FIG. 1, the output line 13 of the shift register 11 is connected to the input terminals of four AND gates 15a, 15b, 15c and 15d in each stage. The other inputs of the AND gates are connected to respective enable lines 14a, 14b, 14c and 14d. In addition, the output terminals of the AND gates 15a, 15b, 15c and 15d are respectively connected to the buffers 16a, 16b, 16c and 16d. The outputs of the buffer circuits are connected to gating lines 17a, 17b, 17c and 17d, respectively. The shift register 11 receives a carry signal 12 from the previous stage. Here, when the shift register 11 is in an active state, in order to make one terminal of each AND gate in this section be high level (HI), enable the line to be high level, and make the data line 17 through the buffer to the active state. Enable pulses are sequentially input to 14a, 14b, 14c and 14d, so that gate lines 17a, 17b, 17c and 17d are sequentially selected. Thereafter, the clock signal is input to the shift register, and the driving of this stage is ended.

In the above embodiment, although the gate control element is described as an AND gate, it is obviously also applicable to the case of other gate control elements, such as a NOR gate (NOR).

In addition, in the above-mentioned embodiment, although the driving sequence of the enabling lines is gradually rising or falling gradually, the driving sequence of more than one gate line in the same segment can be changed, by changing the driving sequence of adjacent segments. In order, the effect of arbitrary scanning can be achieved.

In addition, in the above embodiment, although the gate control element is an AND gate for illustration, it is obviously also applicable to the case of other gate control elements, such as a NOR gate (NOR).

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, the protection scope of the present invention shall be determined by the scope of the appended claims.

Claims (4)

1. active matrix type display, it comprises:

Picture element matrix, the matrix shape that is listed as by the capable Y of a plurality of pixel basis N section * P is disposed;

Source electrode driver is connected to the data line of pixel TFT source terminal in described each pixel in order to driving; And

Gate drivers is connected to the sweep trace of described pixel TFT gate terminal in order to driving;

Wherein said gate drivers comprises at least one shift register in each section, and comprises N * P gating element, and the output line of the shift register of described each section is connected to the input end of P described gating element in described each section, to export a plurality of gating pulses.

2. active matrix type display as claimed in claim 1, wherein said gate drivers is according to descending order or reverse sequence drive each pixel column gradually.

3. active matrix type display as claimed in claim 1 or 2, wherein said gate drivers drives according to random order.

4. active matrix type display as claimed in claim 1, wherein said gating element are and door (AND).

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