CN101176254A - Discrete clock generator and/or timing/frequency reference - Google Patents

Abstract

In various embodiments, the present invention provides a discrete clock generator and/or timing and frequency reference using an LC oscillator topology with a frequency controller that controls and provides a stable resonant frequency that is in turn provided to other secondary circuits such as a processor or controller. Frequency stability is maintained over selected parameters such as temperature and manufacturing process variations. Various apparatus embodiments include a sensor adapted to provide a signal in response to at least one of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In an exemplary embodiment, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules selectively connectable to the resonator or one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances and may be binary weighted. An array of resistor modules is also provided to generate one or more control voltages.

Description

Discrete clock generator and/or timing/frequency reference

technical field

The present invention relates generally to oscillatory or clocked signal generation, and more particularly to discrete clock signal generators and timing/frequency references that are self-exciting, self-referencing, accurate over manufacturing process, voltage and temperature, and have low jitter.

Background technique

An accurate clock generator or timing reference typically relies on a crystal oscillator, such as a quartz oscillator, which provides mechanical resonance at a specific frequency. The difficulty with such crystal oscillators is that they cannot be manufactured as part of the same integrated circuit (IC) that will be driven by its clock signal. For example, microprocessors such as the Intel Pentium processor require a separate clock IC. For this reason, virtually every circuit that requires an accurate clock signal requires an off-chip clock generator.

There are several consequences for such a non-integrated solution. For example, since the processor must be connected through external circuitry, such as circuitry on a printed circuit board (PCB), power dissipation is relatively increased. In applications that rely on limited power sources, such as mobile communications on battery power, this extra power dissipation can be very detrimental.

Additionally, non-integrated solutions increase space and area requirements by requiring additional ICs, either on the PCB or within the finished product, which is also detrimental in a mobile environment. Furthermore, such additional components also increase manufacturing and production costs, since additional ICs must be fabricated and assembled with the main circuit (eg, microprocessor).

Other clock generators that have been manufactured as circuits integrated with other circuits are generally not accurate enough, which varies with manufacturing process, voltage and temperature (PVT). For example, ring, relaxation, and phase-shift oscillators can provide clock signals suitable for some low-sensitivity applications, but cannot provide the higher accuracy required by more complex electronic circuits, such as those requiring high processing power or data communication. required accuracy. Furthermore, these clock generators or oscillators typically exhibit considerable frequency shift, jitter, have relatively low Q values, and suffer from other distortions from noise and other disturbances.

To this end, there is a need for a clock generator or timing reference that can be monolithically integrated with other circuits such as a single IC and that remains highly accurate over PVT variations. Such a clock generator or timing reference should be self-exciting and self-referencing and should not need to lock to or reference another reference signal. Such a clock generator or timing reference should exhibit minimal frequency shift and have relatively low jitter, and should be suitable for applications requiring a highly accurate system clock. Such a clock generator or timing reference should also provide multiple modes of operation, including clock mode, reference mode, energy conservation mode, and pulsed mode. Finally, such a clock generator or timing reference should be able to control the output frequency to provide a stable and desired frequency in response to changes in the environment or junction temperature or changes in other parameters such as voltage, manufacturing process, frequency and age.

Contents of the invention

In various exemplary embodiments, the invention provides an apparatus for generating a frequency reference signal. The device includes a resonator, which may use one or more inductors and capacitors (as an LC tank); a transconductance amplifier; a low-jitter, self-oscillating and self-referencing clock generator and/or timing and frequency Reference is made to frequency controllers and temperature compensators that provide open loop frequency control and selection, are highly accurate over PVT and age (time) variations and can be monolithically integrated with other circuits to form a single integrated circuit. A separate reference oscillator is not required, and the exemplary embodiments are not phase locked, delay locked or otherwise locked to any other frequency reference. Rather, exemplary embodiments may be used as the reference oscillator, which generates a frequency reference signal to which one or more phase-locked or delay-locked loops are then locked. Various exemplary embodiments of the present invention include features that produce highly accurate frequency over fabrication process, voltage, and temperature (PVT) variations. These features include frequency tuning and selection, compensating for frequency variations due to temperature and/or voltage fluctuations, manufacturing process variations, and variations due to integrated circuit aging.

The invention can be provided as a discrete integrated circuit providing a clock signal or other frequency reference signal, which can then be combined with other integrated circuits for any user application. The inventive device can be configured or programmed for frequency selection, signal selection, input/output (I/O) selection, I/O pin selection, spread spectrum selection, and other selections. Several methods are provided for such configuration and programming, including mask programmability during IC design and fabrication, manufacturer or distributor programmability after IC fabrication, and user programmability after IC fabrication.

The invention can also be combined with other integrated circuits to form a single package, usually provided in a single IC package. For example, the clock generator and/or timing and frequency reference of the present invention may be combined with any other second circuit of any kind or type for any function or application such as a different processor, controller, digital signal processor, etc., to A second circuit provides an integrated, self-running clock that does not need to be synchronized or locked to an external reference such as a crystal oscillator.

By way of example and not limitation, a clock generator and/or timing and frequency reference may be combined with any of the following types of processors: microprocessors, digital signal processors, controllers, microcontrollers, universal serial bus (USB) Controllers, Peripheral Component Interconnect (PCI) Controllers, Peripheral Component Interconnect Express (PCI-e) Controllers, FireWire Controllers, AT Attachment (ATA) Interface Controllers, Integrated Drive Electronics (IDE) Controllers, Small Computer System Interface (SCSI) Controllers, Television Controllers, Local Area Network (LAN) Controllers, Ethernet Controllers, Video Controllers, Audio Controllers, Modem Processors, MPEG Controllers, Multimedia Controllers, Communication Controllers, Mobile Communication controller, IEEE 802.11 controller, GSM controller, GPRS controller, PCS controller, AMPS controller, CDMA controller, WCDMA controller, spread spectrum controller, wireless LAN controller, IEEE 802.11 controller, DSL controller controller, T1 controller, ISDN controller, or cable modem controller. Numerous other types of secondary circuitry for integration with the inventive clock generator and/or timing and frequency reference are also within the scope of the invention.

For the exemplary embodiment, a clock generator and/or a timing and frequency reference provides a first reference signal having a first frequency f ₀ . The first reference signal can be used in any of a variety of ways, such as: (1) used directly by a second circuit as a clock control or frequency reference signal; (2) provided to one or more square wave generators or divider circuits , the resulting substantially square wave or frequency-divided signal is provided as output (as one or more second reference signals at selected frequencies (e.g., with frequencies f ₀ , f ₁ , f ₂ , . . . f _K ), any of which One or more are then used as a clock control or frequency reference signal by a second circuit); (3) for locking of a locking circuit, such as one or more phase-locked loops, delay-locked loops, or injection-locked circuits, or by splitter Using a combination of frequency and locking circuits, one or more second reference signals at selected frequencies (eg having frequencies f _K+1 , f _K+2 , . . . f _N ) are also provided as outputs to the second circuit.

These one or more second reference signals may be converted, multiplexed or provided directly to any second circuitry, such as processors, memory and input/output interfaces, which act as clocks or reference signals at a selected frequency. These signals may also be provided in any of a variety of forms, such as single-ended, differential, phase-shifted, quadrature, including inverting and/or non-inverting forms.

Frequency selection for any frequency (f ₀ , f ₁ , f ₂ , . . . f _N ) can be provided in a variety of ways, according to selected embodiments. Frequency selection can occur as part of design and manufacturing, such as by selecting the number and size of inductors and capacitors used in clock generators and/or IC oscillators for timing and frequency references. For example, the size and/or shape of one or more inductors can be selected with appropriate metal layer shielding, and capacitors can be sized to produce a particular frequency or range of frequencies. Frequency selection can also occur post-manufacture by using various calibration and control coefficients or signals as detailed below. In addition, frequency selection can be performed by configuring one or more lock circuits, such as by selecting a frequency division ratio through a programmable counter in a phase-locked loop, which can be part of the design and manufacture of the IC; or can be programmed after manufacture, The same is done by using calibration and control coefficients or signals or by switching frequency dividers into or out of frequency division chains. Additional configuration methods are detailed below.

Alternative embodiments also generate multiple frequency reference signals, whether sinusoidal or square wave signals, such as for use as one or more clock signals or reference frequency sources. In an exemplary embodiment, the clock/frequency reference of the present invention is connected to one or more phase locked loops (PLL) or delay locked loops (DLL) to provide a corresponding plurality of output reference signals at selected frequencies. Different exemplary embodiments can be configured or programmed through control signals or stored coefficients, such as adjusting the frequency division ratio of a PLL or DLL for a corresponding frequency selection.

For applications that may require high Q, low jitter, and low phase noise, the resonator typically includes one or more inductors and capacitors, forming one or more LC tanks or LC resonators. In a first embodiment, a double balanced differential LC resonator layout is used. In other exemplary embodiments, a differential or single-ended LC oscillator topology may be used, such as a differential n-MOS cross-connected topology, a differential p-MOS cross-connected topology, a single-ended Corpis LC oscillator, a single-ended Hartley LC Oscillators, Differential Colpitts LC Oscillators (Common Base and Common Collector Versions), Differential Hartley LC Oscillators (Common Base and Common Collector Versions), Single-Ended Pierce (Pierce) LC oscillators, quadrature oscillators (eg formed from at least two double balanced, differential LC oscillators). In any of these embodiments, an active inductor may be used in an LC oscillator or other reactive component. Any of these LC layouts can be implemented as balanced, cross-connected, differential, or single-ended layouts, and can use any type of transistor, such as n-MOS, p-MOS, or BJT. Alternative LC oscillator arrangements, whether now known or soon to be known, are considered equivalent arrangements and are within the scope of the present invention.

Exemplary embodiments of the present invention also provide several different degrees and types of control. For example, discrete and continuous real-time control is provided to control the output frequency of the self-oscillating oscillator according to the variation. Furthermore, the control is typically provided as an open loop, without the need for a feedback connection and without the need for the oscillator to continuously lock to another reference signal.

Additionally, exemplary embodiments of the present invention provide a clock generator and/or timing and frequency reference having multiple modes of operation, including, for example, an energy conservation mode, a clock mode, a reference mode, and a pulsed mode. Additionally, various embodiments provide multiple output signals at different frequencies and provide low latency and glitch-free transitions between these different signals.

Notably, different embodiments of the present invention generate large and relatively high frequencies, such as the hundreds of MHz and GHz range, which are then divided into multiple lower frequencies. Each such division by N (rational number, integer ratio) results in effective noise reduction, phase noise reduction N and phase noise power reduction ^N2 . Accordingly, various exemplary embodiments of the present invention result in much lower relative period jitter than other oscillators that generate an output directly or through frequency multiplication.

Different device embodiments include resonators, amplifiers, and frequency controllers, which may include different components or modules such as temperature compensators, process variation compensators, voltage isolators and/or voltage compensators, lifetime (time) variation Compensators, frequency dividers, and frequency selectors. The resonator provides a first signal having a resonant frequency. The temperature compensator adjusts the resonant frequency in response to temperature, and the process variation compensator adjusts the resonant frequency in response to manufacturing process variations. Furthermore, various embodiments may further include a frequency divider for dividing a first signal having a resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency a frequency; and a frequency selector providing an output signal from the plurality of second signals. The frequency selector may also include a glitch suppressor. The output signal can be provided in any of a variety of forms, such as differential or single-ended, and square wave or sinusoidal.

Exemplary embodiments of the present invention provide an apparatus for frequency control of an integrated, self-excited harmonic oscillator, comprising a resonator adapted to provide a first signal having a resonant frequency; adapted to respond to at least one of a plurality of parameters a sensor providing a second signal of a parameter such as a control voltage; and a frequency controller connected to the sensor and connectable to the resonator, the frequency controller being adapted to modify a reactive element connected to the resonator in response to the second signal to modify the resonant frequency. A number of parameters are variable and include at least one of the following parameters: temperature, manufacturing process, voltage, frequency, and age (ie, elapsed time).

In an exemplary embodiment, the frequency controller is further adapted to modify the effective reactive or impedance elements connected to the resonator in response to the second signal, such as modifying the total capacitance of the resonator, connecting fixed or variable capacitors in response to the second signal to or from the resonator, modifying the effective reactance of the resonator by changing or switching the varactor to a selected control voltage, or equivalently modifying the inductance or resistance of the resonator in response to the second signal, Such as by connecting or disconnecting a fixed or variable inductor or resistor to or from a resonator. In other embodiments, differentially weighted or sized reactances such as variable capacitors (varactors) can be switched between it and the resonator, between it and a number of different selectable control voltages, or both . For example, in selected embodiments, the reactance of one or more variable capacitors connected to the resonator may be varied by switching the one or more variable capacitors to a selected one of a plurality of control voltages, thereby resulting in different or differentially weighted effective reactances connected to the resonator.

For example, multiple fixed capacitors (with different, binary-weighted or differentially-weighted capacities) can be connected to the resonator to provide discrete levels of frequency control, and varactors connected to the resonator can be provided with one of several control voltages. A selected control voltage, which varies in response to temperature, can be used to keep frequency constant as said temperature fluctuates, and which provides a continuous level of frequency control. Furthermore, any of the control voltages either changes in response to a selected parameter, such as temperature, or is constant relative to the parameter. The different weights of the different reactances used can be embodied in various forms, such as binary weighting, linear weighting, or weighting using any other desired scheme, all of which are considered fully equivalent and within the scope of the present invention.

It should be noted that the terms "fixed" and "variable" are used in a manner known in the art, with "fixed" being understood to mean that the configuration generally does not change with respect to selected parameters, and "variable" meaning that the configuration generally changes with the selected parameters. Variety. For example, a fixed capacitor generally means that its capacitance does not vary with applied voltage, whereas a variable capacitor (variactor) will have a capacitance that varies with applied voltage. However, both can have and generally will have a capacitance that varies with the manufacturing process. Furthermore, for example, a fixed capacitor may be formed as a varactor connected to a constant voltage. Similarly, components may be connected to each other directly or indirectly, in other words, operatively or via signal transmission. For example, one component may be connected to a second component via a third component, such as through a switching arrangement, a divider, a multiplier, or the like. Those skilled in the art will recognize these various situations and environments, as illustrated and described below, and the meanings when such terms are used.

In an exemplary embodiment, the frequency controller may further include: a coefficient register adapted to hold a first plurality of coefficients; and a first array having a plurality of switchable capacitive modules connected to the coefficient register and connectable to the resonator , each switchable capacitive module has a fixed capacitance and a variable capacitance, each switchable capacitive module is responsive to a corresponding coefficient of the first plurality of coefficients to switch between the fixed capacitance and the variable capacitance and each switchable The variable capacitor converts to the control voltage. Multiple switchable capacitive modules can be binary weighted. The frequency controller may also include a second array having a plurality of switchable resistive blocks connected to the coefficient registers and also having a second array of capacitive blocks, the capacitive block and the plurality of switchable resistive blocks also connected to a node to provide a control voltage, each A switchable resistance module switches the switchable resistance module to the control voltage node in response to a corresponding coefficient of the second plurality of coefficients stored in the coefficient register. In selected embodiments, the sensor further includes a temperature-responsive current source, wherein the current source is connected to the second array through a current mirror to generate a control voltage across at least one switchable resistance module of the plurality of switchable resistance modules. Also, in selected embodiments, the current source has at least one of the following: inverse to absolute temperature (CTAT) configuration, proportional to absolute temperature (PTAT) configuration, proportional to square of absolute temperature (PTAT ² ) configuration, or combination of structures. Additionally, each switchable resistance module of the plurality of switchable resistance modules has a different temperature response to the selected current.

In other exemplary embodiments, the sensor is a parameter (temperature, process, voltage, age, etc.) sensor and changes the second signal in response to a change in a selected parameter, for example, the sensor may be a temperature or voltage sensor and responds to temperature or The voltage change changes the second signal. Selected embodiments may also include an analog-to-digital converter coupled to the sensor to provide a digital output signal in response to the second signal, and control logic to convert the digital output signal into the first plurality of coefficients.

In other exemplary embodiments, the frequency controller further includes a process variation compensator connectable to the resonator and adapted to modify the resonant frequency in response to a manufacturing process parameter of the plurality of parameters. The process variation compensator may also include a coefficient register adapted to hold a plurality of coefficients; and an array having a plurality of binary weighted, switchable capacitive modules connected to the coefficient register and the resonator, each switchable capacitive module having a first A fixed capacitance and a second fixed capacitance, each switchable capacitive module is responsive to a corresponding coefficient of the plurality of coefficients to switch between the first fixed capacitance and the second fixed capacitance. In other exemplary embodiments, the process variation compensator may further include a coefficient register adapted to hold a plurality of coefficients; and an array having a plurality of switchable variable capacitive modules connected to the coefficient register and the resonator, each The switchable variable capacitive module is responsive to corresponding coefficients of the plurality of coefficients to switch between the first voltage and the second voltage, such as to a selected control voltage.

In other exemplary embodiments, the frequency controller further includes a coefficient register adapted to hold a first plurality of coefficients; and a first array having a plurality of switchable, capacitive modules connected to the coefficient register and the resonator, each The switchable capacitive modules have variable capacitances, each switchable capacitive module responsive to a corresponding coefficient of the first plurality of coefficients to convert the variable capacitance to a selected control voltage of a plurality of control voltages. In other exemplary embodiments, the process variation compensator may further include a coefficient register adapted to hold at least one coefficient; and at least one switchable variable capacitive module connected to the coefficient register and the resonator, responsive to the at least one coefficient transition to the selected control voltage. The sensor may include a current source responsive to temperature, and the frequency controller may also include a second array having a plurality of resistive modules connected to the current source through current mirrors, the plurality of resistive modules adapted to the other plurality of control voltages, and wherein a plurality of Each of the resistive modules has a different response to temperature and is adapted to provide a corresponding one of the plurality of control voltages in response to the current of the current source.

In other exemplary embodiments, the means for frequency control of a resonator may also be adapted to hold a coefficient register for a first plurality of coefficients; and a device having a plurality of switchable reactance or impedance modules connected to the coefficient register and the resonator A first array, each switchable reactance module responds to a corresponding coefficient of the first plurality of coefficients to switch a corresponding reactance to modify the resonant frequency. The corresponding reactance or impedance may be a fixed or variable inductance, a fixed or variable capacitance, a fixed or variable resistance, or any combination thereof. The corresponding reactance can be switched to the resonator, or when connected to the resonator, can be switched to a control voltage, supply voltage or ground potential, the control voltage being determined by the current source in response to temperature. For example, a corresponding reactance is variable and connected to the resonator and converted to a selected one of the plurality of control voltages. In selected embodiments, the first plurality of coefficients are calculated or determined by the sensor in response to at least one of a plurality of variable parameters, such as temperature, manufacturing process, voltage, frequency, and age.

In other exemplary embodiments, an apparatus for frequency control of an integrated, self-excited harmonic oscillator includes: a plurality of resistive modules adapted to generate a plurality of control voltages; a plurality of controlled reactances connected to the harmonic oscillator module; and a plurality of switches connected to a plurality of resistance modules and a plurality of controlled reactance modules, the plurality of switches connecting a first control voltage of a plurality of control voltages to a first of the plurality of controlled reactance modules in response to a control signal Controlled Reactance block to modify the resonant frequency of the Harmonic Oscillator.

As mentioned above, the apparatus may further comprise a current source connected to the plurality of resistive modules, the current source being adapted to provide a parameter dependent current to at least one of the plurality of resistive modules to generate one of the plurality of control voltages. At least one control voltage of , which depends on the parameter. In other embodiments, the current source is adapted to provide a substantially parameter-independent current to at least one of the plurality of resistive modules to generate at least one of the plurality of control voltages, which is substantially independent of the parameter. According to an example embodiment, each switchable resistance module of the plurality of switchable resistance modules may have a different temperature response to a selected current.

Therefore, when the parameter is temperature, at least one of the plurality of control voltages is temperature dependent, and at least one of the plurality of control voltages is substantially independent of temperature.

The exemplary apparatus may also include a coefficient register coupled to the plurality of switches and adapted to hold a first plurality of coefficients, wherein the control signal is provided by at least one coefficient of the first plurality of coefficients. The plurality of controlled reactance modules may also include a plurality of differentially (e.g., binary) weighted fixed and variable capacitors, and wherein the plurality of switches connect the fixed capacitors to the harmonic oscillator and the plurality of switches in response to the first plurality of coefficients. A first of the control voltages is connected to a variable capacitor connected to the harmonic oscillator. The plurality of resistive modules may further include a plurality of switchable resistive modules connected to the coefficient register and a capacitive module, the capacitive module and the plurality of switchable resistive modules also connected to a node to provide a first control voltage, each switchable resistive The module switches the switchable resistance module to the control voltage node in response to a corresponding coefficient of the second plurality of coefficients held in the coefficient register.

In an exemplary embodiment, an analog-to-digital converter may be connected to a plurality of switchable resistance modules to provide a digital output signal in response to a first control voltage, for example to convert a temperature-dependent current (as a sensor) into digital format ; and a control logic block that converts the digital output signal into a first plurality of coefficients or control signals.

Also, in an exemplary embodiment, the plurality of controlled reactive blocks further includes: a plurality of switchable capacitive blocks connected to the coefficient register and the harmonic oscillator, each switchable capacitive block having a variable capacitance, each A switchable capacitive module converts the variable capacitance to a selected one of the plurality of control voltages in response to a corresponding coefficient of the first plurality of coefficients. According to an embodiment, a current source responsive to a parameter of a plurality of variable parameters is connected to a plurality of resistive modules through a current mirror; wherein each resistive module of the plurality of resistive modules has a different response to the parameter and is adapted to respond to The current of the current source provides a corresponding control voltage of the plurality of control voltages. According to an embodiment, at least one of the plurality of control voltages is substantially parameter dependent, and at least one of the plurality of control voltages is substantially parameter independent.

Also, in an exemplary embodiment, the plurality of controlled reactive blocks further includes: a plurality of differentially weighted switchable capacitive blocks connected to the coefficient register and the harmonic oscillator, each switchable capacitive block having a first fixed Each switchable capacitive module switches between a first fixed capacitance and a second fixed capacitance in response to a corresponding coefficient of the plurality of coefficients. In other embodiments, the plurality of controlled reactive modules further includes: a plurality of switchable variable capacitive modules connected to the coefficient register and the harmonic oscillator, each switchable variable capacitive module responsive to The corresponding coefficient of the plurality of control voltages is converted between the first voltage and the second voltage. In other embodiments, the plurality of controlled reactive modules further includes: a plurality of switchable variable capacitive modules connected to the coefficient register and the harmonic oscillator, each variable capacitive module responsive to a corresponding one of the plurality of coefficients The coefficient is converted to a selected control voltage of the plurality of control voltages, the plurality of control voltages includes a plurality of voltages of different magnitudes, and wherein the selected control voltage varies substantially with temperature.

Also, in an exemplary embodiment, the apparatus may further include: a plurality of switchable resistors switching corresponding resistances to the harmonic oscillator in response to the control signal, thereby modifying the resonance frequency. The apparatus may include a voltage divider connected to a plurality of controlled reactive modules and adapted to provide a selected control voltage in response to a voltage change. Additionally, a lifetime variation compensator may be connected to the resonator and adapted to compare a current value of a selected one of the plurality of parameters with an initial value of the selected parameter and respond to the difference between the current value and the initial value of the selected parameter. The difference between modifies the resonant frequency.

Numerous other exemplary embodiments are described in detail below and include additional regulators and compensators for voltage variations and lifetime (IC lifetime) variations.

The present invention may further comprise a mode selector coupled to the frequency selector, wherein the mode selector is adapted to provide a plurality of operating modes selectable from the group comprising: clock mode, timing and frequency reference mode, energy conservation mode , And by the action of the pulse (or pulse) mode.

For the reference mode, the present invention may also include a synchronization circuit connected to the mode selector; and a controlled oscillator connected to the synchronization circuit and adapted to provide a third signal; wherein in the timing and reference modes, the mode selector is also adapted to Connect the output signal to a synchronization circuit to control the timing and frequency of the third signal. The synchronization circuit may be a delay locked loop, a phase locked loop, or an injection locked circuit.

These and additional embodiments are discussed in more detail below. Numerous other advantages and characteristics of the invention will be apparent from the following detailed description of the invention and embodiments thereof, the claims and the accompanying drawings.

Description of drawings

Objects, features and advantages of the present invention will be more readily appreciated by reference to the following description taken in conjunction with the accompanying drawings and examples which form a part hereof, wherein the same reference numerals are used to identify the same or similar components in different drawings ,in:

Figure 1 is a block diagram of an exemplary system embodiment according to the present invention.

Fig. 2 is a block diagram of a first exemplary apparatus embodiment according to the present invention.

Fig. 3 is a block diagram of a second exemplary apparatus embodiment according to the present invention.

Figure 4 is a high level schematic and block diagram illustrating an exemplary frequency controller, oscillator and frequency calibration embodiment in accordance with the present invention.

5A is an exemplary graph of oscillator voltage waveform (frequency) distortion due to current harmonic components injected into the oscillator with a particular filter response.

5B is an exemplary graph of the oscillator voltage waveform (frequency) shown in FIG. 5A as a function of temperature.

5C is an exemplary graph of oscillator frequency as a function of transconductance of a sustaining amplifier.

6 is a circuit diagram of a first exemplary negative transconductance amplifier, temperature responsive current generator (I(T)), and LC oscillator embodiment in accordance with the present invention.

7A is a circuit diagram of an exemplary temperature-responsive CTAT current generator in accordance with the present invention.

7B is a circuit diagram of an exemplary temperature-responsive PTAT current generator in accordance with the present invention.

7C is a circuit diagram of an exemplary temperature-responsive PTAT ² current generator in accordance with the present invention.

7D is a circuit diagram of an exemplary alternative and scalable temperature-responsive current generator with selected CTAT, PTAT, and PTAT ² configurations in accordance with the present invention.

8 is a block circuit diagram of a second exemplary negative transconductance amplifier, temperature responsive current generator (I(T)), and LC oscillator embodiment in accordance with the present invention.

9 is a circuit diagram of an exemplary first controlled (or controllable) capacitance module used in a frequency-temperature compensation module according to the present invention.

10 is a circuit diagram of an exemplary first voltage control module used in a frequency-temperature compensation module according to the present invention.

11 is a circuit diagram of an exemplary first process variation compensation module according to the present invention.

12 is a circuit diagram of an exemplary second process variation compensation module according to the present invention.

13 is a block diagram of an exemplary frequency calibration module according to the present invention.

14 is a block diagram of an exemplary frequency divider, square wave generator, asynchronous frequency selector and glitch suppression module according to the present invention.

15 is a diagram of an exemplary low-latency frequency conversion in accordance with the present invention.

16 is a block diagram of an exemplary frequency divider according to the present invention.

17 is a block diagram of an exemplary power mode selection module according to the present invention.

18 is a block diagram of an exemplary synchronization module for a second oscillator in accordance with the present invention.

19 is a flowchart of an exemplary method in accordance with the present invention.

20 is a block and circuit diagram of an exemplary controlled impedance module used in a compensation module in accordance with the present invention.

FIG. 21 is a block diagram of a first exemplary frequency controller and apparatus according to the present invention.

22 is a circuit diagram of an exemplary second controlled capacitance module used in a frequency-temperature compensation module according to the present invention.

23 is a circuit diagram of an exemplary second voltage control module used in a frequency-temperature compensation module according to the present invention.

24 is a graph of exemplary frequency control in response to temperature changes in accordance with the present invention.

25 is a block diagram of a second exemplary frequency controller and apparatus according to the present invention.

26 is a circuit diagram of an exemplary third controlled capacitance module and an exemplary third voltage control module used in a parameter compensation module according to the present invention.

27 is a circuit and block diagram of an exemplary voltage variation compensation module according to the present invention.

28 is a circuit diagram of an exemplary fourth voltage control module used in a frequency and process compensation module in accordance with the present invention.

29 is a circuit diagram of an exemplary resistance control module according to the present invention.

FIG. 30 is a block diagram of an exemplary lifetime variation compensator in accordance with the present invention.

31 is a circuit diagram of a third exemplary LC oscillator that may be used in accordance with the present invention.

32 is a circuit diagram of a fourth exemplary LC oscillator that may be used in accordance with the present invention.

33 is a circuit diagram of a fifth exemplary LC oscillator that may be used in accordance with the present invention.

34 is a circuit diagram of a sixth exemplary LC oscillator that may be used in accordance with the present invention.

35 is a circuit diagram of a seventh exemplary LC oscillator that may be used in accordance with the present invention.

36 is a circuit diagram of an eighth exemplary LC oscillator that may be used in accordance with the present invention.

37 is a circuit diagram of a ninth exemplary LC oscillator that may be used in accordance with the present invention.

Figure 38 is a block diagram of an embodiment of an active inductor in accordance with the present invention.

FIG. 39 is a block diagram of a second exemplary system embodiment in accordance with the present invention.

40 is a block diagram of a third exemplary system embodiment in accordance with the present invention.

FIG. 41 is a block diagram of a third exemplary frequency divider embodiment in accordance with the present invention.

FIG. 42 is a block diagram of a fourth exemplary frequency divider embodiment in accordance with the present invention.

FIG. 43 is a block diagram of a fourth exemplary system embodiment in accordance with the present invention.

44 is a block diagram of a fifth exemplary system embodiment in accordance with the present invention.

Figure 45 is a block diagram of an exemplary first discrete device embodiment in accordance with the present invention.

Figure 46 is a block diagram of an exemplary second discrete device embodiment in accordance with the present invention.

Figure 47 is a block diagram of an exemplary third discrete device embodiment in accordance with the present invention.

Figure 48 is a block diagram of an exemplary fourth discrete device embodiment in accordance with the present invention.

Detailed ways

While the invention is susceptible to embodiments in many different forms, specific embodiments thereof are shown in the drawings and described in detail herein, it being understood that the description is considered as illustrative of the principles of the invention and not in limitation thereof for the specific example described here.

As noted above, various embodiments of the present invention provide numerous advantages, including the ability to integrate highly accurate (over PVT and lifetime), low jitter, self-oscillating and self-referencing clock generators and/or timing and frequency references with other circuits , as shown in Figure 1. FIG. 1 is a block diagram of an exemplary system embodiment 150 in accordance with the present invention. As shown in FIG. 1, system 150 is a single integrated circuit, clock generator and/or timing/frequency reference 100 of the present invention and other or second circuit 180, together with interface (I/F) (or input/output (I/F) /O) circuit) 120 are monolithically integrated together. Interface 120 will typically provide power to clock generator 100, such as from a power supply (not shown), ground, and other lines or buses, such as for calibration and frequency selection. As shown, one or more output clock signals are provided on bus 125, which are a plurality of frequencies, such as a first frequency (f ₀ ), a second frequency (f ₁ ), and so on, up to the (n+ 1) Frequency (f _n ). Additionally, an energy conservation mode (or low power mode (LP)) is provided (also on bus 125). The second circuit 180 (or I/F 120) can also provide input to the clock generator 100, such as through select signals (S ₀ , S ₁ , . . . , S _n ) and one or more calibration signals (C ₀ , C ₁ , ..., C _n ). Alternatively, selection signals (S ₀ , S ₁ , ..., S _n ) and one or more calibration signals (C ₀ , C ₁ , ..., C _n ) can be provided directly to clock generator 100 via interface 120, such as on a bus 135, along with power (on line 140) and ground (on line 145).

In addition to the low power mode, the clock generator and/or timing/frequency reference 100 has additional modes which are discussed in detail below. For example, in a clock mode, the device 100 will provide one or more clock signals to the second circuit 180 as output signals. The second circuit 180 may be any type or kind of circuit, such as a microprocessor, digital signal processor (DSP), radio frequency circuit, or any other circuit that may utilize one or more output clock signals. Also, for example, in a timing or frequency reference mode, the output signal from the apparatus 100 may be a reference signal, such as a reference signal for the synchronization of the second oscillator. Accordingly, the terms clock generator and/or timing/frequency reference will be used interchangeably herein, with the understanding that a clock generator will typically also provide a square wave signal, which may or may not be provided with a timing/frequency reference, which is essentially A sinusoidal signal can be used instead. In addition, as detailed below, various embodiments of the present invention also provide a pulsed mode in which output signals from the clock generator and/or timing/frequency reference 100 are provided in bursts or at intervals, for example to increase instruction processing efficiency and Reduce power consumption.

It should be noted that various signals, voltages, current sources that are parameter dependent, etc. are referred to as "substantially" sinusoidal or square wave signals, substantially constant control voltages, or substantially parameter dependent voltages or currents. This will accommodate different fluctuations, noise sources and other distortions that can cause the signal, voltage or current to be distinguished in practice from the more ideal descriptions found in textbooks. For example, as detailed below, an exemplary "substantially" square wave signal is shown in FIGS. 15A and 15B, which exhibit various distortions, such as undershoot, overshoot, and other variations, and are still Treated as a very high quality square wave.

Several important features of the present invention are in system 150 . First, a highly accurate, low jitter, self-oscillating and self-referencing clock generator 100 is monolithically integrated with other (second) circuitry 180 to form a single integrated circuit (system 150). This is a clear difference from the prior art, where a reference oscillator is used to provide a clock signal such as a crystal reference oscillator, which cannot be integrated with other circuits and is off-chip, as a second and separate device, which Must be connected to any additional circuitry through the board. For example, according to the present invention, system 150 including clock generator 100 may use conventional CMOS (Complementary Metal Oxide Semiconductor), BJT (Bipolar Junction Transistor), BiCMOS (Bipolar and CMOS), or the Other fabrication techniques are fabricated with other, second circuits.

Second, there is no need for a separate reference oscillator. Rather, in accordance with the present invention, the clock generator 100 is self-referencing and self-exciting such that it is not referenced or locked to another signal, such as in a phase-locked loop (PLL), delay-locked loop (DLL), or synchronized via injection locking to Reference signal, which is very common in the prior art. Rather, exemplary embodiments may be used as the reference oscillator to generate a frequency reference signal, after which, for example, one or more phase-locked or delay-locked loops lock to the frequency reference signal.

Third, the clock generator 100 provides multiple output frequencies and energy conservation modes so that frequencies can be switched in a low-latency and glitch-free manner. For example, the second circuit 180 may change to an energy conservation mode, such as a battery or lower frequency mode, and request (via a select signal) a lower clock frequency to minimize power consumption, or request a low power clock signal to enter a sleep mode. As detailed below, the latency of such a frequency conversion is essentially negligible, since the latency due to glitch prevention is low (proportional to the number of glitch prevention stages), and only a few clock cycles are used, rather than from the PLL/ The thousands of clock cycles it takes for the DLL to change the output frequency.

Alternative embodiments also generate multiple frequency reference signals, whether sinusoidal or square wave signals, such as for use as one or more clock signals or reference frequency sources. In an exemplary embodiment, the clock/frequency reference of the present invention is connected to one or more phase locked loops (PLL) or delay locked loops (DLL) to provide a corresponding plurality of output reference signals at selected frequencies. These exemplary embodiments are generally programmable through control signals or stored coefficients, such as adjusting the frequency division ratio of a PLL or DLL for a corresponding frequency selection.

Furthermore, given the very high available output frequencies of the clock generator and/or timing/frequency reference 100 described below, new modes of operation are available. For example, the clock start-up time may be practically or substantially negligible, such that the clock generator and/or timing/frequency reference 100 will be repeatedly started and stopped, eg completely off or intermittently on for energy conservation. For example, instead of running continuously with a clock, the clock generator and/or timing/frequency reference 100 may run in relatively short, discrete intervals or bursts (i.e., pulsed), periodically or aperiodically, for use in a second circuit 180 such as processor instruction processing. As detailed below, the pulsed operation saves power due to the fast start-up time because more instructions are processed per milliwatt (mW) of power consumed (million instructions per second or MIPS). Furthermore, the pulsed mode may be used to periodically synchronize a second clock or oscillator, among other uses. Accordingly, clock generator and/or timing/frequency reference 100 (and other embodiments described below) have multiple modes of operation, including clock mode, timing and/or frequency reference mode, energy conservation mode, and pulsed mode.

Fourth, as detailed below, the clock generator and/or timing/frequency reference 100 includes features that maintain highly accurate frequency generation over manufacturing process, voltage, temperature (PVT), and lifetime variations. These features include frequency tuning and selection, and compensation for frequency variations due to temperature and/or voltage fluctuations, manufacturing process variations, and IC aging.

Fifth, the clock generator and/or timing/frequency reference 100 generates very large and relatively high frequencies, such as the hundreds of MHz and GHz range, which are then divided into multiple lower frequencies. Each of these divisions by N (rational numbers, integer ratios) results in effective noise reduction, phase noise reduction N and phase noise power reduction ^N2 . Thus, the clock generator of the present invention results in much lower relative period jitter than other oscillators that generate their output directly or by frequency multiplication.

These features are illustrated in detail in Figure 2, which is a block diagram of a first exemplary apparatus embodiment 200, including a frequency controller 215 according to the present invention. As shown in FIG. 2, device 200 is a clock generator and/or timing/frequency reference providing one or more output signals, such as a clock or reference signal having any of a plurality of frequencies selected using frequency selector 205 . The device (or clock generator) 200 includes an oscillator 210 (with a resonant element), a frequency controller 215, a frequency divider 220, a mode selector 225, and the frequency selector 205 mentioned above. According to the invention, oscillator 210 generates a signal with a relatively high frequency f ₀ . Frequency controller 215 is used to frequency select or tune oscillator 210 due to PVT or lifetime variations mentioned above such that oscillation frequency _f0 can be selected from a number of possible oscillation frequencies, i.e. frequency controller 215 provides Periodic changes still maintain an accurate frequency output signal.

For example, given these PVT variations, the output frequency of an oscillator such as oscillator 210 may vary by plus or minus 5%. For some applications, such as those using ring oscillators, such frequency variability may be acceptable. However, according to the present invention, a higher accuracy clock generator 200 is required, especially for more sensitive or complex applications, such as providing integrated microprocessors, microcontrollers, digital signal processors, communication controllers, etc. clock signal. Accordingly, the frequency controller 215 is used to adjust to these PVT variations such that the output frequency of the oscillator is the selected or desired frequency f ₀ , which varies by a small number of orders, such as ±0.25% or less, and has Fairly low jitter.

Various exemplary embodiments of the frequency controller 215 in accordance with the present invention are described in detail below. For example, referring to FIG. 21 , which is a block diagram of an exemplary frequency controller 1415 and apparatus 1400 according to the present invention, an oscillator (resonator 310 and sustain amplifier 305 ) provides a first output signal having a resonant frequency _f0 . An example frequency controller 1415 is coupled to the oscillator and modifies the resonant frequency f ₀ in response to a second signal, such as a second signal provided by one or more sensors 1440 . An exemplary frequency controller 1415 includes one or more of the following components: a transconductance regulator 1420, a variable parameter regulator (or controller) 1425 (such as one or more of the controlled capacitance or controlled reactance modules described below ), a process (or other parameter) regulator (or compensator) 1430, a voltage compensator 1455, a coefficient register 1435, and possibly a lifetime variation compensator 1460. According to selected embodiments, the frequency controller 1415 may also include one or more sensors 1440 , an analog-to-digital (A/D) converter (ADC) 1445 , and a control logic block 1450 . For example, in accordance with the present invention, the temperature dependent current source I(T) (or more generally, yI(x)) generator 415 shown in FIG. The corresponding output current as a function of temperature. Such temperature dependent output currents can be converted to digital signals by A/D converter (ADC) 1445 and used to provide the respective regulators or compensators 1420, 1425, 1430, 1455 and 1460 of frequency controller 1415 used by the respective coefficient (stored in register 1435) to control the resonant (or output) frequency f ₀ according to different parameters such as variable operating temperature or variable manufacturing process. In other illustrated embodiments, the temperature dependent output current (as a second signal, without intervening A/D conversion) is provided directly to different regulators, such as transconductance regulator 1420 and variable parameter regulator device (or controller) 1425. These regulators in turn modify the resonance, for example by modifying the current flowing through the resonator 310 and sustaining the amplifier 305 or modifying the effective reactance or impedance (such as capacitance, inductance or resistance) connected to the resonator 310 and effectively forming part of the resonator 310 frequency f ₀ . For example, the effective reactance (or impedance) can be modified by connecting or disconnecting fixed or variable capacitors to or from the resonator 310, or by modifying the magnitude of one or more reactances connected to the resonator, such as By modifying the control voltage or other continuous control parameters.

In the various embodiments described below, both the transconductance regulator 1420 and the variable parameter regulator (or controller) 1425 are generally implemented to use a temperature parameter such that a substantially stable resonant frequency f ₀ is provided as a function of operating temperature. Those skilled in the art will appreciate that these regulators may be implemented to provide a substantially stable resonant frequency _f0 as a function of or in response to other variable parameters, such as due to the manufacturing process. changes, voltage changes, aging, and other frequency changes.

Referring now again to Figure 2, to improve performance and reduce jitter (noise) and other disturbances, instead of generating a low frequency output and multiplying it to a higher frequency as is commonly done with PLLs and DLLs, the present invention generates a considerably higher frequency The output f ₀ is then divided into one or more lower frequencies (f _{1 .} . . f _n ) using frequency divider 220 . Thereafter, a clock signal having one or more of the plurality of frequencies from frequency divider 220 is selected using frequency selector 205 . As mentioned above, the frequency selection is glitch-free and has low latency, thereby providing a relatively fast and glitch-free frequency conversion. Additionally, the use of the mode selector 225 provides a variety of operating modes.

Figure 3 is a more detailed block diagram of a second exemplary apparatus embodiment, namely a clock generator and/or timing/frequency reference 300, in accordance with the present invention. 3, clock generator and/or timing/frequency reference 300 includes resonator 310 and sustain amplifier 305 (forming oscillator 395), temperature compensator (or regulator) 315, process variation compensator (or regulator) 320 , a frequency calibration module 325, a voltage variation compensator (or regulator) 380, a lifetime (time) variation compensator (or regulator) 365, one or more coefficient registers 340, and according to selected embodiments, may also include Sensor 385, Analog to Digital Converter (ADC) 390, Frequency Divider and Square Wave Generator 330, Voltage Isolator 355, Resonant Frequency Selector 360, Output Frequency Selector 335, Mode Selector 345, and Low Latency Startup Module 399. Hold amplifier 305, temperature compensator 315, process variation compensator 320, voltage isolator 355, voltage variation compensator 380, lifetime variation compensator 365, resonant frequency selector 360, and frequency calibration module 325 are typically included in the frequency controller Inside, such as the frequency controller 349 (or 215 or 1415). Alternatively, sustain amplifier 305 and resonator 310 may be viewed as comprising oscillator 395, with one or more distinct controller elements (e.g., temperature compensator 315, process variation compensator 320, voltage isolator 355, voltage variation compensator 380, lifetime variation compensator 365, resonant frequency selector 360, sensor 385, ADC 390, and frequency calibration module 325). Note also that the square wave generator (of 330) is not required in timing or frequency reference embodiments.

Resonator 310 may be any type of resonator that conserves energy, such as an inductor (L) and capacitor (C) connected to form an LC tank having all of the various LC tank configurations optional configuration, or is electrically or electromechanically equivalent or commonly referred to in the art as an inductor connected to a capacitor. Such an LC resonator is illustrated as resonator 405 in FIG. 4 . Resonators other than LC resonators are considered equivalent and within the scope of the present invention; for example, resonator 310 may be a ceramic resonator, a mechanical resonator (such as XTAL), a microelectromechanical (MEMS) resonator, or thin-film bulk acoustic resonators. In other examples, different resonators may be represented by electrical or electromechanical analogues as LC resonators and are within the scope of the invention. In an exemplary embodiment, an LC tank has been used as a resonator to provide high Q for a fully integrated solution.

Sustain amplifier 305 provides start-up and sustain amplification for resonator 310 . A temperature compensator 315 provides frequency control to the resonator 310 to adjust the frequency of oscillation based on changes due to temperature. In selected embodiments, temperature compensator 315 may include control of current and frequency, depending on the degree of control desired or required, as described below for selected embodiments. For example, the temperature compensator 315 may include one or both of the transconductance regulator 1420 of FIG. 21 and the parameter regulator 1425, both of which are responsive to temperature fluctuations. Similarly, process variation compensator 320 provides frequency control to resonator 310 to adjust the oscillation frequency based on process variations inherent in semiconductor manufacturing technology, including process variations within a given foundry (e.g., batch or run variations, Variation within a given wafer, and die-to-die within the same wafer) and process variation between different foundries and foundry processes (such as 130nm and 90nm processes). The voltage variation compensator 380 can be used to maintain a stable output frequency with supply voltage variations and other voltage variations. A lifetime variation compensator 365 may be used to maintain a stable output frequency over the lifetime of the IC with corresponding variations in circuit elements over time. The frequency calibration module 325 is used to adjust and select the desired output frequency f ₀ from multiple oscillation frequencies present in the resonator 310 , ie select the output frequency f ₀ from multiple available or possible frequencies. In selected embodiments, coefficient registers 340 are used to hold coefficient values used in various exemplary compensator and calibration embodiments, which are described in more detail below.

As noted above, in selected embodiments, the frequency controller 349 may also include one or more sensors 385 and an analog-to-digital converter (ADC) 380 . In addition, many other compensators and regulators for frequency controllers include components that act as sensors, such as temperature-dependent current sources and other voltage change detectors. In addition to generating a number of saved coefficients for providing control over the various conversion elements, i.e. the Controlled Reactance Module (described below) switching to the resonator 310 (as a discontinuous form of control) and changing the connected or switched reactance to The amount of effective reactance of the resonator 310 (continuous form of control), various sensors, compensators and regulators can also be used to provide other forms of continuous control over the resonant frequency of the resonator 310. As described below, various successive outputs from sensors, current generators, control voltages, etc. are used as control signals within the scope of the present invention. For example, different control voltages, which vary with or remain constant with respect to a selected parameter such as temperature, are used as control signals for modifying the respective magnitudes of controlled capacitance modules implemented using varactors.

In addition to temperature and process compensation, voltage isolator 355 provides isolation from voltage variations, such as from a power supply, and may be implemented alone or as part of other components, such as temperature compensator 315 . In addition to frequency adjustments due to these PVT and lifetime variations, the resonant frequency can also be individually selected by the resonant frequency selector 360 to obtain the selected frequency from the available frequency range.

For clock signal generation, the clock generator 300 uses a frequency divider (in block 330) to convert the output oscillating frequency f ₀ to a number of lower frequencies (f _{1 .} . . f _n ) and uses a square wave generator (also in block 330 330) converts the substantially sinusoidal oscillating signal into a substantially square wave signal for clock applications. Afterwards, the frequency selector 335 selects one or more of the available output signals with multiple frequencies, and the mode selector 345 can also provide operation mode selection, such as providing low power mode, pulsed mode, reference mode, etc. Using these components, clock generator 300 provides multiple highly accurate (with PVT), low jitter, and stable output frequencies f ₀ , f _{1 .} . . f _n with minimal negligible frequency shift due to variations in the PVT , thereby providing sufficient accuracy and stability for sensitive or complex applications as described above.

Figure 4 is a high level schematic and block diagram of an exemplary frequency controller, oscillator and frequency calibration embodiment in accordance with the present invention. As shown in FIG. 4, the resonator is embodied as a resonant LC tank 405, and the frequency controller is embodied as several elements, a negative transconductance amplifier 410 (for implementing a sustain amplifier), temperature response (or temperature-dependent given) current generator I(T) (or more generally, yI(x), responsive to any of said parameters x) 415, temperature responsive (or temperature dependent) frequency (f ₀ (T)) compensation module 420 . A process variation compensation module 425, and may further include a frequency calibration module 430. Different temperature responsive or temperature dependent modules 415 and 420 are sensitive to or responsive to temperature fluctuations and provide corresponding adjustments so that the resonant frequency remains stable and accurate over PCT and lifetime.

The resonant LC tank 405 with sustain amplifiers may equivalently be described as a harmonic oscillator or harmonic core, and all such variations are within the scope of the invention. It should be noted that while the resonant LC tank 405 is an inductor 435 in parallel with a capacitor 440, other circuit topologies are well known and equivalent to the described configuration, such as an inductor in series with a capacitor. Another such equivalent layout is shown in FIG. 8 . Furthermore, as noted above, other types of resonators may also be used and considered equivalent to the exemplary resonant LC tank described herein. Furthermore, as detailed below, additional capacitance and/or inductance, whether fixed or variable (and more generally referred to as impedance or reactance (or reactive elements)), are distributed among the different modules and effectively constitute a resonant LC part of the tank circuit 405 and is used as part of the frequency controller of the present invention. Also, corresponding resistors (resistive elements of different impedance) _RL 445 and _RC 450 are shown separately, but should be understood as being of the nature of inductor 435 and capacitor 440 respectively, which occur as part of fabrication rather than corresponding Additional or separate components from inductor 435 and capacitor 440 . Rather, the additional or intrinsic (parasitic) resistance can also be included as part of the compensation for PVT variation, as described below with reference to FIG. 29 .

The inductor _{435 and capacitor 440 of the resonant LC tank or oscillator 405 are sized at or about to provide a range of oscillation frequencies at or around the selected oscillation frequency f 0 .} Furthermore, inductor 435 and capacitor 440 are sized to have or meet IC layout area requirements, with higher frequencies requiring less area. Those skilled in the art will recognize that, ${\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="S2006800170063E00051.png,S2006800170063E00151.png"\; state="\{\{state\}\}">f</figure-callout>}}_0\&ap;1/2\mathrm{\&pi;}\sqrt{\mathrm{LC}},$ But only as a first order approximation, since other factors such as impedances _RL and R _C , any additional resistors, together with temperature and process variations and other distortions affect f ₀ as described below, and can be included in second and third order Approximate. For example, inductor 435 and capacitor 440 may be sized to produce a resonant frequency in the range of 1-5 GHz; in other embodiments, higher or lower frequencies may be required, all such frequencies are within the scope of the invention. In addition, the inductor 435 and capacitor 440 can be manufactured using any semiconductor or other circuit process technology, and can be compatible with CMOS, compatible with bipolar junction transistors, while in other embodiments, the inductor 435 and capacitor 440 can use silicon-on-insulator wafer (SOI), metal-insulator-metal (MiM), polysilicon-insulator-polysilicon (PiP), GaAs, strained silicon, semiconductor heterojunction technology or MEMS (micro-electromechanical)-based technology manufacturing, again by way of example and not limit. It is to be understood that all such embodiments are within the scope of the invention. Furthermore, other resonator and/or oscillator embodiments may be used in addition to or instead of resonant LC tank 405 and are within the scope of the present invention. As used herein, "LC tank" shall mean any and all inductor and capacitor circuit layouts, structures or layouts that can provide oscillation. It should be noted that the ability to fabricate the oscillator 405 using conventional processes such as CMOS technology enables the clock generator to be integrated and monolithically fabricated with other circuits such as the second circuit 180 and provides the unique advantages of the present invention.

In addition, the capacitor 440 shown in FIG. 4 is only a part of all the capacitors involved in the resonance and frequency determination of the resonant LC tank circuit 405 , and is a fixed capacitor. In selected embodiments, this fixed capacitance may represent approximately 10%-90% of the total capacitance ultimately used in the oscillator. Alternatively, capacitor 440 may also be implemented as a variable capacitor if desired. As detailed below, all capacitances are allocated such that additional fixed and variable capacitances are selectively included within the clock generator and/or timing/frequency reference 300 and, for example, controlled by the frequency controller (215, 1415). Components such as a temperature-responsive frequency (f ₀ (T)) compensation module 420 and a process variation compensation module 425 are provided to select the resonant frequency f ₀ and make the resonant frequency f ₀ substantially independent of temperature and process variations.

In selected embodiments, inductance 435 has been fixed, but could also be implemented in a variable manner, or as a combination of fixed and variable inductance. Thus, those skilled in the art will recognize that the detailed discussion of fixed and variable capacitance applies similarly to inductor selection for frequency tuning and temperature and process independence. For example, different inductances may be switched in or out of the oscillator to similarly provide tuning. Additionally, the inductance of a single inductor can also be adjusted. Thus, all such inductance and capacitance variations are within the scope of the present invention and are illustrated as switchable, variable, and / or fixed reactive elements or components.

As also shown in FIG. 4, the resonant LC tank 405 and the resulting output signal at junctions or lines 470 and 475, referred to as the first (output) signal, are differential signals and provide common mode rejection. Other configurations, including non-differential or other single-ended configurations, are also within the scope of the invention. For example, in a single-ended configuration, only one instantiation of a different module (eg, 485, 460) should be needed, rather than using two to achieve a balanced configuration as shown. Similarly, other components and features described below, such as frequency dividers, should also have single-ended rather than differential configurations. In addition to the differential LC oscillators shown in FIGS. 6 and 8 , additional exemplary LC oscillators, including differential and single-ended LC oscillators, are described below with reference to FIGS. 31-37 . Furthermore, the different embodiments shown use MOSFET transistors (Metal Oxide Semiconductor Field Effect Transistors) of different forms (e.g., CMOS, Accumulation MOSFET (AMOS), Inversion MOSFET (IMOS), etc.); but other implementations are also possible, such as Bipolar junction transistors (BJT), BiCMOS, etc. are used. All such embodiments are considered equivalent and within the scope of the present invention.

Negative transconductance amplifier 410 is chosen to provide temperature compensation through transconductance (g _m ) regulation and the on-resistance of its resistors. Transconductance (g _m ) adjustment is also available independently for frequency selection. Another important advantage of the present invention is the selection of the negative transconductance amplifier 410 to provide startup and sustain amplification, since the oscillation amplitude and frequency are affected by the transconductance of the sustain amplifier, thereby providing amplitude adjustment and frequency trimming in addition to providing temperature compensation ( or tuning). Negative transconductance amplifier 410 injects current into resonant LC tank 405 (and specifically capacitor 440 ) in response to a voltage v across resonant LC tank 405 (as shown, across nodes 470 and 475 ). This current injection will in turn alter (and distort) the voltage waveform (since voltage is an integral of current), resulting in a frequency change or variation, which is generally inversely proportional to the magnitude of the transconductance _gm , as shown in Figure 5A. Note that this transconductance is negative because gain is provided to cancel the lossy nature of the resonant element. Therefore, whenever "transconductance amplifier" is used herein, it should be understood to mean, and is only a simplification of, "negative transconductance amplifier". Transconductance also varies with bias current and is substantially (approximately) proportional to the square root of the current through the amplifier 410 (yI(x)) (for a MOSFET) and substantially (approximately) proportional to the current through the amplifier (yI(x) ) (for a BJT), which is temperature dependent, resulting in a temperature- and bias-current-dependent waveform distortion, as shown in Figure 5B. In addition, as shown in FIG. 5C , the frequency of oscillation is also related to and varies with the transconductance maintaining the negative transconductance amplifier 410 , thereby providing oscillation frequency selection. Furthermore, in addition to being temperature dependent (being I(T)), the current can also be a function of other parameters or variables (hence more generally referred to as current I(x)), such as voltage or external tuning, The current can also be amplified eg by a factor y (discussed below); thus the current is called yI(x).

More generally, as described above, the variable current yI(x) may be used as a sensor or part of a sensor, such as one or more sensors 1440 or transconductance regulator 1420 of FIG. 21 or sensor 1815 of FIG. 25 . For example, when the variable current is provided by the I(T) generator 415 such that the provided current varies with temperature (parameter or variable x=temperature parameter T), so that the I(T) generator 415 acts as a temperature sensors, and may likewise be used in exemplary embodiments, such as by a frequency controller (215, 349, 1415) to adjust the resonant frequency f ₀ in response to temperature fluctuations. For example, transconductance regulator 1420 of FIG. 21 may include a temperature (or other parameter) responsive current source 415 (which also acts as sensor 1440 ) to provide current to sustain amplifier 305 .

The significant inventive breakthrough of the present invention includes the advantageous use of these possible distortions, frequency compensation in generating the selected _f0 value of the oscillator and frequency adjustment by maintaining regulation of the transconductance of the amplifier. Thus, as detailed below, firstly, the transconductance can be modified or changed for frequency selection, and secondly, it can be compensated for frequency changes due to temperature, voltage, manufacturing process, or aging by modifying the The current yI(x) is carried. According to the invention, the chosen frequency f ₀ and its stability against temperature variations can be determined by a suitable choice of transconductance _gm and choice of I(T). In other words, according to the invention, the bias current is made temperature dependent, which is I(T) (or more generally, yI(x)), which in turn affects the transconductance g _m , which in turn affects the oscillation frequency f ₀ . The method can also be used for other variables such as voltage fluctuations, process variations, or aging variations.

Figure 6 is a circuit diagram of an exemplary negative transconductance amplifier (410), temperature-responsive current generator (I(T) 415), and LC tank resonator (405) embodiment in accordance with the present invention. As shown in FIG. 6, the resonant LC tank 500 is connected to a negative transconductance amplifier 505 (comprising transistors M1, M2, M3, and M4) implemented as a complementary cross-connected pair of amplifiers, which in turn passes through a voltage isolator 510 (implemented as A current mirror (transistors 525A and 525B, and interchangeable here) is connected to a temperature-responsive current generator (I(x)) 515 . The current mirror 510 (voltage isolator) can also be implemented in a cascode topology (520A and 520B) to provide increased stability with power supply variations and to isolate the oscillator from the power supply (voltage isolation). The temperature-responsive current generator 515 may use techniques such as CTAT (contrary to absolute temperature), PTAT (proportional to absolute temperature), or PTAT ² (proportional to square of absolute temperature) as shown in FIGS. 7A, 7B, and 7C, respectively, and as The combination of CTAT, PTAT and PTAT ² shown in Figure 7D was performed. In each case, the current I(T) (or yI(x)) injected into the negative transconductance amplifier (complementary cross-connected pair amplifier) 505 is temperature dependent, as shown, increasing current with increasing temperature (PTAT and PTAT ² ) or reduced current (CTAT). Combinations of one or more of these temperature-responsive current generators can also be implemented as shown in Figure 7D, such as a CTAT in parallel with a PTAT.

The choice of a specific temperature-response or temperature-dependent current generator also varies with the fabrication process used; for example, CTAT can be used in the Taiwan Semiconductor (TSMC) fabrication process. More generally, as different manufacturers use different materials, such as aluminum or copper, _RL usually varies, which results in different temperature coefficients, which in turn changes the temperature coefficient of the oscillator, requiring I(T) to compensate for the difference. Accordingly, different ratios of CTAT, PTAT and PTAT ² may be required to provide an effectively flat frequency response over temperature. Not separately shown, the various temperature-responsive current generators shown in Figures 7A, 7B, 7C, and 7D may include a start-up circuit. Furthermore, for the exemplary layout shown, transistors comprising selected temperature-responsive current generator structures can be biased differently, such as enhanced reverse bias for CTAT (M7 and M8) and PTAT ² (M13 and M14). Subthreshold bias for PTAT (M9 and M10 and PTAT ² (M11 and M12)).

8 is a diagram of an additional exemplary negative transconductance amplifier, temperature-responsive (or temperature-dependent) current generator (I(T or I(x)), and LC tank oscillator embodiment in accordance with the present invention. Circuit and Block Diagram. As shown in FIG. 8, a resonant LC tank 550 has a different layout than previously shown, but is also connected to a negative transconductance amplifier 505 implemented as a complementary cross-connected pair of amplifiers (transistors M1, M2, M3 and M4), which in turn is connected to a temperature-responsive (or temperature-dependent) current generator (I(T or I(x)) 515 through a plurality of current mirrors 510 (or 520) and 530. As shown , multiple current mirrors are used in succession to provide gain and increase the current I(T) into the negative transconductance amplifier 505 and the resonant LC tank 550. Typically, current into node B is provided and it drives the negative transconductance amplifier's The last device in the current mirror (transistor M6 in Figure 6) is chosen to be a PMOS device, so several stages of reflection (as shown) may be required to provide the PMOS current mirror input to the _g amplifier. PMOS is usually chosen , because in modern CMOS processes, PMOS devices are usually buried channel devices, which are known to exhibit less flicker noise than NMOS devices of the same size and similar bias voltage. The reduction in flicker noise in the last device results in oscillator Phase noise and jitter are reduced because flicker noise is up-converted around the oscillation frequency by non-linear effective devices in the circuit.

As mentioned above, the portion of the current mirror 510 or 520 (or other circuit) that derives the current into the negative transconductance amplifier 505 should have a high impedance at its output to reduce power supply frequency shift, such as by using long transistor geometries and common base common The emitter structure increases the output resistance and provides good stability at Node B. In addition, shunt capacitor 570 may also be employed to filter to reduce flicker noise from different end devices.

Depending on the application chosen, the use of a negative transconductance amplifier 505 with its I(T) (or yI(x)) bias can provide sufficient frequency stability such that additional frequency controller components are not necessary or necessary in the application. unnecessary. In other embodiments, however, one or more of the components detailed below may be used to provide additional accuracy and less frequency shift.

In addition to providing a temperature-dependent current yI(x) (or I(T)), each of the different transistors M1, M2, M3, and M4 has an associated resistance during conduction that also tends to Causes frequency distortion and frequency shift during oscillation. In every half cycle, either M1 and M4 or M2 and M3 are switched on and conducting. The resistance is also temperature dependent. Therefore, the size (width and length) of transistors M1, M2, M3 and M4 should be adjusted to compensate for the frequency effect. It should be noted that the current injected into the resonant LC tank 405 must be sufficient to sustain the oscillation (as shown in FIG. 5C ), and thus will have a minimum value, which can limit the ease of passing through the negative transconductance amplifier 410 (or 505) and is temperature dependent. The degree or capability of the frequency control implemented by the current generator 415 (or 515). Therefore, I(T) and transistor (M1, M2, M3, and M4) sizes should be selected together for oscillation start-up, maximum current to accommodate power consumption constraints, and fit into the selected IC area and layout. For example, the transconductance _gm may be chosen to provide approximately enough current to ensure start-up and sustain oscillation, which has a frequency characteristic of decreasing frequency with increasing temperature, after which transistors M1, M2, M3, and M4 are sized sufficiently large that Frequency is independent of temperature or increases with temperature, then fine-tunes the frequency-temperature relationship with appropriate I(T) selection. In selected embodiments of the model, this has resulted in a frequency accuracy of approximately ±0.25%-0.5% as a function of PVT, which for many applications is well beyond the desired accuracy.

Referring again to FIG. 4, an additional compensation module is also used as part of the frequency controller (215, 349, 1415) to provide greater control and accuracy to the resonant frequency f ₀ , as for applications requiring greater accuracy and smaller Variation (or frequency shifting) applications, or applications where the technology does not allow previous technology to provide sufficient accuracy over PVT or lifetime variation, such that frequency accuracy on the order of ±0.25% or better is provided. In these cases, a temperature dependent (or temperature-responsive) frequency (f ₀ (T)) compensation module 420 may be used, such as the exemplary temperature-responsive frequency (f ₀ (T)) compensation module 420 . For example, this module can be implemented using controlled (or controllable) capacitor modules 485, each connected to a respective side or rail (lines 470 and 475) of the resonant LC tank circuit 405, each capacitor module being connected at the first Under centralized control provided by a plurality (w) of conversion coefficients (p ₀ . . . p _{(w-1) )} (register 495), and _the voltage controller provides _x-1) ) (register 455) determines the control voltage, as shown in Figures 9 and 10 for typical examples. (The terms "controlled" and "controllable" are used interchangeably herein). A further exemplary embodiment is shown in FIG. 20, which illustrates an exemplary controlled impedance module 1300 used in a frequency-temperature compensation module, such as a controlled (or controllable) capacitance module 485 in place of module 420 or As an additional module; in FIG. 22 it shows another variation of the controlled capacitance module 485 as the controlled capacitance module 1500 has multiple control voltages that are temperature dependent or dependent on other parameters (generated as shown in Figure 23 or 26); in Figure 25, it shows a plurality of controlled reactive modules 1805 that are switched on or off in response to control signals from control logic 1810 and sensors 1815 (connection to or disconnected from the resonator), the control signal includes feedback from the oscillator; in FIG. ) switch on or off and/or switch to the control voltage; and in Figure 27, a plurality of controlled reactance modules 1805 are shown that switch in response to the control signal for voltage variation compensation. There are several different types of transformations available, such as connecting or disconnecting reactance or impedance to the resonator, or converting connected reactance or impedance to a selected control voltage or other control signal.

9 is a circuit diagram of an exemplary first controllable capacitance module 635 according to the present invention, which can be used as the controlled (or controllable) capacitance module 485 in the frequency-temperature compensation module 420 (and connected to the resonant LC tank circuit each side of 405 (nodes or lines 470 and 475)). As shown, the controlled (or controllable) capacitance module 635 includes a set of multiple (w) binary-weighted fixed capacitors ( _Cf ) 620 and binary or other differentially weighted variable capacitors (variactors) The switchable capacitance module 640 of (C _v ) 615 . Any type of fixed capacitor 620 and variable capacitor (variactor) 615 can be used; in selected embodiments, the varactor 615 is an AMOS (accumulation MOSFET), IMOS (inversion MOSFET), and/or junction/diode varactors. Each switchable capacitor module 640 has the same circuit layout, and each capacitor module is distinguished by a binary weighted capacitance, the variable capacitor module 640 ₀ has a capacitance of 1 unit, and the variable capacitor module 640 ₁ has a capacitance of 2 units capacitance, and so on, the variable capacitance module 640 _(w-1) has 2 ^(w-1) units of capacitance, each unit representing a specific capacitance size or value (typically nanofarads (fF) or picofarads (pF )). As noted above, other differential weighting schemes are equally applicable, such as linear or binary, and may also include providing said differential weighting by converting the reactance to a selected control voltage, thereby increasing or decreasing its effective reactance.

Within each switchable module 640 , each fixed and variable capacitance is initially equal, the variable capacitance being allowed to vary in response to the control voltage provided at node 625 . This control voltage in turn varies with temperature or another selected variable parameter, causing all or all of the capacitance provided by controlled capacitance module 635 to also vary with temperature (or other parameter), which in turn serves to vary the resonant frequency f ₀ . In other selected embodiments, any of a plurality of control voltages may be used, including static control voltages, for other types of compensation as described below. Likewise, in each switchable capacitor module 640 , either the fixed capacitor C _f or the variable capacitor C _v is converted into _the circuit by using the conversion coefficients p ₀ . For example, in selected embodiments, for a given or selected block 640, when its corresponding p-factor is logic high (or high voltage), the corresponding fixed capacitance C _f is switched into the circuit, while the corresponding variable capacitance C _v is translated out of the circuit (and connected to the supply rail voltage V _DD or ground (GND), depending on whether the device is AMOS or IMOS, to avoid floating junctions and minimize the capacitance presented to the tank circuit), when its corresponding p When the coefficient is logic low (or low voltage), the corresponding fixed capacitance C _f is switched out of the circuit and the corresponding variable capacitance C _v is switched in and connected to the control voltage provided at node 625 .

In the exemplary embodiment, all 8 switchable capacitance modules 640 (and corresponding 8 conversion factors) have been implemented to provide 256 combinations of fixed and variable capacitances. Thus, effective control over temperature variation of the oscillation frequency is provided.

It should be noted that in this exemplary embodiment, providing for switching in or out of fixed capacitance _Cf or variable capacitance _Cv , the ratio of fixed to variable changes the amount or degree of temperature response of the controllable capacitance module 635 accordingly . For example, as the amount of variable capacitance C _v increases, the controllable capacitance module 635 provides greater variability in response to temperature (or other parameters), thereby adjusting the frequency response of the tank circuit or other oscillator.

10 is a circuit diagram of an exemplary temperature dependent voltage control module 650 for providing control voltage V _CTRL 480 ( FIG. 4 ) in controllable capacitance module 635 (of frequency-temperature compensation module 420 ) in accordance with the present invention. As shown, ^the voltage control module 650 generates a temperature dependent current I(T)( or more generally, current I(x)), and may share the used I(T) generator 415 with the negative transconductance amplifier 410 instead of providing a separate generator 655 . The temperature dependent current I(T) (or I(x)) is reflected by the current mirror 670 to a plurality of switchable resistance modules or branches 675 and fixed capacitance modules or branches 680, all configured in parallel. In other exemplary embodiments, other control voltage generators as described below may also be used depending on the parameter variation to be compensated for.

In other combinations, depending on the selection and weighting of the PTAT, PTAT ² and/or CTAT current generators, temperature dependent currents can also be generated. For example, a PTAT generator and a CTAT generator, having equal magnitudes but opposite slopes, can be combined to create a current generator that provides a constant current with temperature fluctuations. For example, such a current generator can be used to provide a constant current source in the aging variation compensator shown in FIG. 30 . Those skilled in the art will recognize that other current sources may be used, such as a current source that varies with supply voltage, and may be used as a corresponding voltage sensor.

Resistor 685 can be of any type or combination of different types, such as diffused resistors (p or n), polysilicon, metal resistors, salicide or non-salicide resistors, or well resistors (p or n-well). Depending on the type or combination of types of resistors selected, the resistor 685 will also typically have a corresponding temperature dependence (or response) such that for a given current through the selected resistor 685, the temperature-dependent The corresponding voltage change of the change. For example, diffused resistors will generally have a high temperature coefficient (provide a greater voltage change with temperature), while polysilicon resistors will generally have a low temperature coefficient (provide a smaller voltage change with temperature), and for the selected module 675, A series mix of a number of these different resistor types will provide a corresponding response between these high and low response levels. Alternatively, resistor 685 may be sized or weighted to provide different voltage levels as a function of a given current, such as a temperature-dependent current (eg, I(T)), thereby providing a corresponding variable voltage level for the temperature-dependent current. voltage change with temperature.

Each switchable resistance module 675 is switched into or out of the voltage control module 650 by a corresponding q-factor of the second plurality (x) of conversion coefficients q _{0 .} . . q _(x-1) . When the switchable resistance module 675 is switched into the circuit (such as when its corresponding coefficient is a logic high or high voltage), the resulting voltage across its corresponding resistor 685 also varies with temperature due to the temperature-dependent current I(T). It depends on the temperature. In the selected embodiment, three variable resistance modules 675 are used, providing 8 branch combinations. Accordingly, the control voltage provided to node 625 varies with temperature (or other parameter), thereby providing temperature or other parameter dependence or sensitivity to variable capacitor 615 in controllable capacitance module 635 . Other resistance modules, more generally parameter dependent or temperature dependent, are described below in connection with Figures 23 and 26 and Figure 28, respectively.

The first plurality of conversion coefficients p ₀ ...p _(w-1) and the second plurality of conversion coefficients q ₀ ...q _(x-1) can be determined post-manufacture by testing a typical IC with the inventive clock generator. For a given manufacturing process (described below in connection with Figures 11 and 12), once the resonant frequency _f0 has been selected and/or calibrated, the temperature (or other parameter) response of the oscillator is determined and adjusted for ambient or operating temperature Said variation of (or other variable parameter) provides a substantially constant selected resonant frequency f ₀ . In an exemplary embodiment, a first plurality of conversion coefficients p _{0 .} Presumably flat frequency response. As shown in Figure 24, more or less fixed capacitance _Cf or variable capacitance _Cv is switched in or out of the oscillator. For example, when the oscillator's uncompensated frequency response to temperature changes is represented by line 1705 or 1710 , an additional variable capacitance _Cv can be switched in to initially adjust the oscillator's frequency response to line 1715 . Conversely, when the oscillator's uncompensated frequency response to temperature variation is represented by line 1725 or 1730 , an additional fixed capacitance C _f can be switched in to initially adjust the oscillator's frequency response to line 1720 .

Thereafter, a second plurality of conversion factors is also determined by testing different combinations of coefficients to provide an excellent level of tuning resulting in a substantially flat frequency response with varying ambient temperature, as shown in Figure 24, which will partially The frequency response of the compensation (line 1715 or 1720 ) is adjusted to the substantially flat response of line 1700 by selecting the temperature response of different resistors 685 . Thereafter, the first and second plurality of coefficients are loaded into corresponding registers 495 and 455 in all ICs manufactured in the selected process run (or lot). Depending on the manufacturing process, in other cases, each IC may be calibrated individually for greater accuracy. Thus, in conjunction with the temperature compensation provided by negative transconductance amplifier 410 and I(T) generator 415, the overall frequency response of the clock generator is substantially independent of temperature fluctuations.

In other exemplary embodiments, the first plurality of conversion coefficients p ₀ ... p _(w-1) and the second plurality of conversion coefficients q ₀ ... q _(x-1) may also be dynamically determined and changed during operation of the oscillator , such as through sensor 1440 and A/D converter 1445 as shown in FIG. 21 , or through sensor 1815 and control logic (or control loop) 1810 as shown in FIG. 25 . In these alternative embodiments, the saved first and second plurality of coefficients can be deleted or bypassed, as shown in FIGS. Similarly, expand to other multiple coefficients described below).

For example, as shown in FIG. 26 , as detailed below, any of the plurality of current sources 1955 may be provided in different combinations to the plurality of resistive modules to generate a plurality of control voltages in response to a selected parameter P, This can be switched in any combination to each of the plurality of controlled reactance modules 1805, for example embodied as controlled capacitance modules 1505 (FIG. 22), to control the effective reactance of the resonator. In addition, any of a number of constant (temperature independent) control voltages can also be generated, as shown in FIG. 28 . Additionally, other or additional types of current sources may be used, either to generate control voltages or to provide sensor 385, 1440 capabilities, such as current sources that vary with supply voltage V _DD or that are independent of supply voltage, temperature, and other parameters. In addition to discrete control, any of these control voltages can be used for real-time continuous control of parameter changes, such as temperature changes.

Thus, all capacitance provided to the resonant LC tank 405 is allocated to a combination of fixed and variable parts, the variable part responding to provide temperature compensation, thus controlling the resonant frequency _f0 . The more variable capacitance C _v converted into the circuit (controlled capacitor module 635 ), the greater the frequency response to ambient temperature fluctuations. As mentioned above, both fixed and variable capacitors can be implemented using variable capacitors (variactors) connected or switched to substantially constant or variable voltages, respectively.

In addition to providing temperature compensation, it should be noted that the switching or controlled (or controllable) capacitance module 635 can also be used to select or tune the resonant frequency f ₀ . It will be apparent to those skilled in the art that switched or controllable capacitance modules 635 may also be used to provide frequency response to other parameter variations, such as manufacturing process variations, frequency and voltage fluctuations. In addition, as described below in conjunction with FIGS. 20 and 25-27, capacitors, inductors, resistors, or any other reactive or impedance elements may be used in these various exemplary embodiments to provide controlled reactance or impedance modules for multiple Any of three variable parameters such as temperature, voltage, manufacturing process, or frequency can provide the selected frequency response.

Figure 22 is a frequency-temperature compensation module 420 or, more generally, a frequency controller 215, 349, 1415 (along with module 1600 of Figure 23) used (in place of or in addition to modules 485 and 480) in accordance with the present invention. Circuit diagram of an exemplary second controlled capacitor module 1500 . The second controlled capacitance module 1500 operates similarly to the first controlled capacitance module 635, but uses variable capacitance instead of a combination of fixed and variable capacitance, and uses multiple different control voltages instead of a single control voltage. Furthermore, the varactor is not connected to or disconnected from the resonator (i.e. the varactor is always connected to the resonator) and is switched to a different control voltage to control the frequency as a function of a selected parameter such as temperature response. Additionally, selected embodiments may use one module, and differential weighting may be achieved by converting to selected ones of a plurality of control voltages.

Referring to FIG. 22, the second controlled capacitor module 1500 uses at least one of a plurality (g) of variable capacitance modules 1505, each variable capacitance module comprising variable capacitances (C _v ) 1515 _A0 . . . 1515 _{B(g-1 )} (illustrated in pairs A and B, corresponding to a symmetrical connection to either node 475 or 470, and illustrated with binary weighting), which can be switched (through a plurality of transistors or other switches 1520 ₀ ... 1520 _(g-1) ) to a selected control voltage among a plurality of control voltages V ₀ , V ₁ (x), ... V _(k-1) (x), wherein the control voltage V ₀ is substantially unchanged (not substantially responsive to the selected parameter x , such as temperature), while the remaining control voltages V ₁ (x)...V _(k-1) (x) are generally responsive to or sensitive to a selected parameter x such as temperature. As shown, the rear plates of each respective variable capacitor pair 1515 (A and B) are connected to each other (shorted together) and then switched to the selected control voltage. Each of said variable capacitance pairs 1515 may be defined by a corresponding coefficient (shown as a fourth plurality of coefficients d ₀ , d ₁ , ... d _(k-1) ... h ₀ , h ₁ , ... h _(k-1) switchable so that each module 1505 can be switched individually and independently of any of a plurality of control voltages V ₀ , V ₁ (x), ... V _(k-1) (x). Thus, these switchable modules can An effective impedance (eg, reactance) that is changed by switching to one or more control voltages remains connected to the resonator.

FIG. 23 is a circuit diagram of an exemplary second voltage control module 1600 used in a frequency-temperature compensation module according to the present invention. As shown in FIG. 23, a parameter sensitive or responsive current source 655 (such as any of the various CTAT, PTAT, and PTAT ² temperature sensitive current sources and combinations thereof previously described in connection with FIGS. 7A-7D ) (through a or multiple current mirrors (eg, 670, 510, 520)) to an array of k-1 resistive modules 1605 (shown as modules 1605 ₀ , 1605 ₁ , . . . 1605 _(k-1) ), each described _The modules provide individual or independent control voltages V ₁ (x), V ₂ (x), . The different respective resistors 1620 ₀ , 1620 ₁ , . . . 1620 _(k−1) may be of any type, size or weight previously described in connection with FIG. 10 to provide any selected voltage response to a selected parameter such as temperature. As shown, the static control voltage V ₀ is typically used with any voltage divider connected between the voltage supply rail V _DD and ground, with corresponding resistor sizes or values 1605 ₀ and 1605 _y selected to provide the desired static voltage level. Furthermore, multiple different static or constant (i.e., temperature independent) voltages are generated as shown in FIG. 28 by combining different current sources with differently shaped currents in response to temperature (or another parameter) with complementary or Different temperature-dependent resistors with opposite temperature responses combine to result in multiple control voltages having different magnitudes that remain substantially constant over temperature. Any of these different voltages may be used as any of the different control voltages as desired.

In an exemplary embodiment, each of the plurality of control voltages is different to provide a plurality of control voltages, each of which responds or is shaped differently (i.e., provides a different response as a function of a selected parameter such as temperature change). (response curve)), and may be substantially constant in response to different parameters and with respect to selected parameters. Depending on the chosen embodiment, the array of resistive modules 1605 can be switched (via corresponding transistors 1610 (illustrated as transistors 1610 ₀ , 1610 ₁ , . . . 1610 _(k−1) )) into or out of array 1600, or may be statically included (fixed connection 1615, shown as a dashed line in FIG. 23) to automatically generate a predetermined number of control voltages V ₀ , V ₁ (x), . . . V _(k-1) (x). Depending on the choice of resistor 1620 (and/or transistor 1610, if present), each of the distinct control voltages V ₀ , V ₁ (x), ... V _(k-1) (x) will be different and Different responses such as different temperature responses are provided for selected parameters or variables.

Similarly, FIG. 26 is a circuit diagram of an exemplary third voltage control module 1900 that may be used to provide a control voltage to any of the different modules in accordance with the present invention. As shown in FIG. 26, a parameter sensitive or responsive current source 1955 (such as any of the various CTAT, PTAT, and PTAT ² temperature sensitive current sources and combinations thereof previously described in connection with FIGS. 7A-7D ) (through a or multiple current mirrors (eg, 670, 510, 520)) to an array of n-1 resistive modules 1905 (shown as modules 1905 ₀ , 1905 ₁ , . . . 1905 _(n-1) ), each resistive module 1905 provides individual or independent control voltages V ₀ (P), V ₁ (P), V ₂ (P), ... V _(n-1) (P), thereby responding to the selected parameter P or according to the selected parameter P Multiple control voltages are generated and provided to controlled reactance module 1805, controlled capacitance module 1505 (FIG. 22), or any other module that uses one or more control voltages. The different respective resistors 1920 ₀ , 1920 ₁ , . . . 1920 _(n-1) may be of any type, size or weight previously described to provide any selected voltage response to selected parameters. Selection of the current source (or combination of current sources) and resistor size and type enables shaping of the response of any desired control voltage to the selected parameters. In addition, any of a number of different static or constant (ie, temperature independent) voltages shown in FIG. 28 may also be used as desired as any of the different control voltages for any of the modules described.

Depending on the chosen embodiment, _the array of resistive modules 1905 can be switched (via corresponding transistors 1915 (illustrated as transistors 1915 ₀ , 1915 ₁ , . out of the array to automatically generate a plurality of control voltages V ₀ (P), V ₁ (P), V ₂ (P), . . . V _(n-1) (P). Each of these different control voltages is then switched statically or dynamically (using switches 1930, such as full crossbar switches) in any combination to the controlled reactance module 1805 under the control of the control signal and/or the switching of coefficients 1950, It can be connected to a resonator or can also be switched in or out of a tank circuit. Therefore, any of these control voltages can be used to control the effective reactance of the resonator (oscillator), thereby providing both discrete and continuous control over the resulting resonant frequency. For example, any of these parameter-dependent control voltages V ₀ (P), V ₁ (P), V ₂ (P), ... V _(n-1) (P), or any voltage that is substantially independent of the parameter A control voltage (FIG. 28) of , may be provided to the controlled impedance module 1305 or the controlled capacitance module 1505 or 1805 to vary the effective capacitance provided to the resonator to provide frequency control as any of a number of parameters are varied.

Referring again to FIG. 22, when these different control voltages V ₀ , V ₁ (x), ... V _(k-1) (x) or more generally V ₀ (P), V ₁ (P), V ₂ (P) , ...V _(n-1) (P) for each voltage, and any substantially constant control voltage, can be obtained and passed through the fourth plurality of coefficients d ₀ , d ₁ , ...d _(k-1) ... h ₀ , h ₁ , . . . h _(k-1) converted to variable capacitance C _v 1515 in variable capacitance module 1505, highly flexible, fine-tuning, and highly controllable frequency for selected parameters such as temperature The response is provided to the resonator 405, enabling highly accurate frequency control of the resonant frequency f ₀ . For example, variable capacitors 1515 _{A(g -1)} and 1515 _{B(g-1) in block 1505(g-1)} can be set to logic high or high voltage by parameter h ₁ (or corresponding dynamically applied voltage as the control signal ) is switched to the control voltage V ₁ (x), the remaining h parameters in the fourth plurality of parameters are set to logic low or low voltage, thereby providing a first frequency response as a function of temperature or another selected parameter, At the same time, the variable capacitors 1515 _A0 and 1515 _B0 in the module ₁₅₀₅₀ can be converted to the control voltage V _(k ) by setting the parameter d _(k-1) of logic high or high voltage (or the corresponding dynamically applied voltage as the control signal) _-1) (x), the remaining d parameters of the fourth plurality of parameters are set to logic low or low voltage, thereby providing a second frequency response as a function of temperature or another selected parameter, and so on. As mentioned above, the fourth plurality of coefficients d ₀ , d ₁ , ... d _(k-1) ... h ₀ , h ₁ , ... h _(k-1) may also be determined after manufacture by testing one or more ICs, Or it can also be dynamically determined and changed during oscillator operation, such as by sensor 1440 and A/D converter 1445 as shown in FIG. 21 , or by sensor 1815 and control logic (or control Ring) 1810. More generally, the control of the pass or coefficient or control signal is as shown in Figure 26 and can be used for discrete or continuous frequency control as a function of any selected parameter such as temperature, voltage, manufacturing process, age, or frequency Or discrete and continuous frequency control.

Furthermore, instead of saving coefficients for the first, second or fourth plurality of coefficients, especially when the respective values are to be determined dynamically, the respective voltages can be applied directly to different switches (such as transistor 1520 or switching transistors of blocks 640 and 650) as control signals.

Referring again to Figure 4, an additional compensation module is also used to provide greater control and accuracy to the resonant frequency f ₀ , such as for applications that require greater accuracy and less variation (or frequency shift), such that with PVT Provides frequency accuracy of approximately ±0.25% or better. In these cases, a process variation compensation module 425 may be used to control the resonant frequency f ₀ independently of manufacturing process variations, as shown in the exemplary modules in FIGS. 11 and 12 . As noted above, any of the different modules may include any impedance, reactance, or resistance and be made responsive to any selected parameter such as temperature, process variation, voltage variation, and frequency variation.

FIG. 11 is a circuit diagram of an exemplary first process variation compensation module 760 according to the present invention. The first process variation compensation modules 760 can be used as the process compensation modules 460 in FIG. 4, each connected to the mains or side of the resonant LC tank circuit 405 (lines or nodes 470 and 475). Furthermore, each of the first process variation compensation modules 760 is controlled by a third plurality (y) of conversion coefficients r _{0 .} . . r _(y−1) stored in register 465 . The first process variation compensation module 760 provides an array of switchable capacitor modules with differentially weighted (eg, binary weighted) first fixed capacitors 750. Capacitor 750 switches in or out to adjust and select resonant frequency f ₀ . Again, as each capacitive branch is switched into or out of the array or circuit 760, the corresponding first fixed capacitance is added or subtracted from the total capacitance available for oscillation of the resonant LC tank, thereby changing the effective reactance and adjust the resonant frequency. The third plurality of conversion coefficients r ₀ . . . r _(y−1) can also be determined post-fabrication by testing the IC, typically in the same iterative process as determining the first and second (or fourth) plurality of conversion coefficients. This calibration can be accomplished using a frequency calibration module (325 or 430) and a known reference oscillator with a predetermined frequency. The determined r-factor is then saved in the corresponding register 465 of the IC of the production or process batch. Alternatively, each IC can be calibrated individually.

In addition to the calibration method described, the third plurality of conversion coefficients r _{0 .} Variables such as transistor threshold voltage, the size of a resistor or the value of a tank circuit, or the absolute current levels produced by different current sources. Said measured values can then be used to provide corresponding coefficients (third plurality of conversion coefficients r ₀ . . . r _(y−1) ) and/or control signals for corresponding frequency adjustments. For example, the measured or sensed values may be converted to digital values, which are then indexed into a look-up table in memory, after which a stored value is provided based on known values or other calibration or modeling.

To avoid additional frequency distortion, several additional features may be implemented along with the first process variation compensation module 760 . First, to avoid additional frequency distortion, the on-resistance of MOS transistor 740 should be small, so the width/length ratio of the transistor is large. Second, the bulk capacitor can be split into two branches, with two corresponding transistors 740 controlled by the same r-factor. Third, in order for the resonant LC tank to have similar loading under all conditions, when the first fixed capacitance 750 is switched into or out of the circuit 760, the corresponding second fixed capacitance 720 acts as a "dummy" capacitor (with a small Much larger capacitance or the minimum size allowed by the design rules of the manufacturing process) are converted out or into the circuit accordingly based on the inverse of the corresponding r-factor. Thus, there is always approximately or substantially the same on-resistance of transistor 740, only the capacitance varies.

As an alternative to using a "dummy" capacitor, metal fuses may be used in place of transistor 740 . The metal fuses will remain intact to include the corresponding fixed capacitance 750 and may "melt" (open circuit) to remove the corresponding fixed capacitance 750 from the resonant LC tank 405 .

FIG. 12 is a circuit diagram of an exemplary second process variation compensation module 860 according to the present invention. Second process variation compensation modules 860 can be used as process compensation modules 460 in FIG. More generally, the second process variation compensation module 860 is used as part of a frequency controller (215, 349 or 1415), such as a process (or other parameter) regulator or compensator 1430 (FIG. 21). In addition, each of the second process variation compensation modules 860 is controlled by a third plurality of conversion coefficients r ₀ . . . r _(y−1) stored in register 465 . (However, since the circuitry employed in each exemplary process variation compensation module 760 or 860 is different, the corresponding third plurality of conversion coefficients r ₀ ... r _(y-1) are of course different from each other.) Furthermore, the conversion may Control is performed using any of the control signals, as described above.

It should be noted that FIG. 12 provides a different varactor illustration than that used in other figures in that varactor 850 is represented by a MOS transistor rather than a capacitor with an arrow passing through it. Those skilled in the art will recognize that varactors are typically AMOS or IMOS transistors, or more generally, MOS transistors, such as the one shown in Figure 12, and are made by shorting the source and drain of the transistor. configuration. Therefore, as a possible embodiment, the other illustrated varactors may be considered to include AMOS or IMOS transistors as configured in FIG. 12 . Additionally, varactors 850 may also be binary weighted relative to each other, or another differential weighting scheme may be used.

The second process variation compensation module 860 has a similar structural concept, but has another significant difference from the first process variation compensation module 760 . The second process variation compensation module 860 provides an array of multiple switchable variable capacitance modules 865 without MOS switches/transistors, thus eliminating losses or loading through MOS transistors. Instead, the load appears as a low loss capacitor; said low loss also means that the oscillator has less energy to start up. In the second process variation compensation module 860, the MOS varactor 850 is switched to Vin, which may be any of the above-mentioned different multiple control voltages, to provide the resonant LC tank circuit 405 with a corresponding Capacitance levels, either can be switched to ground or mains (voltage V _DD ) to provide either minimum capacitance or maximum capacitance based on varactor 850 geometry. For AMOS, switching to voltage V _DD will provide minimum capacitance and switching to ground will provide maximum capacitance, while for IMOS the opposite is true. Again, the second process variation compensation module 860 consists of an array of varactors 850 as varactors 850, which connect or Switching to any of the plurality of control voltages (Vin), ground or V _DD as switching between the first voltage and the second voltage adjusts and selects the resonant frequency f ₀ . In another alternative, instead of multiples or arrays, only one varactor 850 is used, the effective reactance of which is provided to the tank circuit controlled by the selected control voltage.

As each capacitor branch is switched to the corresponding control voltage, ground or V _DD , the corresponding variable capacitance is added to or excluded from the total capacitance available for oscillation of the resonant LC tank, thus changing its effective reactance and adjust the resonant frequency. More specifically, for AMOS embodiments, connecting to V _DD (as V _in ) provides less capacitance, and connecting to ground (V _in =0) provides greater capacitance, while the opposite is true for IMOS embodiments, where connecting to V _DD (as V _in ) provides greater capacitance and connection to ground (V _in = 0) provides less capacitance, assuming the voltage on the LC tank rails (junctions or lines 470 and 475 of FIG. 4 ) Between 0 volts and the voltage V _DD , is significantly or substantially away from any voltage level. Connecting to a voltage between V _DD and ground such as many of the different control voltages as Vin will provide a corresponding intermediate level of capacitance to the tank circuit. The third plurality of conversion coefficients r ₀ ... r _(y-1) is also determined post-manufacture by testing the IC, and is typically also an iterative process that determines the first and second plurality of conversion coefficients. The determined r-factor is then saved in the corresponding register 465 of the IC for that production or process lot. Again, individual ICs can also be calibrated and tested individually. Additionally, any selected number of modules 850 may be dynamically controlled to provide continuous frequency control during oscillator operation.

As noted above, depending on the type of varactor (AMOS or IMOS), switching any of the varactor modules 865 to either V _DD or ground as the first and second voltage levels will result in a corresponding maximum capacitance or zero (which can be negligible) capacitance is included as the effective capacitance of the resonator (LC tank). However, as described above, capacitance levels between said maximum and minimum capacitances may also be generated by switching the variable capacitance module 865 to a corresponding control voltage. Using multiple control voltages with different magnitudes will cause the corresponding capacitance of the variable capacitance module 865 to be added to (or subtracted from) the LC tank, thus changing its effective reactance and adjusting the resonant frequency.

28 is a circuit diagram of an exemplary fourth voltage control module 2050 used in a frequency, process or other parameter compensation module in accordance with the present invention. Referring to Figure 28, a plurality of substantially constant voltage modules 2060 (illustrated as _2060A , _2060B , _2060C ... _2060K ) are used to generate a corresponding plurality of control voltages that are substantially constant with respect to a selected parameter such as temperature remains unchanged and has correspondingly multiple different magnitudes, thereby generating multiple control voltages V _A , V _B , V _C . . . V _K with different magnitudes. As shown, a plurality of different, substantially static or constant (i.e. temperature independent) voltages are generated by combining different current sources 2055 (illustrated as current sources 2055 _A , 2055 _B , 2055 _C . . . 2055 _K ). , each current source has a different response to temperature or another parameter (differently shaped current in response to temperature (or another parameter)), and has a corresponding plurality of resistors 2040 (shown as corresponding resistors 2040 _A , 2040 _B , 2040 _C . . . 2040 _K ), each resistor has a temperature or other parameter dependent response that is inverse or complementary to that of the corresponding current source 2055 of the particular module 2060. Each respective current source 2055 and resistor 2040 is selected to have said opposite or complementary response to each other, thereby effectively canceling the other's response to the selected parameter. For example, current source 2055 is selected to be a specific combination of appropriately sized PTAT, CTAT or CTAT ² current sources, and resistor 2040 is selected based on size, type, etc., such that the resulting voltage remains substantially constant over parameter changes, such as temperature. Any of these different voltages can be used as any of the different control voltages as desired to provide a corresponding Vin to the variable capacitance module 865 shown in FIG. 12 to adjust the effective capacitance (reactance) and The resulting resonance frequency.

It should also be noted that the illustrated module embodiments, such as temperature compensator 315 (or 410, 415 and/or 420) and process variation compensator 320 (or 425 and 460) as shown in FIGS. other purposes. For example, different illustrated embodiments of compensator 315 (or 410, 415, and/or 420) may be made to be process-dependent rather than temperature-dependent. Similarly, the different illustrated embodiments of compensator 320 (or 425 and 460 ) may be made temperature dependent rather than process dependent. Accordingly, embodiments of these and other modules should not be considered limited to the exemplary circuits and structures shown, as those skilled in the art will recognize additional and equivalent circuits and applications, all of which are within the scope of the invention.

As noted above, the various illustrated controlled capacitance modules (485, 635, 460, 760, 860, 1501) can be generalized to any reactive or impedance element, whether capacitive, inductive, resistive or capacitive, inductive or resistive combined. An array 1300 of such a plurality of (a) switchable, controlled impedance (or reactance) modules 1305 is shown in FIG. Any of the regulators or compensators (315, 320, 355, 1420, 1425, 1430). Each of the differently weighted, controlled reactance or impedance modules ₁₃₀₅ (illustrated as 1305 ₀ , _{1305 1 ,} . Or "dummy" reactances 1320, which are switchable in response to respective coefficients s of the fifth plurality of coefficients (s ₀ , s ₁ , . . . s _(a-1) ). As noted above, in any of the different embodiments, the array of controlled reactance or impedance modules 1305 are generally implemented to operate relative to any of the different controlled capacitance modules. The fifth plurality of coefficients may be determined post-manufacture or determined dynamically as described above with respect to other coefficient sets. Additionally, depending on the embodiment, different reactances or impedances can be switched into or out of the array 1300 or to different control voltages or grounds, as previously shown, and can be used to respond to a number of parameters such as temperature changes, voltage fluctuations, Any parameter in manufacturing process or frequency provides the selected frequency response of the oscillator.

Similarly, referring to Figure 25, _an array of n switchable, controlled reactance modules 1805 is shown (controlled reactance modules 1805 ₀ . 315, 320, 355, 1420, 1425, 1430) are used in the frequency controller (215, 1415) of the present invention. These controlled reactance modules 1805 may also be binary, linear, or differently weighted, and switched in or out of different circuits, switched to one or more control voltages, or any combination thereof, the set may be responsive to any selected parameter . As noted above, in any of the different embodiments, the array of controlled reactive modules 1805 is generally implemented to operate relative to any of the different controlled capacitive modules. In this exemplary embodiment, instead of switching to the oscillator via multiple coefficients, the controlled reactance module 1805 dynamically switches voltage or current provided directly by the sensor 1815 and control logic 1810, with feedback (line or node 1820) , and it may be performed as known in the art or as described above, and all such variations are considered to be within the scope of the invention. Furthermore, a reactive module is viewed more broadly as an impedance module, having both resistive and/or reactive characteristics, such as using different resistors as shown in FIG. 29 .

For example, the change in the selected parameter can be determined in any of the various ways previously described, such as by a temperature sensitive current source, other temperature sensor, or any other type of sensor responsive to the selected parameter. For example, a sensor may include a voltage across a diode, providing a voltage output responsive to temperature. Referring to FIG. 21, the output of such a sensor 1440 may be provided to an A/D converter 1445, which provides a digital output indication of the level of the sensed parameter, which may then be used as a corresponding coefficient (of the plurality of coefficients described above). any coefficient) or any module for dynamically switching between a different controlled reactance or impedance module (eg 1305, 1805) or a different second controlled capacitance module. Similarly, the output of sensor 1815 may be provided to control logic 1810, which may also adjust the different reactances either statically or dynamically, with or without feedback from the resonator.

FIG. 27 is a circuit and block diagram of an exemplary voltage variation compensation module 2000 according to the present invention, and may be used as the voltage variation compensator 380, 1455 shown in FIGS. 3 and 21 . Referring to FIG. 27 , switchable resistance module 1650 forms a voltage divider, using resistors 1620 ₀ and 1620 _y , to provide voltage V ₀ . In case the supply voltage V _DD (mains) fluctuates, the voltage V ₀ varies accordingly. Since the voltage can be switched (switch 1930) (as described above) to any of the controlled reactive modules 1805 under the control of the control signal or coefficient 1950, the effective capacitance of the tank circuit is also varied, thereby adjusting the resonant frequency. Thus, the resonance frequency can be controlled as the voltage fluctuates. Other implementations will be apparent based on the other illustrated embodiments and are within the scope of the invention.

As mentioned above, in addition to the intrinsic or parasitic resistances _RL 445 and _RC 450 of FIG. 4, the resonant frequency of the tank circuit can also be modified by changing the resistance of the tank circuit. 29 is a circuit diagram of an exemplary resistance control module 2100 that may be used as a different frequency control module and a different frequency controller, or a portion thereof, in accordance with the present invention. The resistance control module 2100 may be inserted at node Q in the resonator 405 of FIG. 4, in series with the inductor 435 and _RL 445, or in series with the capacitor 440 and _RC 450, or both. Each switchable resistance module 2115 (illustrated as a plurality of switchable resistance modules 2115 _M , 2115 _N , 2115 _O . . . 2115 _U ) has differently weighted (eg, binary weighted) resistors 2105 (shown as corresponding resistors 2105 _M , 2105 _N , 2105 _O ... 2105 _U ), and may be controlled by control signals and/or coefficients 1950 via corresponding transistors or switches 2110 (shown as transistors 2110 _M , 2110 _N , 2110 _O ... 2110 _U ) Switching into or out of the array or module 2100. As noted above, the switching also provides another mechanism for controlling or adjusting the resonant frequency of the resonator 405, and may be a function of any selected parameter, or may be independent of the parameter, for resonant frequency selection.

FIG. 30 is a block diagram of an exemplary lifetime variation compensator 2200 in accordance with the present invention. As shown in Figure 30, different sensors are used to measure corresponding parameters, which are affected by the time path or which change with the life of the IC, such as the voltage sensor 2205 measures the threshold voltage of a transistor, and the resistance sensor 2210 measures one or more of the tank circuit. Resistive magnitude or value, and/or current sensors measure the absolute current levels produced by different current sources. The selected measurement (via multiplexer 2220 ) at a given point in time is provided to ADC 2225 for conversion to a digital value, which is held in a register or other non-volatile memory 2230 . When the IC is first powered or initialized, an initial measurement is saved in register 2230 to provide a basis for comparison for subsequent measurements. Subsequently, additional measurements may be performed and the resulting values stored as corresponding current values in register 2230, shown as current and initial values for voltage, resistance and current. For a given parameter, such as voltage, current and initial values may be read and compared, after which comparator 2235 provides a corresponding lifetime compensation signal proportional to any difference between the two values. The difference provided by the lifetime compensation signal can then be used in corresponding coefficients and/or control signals for corresponding frequency adjustments. For example, the lifetime compensation signal may be indexed into a look-up table in memory 2240, which in turn provides stored values based on known values, or other calibration or modeling of lifetime effects, and using any of the various regulators described above Adjust the frequency accordingly with the compensator.

As mentioned above, the clock generator and timing/frequency reference (100, 200, 300) of the present invention can use a wide range of oscillators. In an exemplary embodiment, a resonant LC oscillator is used to provide the output signal as the first reference signal, which has much higher Q, low jitter and reduced phase noise. Exemplary first and second differential LC oscillators have been described above with reference to FIGS. 4 , 6 and 8 . Additional types of resonant oscillators are also within the scope of the present invention, and an exemplary LC oscillator will be described below with reference to FIGS. 31-37 , with the active inductor shown in FIG. 38 . These additional exemplary LC oscillators and inductor types (passive or active) are all equally usable for the previously described LC oscillators, and to illustrate their equivalent operation, together with the previously described and The exemplary frequency controller components shown in FIG. 4 , compensation modules 420 and 425 are illustrated together. It should be understood that any other controller reactance modules, control voltage generators, frequency control, calibration, frequency selection, frequency division, and other components other than those specifically shown in FIGS. 31-37 may equally be used.

It should also be noted that the exemplary active inductor shown in Figure 38 or any other active inductor can be substituted for any of the passive inductors shown in any of the layouts in Figures 1-37. Similarly, the different layouts are illustrated using n-MOS or p-MOS transistors, but any type of transistor could equally be used. Thus, the use of any passive or active inductor or any type of transistor is considered equivalent and within the scope of this invention.

The different LC oscillators shown below can provide differential or single-ended first reference signals. Different compensation modules 420 and 425, which can be implemented in various ways as controlled reactance modules as described above, can be combined in various ways with different oscillators. First, a controlled reactance module (illustrated as compensation modules 420 and 425 ) may be connected in parallel with any of the one or more capacitors shown. In many cases, multiple instances of the controlled reactance module can be connected to the LC oscillator shown. Accordingly, the corresponding nodes for connection are labeled as Node A and Node B to indicate the corresponding nodes connected to a given LC oscillator layout, additional illustrations may be used to illustrate as corresponding node A' and B' nodes and/or corresponding A'' and B'' nodes. Second, not separately shown in the various Figures 31-37, a controlled reactance module (illustrated as compensation modules 420 and 425) may be used in place of any of the one or more capacitors shown. Those skilled in the art will recognize numerous other variations, all of which are considered equivalents and within the scope of the invention.

31 is a circuit diagram of a third exemplary LC oscillator 2260, which is a variation of the LC oscillator shown in FIG. 8, implemented with a differential n-MOS cross-connected topology that may be used in accordance with the present invention. As shown, apparatus 2250 includes a third exemplary LC oscillator 2260 with a differential n-MOS cross-connect topology and the frequency controller and frequency calibration blocks (compensation blocks 420 and 425) previously described in the double-balanced configuration of FIG. ). The output frequency _f0 is obtained between junctions _470A and _475A , which are equivalent to junctions 470 and 475 previously described and supersede all references in the drawings and in this specification.

The cross-connected n-MOS transistors 2251 and 2251 are connected to the bias current through current mirror 530A (or 530B), such as using current I(x) generator 515 (or 415) responsive to a parameter also as previously described or Use another fixed or variable current source. The frequency controller module (480, 485, with coefficient registers 455 and 495) and the frequency calibration module (460, with coefficient register 465) are connected to the oscillator across nodes A and B as shown, and also as previously described run. Inductors 2253 and 2254 (with inductance as shown) may be equivalently replaced by center-tapped inductor 2257 (center-tapped to V _DD ) and inserted between nodes A and B as shown, and may be fixed or variable. variable inductor. Furthermore, also as previously stated, different capacitances may be implemented as fixed or variable capacitances, and are shown with both fixed and variable capacitors. In exemplary embodiments, the resistors may also be fixed or variable resistors.

It will be apparent to those skilled in the art that a similarly cross-connected n-MOS version of the oscillator shown in FIG. .

FIG. 32 is a circuit diagram of a fourth exemplary LC oscillator 2280 , which is a variation of the LC oscillator shown in FIG. 8 , implemented with a differential p-MOS cross-connected topology that may be used in accordance with the present invention. As shown, apparatus 2270 includes a fourth exemplary LC oscillator 2280 with a differential p-MOS cross-connect topology and the frequency controller and frequency calibration modules (compensation modules 420 and 425) previously described in the double-balanced configuration of FIG. ). The output frequency _f0 is obtained between junctions _470B and _475B , which are equivalent to junctions 470 and 475 previously described and supersede all references in the drawings and in this specification.

The cross-connected p-MOS transistors 2271 and 2271 are connected to the bias current through the current mirror 510 (or 520), such as using the parameter-responsive current I(x) generator 515 (or 415) also as previously described or Use another fixed or variable current source. The frequency controller module (480, 485, with coefficient registers 455 and 495) and the frequency calibration module (460, with coefficient register 465) are connected to the oscillator across nodes A and B as shown, and also as previously described run. Inductors 2273 and 2274 (with inductance as shown) may be equivalently replaced by center tapped inductor 2277 (center tap connected to ground) and inserted between nodes A and B as shown, and may be fixed or variable inductor. Furthermore, also as previously stated, different capacitances may be implemented as fixed or variable capacitances, and are shown with both fixed and variable capacitors. In exemplary embodiments, the resistors may also be fixed or variable resistors.

Also, it will be apparent to those skilled in the art that a similarly cross-connected p-MOS version of the oscillator shown in FIG. M4).

33 is a circuit diagram of a fifth exemplary LC oscillator 2305 having a single-ended Colpit substructure (or layout) that may be used in accordance with the present invention. As shown, apparatus 2300 includes a fifth exemplary LC oscillator 2305 having a single-ended Colpitt structure (or layout) and portions of the previously described frequency controller and frequency calibration modules (single-ended components of compensation modules 420 and 425 terminal version). The frequency controller and frequency calibration modules (485, 460) are connected in parallel across nodes A and B to capacitor 2310 as shown or in parallel across nodes A' and B' to capacitor 2315, or to both capacitors (in parallel with capacitor 2310 across nodes A and B and in parallel with capacitor 2315 across nodes A' and B', respectively). The output frequency _f0 is obtained between junctions _470C and _475C , which are equivalent to junctions 470 and 475 previously described and supersede all references in the drawings and in this specification.

Transistor 2325 is connected to a fixed or varying bias voltage, or to another circuit node (not separately shown). In addition, a bias current is also provided, such as using a parameter responsive current I(x) generator 515 as also previously described or using another fixed or variable current source. The frequency controller modules (480, 485, with coefficient registers 455 and 495) and the frequency calibration module (460, with coefficient register 465) also operate as previously described. Furthermore, the different reactances (inductor 2320, capacitors 2310 and 2315) may be implemented as fixed or variable reactances, also as previously described. In an exemplary embodiment, resistor 2330 may also be a fixed or variable resistor.

FIG. 34 is a circuit diagram of a sixth exemplary LC oscillator having a differential, common-base Colpy substructure (or layout) that may be used in accordance with the present invention. As shown, apparatus 2400 includes a sixth exemplary LC oscillator 2405 having a differential, common-base Colpy sub-structure (or layout) and the frequency controller and frequency calibration block previously described in the double-balanced structure of FIG. 4 . The output frequency _f0 is obtained between junctions _470D and _475D , which are equivalent to junctions 470 and 475 previously described and supersede all references in the drawings and in this specification.

Transistors 2425 and 2426 may be connected to a fixed or varying bias voltage. While illustrating the use of n-MOS transistors, transistors 2425 and 2426 also provide an example of the equivalent use of bipolar junction transistors in the present invention. Additionally, one or more bias currents are also provided, such as using a parameter responsive current I(x) generator 515 as also previously described or using one or more other fixed or variable current sources. Frequency controller modules (480, 485 with coefficient registers 455 and 495) and frequency calibration module (460 with coefficient registers 465) in parallel with capacitor 2415 across nodes A and B or across nodes A' and B as shown 'in parallel with capacitor 2410 or in parallel with capacitor 2430 across nodes A'' and B'', or any combination of these three configurations, and also operate as previously described. Furthermore, the different reactances (inductor 2420, capacitors 2410, 2415, and 2430) may be implemented as fixed or variable reactances, also as previously described.

35 is a circuit diagram of a seventh exemplary LC oscillator 2505 having a differential, common-collector substructure (or layout) that may be used in accordance with the present invention. As shown, apparatus 2500 includes a seventh exemplary LC oscillator 2505 having a differential, common-collector Colpiert configuration (or layout) and the frequency controller and frequency calibration module previously described in the double-balanced configuration of FIG. 4 . The output frequency _f0 is obtained between junctions _470E and _475E , which are equivalent to junctions 470 and 475 previously described and supersede all references in the drawings and in this specification.

One or more bias currents are provided, such as using a parameter responsive current I(x) generator 515 as also previously described or using one or more other fixed or variable current sources. Frequency controller modules (480, 485 with coefficient registers 455 and 495) and frequency calibration module (460 with coefficient registers 465) in parallel with capacitor 2515 across nodes A and B or across nodes A' and B as shown ' in parallel with capacitor 2510 or in parallel with capacitor 2530 across nodes A'' and B'', or any combination of these three configurations, and also operate as previously described. Furthermore, the different reactances (inductor 2520, capacitors 2510, 2515, and 2530) may be implemented as fixed or variable reactances, also as previously described.

36 is a circuit diagram of an eighth exemplary LC oscillator 2605 having a single-ended Hartley configuration (or layout) that may be used in accordance with the present invention. As shown, apparatus 2600 includes an eighth exemplary LC oscillator 2605 having a single-ended Hartley configuration (or layout) and portions of the frequency controller and frequency calibration module previously described. Also, since the oscillator 2605 is single-ended rather than differential, the frequency controller and frequency calibration modules (485, 460) are only connected to one rail (node _470F ) instead of having the double-balanced configuration of FIG. As shown, output frequency _f0 is obtained between nodes _470F and _475F , which are equivalent to nodes 470 and 475 previously described and supersede all references in the drawings and this specification . (Additionally, while the frequency controller and frequency calibration module (485, 460) graphs between the junction and the ground potential on node 475F, the frequency controller and frequency calibration module (485, 460) is also viewed as Capacitor 2610 in parallel across node 470F between _F and V _DD is equivalent to AC ground.)

Transistor 2625 may be connected to a fixed or varying bias voltage. In addition, a bias current is also provided, such as using a parameter responsive current I(x) generator 515 as also previously described or using another fixed or variable current source. The frequency controller modules (480, 485, with coefficient registers 455 and 495) and the frequency calibration module (460, with coefficient register 465) also operate as previously described. In addition, different reactances (inductors 2615 and 2620, capacitor 2610) may be implemented as fixed or variable reactances, also as previously described. In an exemplary embodiment, resistor 2630 may also be a fixed or variable resistor.

Comparing Figures 33 and 36, it is clear that the Hartley structure can be derived from the Clopitts structure by switching the capacitor for the inductor and the inductor for the capacitor. Thus, referring again to Figures 34 and 35, it will be apparent to those skilled in the art that differential Hartley oscillator structures, whether of the common base or common collector type, can be achieved by converting the capacitors and Inductors are formed. Thus, the differential Hartley oscillator structure is not shown separately.

37 is a circuit diagram of a ninth exemplary LC oscillator with a single-ended Pierce structure (or layout) that may be used in accordance with the present invention. As shown, apparatus 2700 includes a ninth exemplary LC oscillator 2705 having a single-ended Pierce configuration (or layout) and portions of the frequency controller and frequency calibration module previously described. Also, since the oscillator 2705 is single-ended rather than differential, the frequency controller and frequency calibration modules (485, 460) are connected to only one rail (node 470 _G ) instead of having the double-balanced configuration of FIG. 4 . As shown, output frequency _f0 is obtained between nodes _470G and _475G , which are equivalent to nodes 470 and 475 previously described and supersede all references in the drawings and this specification . In addition, frequency controller and frequency calibration modules (485, 460) are connected in parallel with capacitor 2710 across nodes A and B as shown, or in parallel with capacitor 2715 across nodes A' and B', or both Parallel connections (parallel to capacitor 2710 across nodes A and B and capacitor 2715 across nodes A' and B', respectively).

Oscillator 2705 includes an inductive load 2720, which may be, for example, an inductor or an inductor in parallel with a capacitor (presenting a total inductance), also as previously described, which may be implemented as a fixed or variable load. Inductive load 2705 is connected in parallel with inverter 2725 and resistor 2730 . The frequency controller modules (480, 485, with coefficient registers 455 and 495) and the frequency calibration module (460, with coefficient register 465) also operate as previously described. In addition, the various capacitors 2710 and 2715 may be implemented as fixed or variable capacitors, also as previously described. In an exemplary embodiment, resistor 2730 may also be a fixed or variable resistor.

It should be noted that any of the different LC oscillator topologies can be implemented to provide an orthogonal structure (or topography) that can be used with frequency compensation (for temperature, process variations, and other parametric variations) in accordance with the present invention. For example, two LC oscillators may be cross-connected to each other (and suitably constructed with a frequency controller module (480, 485, with coefficient registers 455 and 495) and a frequency calibration module (460, with coefficient register 465) to provide ° phase relationship (0°, 90°, 180° and/or 270°) of multiple first reference signals).

FIG. 38 is a circuit diagram of an exemplary active inductor 2910 structure that may be used in accordance with the present invention. While the active inductor 2910 is illustrated using a bipolar junction transistor, an equivalent circuit can be obtained using any type of CMOS transistor. Active inductor 2910 can be used for any inductor or inductive load of any LC oscillator described herein or its equivalent, and can provide savings in IC area. The active inductor 2910 shown is typically connected at node D to the rest of the oscillator. A bias current is also provided, such as using a parameter-responsive current I(x) generator 515, also as previously described, or using another fixed or variable current source. Furthermore, the active inductor 2910 is shown by way of example and not limitation—other active inductor circuits may be equivalently used, including with other types of transistors and circuit structures.

Those skilled in the art will recognize that numerous variations can be made to the different exemplary LC oscillator embodiments described above. For example, different amplifiers can be implemented in various ways, such as with only p-channel transistors, only n-channel transistors, or a combination of p- and n-channel transistors as shown. Furthermore, different amplifiers and current mirrors may have different circuit locations and structures relative to different resonators. Single or multiple inductor or capacitor variations can be used equivalently. The different layouts can be symmetric or asymmetric, complementary or non-complementary, or cross-connect or non-cross-connect. All such variations are considered equivalents and within the scope of the present invention.

Referring again to FIG. 21, the frequency controller 215, 349, 1415 of the present invention may include one or more of the following components: (1) a transconductance regulator 1410 (such as 410, 415 and the embodiment shown in FIGS. 6-8 ), which in an exemplary embodiment may also be and may be connected to the sustaining amplifier 305; (2) variable parameter regulator 1425 to respond to any selected parameter such as temperature, manufacturing process variation, voltage variation, or frequency adjustment Resonant frequency f ₀ , such as different controlled capacitance modules 485, 635, 1505 or controlled reactance modules 1305, 1805; (3) Process (or other parameter) regulators or compensators 1430, such as process variation compensators 425, 760 , 860, or controlled reactance modules 1305, 1805; (4) voltage variation compensators 380, 1455; and/or (5) lifetime (time) variation compensators (or regulators) 365, 1460. Those skilled in the art will appreciate that the different divisions between transconductance modules 1410, variable parameter regulators 1425, or process (or other parameter) regulators or compensators 1430 or other compensators and regulators are arbitrary and not intended. The scope of the invention is limited because each of them can be made responsive to any of the parameters described above, and each can be used for any of the purposes described above (e.g., the variable parameter module 1425 can be used to compensate for manufacturing process variations, etc., rather than temperature Variety). Additionally, one or more coefficient registers 1435 (eg, 455, 465, 495) may be used to hold any of the plurality of coefficients described above, depending on the chosen implementation. In alternative embodiments, the coefficients may not be needed, the voltage or current converted or applied directly as a control signal either statically or dynamically.

Also in an exemplary embodiment, these various components may include sensors 1440, 1815 (such as yI(x) (or I(T)) generators 415, 515), or the sensors may be provided as separate components, such as connected to diode current source, as described above. Also, depending on selected embodiments, an A/D converter 1445 and control logic 1450, 1810 may also be included to provide selected frequency control.

In summary, exemplary embodiments of the present invention provide an apparatus for frequency control of a resonator adapted to provide a first signal having a resonance frequency. The apparatus includes a sensor (1440, 1815) adapted to provide a second signal, such as a control voltage, in response to at least one of the plurality of parameters; and a frequency controller (215, 1415) connected to the sensor and connectable to the resonator , the frequency controller is adapted to modify the resonant frequency in response to the second signal. A number of parameters are variable and include at least one of the following parameters: temperature, manufacturing process, voltage, frequency, and age.

In an exemplary embodiment, the frequency controller is further adapted to modify a reactive or impedance element connected to the resonator in response to the second signal, such as modifying the total capacitance of the resonator in response to the second signal ( FIG. 9 ), will be fixed or variable A varactor (635) is connected to or disconnected from the resonator; the effective reactance of the varactor connected to the resonator is modified by switching the varactor to a selected control voltage, or equivalently, in response to The second signal modifies the inductance of the resonator, such as by connecting or disconnecting a fixed or variable inductance to or from the resonator; or modifies the resistance (or other impedance) of the resonator in response to the second signal, such as by connecting a resistor to or disconnect from the resonator.

In an exemplary embodiment, the frequency controller may further include: a coefficient register adapted to hold a first plurality of coefficients; and a first array ( 635), each switchable capacitance module has a fixed capacitance 615 and a variable capacitance 620, each switchable capacitance module is responsive to a corresponding coefficient in the first plurality of coefficients to switch between the fixed capacitance and the variable capacitance and convert each A variable capacitor switches to the control voltage. The plurality of switchable capacitive modules may be binary weighted modules. The frequency controller may also include a second array 650 having a plurality of switchable resistive blocks connected to the coefficient register and also having a capacitive block, the capacitive block and the plurality of switchable resistive blocks also connected to node 625 to provide a control voltage, each A switchable resistance module switches the switchable resistance module to the control voltage node 625 in response to a corresponding coefficient of the second plurality of coefficients stored in the coefficient register. In selected embodiments, the sensor also includes a temperature-responsive current source 655, wherein the current source is connected to the second array through a current mirror 670 to generate control across at least one switchable resistance module of the plurality of switchable resistance modules. Voltage. Also, in selected embodiments, the current source has at least one CTAT, PTAT, or PTAT ² structure (FIGS. 7A-7D). Additionally, each switchable resistance module of the plurality of switchable resistance modules has a different temperature response to the selected current.

In other exemplary embodiments, the sensor is a temperature sensor and changes the second signal in response to a change in temperature. Selected embodiments may also include an analog-to-digital converter 1445 coupled to the temperature sensor to provide a digital output signal in response to the second signal, and a control logic block 1450 to convert the digital output signal into a first plurality of coefficients.

In other exemplary embodiments, the frequency controller further includes a process variation compensator 320, 425, 760 or 860, which is connectable to the resonator and adapted to modify the resonant frequency in response to a manufacturing process parameter of a plurality of parameters . The process variation compensator may also include a coefficient register adapted to hold a plurality of coefficients; and an array 760 having a plurality of switchable capacitance blocks connected to the coefficient register and the resonator, each switchable capacitance block having a first fixed capacitance 750 and The second fixed capacitance 720, each switchable capacitance module responds to a corresponding coefficient of the plurality of coefficients to switch between the first fixed capacitance and the second fixed capacitance. In other exemplary embodiments, the process variation compensator may further include a coefficient register adapted to hold a plurality of coefficients; and an array 860 having a plurality of binary-weighted switchable variable capacitance modules 865 connected to the coefficient registers and the resonator , each switchable variable capacitance module is responsive to a corresponding coefficient of the plurality of coefficients to switch between the first voltage and the second voltage.

In other exemplary embodiments, the frequency controller further includes a coefficient register adapted to hold the first plurality of coefficients; and a plurality of switchable, binary-weighted capacitance modules 1505 connected to the coefficient register and connectable to the resonator A first array 1500, each switchable capacitance module having a variable capacitance 1515, each switchable capacitance module responsive to a corresponding coefficient of a first plurality of coefficients to convert (1520) the variable capacitance to one of a plurality of control voltages Selected control voltage. The sensor may include a current source responsive to temperature, and the frequency controller may also include a second array 1600 having a plurality of resistor modules 1605 connected to the current source (655) through current mirrors (670, 510, 520), the plurality of resistors The modules are adapted to provide a plurality of control voltages, and wherein each resistive module of the plurality of resistive modules has a different response to temperature and is adapted to provide a respective control voltage of the plurality of control voltages in response to the current of the current source.

In other exemplary embodiments, an apparatus for frequency control of a resonator includes a coefficient register adapted to hold a first plurality of coefficients; and having a plurality of switchable reactance modules (1305, 1805) connected to the coefficient register and the resonator ) of a first array (1300, 1800), each switchable resistance module switching a corresponding reactance to the resonator in response to a corresponding coefficient of the first plurality of coefficients to modify the resonant frequency. The corresponding reactance may be fixed or variable inductance, fixed or variable capacitance, or any combination thereof. A corresponding reactance is switchable between the resonator and a control voltage, which can be determined by the current source in response to temperature, or ground potential. For example, the corresponding reactance is a variable reactance and switches between the resonator and a selected one of the plurality of control voltages. In selected embodiments, the first plurality of coefficients is calibrated or determined by the sensor in response to at least one of a plurality of variable parameters such as temperature, manufacturing process, voltage, and frequency.

In an exemplary embodiment, the plurality of switchable reactive modules may also include a plurality (635) of binary-weighted switchable capacitive modules 640, each switchable capacitive module having a fixed capacitance and a variable capacitance, each switchable The capacitive module switches between fixed capacitance and variable capacitance responsive to a respective coefficient of the first plurality of coefficients and converts each variable capacitance to a control voltage. The apparatus may also include a current source 655 responsive to temperature; and a second array having a plurality of switchable resistive modules 675 connected to the coefficient register and optionally to the current source, the second array also having a capacitive module 680 , the capacitive module and the plurality of switchable resistor modules are also connected to node 625 to provide a control voltage, each switchable resistor module switching the switchable resistor module to The voltage node is controlled, and wherein each of the plurality of switchable resistance modules has a different temperature response to a selected current of the current source.

In other exemplary embodiments, the plurality of switchable reactive modules further includes a plurality of 1500 binary-weighted switchable capacitive modules 1505, each switchable capacitive module having a variable capacitance 1515, each switchable capacitive module responding to A corresponding coefficient in the first plurality of coefficients converts (1520) the variable capacitance to a selected control voltage of the plurality of control voltages. The apparatus may also include a current source 655 responsive to temperature; and a second array having a plurality of resistive modules 1605 connected to the current source through current mirrors (670, 510, 520), the plurality of resistive modules being adapted to provide multiple control voltages, and wherein each resistance module of the plurality of resistance modules has a different response to temperature and is adapted to provide a corresponding control voltage of the plurality of control voltages in response to the current of the current source.

In other exemplary embodiments, the plurality of switchable reactive blocks may also include a plurality 760 of binary-weighted, switchable capacitive blocks connected to the coefficient register and the resonator, each switchable capacitive block having a first fixed capacitance 750 and The second fixed capacitance 720, each switchable capacitance module switches between a first fixed capacitance and a second fixed capacitance in response to a corresponding coefficient of the plurality of coefficients. In other exemplary embodiments, the plurality of switchable reactive blocks may further include a plurality 860 of binary-weighted switchable variable capacitor blocks 865 connected to the coefficient register and the resonator, each switchable variable capacitor block responding to a plurality of A corresponding coefficient of the coefficients is used to convert between the first voltage and the second voltage.

In an exemplary embodiment, a device according to the invention comprises a resonator 310, 405 adapted to provide a first signal having a resonant frequency; and a temperature compensator 315 connected to the resonator and adapted to modify the resonant frequency in response to temperature changes . The resonator is at least one of the following resonators: an LC tank circuit resonator constructed from an inductor (L) and a capacitor (C), a ceramic resonator, a mechanical resonator, a microelectromechanical resonator, or a thin film bulk acoustic resonance device. The apparatus may also include a negative transconductance amplifier 410 connected to the resonator and a temperature compensator, wherein the temperature compensator is further adapted to modify current through the negative transconductance amplifier in response to temperature changes. The temperature compensator may also include current sources 415, 515, 655 responsive to temperature changes.

In other exemplary embodiments, the temperature compensator further includes: a current source 415, 515, 655 adapted to provide a current responsive to a change in temperature; a coefficient register adapted to hold the first plurality of coefficients; connected to the resonator and the current A plurality of resistive modules 675, 1605 of the source, at least one resistive module of the plurality of resistive modules adapted to provide the control voltage or voltages; and a plurality of switchable reactive modules (1305, 1805, 635, 1505) connected to The resonator and the current source are selectively connected to at least one resistance module among the plurality of resistance modules.

In other exemplary embodiments, the present invention provides a frequency controller for frequency control of a resonator comprising: a coefficient register adapted to hold a first plurality of coefficients and a second plurality of coefficients; A current source 415, 515, 655 for current; a first array with a plurality of switchable resistive blocks 675, 1605 connected to a coefficient register and also having a capacitive block, the first array also connected to the current source through a current mirror to generate a trans at least one control voltage for at least one switchable resistance module of the plurality of switchable resistance modules, each switchable resistance module switching the switchable resistance module in response to a corresponding coefficient of the second plurality of coefficients to provide control to the control voltage node voltage; and a second array having a plurality of binary-weighted switchable capacitive modules 640 connected to the coefficient register and the resonator, each switchable capacitive module having a fixed capacitance and a variable capacitance, each switchable capacitive module Switching between fixed capacitance and variable capacitance responsive to a corresponding coefficient of the first plurality of coefficients and switching each variable capacitance to a control voltage node.

Referring again to Figures 3 and 4, the clock generator and/or timing/frequency reference (100, 200 or 300) may also include a frequency calibration module (325 or 430). This frequency calibration module is the subject of a separate patent application, but its high-level functionality is briefly described below. Figure 13 is a high level block diagram of an exemplary frequency calibration module 900 (which may be used as module 325 or 430) in accordance with the present invention. The frequency calibration module 900 includes a digital frequency divider 910, a counter-based frequency detector 915, a digital pulse counter 905, and a calibration register 930 (which can also be used as register 465). Using the test IC, the output signal from the clock generator ( 100 , 200 or 300 ) is frequency divided ( 910 ) and compared to a known reference frequency 920 in a frequency detector 915 . Depending on whether the clock generator (100, 200 or 300) is fast or slow relative to the reference, a falling or rising pulse is provided to the pulse counter 905. Based on these results, a third plurality of conversion coefficients r ₀ ... r _(y-1) is determined and the clock generator (100, 200 or 300) is calibrated to the selected reference frequency. Again, individual ICs can also be calibrated and tested individually.

Referring again to Figures 2, 3 and 4, those skilled in the art will appreciate that a highly accurate, low jitter, self-running and self-referencing oscillator has been described that remains highly accurate over PVT variations, thereby providing the , a differential, substantially sinusoidal signal with a selectable and tunable resonant frequency f ₀ . For many applications, this signal is sufficient and can be used directly (and may be on bus 125 or 135 of FIG. 1, on line 250 of FIG. 2, or on line 350 of FIG. between outputs). For example, this signal can be used as a timing or reference frequency. There may be additional applications in accordance with the present invention, including clock generation (essentially square wave), frequency division, low latency frequency conversion, and mode selection, as described below.

14 is a block diagram of an exemplary frequency divider and square wave generator 1000, and an exemplary asynchronous frequency selector 1050 with an exemplary glitch suppression module 1080 in accordance with the present invention. As mentioned above, frequency divider and square wave generator 1000 may be included in or include modules 220 and/or 330, and frequency selector 1050 (with or without glitch suppression module 1080) may be Included in or comprising modules 205 and/or 335 .

Referring to FIG. 14, the output signal of the oscillator is a differential and substantially sinusoidal signal having a resonant frequency _f0 , such as on line 250 of FIG. 2, or on line 350 of FIG. The output between is input to frequency divider and square wave generator 1000. The frequency of this substantially sinusoidal signal is divided by any one or more arbitrary values N into m different frequencies (including f ₀ , where appropriate), and converted into a substantially square wave signal, resulting in m+1 different usable frequencies A plurality of substantially square wave signals of , ie output frequencies f ₀ , f ₁ , f ₂ , . . . f _m on the line or bus 1020 . Any of these substantially square wave signals having m+1 different available frequencies may be asynchronously selected by an exemplary asynchronous frequency selector 1050, which may be embodied as a multiplexer as shown. The selection of any of these substantially square-wave signals having m+1 different available frequencies can be done through a number of selection lines (S _m ... S ₀ ) 1055 to provide a substantially square-wave signal of the selected frequency, i.e. the line Output on 1060.

As part of the asynchronous frequency selection, glitch suppression is also provided by a glitch suppression module 1080, which can be embodied in a variety of ways, including through the use of one or more exemplary D flip-flops (DFFs) shown in FIG. 14 . Glitches can occur on asynchronous frequency transitions where either the low or high state is not held for sufficient time and can cause metastability in circuits driven by the output clock signal. For example, an asynchronous frequency transition may cause a transition from a low state at a first frequency to a high state at a second frequency, causing voltage spikes or glitches when the second frequency high state is about to transition back to a low state. To avoid possible glitches being provided as part of the output clock signal, a selected substantially square wave signal (with a selected frequency) is provided on line 1060 to the first DFF 1065 which provides a hold state; if a glitch occurs, it will be held Until a clock edge triggers the DFF. To avoid glitches on clock edges, the DFF can be clocked at a lower frequency than the maximum available, or one or more additional DFFs (such as the DFF1070) can be used, since the Q output of the DFF1065 will already be clocked while waiting for another clock signal. Stable as a first state (high or low) or a second state (low or high), such as or power or ground mains. The inventors have shown that 2 DFFs are sufficient, additional DFFs can be added as needed, but having additional DFFs will result in increased transition latency. While using the exemplary DFF diagram, other flip-flops or counters could be used, and those skilled in the art will recognize numerous other equivalent implementations that will achieve the result, all such variations being within the scope of the invention.

The exemplary low-latency frequency conversion according to the present invention is shown in FIG. 15 . Figure 15 is also an illustration of a "substantial" square wave of the present invention, which is typical of actual square waves used in different layouts, exhibiting reasonable variation, undershoot and overshoot in their respective high and low states (and not a textbook example perfect "straightness"). Part A of Figure 15 shows the asynchronous glitch-free transition from 1 MHz to 33 MHz, and part B shows the measured glitch-free transition from 4 MHz to 8 MHz, then to 16 MHz, and then to 33 MHz.

Referring again to FIG. 14, the frequency divider and square wave generator 1000 can be implemented in myriad ways, such as differential or single-ended, and the illustrated frequency divider is merely exemplary. Since the output of the oscillator shown in Figure 4 is a differential output (across lines or rails 470 and 475), the first frequency divider 1005 is also a differential frequency divider and provides complementary outputs to present a substantially constant load to the oscillator and maintains phase alignment, and is a fast divider to support high frequencies such as frequencies in the GHz range. Furthermore, it may be necessary or desirable to reject any relaxation mode oscillations of the first frequency divider 1005 . The second frequency divider 1010 can also be a differential frequency divider and provide any arbitrary frequency division (by M), such as division by integers, multiples of 2, rational numbers, or any other quantity or number. The layout or structure of such frequency dividers is well known in the art, and any such frequency divider may be used. By way of example and without limitation, the frequency divider may be a chain (multi-segment) of counters or flip-flops 1075, such as those shown in FIG. 16, as a second differential frequency divider 1074, which provides In frequency division, the output of each segment provides a different frequency and also provides a clock signal for the next segment and feeds back to its own input as shown. As shown, multiple frequencies are then available for output on line or bus 1020, such as f ₀ /2, f ₀ /4, and so on, up to f ₀ /2 ^N . Additionally, as shown, a buffer 1085 may also be used from the oscillator to the first divider 1005 to provide sufficient voltage to drive the first divider 1005, and buffering between stages of the second divider 1010 to isolate state-dependent load changes that can also affect signal rise and fall times.

It should also be noted that using a different flip-flop also provides a substantially square wave, since any substantially sinusoidal signal has been provided to clock a flip-flop whose output is then pulled to a high or low voltage. Other square wave generators, such as those well known in the art, may also be used. In the illustrated embodiment, to maintain phase alignment, the differential signal is maintained through the final division. After the final frequency division, multiple signals (each with a different frequency) are adjusted (in block 1015) to provide a substantially evenly divided (eg 50:50) duty cycle such that the signal is at the first (high) state is substantially equal to the time the signal is in the second (low) state.

17 is a block diagram of an exemplary mode selection module according to the present invention. There are situations where a highly accurate high performance reference such as the clock generator (100, 200 or 300) of the present invention is not necessary, eg in low power, standby mode. In these cases, either no clock output is provided, or a low power, reduced performance clock 1105 output is provided in accordance with the present invention. For example, at fairly low frequencies, low-performance ring oscillators can provide moderate, low-power performance. As shown in FIG. 17, for these conditions, the output of the low power oscillator 1105 can be selected (via the multiplexer 1100) and provided as a clock output to other circuits. However, at higher frequencies, the low performance oscillator consumes much more power, usually significantly more than the oscillator of the present invention. There is usually a frequency-dependent "break-even" point after which a clock generator (100, 200, or 300) provides higher performance and lower power consumption and can be selected (via multiplexer 1100) and used as The clock output is provided to other circuits. Therefore, the clock generator (100, 200 or 300) can also be used to provide a low power mode.

Furthermore, using the mode selector 1110, other modes can also be selected, such as no power mode, instead of just low frequency or sleep mode, in which the clock generator (100, 200 or 300) can be restarted fairly quickly, or A pulsed mode in which the clock generator (100, 200 or 300) can be periodically or aperiodically repeated bursts or stopped and restarted at intervals. The different reference modes are described below.

This pulsed clocking control using the clock generator and/or timing/frequency reference (100, 200 or 300) of the present invention provides power savings compared to the prior art. While more power is drawn during a particular burst, since the clock has a considerably higher frequency, more instructions are processed in that interval, followed by no or limited power dissipation during non-pulse or off intervals, thereby Results in higher MIPS/mW compared to a continuously running clock. In contrast, the pulsed clock control results in more power consumption and lower efficiency of the prior art clock due to the considerably longer start-up time and lockup of the prior art clock.

FIG. 18 is a block diagram of an exemplary synchronization module 1200 for a second oscillator in accordance with the present invention. As noted above, a clock generator and/or timing/frequency reference (100, 200, or 300) may provide a reference pattern to synchronize other oscillators or clocks, which may or may not be low power, such as the second oscillator 1210 (eg, ring , relaxation, or phase-shift oscillator). The output signal of the clock generator and/or timing/frequency reference (100, 200 or 300) is also frequency-divided as required to form a plurality of available reference frequencies from which a reference frequency is selected. This can be achieved using the modules described above, such as by using an existing frequency divider (220, 330, 1000, for example), and then providing a reference signal from frequency selector 1050 (or 205 or 335). For example, referring to FIG. 3 , mode selector 345 may select a reference mode and provide an output reference signal from frequency selector 335 to second oscillator (with synchronization module) 375 . A synchronization module such as a PLL or DLL 1205 is then used to synchronize the output signal from the second oscillator 1210 to a reference signal provided by a clock generator and/or a timing/frequency reference (100, 200 or 300). In addition to the continuous sync mode, pulsed synchronization is also available, where a clock generator and/or timing/frequency reference (100, 200 or 300) provides a pulsed output and synchronization occurs at intervals between these pulses, i.e. During the synchronization interval.

Figure 19 is a flowchart of an exemplary method in accordance with the present invention and provides a useful overview. The method begins with a start step 1220, eg initiated by a clock generator and/or timing/frequency reference (100, 200 or 300). It should be noted that while illustrated in Figure 19 as sequential steps, these steps may occur in any order, and typically may occur concurrently with the clock generator and/or timing/frequency reference (100, 200 or 300) operation. Referring to FIG. 19 , a resonant signal having a resonant frequency is generated at step 1225 , such as through the LC tank 405 or the resonator 310 . At step 1230, the resonant frequency is adjusted in response to temperature, such as by temperature compensator 315, which adjusts current and frequency. At step 1235 , the resonant frequency is adjusted in response to manufacturing process variations, such as by process variation compensator 320 . As described above, step 1235 may be performed as a first calibration step followed by temperature adjustment of step 1230 . In step 1240, the resonant signal having the resonant frequency is divided into a plurality of second signals having corresponding frequencies, such as by frequency divider 330 or 1000, wherein the plurality of frequencies are substantially equal to or lower than the resonant frequency. At step 1245 , the output signal is selected from a plurality of second signals, such as by frequency selector 335 or 1050 . According to a selected embodiment or mode, a selected output signal may be provided directly as a reference signal.

In other embodiments, such as when the output signal is a differential rather than a single-ended signal, and when the resonant signal is a substantially sinusoidal signal, the method continues at step 1250 to convert the differential, substantially sinusoidal signal to a substantially sinusoidal signal as needed. Single-ended substantially square wave signals of equal high and low duty cycle on equal, make use of module 330 or 1000 to generate a clock output signal. In step 1255, the operating mode is also selected from a plurality of operating modes, such as by using the mode selector 225 or 345, wherein the various operating modes may be selected from the group consisting of clock mode, timing and frequency reference mode, power saving mode, and controlled mode. Pulse action mode. When the reference mode is selected at step 1255, at step 1260 the method proceeds to step 1265 to synchronize a third signal (eg, from the second oscillator) in response to the output signal, as shown in FIG. 18 . After step 1260 or 1265, the method ends or repeats (continues) (eg, clock generator and/or timing/frequency reference (100, 200 or 300) continues to run), returning to step 1270 .

Figure 39 is a block diagram of a second exemplary system embodiment 1195 in accordance with the present invention. As shown, the second exemplary system 1195 includes a clock generator (timing/frequency reference) (100, 200, 300) as described above and any type or kind of second circuitry for any function, application, or purpose 180, such as processor 1275 as shown and defined below. The second circuit 180 may also include a memory 1280, an interface 1285 for input and output (I/O), and other circuit components for any selected application or function. The second exemplary system 1195 is generally embodied as a single integrated circuit providing one or more first reference signals as one or more system clocks or references, which is integrated with other components and which does not require any external references or clocks such as Crystal Oscillator Reference. For example, the clock/reference ( 100 , 200 , 300 ) is self-running and not locked to any reference clock or signal, but provides a reference clock or signal to other, second circuit 180 .

The second exemplary system 1195 may also be embodied as multiple integrated circuits connected by wire bonds within the same IC package. For example, a clock generator (timing/frequency reference) (100, 200, 300) may be embodied on a first IC, and a second circuit 180 may be embodied on a second IC, interconnected by one or more bonding wires , the first IC (clock) provides one or more first reference signals as one or more system clocks or references to the second IC (second circuit 180), thereby providing the clock or reference as part of a single package assembly , without the need for any external reference or clock such as a crystal oscillator reference.

As shown in FIG. 39, in addition to a clock generator (timing/frequency reference) (100, 200, 300), a second exemplary system 1195 includes one or more types of second circuitry, such as one or more A processor 1275, and possibly an I/O interface (or other I/O device) 1285 and a memory 1280. Each of these components receives one or more first reference signals, typically used as one or more clock control signals. In second exemplary system 1195, I/O interface 1285 may be implemented as an interface known or to become known in the art for communication between processor 1275, memory 1280, and any channels, buses, input and output devices, described herein. Data communication is provided between mechanisms and media (not separately shown), including wireless, optical or wired, using any available standard, technology or media without limitation. For example, when the second exemplary system 1195 is used as a computer processor, the I/O interface 1285 is adapted to interface with one or more buses such as PCI bus, PCI Express bus, Universal Serial Bus (USB1 or USB2), etc. provide data communication. Additionally, I/O interface 1285 may provide an interface to any CD or disk drive, or to a communication channel for communicating over a network, providing communication with any form of medium or communication means, such as providing an Ethernet port. Also, for example, I/O interface 1285 may provide all signaling and physical interface functions, such as, but not limited to, impedance matching, external communication lines or channels to the network (such as Ethernet, T1 or ISDN lines), and internal server Or data input and data output between computer communication buses such as one of the various PCI or USB buses. Additionally, depending on selected embodiments, I/O interface 1285 (or processor 1275) may also be used to provide data link layer and media access control functions.

Memory 1280 may be embodied in any number of forms, including within any computer or other machine-readable data storage medium, for storage or storage of information such as computer-readable instructions, data structures, program modules, or other data, according to selected embodiments. Communication memory devices or other storage or communication devices, whether currently known or soon to be available, including, but not limited to, magnetic disk drives, optical drives, magnetic disk or tape drives, hard drives, other machine-readable storage or memory media such as Floppy disk, CDROM, CD-RW, digital versatile disk (DVD) or other optical drive, memory integrated circuit (IC), or the memory portion of an integrated circuit (such as memory resident in a processor IC), whether volatile or Non-volatile memory, whether removable or non-deletable memory, including but not limited to RAM, FLASH, DRAM, SDRAM, SRAM, MRAM, FRAM, ROM, EPROM or E ² PROM, or any other type of memory, storage medium, or data storage devices or circuits, which may be known or soon to be known. Furthermore, such computer-readable media includes any form of communication media that embodies computer-readable instructions, data structures, program modules, or other data in a data or conditioned signal, such as an electromagnetic or optical carrier wave or other transport mechanism, including Any information copy medium that encodes data or other information in a wired or wireless signal, including electromagnetic, optical, acoustic, RF, or infrared signals.

The second exemplary system 1195 also includes one or more types of processing circuitry, such as one or more processors 1275, which may be single-core or multi-core, general-purpose or special-purpose processors and adapted to perform any type of function. As the term "processor" is used and defined herein, the processor 1275 may be any type of circuitry adapted to perform any type or kind of function, application or other purpose, and may include the use of a single integrated circuit (IC) , or may include the use of multiple integrated circuits or other components connected, arranged or grouped together, such as microprocessors, digital signal processors (DSPs), controllers or microcontrollers, parallel processors, multi-core processors, Conventional ICs, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), Adaptive Computing ICs, associated memories such as RAM, DRAM, and ROM, and other ICs and components. Thus, as used herein, the term processor should be understood to mean and include equivalently a single IC, or conventional IC arrangement, ASIC, processor, microprocessor, controller, FPGA, adaptive computing IC, or any Other integrated circuit groupings of appropriate function, and associated memory such as microprocessor memory or additional RAM, DRAM, SDRAM, SRAM, MRAM, ROM, FLASH, EPROM or ^E2PROM . The processor (e.g., processor 1275) and its associated memory may be adapted or constructed (programmed, microcode, FPGA interconnect, or hardwired) to perform as described below with the second exemplary system 1195 (or as described below) Any function related to any selected application of the third, fourth or fifth exemplary system of . For example, any function or method may be programmed and stored in processor 1275 and its associated memory (and/or memory 1280) and other equivalent components as a set of program instructions or other code (or equivalent configuration or other program) to For subsequent execution when the processor is running (ie, powered on and running). Likewise, while the processor 1275 may be implemented in whole or in part as an FPGA, conventional IC, and/or ASIC, the FPGA, conventional IC, or ASIC may also be designed, configured, and/or hardwired to implement any selected function or method. For example, processor 1275 may be implemented as an arrangement of microprocessors, DSPs, and/or ASICs, collectively referred to as "processors," which are individually programmed, designed, modified, or configured to perform selected functions, such as communication functions, data processing function etc.

For example and without limitation, processor 1275 may be implemented as a microprocessor, digital signal processor, controller, microcontroller, universal serial bus (USB) controller, peripheral component interconnect (PCI) controller, peripheral component interconnect Connect Express (PCI-e) controllers, FireWire controllers, AT Attachment (ATA) interface controllers, Integrated Drive Electronics (IDE) controllers, Small Computer System Interface (SCSI) controllers. In other embodiments, the processor 1275 may be implemented to provide other forms of control functions, such as a television controller, local area network (LAN) or Ethernet controller, video controller, audio controller, modem processor or controller, Cable modem controller or processor, multimedia controller, MPEG controller such as MPEG-1 (video CD, MP3), MPEG-2 (digital TV, DVD), MPEG-4 (multimedia for fixed and mobile network applications) ), MPEG-7 (description and search of audio and visual content), MPEG-21 (multimedia framework). In other embodiments, the processor 1275 may be implemented to provide communication functions, such as one or more communication controllers for mobile communication (mobile communication Controllers, IEEE 802.11 controllers, GSM controllers, GPRS controllers, PCS controllers, AMPS controllers, CDMA controllers, WCDMA controllers, spread spectrum controllers, wireless LAN controllers, different forms of IEEE 802.11 controllers, etc. ) or one or more communication controllers for non-mobile communication (such as DSL controller, T1 controller, ISDN controller) or other multimedia or other communication controllers.

Continuing with the example above, selected frequencies could include 12, 30, 48, or 480MHz for USB controllers (USB1 or USB2); 33 or 66MHz for PCI controllers or for PCI-e controllers, Firewire control 6MHz for controllers, ATA controllers, or SCSI controllers; 10.7MHz for TV controllers; 50MHz for local area network (LAN) or Ethernet controllers; 27MHz or 54MHz for video controllers; 24.576MHz for a modem processor; 56.448MHz for a modem processor; other frequencies suitable for the different MPEG controllers or communication controllers mentioned above. Other frequencies may also be selected based on the application, such as selecting an appropriate GHz frequency when the processor 1275 is used in a computer.

The different frequencies as described above can be determined in any of a number of ways, whether provided directly by the clock generator (timing/frequency reference) (100, 200, 300) as the first frequency _f of the first reference signal or by one or One or more second frequencies of a plurality of second reference signals (via one or more frequency dividers (1000, 1010, 1074, 1218, 1219) or locking circuit 1204 and other components described below). For example, different frequencies may be determined as part of design and manufacture, or after manufacture (eg, by calibration and programming), or both. More specifically, frequency selection can occur as part of design and manufacture, such as by selecting the number and size of inductors and capacitors used in the LC oscillator of the clock/reference (100, 200, 300). For example, the size and/or shape of one or more inductors (eg, 445) may be selected by appropriate metal layer masking. As mentioned above, frequency selection can also take place post-manufacture by using different calibration and control coefficients or signals as described above. In addition, as described below, frequency selection may be performed by configuring one or more lock circuits 1204 or frequency dividers, such as by selecting a frequency division ratio through a programmable counter, which is part of the IC design and manufacture, or may be performed after manufacture. Programming, again by using calibration or control coefficients or signals or by switching the dividers into or out of the divider chain.

In addition to the one or more processors 1275, I/O interface 1285, and memory 1280 shown, those skilled in the art will appreciate that different exemplary systems may include additional or different components, and will generally vary with the selected Apply changes. For example, different applications may require additional circuitry, such as different physical layer implementations in addition to those described for I/O interface 1285 .

Figure 40 is a block diagram of a third exemplary system embodiment 1201 in accordance with the present invention. As shown in FIG. 40, a first reference signal having a first frequency (f ₀ ) is provided either directly to the processor 1275 (as in the example of the second circuit 180), or to an additional, shown inverter 1196 , frequency dividers (1000, 1074, 1218 and/or 1219 (described below)), locking circuits 1204 (illustrated as locking circuits 1204 ₁ , locking circuits 1204 ₂ , . . . , locking circuits 1204 _N ), and the dividing A second circuit that is a combination or replacement of frequency converters, locking circuits, etc. The further second circuit is adapted to receive a first reference signal having a first frequency and provide selected frequencies _f1 , _f2 , ... _fN and have any selected phase relationship (e.g. inverted, 90 degrees, quadrature, etc. ) of one or more corresponding second reference signals.

The third exemplary system 1201 (and various other exemplary embodiments described below) generate multiple reference signals, whether sinusoidal or square wave signals, such as for use as one or more clock signals or frequency references. A clock/frequency reference (100, 200, 300) provides a first reference signal (having a first frequency f ₀ ) and is connected to one or more locking circuits 1204 such as phase locked loops, delay locked loops, injection locked circuits (shown as Locking circuit 1204 ₁ , locking circuit 1204 ₂ , . . . , locking circuit 1204 _N ) to provide a corresponding plurality of output signals at selected frequencies f _K+1 , f _K+2 , . . . f _N . Each locking circuit in plurality of locking circuits 1204 has a corresponding one of a plurality of different dividing ratios. In operation, each lock circuit 1204 is adapted to phase, delay or otherwise lock to a first reference signal provided by a clock/frequency reference (100, 200, 300) and provide A second reference signal at the output frequency is output. Each lock circuit, such as a PLL or DLL, can be implemented as known in the art, such as PLL _1204A as shown in FIG. 43 and described below.

In an exemplary embodiment, the frequency of the second reference signal may be a fixed frequency, such as fixed by hard-wiring or configuring a frequency divider or a frequency division ratio during manufacture, or may be a variable frequency, such as by a control circuit ( or logic) or saved coefficients (1215) (block 1215, which may be registers holding coefficients or other circuits providing control signals) are selected or programmed after manufacture to adjust the divider ratio of locking circuit 1204 for the corresponding frequency selection, This will be further described below. Any saved coefficients (1215) may also be part of the various frequency calibration and frequency control coefficients held in registers 455, 465 and 495 as described above. Alternatively, user input, such as for frequency selection, may also be provided via a user interface (not shown separately).

As described above in connection with FIG. 14 (frequency divider 1000, 1010) and FIG. 16 (differential signal frequency divider 1074), the clock/frequency reference (100, 200, 300) from the clock/frequency reference (100, 200, 300) The output signal of the oscillator may also be frequency-divided to provide one or more second reference (or clock) signals having one or more selected second frequencies. 41 is a block diagram of a third exemplary frequency divider embodiment 1218 for asynchronous frequency division in accordance with the present invention. Figure 42 is a block diagram of a fourth exemplary frequency divider embodiment 1219 for synchronous frequency division in accordance with the present invention. As previously mentioned, for these embodiments, each flip-flop (or counter) 1214 (illustrated as flip-flops 1214 ₀ , 1214 ₁ , . . . 1214 ₅ ) provides frequency division by a factor of two, or when implemented as a counter, provides The frequency division of whatever maximum (terminal or extreme) number the counter is suitable for counting. FIG. 41 shows the structure of a flip-flop (or counter) 1 214 that provides asynchronous frequency division. Figure 42 shows the structure of a flip-flop (or counter) 1214 with other gate logic ("AND" gate) 1217, which provides synchronous frequency division. Combinational logic circuits of any configuration may be used to provide the selected synchronization other than the gate logic circuit (AND gate) 1217 shown for the divide-by-8 circuit shown in FIG. An example of , and all such variations are within the scope of the invention.

Frequency dividers, such as third exemplary frequency divider 1218 and fourth exemplary frequency divider 1219, may be connected to oscillators of different clock generator (timing/frequency reference) (100, 200, 300) embodiments, thereby One or more second reference signals are provided having a corresponding plurality of second frequencies illustrated as _f2 , _f3 , ... _fK . Alternatively, the frequency dividers, such as the third exemplary frequency divider 1218 and the fourth exemplary frequency divider 1219, may be oscillators connected to different clock generator (timing/frequency reference) embodiments (100, 200, 300) A portion of a locking circuit 1204 of the device, such as one or more phase-locked loops (PLLs), delay-locked loops (DLLs), or injection-locked circuits. An exemplary lock circuit is illustrated as PLL 1205 in FIG. 18 . The locking circuit embodiment is described below in connection with FIGS. 43 and 44 . In addition, different frequency dividers (1000, 1010, 1074, 1218, 1219) may also be connected to one or more locking circuits 1204, as shown in FIG.

Both asynchronous and synchronous frequency division to provide one or more output signals having selected frequencies are within the scope of the present invention. Furthermore, the frequency division can be switched between asynchronous or synchronous frequency division at any point in the frequency division chain (ie, sequentially connected flip-flops (or counters) 1214 as shown). The frequency division may be any number of frequency divisions. The frequency division can be a single-ended or differential clock or reference signal (eg, as shown in Figures 14, 16, 41 and 42). Numerous other circuit topologies for frequency division will be apparent to those skilled in the art and are considered equivalents, and all such variations are within the scope of the invention.

Continuing to refer to FIG. 40, a third exemplary system 1201 may include a clock generator (timing/frequency reference) (100, 200, 300) and any one or more of the second circuits shown, such as an inverter 1196, a square wave generator 1015, frequency divider (1000, 1010, 1074, 1218, 1219), lock circuit 1204, or any of the various other types of second circuits previously mentioned, such as one or more processors 1275, memory 1280 or I/O interface 1285. For example, the third exemplary system 1201 may be implemented to include providing (on line 1197) a first reference signal having a first frequency (f ₀ ) directly to further second circuitry 1198 such as a processor 1275, one or more Frequency dividers (1000, 1010, 1074, 1218, 1219) are adapted to lower frequency multiple second reference signals, eg for power saving. Also, for example, the third exemplary system 1201 can be implemented to include one or more locking circuits 1204 and/or one or more frequency dividers (1000, 1010, 1074, 1218, 1219) connected to the locking circuits 1204 to, for example, A plurality of second reference signals at any respective frequency is provided based on a respective division ratio (providing any rational multiple of the first frequency f ₀ ).

Figure 43 is a block diagram of a fourth exemplary system embodiment 1202 in accordance with the present invention. A clock/frequency reference (100, 200, 300) provides a first reference signal (with a first frequency f ₀ ) and is connected to at least one locking circuit 1204 such as a phase-locked loop (PLL), delay-locked loop (DLL) or injection The circuit is locked to provide a corresponding second reference signal, such as a clock output signal of a selected frequency, shown as frequency f _N . (A fifth system embodiment having multiple locking circuits 1204 is described below in conjunction with FIG. 44.) In operation, each locking circuit (such as a PLL or DLL) 1204 is adapted to phase, delay, or otherwise lock to a clock/frequency reference ( 100, 200, 300) and provide as output an output signal (second reference signal) having a second frequency determined from the first frequency and the corresponding frequency division ratio. Illustrated as a PLL embodiment for purposes of example and not limitation, PLL _1204A (as a type of locking circuit 1204) includes a first frequency divider (or multiplier) 1206 (eg, ÷N) and a second A frequency divider (or multiplier) 1207 (such as ÷M) to form a corresponding frequency division ratio to provide a second frequency, which is a rational multiple (M/N) of the first frequency f ₀ . In the embodiment shown, the second frequency divider 1207 effectively acts as a multiplier (dividing the output frequency f _N into lower frequencies to match and phase lock to f ₀ /N). According to selected embodiments, the output frequency of the second reference signal (eg f _N ) may be any rational multiple of the first frequency f ₀ , whether higher or lower.

Lock circuit 1204, when implemented as a phase locked loop _1204A , also includes a phase detector 1208, a charge pump 1209, an optional filter 1211, and a voltage controlled oscillator (VCO) 1212 (as shown in FIG. oscillator 1210). VCO 1212 provides a second reference signal having a second frequency f _N that is used as a clock or other reference by processor 1275 , memory 1280 and I/O interface 1285 in integrated third system embodiment 1202 .

The clock/reference (100, 200, 300) is adapted to provide as output a first reference signal having a first frequency _f0 , or together with a frequency divider or lock circuit 1204 a second reference signal shown in FIG. 43 as frequency _fN . frequency, or together with a plurality of locking circuits 1204 or frequency dividers provide as output a corresponding plurality of second reference signals having respective frequencies f ₁ , f _{2 .} . . f _N illustrated in FIG. 44 . As mentioned above, frequency selection can occur as part of design and manufacture, such as by selecting the number and size of inductors and capacitors used in the LC oscillator of the clock/reference (100, 200, 300). For example, the size and/or shape of one or more inductors (eg, 445) may be selected by appropriate metal layer masking. Frequency selection can also occur post-manufacture by using different calibration and control coefficients or signals as described above. In addition, frequency selection can be performed by configuring one or more lock circuits 1204 (PLL or DLL), such as by selecting a frequency division ratio through a programmable counter, which is part of the IC design and manufacture, or can be programmed after manufacture, as well This is done by using calibration or control coefficients or signals or by switching frequency dividers into or out of frequency division chains.

FIG. 44 is a block diagram of a fifth exemplary system 1203 in accordance with the present invention. The fifth exemplary system 1203 includes the components previously described for the fourth system 1202, namely clock/frequency reference (100, 200, 300), control logic or saved coefficients (1215), one or more processors 1275, I /O interface (or other I/O device) 1285, and memory 1280. The fifth exemplary system 1203 also includes a plurality of locking circuits 1204 and frequency dividers (1000, 1010, 1074, 1218, 1219), such as phase locked loops or delay locked loops (or injection locked circuits) and synchronous or asynchronous frequency divisions, respectively to provide a corresponding plurality of second reference signals (clocks or other reference signals) having a corresponding plurality of second frequencies, including signals of any type or shape (single-ended, differential, square wave, sinusoidal, spread spectrum), Fig. Shown are a plurality of second reference signals with respective second frequencies f ₁ , f ₂ , f ₃ , f _K , . . . f _N . _A plurality of _second reference signal possibilities with corresponding frequencies f ₁ , f ₂ , f ₃ , f _K , . . . One or more second reference signals to one or more processors 1275 , I/O interface 1285 and memory 1280 .

Conversion circuit 1290 may be controlled by frequency selection and control logic circuit 1295 and/or control logic or registers (1215) holding coefficients (described above). For example, the control logic circuit 1295 may provide one or more control signals to the conversion circuit 1290, which in turn is adapted to convert selected second reference signals of the plurality of second reference signals to the processor in response to the one or more control signals. 1275 and other components. Similarly, one or more stored coefficients (such as stored in coefficient register 1215) can be used to control the switching of a selected second reference signal of a plurality of second reference signals to the processing channel by controlling the gate voltage of the switching or pass transistor 1275 and other components. Additionally, frequency selection and control logic 1295 may also be used to control multiple lock circuits 1204, such as by programming corresponding frequency division ratios. In an exemplary embodiment, switching circuit 1290 is implemented to provide substantially glitch-free switching, and may be implemented by any type of switching structure or matrix, such as by one or more multiplexers, pass transistors, crossbars, or other conversion or configurable circuits. Alternatively, conversion circuit 1290 may be omitted and multiple clock or reference signals of different frequency or phase relationships, types or shapes (e.g., single-ended, differential, square wave, sinusoidal, spread spectrum) provided directly to one or more processors 1275 , I/O interface 1285 and memory 1280 . Additionally, conversion circuit 1290 may be implemented with non-reconfigurable circuitry, such as with different fuses or other electrically programmable connections, ROM connections, or other one-time configurable connections. Numerous variations on the control of the selection of one or more of the plurality of second reference signals provided to the second processing circuit such as the processor 1275, the memory 1280, the I/O interface 1285 will be apparent to those skilled in the art, these Variations are considered equivalent and within the scope of the invention. For example, the fifth exemplary system 1203 may be used to provide a plurality of single-ended or differential and square wave or sinusoidal clock or reference signals having any selected frequency and/or phase relationship. Continuing with the example, first, a much higher frequency signal may be provided to one or more processors 1275, I/O interface 1285, and memory 1280 for high performance when sufficient power is available. Second, a much lower frequency signal may be provided to one or more processors 1275, I/O interface 1285, and memory 1280 for power saving capabilities when the power source is limited, such as to reduce power when the power source is a battery . Third, much lower frequency signals may be provided to one or more processors 1275, I/O interface 1285, and memory 1280 for more power savings such as for sleep or hibernation modes. In addition to determining the frequency by selecting the number and size of inductors and capacitors used in the LC oscillator of the clock/reference (100, 200, 300), frequency selection and control logic 1295 and/or control logic or saved coefficients ( 1215) can be programmed or calibrated to control the switching circuit 1290 to provide any of said corresponding clocks or other second reference signals having frequencies _fi , _f2 , ... _fN .

Four exemplary discrete device embodiments are shown in Figures 45-48. Similar to the other illustrated embodiments, these discrete device embodiments are also adapted to operate without locking to an external reference signal, such as not locking to any type of crystal (XTAL) reference. Furthermore, any of these discrete device embodiments may be provided as configurable or programmable, such as selectable frequencies and output pins for one or more second reference signals, or as non-configurable or non-programmable form, such as providing a predetermined or fixed frequency and an output pin for one or more second reference signals. For example, discrete device embodiments may be provided as "standard" ICs that provide one or more clock signals of predetermined frequencies, or may be provided as configurable ICs with user selection of output frequency, signal type, signal level, etc. As detailed below, the configuration and/or selection may occur as part of design and manufacture, such as by mask programming of reactance sizes, quantities, and interconnections, or post-fabrication, such as by configuring and selecting interconnects, Reactance conversion, frequency division ratio, etc. Furthermore, the configuration may be combined with the exemplary integrated embodiments described above.

Figure 45 is a block diagram of an exemplary first discrete device embodiment 3000, typically implemented as a discrete (ie, single) integrated circuit, in accordance with the present invention. As shown in Figure 45, the first discrete device 3000 includes a clock/frequency reference (100, 200, 300), one or more frequency dividers (1000, 1010, 1074, 1218, or 1219) operating as previously described , and/or one or more locking circuits 1204, and also includes one or more input/output (I/O) interface circuits 3010. Furthermore, as an option, the first discrete device 3000 may also include control logic and/or a detector ( 1215 ) storing coefficients and a user interface 3025 . Not separately shown, the first discrete device 3000 typically includes input devices for power and control signals, and may also include a voltage regulator.

As mentioned above, one or more locking circuits 1204 may be phase-locked loops or delay-locked loops (or injection locked circuits), one or more frequency dividers (1000, 1010, 1074, 1218, 1219) (including locking circuits 1204 Any divider in the ) can be synchronous or asynchronous, individual or differential divider. The locking circuit 1204 and/or the frequency dividers (1000, 1010, 1074, 1218, 1219) may also be implemented in a configurable or non-configurable type. In this exemplary first discrete device 3000, as well as other exemplary discrete embodiments described below, one or more frequency dividers (1000, 1010, 1074, 1218, or 1219) and/or one or more locking circuits 1204 A corresponding plurality of second reference signals (clocks or other reference signals), including any type or shape (single-ended, differential, square wave, sinusoidal, spread spectrum, etc.), having a corresponding plurality of second frequencies is provided, illustrated as having a corresponding A plurality of second reference signals of second frequencies f ₁ , f ₂ , . . . f _N . _A plurality of _second reference signals with corresponding frequencies f ₁ , f ₂ , . (Furthermore, depending on the number of frequency dividers and/or lock circuits that are "chained" in succession, as shown in Figures 45 and 48, where one or more second reference signals are present between successive circuits, the resulting output (from The last of the frequency dividers or locking circuits) may be referred to as a plurality of third reference signals with a corresponding plurality of third frequencies f ₁ , f ₂ , . . . _fN ).

Similar to I/O interface 1285, I/O interface 3010 may be implemented as known or to become known in the art to provide (output) slave clock/frequency references (100, 200, 300) and various frequency dividers (1000 , 1010, 1074, 1218, 1219) and the communication of the first and/or second reference signal of any of the locking circuit 1204 to any other device or structure (such as an off-chip device), such as but not limited to, other devices or Structures such as one or more IC input/output pins, or channels, buses, input and output devices, other circuits, other I/O pads, mechanisms and media described herein, the communication including wireless, optical or wired manner and use of any available standards, techniques or media. For example, when the first discrete device 3000 is used to provide a clock control IC for a computer or communication system, the I/O interface 3010 is adapted to communicate reference signals to (and possibly receive from) a circuit board (PCB) on a printed circuit board (PCB). One or more wires, one or more buses such as PCI bus, PCI express bus, universal serial bus (USB1 or USB2), or to one or more other ICs, such as when connected to another IC time. Additionally, I/O interface 3010 may provide an interface to any other device or structure previously described.

For the purposes of the present invention, while referred to as I/O interface 3010, I/O interface 3010 need only provide an output of a different first and/or second reference signal. Depending on selected embodiments, I/O interface 3010 may also be implemented to accept different types of inputs. Similarly, in exemplary embodiments using switchable or configurable connections (described below), I/O interface 3010 may be implemented for both output and input functions, with the input signals acting as I/O pins Part of the configuration is translated or transferred to other parts of the IC accordingly.

I/O interface 3010 is used to provide any and/or all signaling and physical interface functions, such as impedance matching. Signal transmission or other data output from the first discrete device 3000 to any other device, and any other communication function suitable for any chosen application. In an exemplary embodiment, I/O interface 3010 may be implemented as a configurable or programmable type, such as for selecting an output signal level (e.g., full voltage rail to full voltage rail, or partial voltage rail to partial voltage rail), Select the output signal type (such as single-ended or differential), and used to change or match the load to be driven. In other exemplary embodiments, the I/O interface 3010 may also be implemented as a non-configurable type, such as providing one or more second reference signals of a fixed or predetermined level, type, and load.

The configurability or programmability can also be used for other configurable or programmable components of the other illustrated discrete embodiments, and the configurability and/or programmability can be controlled by control circuitry or logic and/or by saving coefficients One or both of the register (1215) and user interface 3025 are provided and implemented as part of design and manufacture, or after manufacture by the manufacturer, distributor, or end user. (Implementation by control circuitry or logic and/or registers (1215) holding coefficients is illustrated using dashed lines in FIG. The selection, switching or routing circuitry is implemented as described in detail below in connection with the configurable switching or routing circuitry 3040 of FIGS. 46-48. For example, the configuration and/or programming may be implemented using switches, fuses, laser trimming, pass transistors, multiplexers, demultiplexers, FPGAs, other configurable logic, and the like. Different configurations or programs can be of a one-time configuration, such as when implemented through fuse links, mask programming, or static coefficients held in ROM; or can be of the reconfigurable type, such as by storing variable coefficients in a non-volatile Non-volatile memory such as FLASH or EPROM is used to control the corresponding switches or multiplexers.

Furthermore, configurability or programmability may be provided as part of the design and manufacture of different embodiments. For example, as described above, a different plurality of coefficients or control signals are determined post-manufacture for selecting the first frequency of the first reference signal by calibration to another reference frequency signal, such as an external frequency reference. The first frequency can also be controlled by selecting the size (and/or number) of reactances (inductors and/or capacitors), by selecting multiple connections and/or interconnections of multiple switchable controlled reactance modules Different reactances of different reactances or make it disconnected or select multiple sizes of switchable controlled reactance modules, mask programming by selecting the type of signal such as single-ended or differential. The first frequency may also be configured post-manufacture by selecting multiple connections or interconnections of multiple switchable controlled reactance modules and other interconnections of various components.

Other configurations are also mask programmable or can be configured or selected as part of the IC fabrication process. For example, any of the different connections and interconnections between components can be programmed in any conductive layer mask. For example, selection of the output location of the one or more second reference signals may occur at any point in the frequency division or locking chain and may be selected by correspondingly selecting interconnects provided in the conductive mask layer. Continuing with the example, for design and manufacturing configurability, the I/O interface 3010 can be configured by providing different interconnections (through a conductive layer mask) to selected ones of multiple drivers or amplifiers to provide Corresponding signal level, or by soldering to selected potential or floating potential. Furthermore, any of the different process parameters and dimensions may also be modified due to programmability and/or configurability, such as by any of the different etch, doping, ion implantation, deposition, layer thickness, conduction selection (such as metal to polysilicon), stressed or strained substrates such as the use of strained silicon, etc. Other methods and types of configurability and programmability will be apparent to those skilled in the art and are considered equivalents and within the scope of the present invention.

With continued reference to FIG. 45, spread spectrum functionality may also be implemented in accordance with the present invention. For example and without limitation, spread spectrum functionality may be implemented within a clock/frequency reference (100, 200, 300) to vary the first frequency of the first reference signal over time, or in a different frequency divider (1000, 1010 , 1074, 1218, 1219) or within any of the locking circuit 1204 to change any second frequency of the corresponding second reference signal over time. For example, control circuitry (control logic and/or registers holding coefficients (1215)) may be connected to a plurality of switchable controlled reactance modules and adapted to provide time-dependent switching of the plurality of switchable controlled reactance modules to modify the first frequency and provide a spread spectrum first reference signal having a plurality of different first frequencies over time. Also, for example, control circuitry (control logic and/or registers holding coefficients (1215)) may be connected to one or more latch circuits 1204, said control circuitry being adapted to provide a time-dependent variation of the division ratio to provide A spread spectrum second reference signal having a plurality of different second frequencies is varied over time. Continuing with the example, the different first and second frequency dividers (1206 and 1207) (of lock circuit 1204) or any other frequency dividing circuit (1000, 1010, 1074, 1218, 1219) may be implemented as counters, the The control circuit is adapted to modify an ultimate or threshold count based on which the counter provides an output signal to vary the one or more second reference signals to provide a spread spectrum second reference signal having a plurality of different second frequencies over time.

Different calibrations and configurations may be provided via user interface 3025 after manufacture. The user interface 3025 may be implemented to provide input to various types of control circuits (eg 3015, 1810) and/or coefficient registers (eg 455, 465, 495, 1215, 1950, 3020) to enter any selection or configuration. For example, the user interface 3025 may be connected to a test bench or other computer interface to automatically enter the selections and configurations, as known or to become known in the art, such as to interfaces for programming FPGAs, non-volatile memory, or other different types of workstations or other equipment with configurable logic.

FIG. 46 is a block diagram of an exemplary second discrete device 3030 in accordance with the present invention. FIG. 47 is a block diagram of an exemplary third discrete device 3050 in accordance with the present invention. FIG. 48 is a block diagram of an exemplary fourth discrete device 3070 in accordance with the present invention. The second discrete device 3030 is implemented using one or more frequency dividers (1000, 1010, 1074, 1218, 1219) such as configurable counters. The third discrete means 3050 is implemented using one or more locking circuits 1204 (with configurable divider ratios, typically also implemented with configurable counters for integrated first and second divider circuits). The fourth discrete means 3070 is implemented using one or more frequency dividers (1000, 1010, 1074, 1218, 1219) such as configurable counters and one or more locking circuits 1204 (also with configurable division ratios). Additionally, control circuitry 3015 and coefficient registers 3020 of control circuitry or logic and/or registers holding coefficients (1215) are shown separately.

Instead of providing different first reference signals and/or multiple second reference signals directly to corresponding I/O interfaces 3010 of the plurality of I/O interfaces 3010, for these exemplary second, third and fourth discrete devices In an embodiment, the first reference signal and the plurality of second reference signals are provided to a configurable switching (or routing) circuit 3040 . More specifically, one or more frequency dividers (1000, 1010, 1074, 1218, or 1219) and/or one or more locking circuits 1204 will have corresponding multiples of corresponding multiples of second (or third) frequencies A second (or third) reference signal (clock or other reference signal) is provided to the configurable switching (or routing) circuit 3040, said reference signal including any type or shape of signal (single-ended, differential, square wave, sinusoidal , spread spectrum) (illustrated as a plurality of second or third reference signals having respective second or third frequencies f ₁ , f ₂ , . . . f _N ), the first reference signal having a first frequency f ₀ . Thereafter, the configurable conversion (or routing) circuit 3040 selectively converts or transmits the first reference signal and the plurality of second reference signals to selected I/O interfaces 3010 of the plurality of I/O interfaces 3010 . The selective switching or routing may also be controlled by control circuit 3015 (of control circuit/coefficient register 1215 ) and/or coefficient register 3020 , and configured or programmed by user interface 3025 .

Configurable switching (or routing) circuitry 3040 may be implemented using any type of configurable, programmable, switching, or routing circuitry. For example, the configuration and/or programming may be implemented using multiplexers, demultiplexers, switches, fuses, laser trimming, pass transistors, FPGAs, or any other type of configurable logic or switches. The different configurations or programs may be one-time configurations providing direct routing of signals (direct interconnection), as when implemented by masked connections, fuse connections, or fixed coefficients held in ROM; or may be of the reconfigurable type, Such as by storing variable coefficients in non-volatile memory, by state machines implemented in control circuits and other types of control circuits for controlling corresponding switches or multiplexers. The selected switching or routing provided by the configurable switching (or routing) circuit 3040 may be programmed or configured as part of the fabrication process described above, such as through mask-programmable connections, or may be determined after fabrication, such as through control Circuitry or logic and/or registers (1215) to hold coefficients and user interface 3025.

For example, a generic, flexible and/or adaptive integrated circuit incorporating different exemplary embodiments may be designed (and fabricated) to support a wide range of first and second frequencies, as described above, such as through mask programmability. After manufacture, typically through the user interface 3025 or other mechanism previously described, the selected device (IC) can be calibrated to have a first reference signal at one or more first frequencies, as by determining the previously described (and saving Different coefficients in a coefficient register such as one of the previously described registers or coefficient register 3020). Furthermore, according to selected embodiments, the calibration may provide one or more control signals.

Continuing with the example, again through the user interface 3025, to provide a particular output frequency and signal type from a generic or flexible IC, any of the different second and/or third frequencies, along with their output location, level and type, can be selected. choose. Also after manufacture, the different configurations or programming described above can be implemented by using control signals (from control circuit 3015) or coefficients (such as conversion or control coefficients) (stored in coefficient registers 3020) and used to convert or send different first One and the second reference signal. In addition, through the user interface 3025, the manufacturer, distributor or end user can also configure the switching (or routing) circuit 3040 and other parameters previously described, such as different locking circuits 1204 or frequency dividers (1000, 1010, 1074, 1218, 1219) Different frequency division ratios or ultimate (limit) counts for frequency selection of one or more second (or third) reference signals, selected configuration of I/O interface 3010 (e.g. signal level, signal type ) and configurable switching (or routing) circuitry 3040 can switch or send any selected first or second reference signal with a corresponding selected (and configurable) frequency to any of the plurality of I/O interfaces 3010 /O interface. For example, this additional feature can be used to customize IC pin programming to provide one or more selected clock signals at selected IC pins.

In summary, the present invention provides an integrated circuit comprising an oscillator comprising an inductor and a capacitor, the oscillator being adapted to provide a first reference signal having a first frequency, the oscillator being further adapted to operate without locking to an external reference signal operating; also comprising: a voltage controller adapted to provide a plurality of voltage control signals; a plurality of switchable controlled reactive modules connected to the oscillator and the voltage controller, each reactive module of the plurality of reactive modules adapted to respond to A corresponding one of the plurality of voltage control signals provides a selected reactance to modify the first frequency; and an output circuit adapted to provide an interface for external signal communication.

Exemplary integrated circuits may also include a frequency divider circuit coupled to the oscillator, the frequency divider circuit being adapted to provide a second reference signal at a second frequency. A locking circuit is connectable to the frequency divider circuit and adapted to lock to the second reference signal and provide a third reference signal having a third frequency determined from the second frequency and the division ratio of the locking circuit. Furthermore, a control circuit may be connected to the locking circuit, the control circuit being adapted to provide a time-varying frequency division ratio to provide a spread-spectrum third reference signal having a plurality of different third frequencies as a function of time. Alternatively, a control circuit may be connected to a plurality of switchable controlled reactive modules, the control circuit being adapted to provide time-dependent switching of the plurality of switchable controlled reactive modules, thereby providing a time-varying function with a plurality of different first frequency of the spread spectrum first reference signal.

The output circuit is configurable to select a signal type of a plurality of signal types of the second reference signal, the plurality of signal types including at least one of the following signal types: differential, single-ended, full voltage rail to full voltage rail, or partial Voltage rail to part voltage rail.

An exemplary integrated circuit may also include a plurality of locking circuits coupled to the frequency divider circuit, the plurality of locking circuits being adapted to lock to the second reference signal and provide a corresponding plurality of third reference signals having a plurality of corresponding third frequencies, the plurality of Each of the corresponding third frequencies is determined from the second frequency and the division ratio of a corresponding lock circuit of the plurality of lock circuits. Each locking circuit of the plurality of locking circuits may be one of the following locking circuits: a phase locked loop, a delay locked loop, or an injection locked circuit. Furthermore, each of the plurality of lock circuits is configurable in selecting a frequency division ratio.

An exemplary integrated circuit may further include a plurality of output circuits adapted to provide a corresponding plurality of output interfaces for signal communication; and a first conversion circuit connected to the plurality of lock circuits and the plurality of output circuits, the first conversion circuit being adapted to for selectively switching a selected third reference signal of the plurality of third reference signals to a selected output circuit of the plurality of output circuits. The control circuit is connectable to the plurality of output circuits and is adapted to provide a control signal to selected ones of the plurality of output circuits to select a signal type of the plurality of signal types of the corresponding third reference signal. A control circuit is connectable to the first conversion circuit and adapted to provide a control signal to the first conversion circuit to convert the selected third reference signal to the selected output circuit.

Similarly, a coefficient register is connectable to the first conversion circuit and adapted to provide a first control coefficient of the first plurality of control coefficients to the first conversion circuit for converting the selected third reference signal to the selected output circuit. The coefficient register may also be connected to a plurality of switchable controlled reactive modules, the coefficient register being adapted to hold a second plurality of coefficients and to provide a corresponding coefficient of the second plurality of coefficients to control the conversion of the respective controlled reactive module to the oscillator. The second plurality of coefficients may be determined after manufacture by calibration to an external signal providing a reference frequency. Exemplary integrated circuits may further include a user interface coupled to the coefficient register, adapted to provide coefficients of the first plurality of coefficients or the second plurality of coefficients to the coefficient register in response to user input.

For example, the first conversion circuit may include multiplexers and demultiplexers, or multiple pass transistors or crossbars.

The first frequency is mask programmable by selecting the size of the inductor, or by selecting multiple connections of multiple switchable controlled reactive modules, or by selecting multiple sizes of multiple switchable controlled reactive modules. The first frequency is configurable post-manufacture by selecting a plurality of connections of a plurality of switchable controlled reactance modules.

Another exemplary integrated circuit embodiment may include: a harmonic oscillator including an inductor and a capacitor adapted to provide a first reference signal having a first frequency; a plurality of controlled a reactance module, each of the plurality of reactance modules adapted to provide a selected reactance to modify the first frequency in response to a control voltage of the plurality of control voltages; a first coefficient register adapted to hold a first plurality of conversion coefficients; a first plurality of switches connected to a plurality of controlled reactance modules, each switch of the first plurality of switches being responsive to a corresponding conversion factor of the first plurality of conversion factors to connect a selected one of the plurality of control voltages to to a corresponding controlled reactance module; a first frequency divider connected to the harmonic oscillator, the first frequency divider being adapted to provide a second reference signal of a second frequency; and a plurality of locking circuits connected to the first frequency divider , the plurality of locking circuits are adapted to lock to the second reference signal and provide a corresponding plurality of third reference signals having a plurality of corresponding third frequencies, each third frequency of the plurality of corresponding third frequencies derived from the second frequency and the plurality of The frequency division ratio of the corresponding locking circuit in each locking circuit is determined. The harmonic oscillator can also be adapted to run without locking to an external reference signal.

Also, in summary, another exemplary configurable integrated circuit embodiment may include an oscillator comprising an inductor, a capacitor, and a transconductance amplifier, the oscillator being adapted to provide a first reference signal having a first frequency, the oscillator being further adapted to To operate without locking to an external reference signal, the transconductance amplifier also includes a variable current source adapted to provide a corresponding current in response to operating temperature; a voltage controller adapted to provide multiple voltage control signals; connected to the oscillator and a plurality of switchable controlled reactance modules of a voltage controller, each reactance module of the plurality of reactance modules adapted to provide a selected reactance to modify the first frequency in response to a corresponding one of the plurality of voltage control signals; connected to a first frequency divider of the oscillator, the first frequency divider being adapted to provide a second reference signal of a second frequency; and a plurality of configurable locking circuits connected to the first frequency divider, the plurality of locking circuits being adapted to lock to second reference signal and providing a corresponding plurality of third reference signals having a plurality of corresponding third frequencies, each of the plurality of corresponding third frequencies derived from the second frequency and a corresponding locking circuit of the plurality of locking circuits Configurable divider ratio determination.

Also in summary, the present invention provides an integrated circuit comprising: a resonator comprising an inductor and a capacitor, the resonator being adapted to provide a first reference signal having a first frequency; a voltage controller adapted to provide a plurality of voltage control signals; connected to a plurality of switchable controlled reactance modules of the resonator and voltage controller, each reactance module of the plurality of reactance modules adapted to provide a selected reactance to modify the first frequency in response to a corresponding one of the plurality of voltage control signals ; and a processor connected to the resonator. The IC may also include a locking circuit coupled to the resonator, the locking circuit being adapted to lock to the first reference signal and provide a second reference signal having a second frequency, wherein the second frequency is a rational multiple of the first frequency; and wherein the processor connected to the resonator through a locking circuit and adapted to receive a second reference signal.

For example, the first or second reference signal may be a square wave clock signal. A processor may be any type of circuitry suitable for performing a function, such as any of the following types of processors: microprocessors, digital signal processors, controllers, microcontrollers, universal serial bus (USB) controllers, peripheral components PCI Interconnect (PCI) Controller, Peripheral Component Interconnect Express (PCI-e) Controller, FireWire Controller, AT Attachment (ATA) Interface Controller, Integrated Drive Electronics (IDE) Controller, Small Computer System Interface (SCSI) ) controller, TV controller, local area network (LAN) controller, Ethernet controller, video controller, audio controller, modem processor, MPEG controller, multimedia controller, communication controller, mobile communication controller, IEEE 802.11 controller, GSM controller, GPRS controller, PCS controller, AMPS controller, CDMA controller, WCDMA controller, spread spectrum controller, wireless LAN controller, IEEE 802.11 controller, DSL controller, T1 controller , ISDN controller, or cable modem controller. The integrated circuit may also include: a memory connected to the processor and further connected to the locking circuit to receive the second reference signal; and an input/output interface connected to the processor and further connected to the locking circuit to receive the second reference signal. The locking circuit may be one of the following locking circuits: a phase locked loop, a delay locked loop, or an injection locked circuit.

In other exemplary embodiments, the integrated circuit further includes a plurality of locking circuits coupled to the resonator, the plurality of locking circuits being adapted to lock to the first reference signal and provide a corresponding plurality of second reference signals having a plurality of corresponding frequencies; and may further include switching circuitry connected to the plurality of locking circuits and the processor, the switching circuitry being adapted to selectively connect the processor by switching selected second reference signals of the corresponding plurality of second reference signals to the processor. to multiple lockout circuits. The integrated circuit may further comprise: a control circuit connected to the conversion circuit, the control circuit being adapted to provide a control signal to the conversion circuit to convert the selected second reference signal to the processor; and/or a coefficient register connected to the conversion circuit, the coefficient register Adapted to provide control coefficients to the conversion circuit for converting the selected second reference signal to the processor. Each of the plurality of locking circuits may also include a plurality of asynchronous or synchronous frequency divider circuits, and a plurality of corresponding frequencies are determined by respective frequency division ratios of the plurality of frequency divider circuits. The integrated circuit may also include a spread spectrum generator connected to the resonator or the locking circuit, the spread spectrum generator being adapted to provide a time-varying adjustment of the first reference signal or the second reference signal.

In other exemplary embodiments, an integrated circuit may include: a harmonic oscillator including an inductor and a capacitor adapted to provide a first reference signal having a first frequency; a harmonic oscillator adapted to generate a plurality of voltage control signals a plurality of resistive modules; a plurality of controlled reactive modules connected to the harmonic oscillator and the plurality of resistive modules, each reactive module of the plurality of reactive modules being adapted to provide a selected reactance to modify a first frequency; a first coefficient register connected to a plurality of switches, the first coefficient register being adapted to hold a first plurality of conversion coefficients; a first coefficient register connected to a plurality of resistance blocks and a plurality of controlled reactance blocks a plurality of switches, each switch of the first plurality of switches responsive to a respective conversion factor of the first plurality of conversion factors to connect a selected one of the plurality of control voltages to a corresponding controlled reactance module; operatively connected to a locking circuit for the harmonic oscillator, the locking circuit being adapted to lock to the first reference signal and provide a second reference signal having a second frequency; and a processor operatively connected to the locking circuit to receive the second reference signal.

The integrated circuit may also include: a plurality of locking circuits operatively connected to the harmonic oscillator, the plurality of locking circuits being adapted to lock to the first reference signal and provide a corresponding plurality of second reference signals having a plurality of corresponding frequencies; and A second plurality of switches connected to the plurality of latch circuits and the processor, the second plurality of switches adapted to switch selected ones of the corresponding plurality of second reference signals to the processor. Additionally, a control circuit may be connected to the second plurality of switches, the control circuit being adapted to provide control signals to the second plurality of switches to switch the selected second reference signal to the processor. Alternatively, a second coefficient register may be connected to the second plurality of switches, the second coefficient register being adapted to provide control coefficients to the second plurality of switches for converting the selected second reference signal to the processor.

In other exemplary embodiments, an integrated circuit includes: a resonator including an inductor and a capacitor adapted to provide a first reference signal having a first frequency; adapted to provide a second signal in response to operating temperature or manufacturing process variations a sensor; a voltage controller adapted to provide a plurality of voltage control signals; a plurality of switchable controlled reactive modules connected to the resonator and the voltage controller, each of the plurality of reactive modules being adapted to respond to a plurality of A corresponding one of the voltage control signals provides a selected reactance to modify the first frequency; a plurality of locking circuits operatively connected to the resonator, the plurality of locking circuits being adapted to lock to the first reference signal and providing a plurality of corresponding frequencies A corresponding plurality of second reference signals; a processor adapted to receive a selected second reference signal of the plurality of second reference signals; and a switching circuit connected to the plurality of locking circuits and the processor, the switching circuit being adapted to convert the selected Select the second reference signal to switch to the processor.

Also, in general, the present invention provides an apparatus comprising: a resonator adapted to provide a first signal having a resonant frequency; an amplifier connected to the resonator; and an amplifier adapted to select a first signal having a plurality of frequencies. The frequency controller (connected to the resonator) for the resonant frequency of the frequency. The apparatus also includes a frequency divider (connected to the resonator) adapted to divide a first signal having a first frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or Lower than the first frequency, such as dividing by a rational number to achieve frequency division.

The first signal may be a differential signal or a single-ended signal. When the first signal is a differential signal, the frequency divider is also adapted to convert the differential signal into a single-ended signal. Similarly, when the first signal is a substantially sinusoidal signal, the frequency divider is also adapted to convert the substantially sinusoidal signal into a substantially square wave signal.

In a different embodiment, a frequency divider may comprise a plurality of flip-flops or counters connected in series in succession, where the output of a selected flip-flop or counter is the frequency of the previous flip-flop or counter divided by 2, or more generally, A plurality of frequency dividers are connected in series one after the other, wherein the output of a successive frequency divider is of lower frequency than the output of the previous frequency divider. Multiple dividers can be differential, single-ended, or a combination of differential and single-ended, such as differential followed by a final single-ended segment. The frequency divider may also include a square wave generator adapted to convert the first signal into a substantially square wave signal having substantially equal high and low duty cycles.

The invention may also comprise a frequency selector connected to the frequency divider, adapted to provide an output signal from the plurality of second signals. Frequency selectors may also include multiplexers and glitch suppressors.

The present invention may further comprise a mode selector connected to the frequency selector, wherein the mode selector is adapted to provide a plurality of operating modes selectable from the group consisting of clock mode, timing and frequency reference mode, power saving mode, And by pulse action mode.

For the reference mode, the present invention may also include a synchronization circuit connected to the mode selector; and a controlled oscillator connected to the synchronization circuit and adapted to provide a third signal; wherein in the timing and reference modes, the mode selector is also adapted to Connect the output signal to a synchronization circuit to control the timing and frequency of the third signal. The synchronization circuit may be a delay locked loop, a phase locked loop, or an injection locked circuit.

In selected embodiments, the amplifier may be a negative transconductance amplifier. The frequency controller is also adapted to modify current through the negative transconductance amplifier in response to temperature, which may include a current source responsive to temperature. The current source may have one or more configurations selected from a variety of configurations, such as configurations including CTAT, PTAT, and PTAT ² configurations. Additionally, the frequency controller is adapted to modify the current through the negative transconductance amplifier to select a resonant frequency, modify the transconductance of the negative transconductance amplifier to select a resonant frequency, or modify the current through the negative transconductance amplifier in response to a voltage. The frequency controller may also include a voltage isolator coupled to the resonator and adapted to substantially isolate the resonator from voltage variations, and may include a current mirror, which may also include a cascode structure. The frequency controller is also adapted to modify the capacitance or inductance of the resonator in response to manufacturing process changes, temperature changes or voltage changes.

The frequency controller may have different embodiments of these different functions, and may also include: a coefficient register adapted to hold a first plurality of coefficients; and a first array having a plurality of switchable capacitance modules connected to the coefficient register and the resonator , each switchable capacitance module has a fixed capacitance and a variable capacitance, each switchable capacitance module is responsive to a corresponding coefficient of the first plurality of coefficients to switch between the fixed capacitance and the variable capacitance and convert each variable capacitance converted to the control voltage. The plurality of switchable capacitive modules may be binary weighted modules, or have another weighting scheme. The frequency controller may also include a second array having a plurality of switchable resistive blocks connected to the coefficient register and also having a second array of capacitive blocks, the capacitive block and the plurality of switchable resistive blocks also connected to a node to provide a control voltage, each switchable a switching resistance module switching the switchable resistance module to a control voltage node in response to a corresponding coefficient of the second plurality of coefficients held in the coefficient register; and a temperature dependent current source connected to the second array through a current mirror.

The frequency controller may also include a process variation compensator coupled to the resonator and adapted to modify the resonant frequency in response to manufacturing process variations. In an exemplary embodiment, a process variation compensator may include: a coefficient register adapted to hold a plurality of coefficients; and an array having a plurality of switchable capacitance modules connected to the coefficient register and the resonator, each switchable capacitance module having A first fixed capacitance and a second fixed capacitance, each switchable capacitance module switching between the first fixed capacitance and the second fixed capacitance in response to a corresponding coefficient of the plurality of coefficients. The plurality of switchable capacitive modules may be binary weighted modules, or have another weighting scheme.

In another exemplary embodiment, a process variation compensator may include: a coefficient register adapted to hold a plurality of coefficients; and an array having a plurality of switchable variable capacitance modules connected to the coefficient register and the resonator, each capable of The switching variable capacitance module switches between the first voltage and the second voltage in response to a corresponding coefficient of the plurality of coefficients. The plurality of switchable variable capacitance modules may also be binary weighted modules, or have another weighting scheme.

The invention may also include a frequency calibration module connected to the frequency controller and adapted to modify the resonant frequency in response to the reference signal. For example, the frequency calibration module may comprise a frequency divider connected to the frequency controller, the frequency divider being adapted to convert an output signal derived from a first signal having a first frequency to a lower frequency to provide a frequency divided signal; Also comprising a frequency detector connected to the frequency divider, the frequency detector being adapted to compare the reference signal and the frequency-divided signal and providing one or more rising or falling signals; and a pulse counter connected to the frequency detector, the pulse counter It is adapted to determine the difference between the one or more rising or falling signals as an indication of the difference between the output signal and the reference signal.

A resonator for use with the present invention may comprise an inductor (L) and a capacitor (C) connected to form an LC tank, having a selected one of a variety of LC tank configurations, such as series, parallel, etc., and may Includes other components. In other embodiments, the resonator may be selected from the group consisting of ceramic resonators, mechanical resonators, micro-electromechanical resonators, and thin-film bulk acoustic resonators, or the electrical equivalent of an inductor (L) connected to a capacitor (C ) of any other resonator.

For example, a resonator typically includes one or more inductors and capacitors, forming one or more LC tanks or LC resonators. In a first embodiment, a double balanced differential LC resonator layout is used. In other exemplary embodiments, differential or single-ended LC oscillator topologies may be used, such as a single-ended Corpis LC oscillator, a single-ended Hartley LC oscillator, a differential Corpis LC oscillator (common base and common set version), differential Hartley LC oscillators (common base and common set versions), single-ended Pierce LC oscillators, quadrature oscillators (such as formed by at least two double-balanced, differential LC oscillators), or active Inductor LC oscillator (which can be implemented as either a differential or single-ended LC oscillator). Alternative LC oscillator arrangements, whether now known or soon to be known, are considered equivalent arrangements and are within the scope of the present invention.

The inventive device can be used as a timing and frequency reference or as a clock generator. In addition, the present invention may also include a second oscillator (such as a ring, relaxation, or phase-shift oscillator) providing the output signal of the second oscillator; and a mode selector connected to the frequency controller and the second oscillator, the mode selection The oscillator is adapted to switch to a second oscillator output signal to provide a power saving mode. Additional modes of operation may be provided by a mode selector connected to the frequency controller, which may be adapted to periodically start and stop the resonator to provide a pulsed output signal, or to selectively start and stop the resonator to provide power savings model.

In another selected embodiment, the inventive device comprises: a resonator adapted to provide a first signal having a resonant frequency; an amplifier connected to the resonator; a temperature compensator connected to the amplifier and the resonator, the temperature compensator being adapted to to modify the resonant frequency in response to temperature; a process variation compensator connected to the resonator, the process variation compensator being adapted to modify the resonant frequency in response to temperature; a frequency divider connected to the resonator, the frequency divider being adapted to convert a The first signal is divided into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonance frequency; and a frequency selector connected to the frequency divider, the frequency selector being adapted to select from the plurality of second Signal provides an output signal.

In another selected embodiment, the inventive apparatus generates a clock signal and includes: an LC resonator adapted to provide a differential, substantially sinusoidal first signal having a resonant frequency; a negative transconductance amplifier connected to the LC resonator a temperature compensator connected to the negative transconductance amplifier and the LC resonator, the temperature compensator being adapted to modify the current in the negative transconductance amplifier in response to the temperature and also modifying the capacitance of the LC resonator in response to the temperature; connected to the LC resonator a process variation compensator adapted to modify the capacitance of the LC resonator in response to manufacturing process variations; a frequency divider connected to the resonator adapted to convert and divide a first signal having a resonant frequency into a plurality of single-ended, substantially square-wave second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency, and each second signal having substantially equal high and low duty cycles; and a frequency selector connected to the frequency divider, the frequency selector being adapted to provide an output signal from a plurality of second signals.

From the foregoing it can be seen that numerous changes and modifications can be made without departing from the spirit and scope of the novel concept of the present invention. It should be understood that there is no intention to be limited to the particular methods and apparatus shown herein, but that the appended claims cover all such modifications as fall within the scope of the invention.

Claims (51)

1. integrated circuit comprises:

The oscillator that comprises inductor and capacitor, oscillator are suitable for providing first reference signal with first frequency, and oscillator also is suitable for moving being not locked under the situation of external reference signal;

Be suitable for providing the voltage controller of a plurality of voltage control signals;

Be connected to a plurality of convertible controlled reactance modules of oscillator and voltage controller, thereby each reactance module in a plurality of reactance module is suitable for providing selected reactance to revise first frequency in response to the relevant voltage control signal in a plurality of voltage control signals; And

Be suitable for being provided for the output circuit of the output interface of signal communication.

2. according to the integrated circuit of claim 1, also comprise:

Be connected to the control circuit of a plurality of convertible controlled reactance modules, control circuit is suitable for providing the time-varying conversion of a plurality of convertible controlled reactance modules to have spread-spectrum first reference signal of a plurality of different first frequencies to provide to change in time.

3. according to the integrated circuit of claim 1, also comprise:

Be connected to the divider circuit of oscillator, divider circuit is suitable for providing second reference signal of second frequency.

4. according to the integrated circuit of claim 3, also comprise:

Be connected to divider circuit and be suitable for locking onto second reference signal and the lock-in circuit of the 3rd reference signal with the 3rd frequency is provided, the 3rd frequency is determined from the frequency dividing ratio of second frequency and lock-in circuit.

5. according to the integrated circuit of claim 4, also comprise:

Be connected to the control circuit of lock-in circuit, described control circuit is suitable for providing time-varying frequency dividing ratio to change spread-spectrum the 3rd reference signal with a plurality of different the 3rd frequencies in time to provide.

6. according to the integrated circuit of claim 3, wherein configurable aspect the signal type of output circuit in selecting a plurality of signal types of second reference signal, a plurality of signal types comprise at least one in the following signal type: difference, single-ended, full voltage main line arrive the part voltage rail to full voltage main line or part voltage rail.

7. according to the integrated circuit of claim 3, also comprise:

Be connected to a plurality of lock-in circuits of divider circuit, a plurality of lock-in circuits are suitable for locking onto second reference signal and corresponding a plurality of the 3rd reference signals with a plurality of corresponding the 3rd frequencies are provided, and the frequency dividing ratio of the corresponding lock-in circuit of each the 3rd frequency from second frequency and a plurality of lock-in circuit in a plurality of corresponding the 3rd frequencies is determined.

8. according to the integrated circuit of claim 7, each lock-in circuit in wherein a plurality of lock-in circuits can be one of following lock-in circuit: phase-locked loop, delay lock loop or injection locking circuit.

9. according to the integrated circuit of claim 7, each lock-in circuit in wherein a plurality of lock-in circuits is configurable aspect the selection frequency dividing ratio.

10. according to the integrated circuit of claim 7, also comprise:

Be suitable for being provided for a plurality of output circuits of corresponding a plurality of output interfaces of signal communication; And

Be connected to first change-over circuit of a plurality of lock-in circuits and a plurality of output circuits, first change-over circuit is suitable for selectively selected the 3rd reference signal in a plurality of the 3rd reference signals being transformed into the selected output circuit in a plurality of output circuits.

11. the integrated circuit according to claim 10 also comprises:

Be connected to the control circuit of a plurality of output circuits, thereby control circuit is suitable for that control signal is offered selected output circuit in a plurality of output circuits selects signal type in a plurality of signal types of corresponding the 3rd reference signal, and a plurality of signal types comprise at least one in the following signal type: difference, single-ended, full voltage main line to full voltage main line or part voltage rail to the part voltage rail.

12. the integrated circuit according to claim 10 also comprises:

Be connected to the control circuit of first change-over circuit, described control circuit is suitable for control signal is offered first change-over circuit so that selected the 3rd reference signal is transformed into selected output circuit.

13. the integrated circuit according to claim 10 also comprises:

Be connected to the coefficient register of first change-over circuit, coefficient register is suitable for first control coefrficient in more than first control coefrficient is offered first change-over circuit so that selected the 3rd reference signal is transformed into selected output circuit.

14. integrated circuit according to claim 13, wherein coefficient register is also connected to a plurality of convertible controlled reactance modules, and coefficient register is suitable for preserving more than second coefficient and provides more than second corresponding coefficient in the coefficient to be transformed into oscillator to control corresponding controlled reactance modules.

15. according to the integrated circuit of claim 14, wherein a plurality of convertible controlled reactance modules also comprise:

Be connected to more than second switch of coefficient register; And

Be connected to a plurality of variable capacitors of more than second switch and voltage controller accordingly, a plurality of variable capacitors are suitable for providing selected electric capacity in response to corresponding control voltage.

16. according to the integrated circuit of claim 15, wherein a plurality of convertible controlled reactance modules also comprise:

Be connected to a plurality of fixed capacitors of more than second switch accordingly, a plurality of fixed capacitors are suitable for providing selected electric capacity in response to corresponding coefficient.

17. according to the integrated circuit of claim 14, wherein more than second coefficient provides the external signal of reference frequency to determine by being calibrated to after manufacturing.

18. the integrated circuit according to claim 14 also comprises:

Be connected to the user interface of coefficient register, described user interface is suitable in response to user input the coefficient in more than first coefficient or more than second coefficient being offered coefficient register.

19. according to the integrated circuit of claim 10, wherein first change-over circuit comprises a plurality of multiplexers and demultiplexer, or a plurality of transmission transistor or cross bar switch.

20. integrated circuit according to claim 1, but wherein first frequency mask programming, its size by selecting inductor or a plurality of connections by selecting a plurality of convertible controlled reactance modules or undertaken by a plurality of sizes of selecting a plurality of convertible controlled reactance modules.

21. according to the integrated circuit of claim 1, wherein first frequency can dispose after manufacturing by a plurality of connections of selecting a plurality of convertible controlled reactance modules.

22. according to the integrated circuit of claim 1, wherein oscillator has at least one structure in the following structure: two balanced differential LC structures, difference n-MOS interconnection layout, difference p-MOS interconnection layout, the single-ended Bi Zi of examining LC structure, single-ended Hartley LC structure, difference cobasis are examined Bi Zi LC structure, difference and are collected altogether and examine Bi Zi LC structure, difference cobasis Hartley LC structure, difference and collect Hartley LC structure, single-ended Pierre Si LC oscillator or quadrature LC oscillator structure altogether.

23. according to the integrated circuit of claim 1, wherein oscillator also comprises the trsanscondutance amplifier with variable current source, variable current source is suitable for providing corresponding electric current in response to environment or operating temperature.

24. integrated circuit comprises:

The harmonic oscillator that comprises inductor and capacitor, harmonic oscillator are suitable for providing first reference signal with first frequency;

Be connected to a plurality of controlled reactance modules of harmonic oscillator, each reactance module in a plurality of reactance module is suitable for providing selected reactance to revise first frequency in response to the control voltage in a plurality of control voltages;

Be suitable for preserving first coefficient register of more than first conversion coefficient;

Be connected to more than first switch of a plurality of controlled reactance modules, the corresponding conversion coefficient of each switching response in more than first conversion coefficient in more than first switch is connected to corresponding controlled reactance modules with the selected control voltage in a plurality of control voltages;

Be connected to first frequency divider of harmonic oscillator, first frequency divider is suitable for providing second reference signal of second frequency; And

Be connected to a plurality of lock-in circuits of first frequency divider, a plurality of lock-in circuits are suitable for locking onto second reference signal and corresponding a plurality of the 3rd reference signals with a plurality of corresponding the 3rd frequencies are provided, and the frequency dividing ratio of the corresponding lock-in circuit of each the 3rd frequency from second frequency and a plurality of lock-in circuit in a plurality of corresponding the 3rd frequencies is determined.

25. according to the integrated circuit of claim 24, wherein harmonic oscillator also is suitable for moving being not locked under the situation of external reference signal.

26. the integrated circuit according to claim 24 also comprises:

Be connected to the control circuit of a plurality of lock-in circuits, control circuit is suitable for providing the time-varying frequency dividing ratio of first lock-in circuit in a plurality of lock-in circuits to change spread-spectrum the 3rd reference signal with a plurality of different the 3rd frequencies in time to provide.

27. the integrated circuit according to claim 24 also comprises:

Be connected to the control circuit of a plurality of controlled reactance modules, control circuit is suitable for providing the time-varying conversion of a plurality of control voltages to have spread-spectrum first reference signal of a plurality of different first frequencies to provide to change in time.

28. the integrated circuit according to claim 24 also comprises:

Be connected to more than second switch of a plurality of controlled reactance modules, each switching response in more than second switch is connected to harmonic oscillator in control signal with selected controlled reactance modules.

29. the integrated circuit according to claim 28 also comprises:

Be connected to the control circuit of more than second switch, control circuit is suitable for providing a plurality of controlled reactance modules to have spread-spectrum first reference signal of a plurality of different first frequencies to the time-varying conversion of harmonic oscillator to provide to change in time.

30. integrated circuit according to claim 24, wherein configurable aspect the signal type of divider circuit in selecting a plurality of signal types of second reference signal, a plurality of signal types comprise at least one in the following signal type: difference, single-ended, full voltage main line arrive the part voltage rail to full voltage main line or part voltage rail.

31. according to the integrated circuit of claim 24, each lock-in circuit in wherein a plurality of lock-in circuits is at least one in the following lock-in circuit: phase-locked loop, delay lock loop or injection locking circuit.

32. according to the integrated circuit of claim 24, each lock-in circuit in wherein a plurality of lock-in circuits is configurable aspect the selection frequency dividing ratio.

33. the integrated circuit according to claim 24 also comprises:

A plurality of output circuits; And

Be connected to second change-over circuit of a plurality of lock-in circuits and a plurality of output circuits, second change-over circuit is suitable for selected the 3rd reference signal in a plurality of the 3rd reference signals is transformed into selected output circuit in a plurality of output circuits selectively.

34. it is, configurable aspect the signal level of each output circuit in wherein a plurality of output circuits in a plurality of signal levels of the output of corresponding the 3rd reference signal of selecting to be used for a plurality of the 3rd reference signals according to the integrated circuit of claim 33.

35. the integrated circuit according to claim 33 also comprises:

Be connected to the control circuit of second change-over circuit, described control circuit is suitable for control signal is offered second change-over circuit so that selected the 3rd reference signal is transformed into selected output circuit.

36. the integrated circuit according to claim 33 also comprises:

Be connected to second coefficient register of second change-over circuit, second coefficient register is suitable for the control coefrficient in more than second control coefrficient is offered second change-over circuit so that selected the 3rd reference signal is transformed into selected output circuit.

37. according to the integrated circuit of claim 33, wherein second change-over circuit comprises a plurality of multiplexers and demultiplexer or a plurality of transmission transistor or cross bar switch.

38. according to the integrated circuit of claim 24, wherein a plurality of convertible controlled reactance modules also comprise:

Be connected to more than second switch of first coefficient register; And

Be connected to a plurality of variable capacitors of more than second switch and voltage controller accordingly, a plurality of variable capacitors are suitable for providing selected electric capacity in response to corresponding control voltage.

39. according to the integrated circuit of claim 38, wherein a plurality of convertible controlled reactance modules also comprise:

Be connected to a plurality of fixed capacitors of more than second switch accordingly, a plurality of fixed capacitors are suitable for providing selected electric capacity in response to corresponding coefficient.

40. according to the integrated circuit of claim 36, wherein more than second coefficient determined by being calibrated to second reference frequency signal after manufacturing.

41. the integrated circuit according to claim 36 also comprises:

Be connected to the user interface of first and second coefficient registers, described user interface is suitable in response to user input the coefficient in more than first conversion coefficient or more than second control coefrficient being offered coefficient register.

42. integrated circuit according to claim 24, but wherein first frequency mask programming, its size by selecting inductor or a plurality of connections by selecting a plurality of convertible controlled reactance modules or undertaken by a plurality of sizes of selecting a plurality of convertible controlled reactance modules.

43. according to the integrated circuit of claim 24, wherein first frequency can dispose after manufacturing by a plurality of connections of selecting a plurality of convertible controlled reactance modules.

44. according to the integrated circuit of claim 24, wherein oscillator has at least one structure in the following structure: two balanced differential LC structures, difference n-MOS interconnection layout, difference p-MOS interconnection layout, the single-ended Bi Zi of examining LC structure, single-ended Hartley LC structure, difference cobasis are examined Bi Zi LC structure, difference and are collected altogether and examine Bi Zi LC structure, difference cobasis Hartley LC structure, difference and collect Hartley LC structure, single-ended Pierre Si LC oscillator or quadrature LC oscillator structure altogether.

45. according to the integrated circuit of claim 1, wherein oscillator also comprises the trsanscondutance amplifier with variable current source, variable current source is suitable for providing corresponding electric current in response to environment or operating temperature.

46. according to the integrated circuit of claim 45, wherein variable current source has following at least one structure: in contrast to absolute temperature CTAT structure, be proportional to absolute temperature PTAT structure or be proportional to square PTAT of absolute temperature ²Structure.

47. configurable integrated circuit comprises:

The oscillator that comprises inductor, capacitor and trsanscondutance amplifier, oscillator is suitable for providing first reference signal with first frequency, oscillator also is suitable for moving being not locked under the situation of external reference signal, and trsanscondutance amplifier also comprises the variable current source that is suitable for providing in response to operating temperature corresponding electric current;

Be suitable for providing the voltage controller of a plurality of voltage control signals;

Be connected to a plurality of convertible controlled reactance modules of oscillator and voltage controller, each reactance module in a plurality of reactance module is suitable for providing selected reactance to revise first frequency in response to the relevant voltage control signal in a plurality of voltage control signals;

Be connected to first frequency divider of oscillator, first frequency divider is suitable for providing second reference signal of second frequency; And

Be connected to a plurality of configurable lock-in circuit of first frequency divider, a plurality of lock-in circuits are suitable for locking onto second reference signal and corresponding a plurality of the 3rd reference signals with a plurality of corresponding the 3rd frequencies are provided, and the configurable frequency dividing ratio of the corresponding lock-in circuit of each the 3rd frequency from second frequency and a plurality of lock-in circuit in a plurality of corresponding the 3rd frequencies is determined.

48. the configurable integrated circuit according to claim 47 also comprises:

Be connected to the control circuit of a plurality of configurable lock-in circuits, control circuit is suitable in time and the configurable frequency dividing ratio that becomes the selected configurable lock-in circuit of configuration changes spread-spectrum the 3rd reference signal with a plurality of different the 3rd frequencies to provide in time.

49. the configurable integrated circuit according to claim 47 also comprises:

A plurality of output circuits; And

Be connected to first change-over circuit of a plurality of lock-in circuits and a plurality of output circuits, first change-over circuit is suitable for selected the 3rd reference signal in a plurality of the 3rd reference signals is transformed into selected output circuit in a plurality of input and output circuit selectively.

50. according to the configurable integrated circuit of claim 47, wherein resonator has at least one structure in the following structure: two balanced differential LC structures, difference n-MOS interconnection layout, difference p-MOS interconnection layout, the single-ended Bi Zi of examining LC structure, single-ended Hartley LC structure, difference cobasis are examined Bi Zi LC structure, difference and are collected altogether and examine Bi Zi LC structure, difference cobasis Hartley LC structure, difference and collect Hartley LC structure, single-ended Pierre Si LC oscillator or quadrature LC oscillator structure altogether.

51. the integrated circuit according to claim 47 also comprises:

Be connected to the coefficient register of a plurality of convertible controlled reactance modules, coefficient register is suitable for preserving a plurality of coefficients and provides corresponding coefficient to be transformed into resonator to control corresponding controlled reactance modules.

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