CN101169803A - 验证设计规则校验程序的方法和系统 - Google Patents
验证设计规则校验程序的方法和系统 Download PDFInfo
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- CN101169803A CN101169803A CNA200710167404XA CN200710167404A CN101169803A CN 101169803 A CN101169803 A CN 101169803A CN A200710167404X A CNA200710167404X A CN A200710167404XA CN 200710167404 A CN200710167404 A CN 200710167404A CN 101169803 A CN101169803 A CN 101169803A
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- drc
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/552,245 | 2006-10-24 | ||
| US11/552,245 US7823103B2 (en) | 2006-10-24 | 2006-10-24 | Method and system of introducing hierarchy into design rule checking test cases and rotation of test case data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101169803A true CN101169803A (zh) | 2008-04-30 |
| CN101169803B CN101169803B (zh) | 2012-04-04 |
Family
ID=39361109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710167404XA Expired - Fee Related CN101169803B (zh) | 2006-10-24 | 2007-10-23 | 验证设计规则校验程序的方法和系统 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7823103B2 (zh) |
| CN (1) | CN101169803B (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103646031A (zh) * | 2013-11-08 | 2014-03-19 | 上海华力微电子有限公司 | Drc文件的坐标数据对比方法 |
| US10628549B2 (en) | 2015-04-15 | 2020-04-21 | Sage Design Automation Ltd | Automation generation of test layouts for verifying a DRC deck |
| CN118862815A (zh) * | 2023-04-18 | 2024-10-29 | 北京平头哥信息技术有限公司 | 检测芯片载体可制造性的方法、系统及存储介质 |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090187867A1 (en) * | 2008-01-22 | 2009-07-23 | Lawrence Jay A | Techniques for Verifying Error Detection of a Design Rule Checking Runset |
| US10248915B2 (en) * | 2008-03-07 | 2019-04-02 | International Business Machines Corporation | Risk profiling for enterprise risk management |
| US8510685B1 (en) * | 2009-12-30 | 2013-08-13 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for creating a hierarchical output for an operation in an electronic design |
| US8539416B1 (en) | 2009-12-30 | 2013-09-17 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for creating a hierarchical output for an operation in an electronic design |
| US9057764B2 (en) * | 2011-10-27 | 2015-06-16 | International Business Machines Corporation | Detection of unchecked signals in circuit design verification |
| US9934349B2 (en) | 2015-03-26 | 2018-04-03 | Nxp Usa, Inc. | Method for verifying design rule checks |
| WO2017055075A1 (en) | 2015-09-28 | 2017-04-06 | Asml Netherlands B.V. | Hierarchical representation of two-dimensional or three-dimensional shapes |
| US9971861B2 (en) * | 2016-02-10 | 2018-05-15 | International Business Machines Corporation | Selective boundary overlay insertion for hierarchical circuit design |
| US20220091844A1 (en) * | 2020-08-02 | 2022-03-24 | Drexel University | System for achieving insights through interactive facet-based architecture recovery (i-far) |
| US11775729B2 (en) | 2021-05-03 | 2023-10-03 | Samsung Electronics Co., Ltd. | Technology file process rule validation |
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| US4729096A (en) | 1984-10-24 | 1988-03-01 | International Business Machines Corporation | Method and apparatus for generating a translator program for a compiler/interpreter and for testing the resulting translator program |
| US5497334A (en) * | 1993-02-19 | 1996-03-05 | International Business Machines Corporation | Application generator for use in verifying a hierarchical circuit design |
| US5787006A (en) | 1996-04-30 | 1998-07-28 | Micron Technology, Inc. | Apparatus and method for management of integrated circuit layout verification processes |
| US5729096A (en) | 1996-07-24 | 1998-03-17 | Motorola Inc. | Inverter protection method and protection circuit for fluorescent lamp preheat ballasts |
| US6023567A (en) | 1996-10-07 | 2000-02-08 | International Business Machines Corporation | Method and apparatus for verifying timing rules for an integrated circuit design |
| US5987240A (en) * | 1996-10-29 | 1999-11-16 | International Business Machines Corporation | Design rules checker for an integrated circuit design |
| US6370679B1 (en) * | 1997-09-17 | 2002-04-09 | Numerical Technologies, Inc. | Data hierarchy layout correction and verification method and apparatus |
| US6453452B1 (en) * | 1997-12-12 | 2002-09-17 | Numerical Technologies, Inc. | Method and apparatus for data hierarchy maintenance in a system for mask description |
| US6243854B1 (en) * | 1998-04-28 | 2001-06-05 | International Business Machines Corporation | Method for selecting hierarchical interactions in a hierarchical shapes processor |
| US6063132A (en) | 1998-06-26 | 2000-05-16 | International Business Machines Corporation | Method for verifying design rule checking software |
| GB9914380D0 (en) * | 1999-06-21 | 1999-08-18 | Regan Timothy J | Method of scaling an integrated circuit |
| US6611946B1 (en) * | 1999-10-14 | 2003-08-26 | Synopsys, Inc. | Method and system for automatic generation of DRC rules with just in time definition of derived layers |
| US6571374B1 (en) * | 2000-02-28 | 2003-05-27 | International Business Machines Corporation | Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips |
| AU2001266660A1 (en) * | 2000-06-02 | 2001-12-17 | Virtio Corporation | Method and system for virtual prototyping |
| US6425113B1 (en) * | 2000-06-13 | 2002-07-23 | Leigh C. Anderson | Integrated verification and manufacturability tool |
| US6718521B1 (en) * | 2000-08-14 | 2004-04-06 | International Business Machines Corporation | Method and system for measuring and reporting test coverage of logic designs |
| JP2002197134A (ja) | 2000-12-27 | 2002-07-12 | Nec Microsystems Ltd | 階層レイアウトパターンのデザインルールチエック方法 |
| US6901574B2 (en) * | 2001-02-09 | 2005-05-31 | Lacour Patrick J. | Data management method for mask writing |
| US6816997B2 (en) | 2001-03-20 | 2004-11-09 | Cheehoe Teh | System and method for performing design rule check |
| US6957403B2 (en) * | 2001-03-30 | 2005-10-18 | Syntest Technologies, Inc. | Computer-aided design system to automate scan synthesis at register-transfer level |
| US6658633B2 (en) * | 2001-10-03 | 2003-12-02 | International Business Machines Corporation | Automated system-on-chip integrated circuit design verification system |
| CA2360291A1 (en) * | 2001-10-30 | 2003-04-30 | Benoit Nadeau-Dostie | Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby |
| JP3848157B2 (ja) * | 2001-12-27 | 2006-11-22 | 株式会社東芝 | Lsi設計検証装置、lsi設計検証方法、及びlsi設計検証プログラム |
| US6732338B2 (en) | 2002-03-20 | 2004-05-04 | International Business Machines Corporation | Method for comprehensively verifying design rule checking runsets |
| US6769099B2 (en) | 2002-04-12 | 2004-07-27 | Sun Microsystems, Inc. | Method to simplify and speed up design rule/electrical rule checks |
| US6775806B2 (en) | 2002-06-10 | 2004-08-10 | Sun Microsystems, Inc. | Method, system and computer product to produce a computer-generated integrated circuit design |
| US6871332B2 (en) | 2002-07-23 | 2005-03-22 | Sun Microsystems, Inc. | Structure and method for separating geometries in a design layout into multi-wide object classes |
| US6883149B2 (en) | 2002-09-30 | 2005-04-19 | Sun Microsystems, Inc. | Via enclosure rule check in a multi-wide object class design layout |
| US7007207B2 (en) * | 2002-10-21 | 2006-02-28 | International Business Machines Corporation | Scheduling of transactions in system-level test program generation |
| US20040088682A1 (en) * | 2002-11-05 | 2004-05-06 | Thompson Ryan C. | Method, program product, and apparatus for cache entry tracking, collision detection, and address reasignment in processor testcases |
| CN1521830A (zh) * | 2003-02-12 | 2004-08-18 | 上海芯华微电子有限公司 | 集成电路设计、验证与测试一体化的技术方法 |
| US7096440B2 (en) * | 2003-07-22 | 2006-08-22 | Lsi Logic Corporation | Methods and systems for automatic verification of specification document to hardware design |
| US7181702B2 (en) * | 2003-08-30 | 2007-02-20 | Jeffrey Horn | System and method to solve shape nesting problems |
| JP2005202928A (ja) * | 2003-12-19 | 2005-07-28 | Fujitsu Ltd | レイアウト処理装置、レイアウト処理方法、及びプログラム |
| US7392169B2 (en) * | 2004-10-21 | 2008-06-24 | International Business Machines Corporation | Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language |
| US7237210B2 (en) * | 2005-02-08 | 2007-06-26 | International Business Machines Corporation | Methods, systems and media for managing functional verification of a parameterizable design |
| US7434184B2 (en) * | 2005-08-08 | 2008-10-07 | Zhe Li | Method for detecting flaws in a functional verification plan |
| US7254791B1 (en) * | 2005-09-16 | 2007-08-07 | National Semiconductor Corporation | Method of measuring test coverage of backend verification runsets and automatically identifying ways to improve the test suite |
| US7478348B2 (en) * | 2006-03-27 | 2009-01-13 | International Business Machines Corporation | Method and apparatus of rapid determination of problematic areas in VLSI layout by oriented sliver sampling |
-
2006
- 2006-10-24 US US11/552,245 patent/US7823103B2/en not_active Expired - Fee Related
-
2007
- 2007-10-23 CN CN200710167404XA patent/CN101169803B/zh not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103646031A (zh) * | 2013-11-08 | 2014-03-19 | 上海华力微电子有限公司 | Drc文件的坐标数据对比方法 |
| US10628549B2 (en) | 2015-04-15 | 2020-04-21 | Sage Design Automation Ltd | Automation generation of test layouts for verifying a DRC deck |
| TWI708140B (zh) * | 2015-04-15 | 2020-10-21 | 以色列商薩吉設計自動化有限公司 | 用以驗證設計規則檢查疊組之測試佈局的自動產生技術 |
| CN118862815A (zh) * | 2023-04-18 | 2024-10-29 | 北京平头哥信息技术有限公司 | 检测芯片载体可制造性的方法、系统及存储介质 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20080109772A1 (en) | 2008-05-08 |
| US7823103B2 (en) | 2010-10-26 |
| CN101169803B (zh) | 2012-04-04 |
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| PB01 | Publication | ||
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20171121 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171121 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
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| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120404 Termination date: 20191023 |
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| CF01 | Termination of patent right due to non-payment of annual fee |