CN101165916A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor device and a method for fabricating the same. A resurf region of N type and a base region of P type adjacent to each other are formed in surface portions of a semiconductor substrate of the P type. A N emitter region is formed in the base region to be spaced from the resurf region. A gate insulating film is formed to cover a portion of the base region disposed between the emitter region and the resurf region, and a gate electrode is formed on the gate insulating film. A top semiconductor layer of P type electrically connected to the base region is formed in a surface portion of the resurf region. A collector region of the P type is formed in a surface portion of the resurf region to be spaced from the top semiconductor layer. The collector region and the top semiconductor layer have substantially the same impurity concentration and are disposed at substantially the same depth. Thus, the invention provides a high pressuretight semiconductor device for reducing the loss on the whole range from light to heavy load.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor device such as a high withstand voltage lateral insulated gate bipolar transistor used in a switching power supply device and a manufacturing method thereof.

Background technique

In recent years, attention has been paid to reducing the standby power of home appliances and the like from the standpoint of countermeasures against global warming, and there has been a strong demand for switching power supply devices with low power consumption during standby.

Next, a conventional switching power supply device will be described.

FIG. 36 shows an example of the circuit configuration of a conventional switching power supply device. As shown in FIG. 36 , the existing switching power supply device has an upstream rectification and filtering circuit 411 , a main circuit 412 , a transformer 404 and a downstream rectification and filtering circuit 421 .

Specifically, the AC voltage input between the input ends 416 and 417 of the upstream rectifying and filtering circuit 411 is rectified and filtered by the upstream rectifying and filtering circuit 411 , and then provided to the main circuit 412 as an input DC voltage. Here, the upstream rectification filter circuit 411 has a diode bridge 431 and an input capacitor 432 , and the voltage after full-wave rectification by the diode bridge 431 is filtered by the input capacitor 432 and supplied to the main circuit 412 .

In the main body circuit 412, a semiconductor switching element 413 and a voltage control circuit 414 are provided. The semiconductor switch element 413 and the voltage control circuit 414 can be integrated in one chip. A primary winding 441 is provided in the transformer 404, and the primary winding 441 and the semiconductor switching element 413 are connected in series, and the input DC voltage from the upstream rectification and filtering circuit 411 is supplied to the series connection circuit.

The control terminal of the semiconductor switch element 413 is connected to the voltage control circuit 414 , which is configured in such a way that the on state and the off state of the semiconductor switch element 413 are controlled by the gate signal output by the voltage control circuit 414 .

In the transformer 404 , a secondary winding 442 magnetically coupled to the primary winding 441 and an auxiliary winding 443 magnetically coupled to the primary winding 441 and the secondary winding 442 are provided. When the semiconductor switching element 413 performs a switching operation, the current intermittently flows through the primary winding 441 , and is induced in the secondary winding 442 and the auxiliary winding 443 to generate a voltage.

The downstream rectification and filtering circuit 421 rectifies and filters the voltage induced on the secondary winding 442 to generate a DC output voltage, and then outputs the DC output voltage from the output terminals 426 and 427 . Specifically, the downstream rectification and filtering circuit 421 has a diode 422 , a choke coil 423 , a first output capacitor 424 and a second output capacitor 425 . The choke coil 423, the first output capacitor 424, and the second output capacitor 425 are connected to each other in a π shape, so that the induced voltage generated on the secondary winding 442 is half-wave rectified by the diode 422 , and then filtered by the choke coil 423 , the first output capacitor 424 and the second output capacitor 425 .

The voltage generated at both ends of the auxiliary winding 443 is input to the control terminal of the semiconductor switching element 413 through the voltage control circuit 414 . That is, the switching power supply device shown in FIG. 36 is an RCC (ringing choke converter: ringing choke converter) type device, and the semiconductor switching element 413 performs self-excited switching operation according to the voltage generated on the auxiliary winding 443 .

The voltage between the output terminals 426 and 427 is fed back to the voltage control circuit 414 through the optocoupler 429 . For example, when the voltage between the output terminals 426 and 427 drops, the voltage control circuit 414 forcibly prolongs the conduction time of the semiconductor switching element 413, and on the contrary, the voltage between the output terminals 426 and 427 rises. In this case, the voltage control circuit 414 forcibly shortens the conduction time of the semiconductor switching element 413 . Thus, the voltages appearing at the output terminals 426 and 427 are maintained at a constant value.

Since the voltage induced in the auxiliary winding 443 is used to generate the auxiliary DC voltage inside the voltage control circuit 414, the voltage control circuit 414 operates using the auxiliary DC voltage except when the switching power supply is activated.

It should be added that when the switching power supply device is started, that is, when an AC voltage is applied between the input terminals 416 and 417, the auxiliary winding 443 is not induced to generate a voltage because the semiconductor switching element 413 has not yet performed switching operations. The voltage control circuit 414 is in a power-off state. Therefore, in order to start the switching operation of the semiconductor switching element 413, a low voltage suitable for starting the voltage control circuit 414 is supplied from the upstream rectifying filter circuit 411 through an external resistor 451 (high withstand voltage, high power).

In the switching power supply described above, losses mainly occur in the semiconductor switching element 413 . Normally, a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor: Metal Oxide Semiconductor Field-Effect Transistor) is used as the switching element 413 . In general, in bipolar transistors, the switching loss when switching from the on state to the off state is large, while in MOSFETs, the switching loss is small because of the fast switching speed. But on the other hand, in MOSFETs, the conduction loss cannot be ignored because the on-resistance is large, which is different from bipolar transistors. Therefore, when a large current flows through the MOSFET, a large loss is caused.

In recent years, in addition to unipolar MOSFETs, bipolar IGBTs (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor), which inject minority carriers into the drift layer, have attracted much attention in the field of switching power supply technology. In the case of using an IGBT as the switching element 413 in the conventional switching power supply device shown in FIG. The switching speed is slower and the result is higher switching losses.

In the above-mentioned RCC switching power supply, when the load connected to the output terminals 426 and 427 is large, the switching frequency of the switching element 413 is reduced, and the conduction time of the switching element 413 is prolonged. As a result, a large current flows through the primary winding 441, so that the voltage between the output terminal 426 and the output terminal 427 is maintained at a constant value. Conversely, when the load is light such as in the standby mode, the switching frequency of the switching element 413 is increased, and the conduction time is shortened. As a result, the current flowing through the primary winding 441 decreases, so that the voltage between the output terminal 426 and the output terminal 427 is maintained at a constant value.

Therefore, when the two losses of switching loss and conduction loss are considered comprehensively, when the load is large, the frequency is low and the current is large, so it is unfavorable for MOSFET and favorable for IGBT. On the contrary, when the load is small such as in standby mode, because the frequency is high and the current is small, it is beneficial to the MOSFET and not to the IGBT.

Fig. 37 is a graph showing the results of comparing the relationship between load and loss when MOSFETs (horizontal, drift region with RESURF structure) and IGBTs (lateral) are used in switching power supplies, respectively. picture. As shown in Figure 37, on the side where the output power is small (small load), the loss of the IGBT is large because the switching frequency is high; on the side where the output power is large (large load), the switching frequency is low, so The loss of MOSFET is larger.

[Patent Document 1] Japanese Laid-Open Patent Publication No. 7-153951

[Patent Document 2] Japanese Laid-Open Patent Publication No. 2002-345242

[Patent Document 3] Japanese Publication Patent Publication Japanese Patent Publication No. 6-52791 (US Patent No. 5072268 specification)

[Patent Document 4] Japanese Patent No. 2629437

[Patent Document 5] Specification of US Patent No. 4811075

[Patent Document 6] Specification of US Patent No. 5313082

[Patent Document 7] Japanese Laid-Open Patent Publication No. 8-213617

[Patent Document 8] Japanese Laid-Open Patent Publication No. 2007-115871 (US Patent Application No. 11/582441)

[Non-Patent Document 1] D.S.Byeon and others, The separated shorted-anodeinsulated gate bipolar transistor with the suppressed negative differential resistance regime, Microelectronics Journal 30, 1999, p.571-575

As mentioned above, when a MOSFET is used as a switching element, the conduction loss is large when the load is large; when an IGBT is used as a switching element, the switching loss is large when it is on standby and when the load is small. Therefore, in the conventional semiconductor switching element, it is difficult to reduce the loss over the entire range from a small load to a heavy load.

In Patent Document 1, a structure is proposed in which a vertical IGBT and a vertical power MOSFET are co-existed in one chip of a switching element. However, in said structure, the current capability of the vertical power MOSFET is too small relative to the driving capability of the vertical IGBT. The result is that, in practice, it is difficult to drive power MOSFETs at small loads. Furthermore, in this structure, since it is necessary to form a step on the back surface of the semiconductor substrate, it is difficult in the manufacturing process.

In Patent Document 2, a structure using a Schottky junction IGBT as a switching element is proposed. However, in this Schottky junction IGBT, since the loss is larger than that of a power MOSFET when the load is small, and the loss is larger than that of the conventional IGBT when the load is heavy, the structure based on Patent Document 2 does not necessarily mean that the loss is reduced. There is progress in the structure.

Moreover, since the switching elements disclosed in Patent Documents 1 and 2 all have a vertical structure, for example, when using the switching element with the vertical structure as the semiconductor switching element 413 of the conventional switching power supply device shown in FIG. 36 , It is difficult to form the voltage control circuit 414 and the semiconductor switching element 413 in one chip. This is also a problem.

Although the purpose is not to selectively use both MOSFET and IGBT with one element, in Non-Patent Document 1 and Patent Document 3, a lateral IGBT with an anode short-circuit structure has been proposed as a function of the gap between MOSFET and IGBT. The intermediate role of semiconductor components.

FIG. 38 is a cross-sectional view showing an example of a lateral IGBT disclosed in Patent Document 3 having an anode short-circuit structure. In the structure shown in FIG. 38 , a P ⁺ -type pocket 514 and an N ⁺ -type pocket 515 are short-circuited through a drain electrode 513 . In this anode-short-circuited lateral IGBT, when a forward bias voltage is applied between the drain electrode 513 and the source electrode 505, and a positive voltage is applied to the gate electrode 512, the current starts to pass through the N ⁺ -type pocket region 515 N ⁺ -type source region 507 flows to source electrode 505 (MOSFET operation). Afterwards, when the potential of the part of the N-type well region 503 located on the lower side of the P ⁺ -type pocket region 514 drops to about 0.6V lower than that of the P ⁺ -type pocket region 514, holes begin to be injected from the P ⁺ -type pocket region 514 into the N-type well region 503. In the well region 503, the IGBT is in the working state. Because electrons are discharged from the N-type well region 503 to the N ⁺ -type pocket region 515 when the gate signal is turned off, the anode-short-circuited lateral IGBT shown in FIG. 38 has the characteristic of fast switching operation. Furthermore, since this switching element has a lateral structure, when this switching element is used as, for example, the semiconductor switching element 413 shown in FIG. 36, the voltage control circuit 414 and the semiconductor switching element 413 can be formed in one chip.

However, even if the anode-short-circuited lateral IGBT shown in FIG. 38 is used as a switching element, it is difficult to reduce the loss over the entire range from a small load to a large load. The reason is that in this switching element, only when the length 523 of the P ⁺ -type pocket region 514 is set to a large value, the switching element can be easily transferred from the MOSFET operation to the IGBT operation. The region also performs MOSFET operation, resulting in increased losses. If the length 523 of the P ⁺ -type pocket region 514 is set to a larger value, a potential difference is easily generated between the P ⁺ -type pocket region 514 and the N-type well region 503 , and the switching element is easily transferred to the IGBT to work. However, when the length 523 of the P ⁺ -type pocket region 514 is set to a large value, the unit area of the element is large. As a result, the on-resistance of the element becomes large both when the MOSFET is in operation and when the IGBT is in operation, resulting in increased loss.

Therefore, from a practical point of view, even if the anode-short-circuited lateral IGBT shown in FIG. 38 is used in a switching power supply device, it is difficult to reduce the loss over the entire range from a small load to a heavy load.

Contents of the invention

The present invention is researched and developed to solve the problem. Its object is to provide a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

In order to achieve the above object, the first semiconductor device involved in the present invention includes: a second conductivity type RESURF region, a first conductivity type base region, a second conductivity type emitter region, a first gate insulating film, a second conductivity type a gate electrode, a first conductive type top semiconductor layer, a first conductive type collector region, a collector electrode, and an emitter electrode, and the second conductive type reduced surface electric field region is formed on the surface of the first conductive type semiconductor substrate In part; the base region of the first conductivity type is formed in the semiconductor substrate in a manner adjacent to the RESURF region; the emitter region of the second conductivity type is isolated from the RESURF region formed in the base region; the first gate insulating film is formed to cover a portion of the base region between the emitter region and the resurf region; the first gate a pole electrode is formed on the first gate insulating film; the top semiconductor layer of the first conductivity type is formed in the surface portion of the RESURF region and is electrically connected to the base region; the first conductivity type A collector region is formed in a surface portion of the RESURF region in isolation from the top semiconductor layer, and has substantially the same impurity concentration as that of the top semiconductor layer, and is located substantially at the same distance from the top semiconductor layer. the same deep position; the collector electrode is formed on the semiconductor substrate and is electrically connected to the collector region; the emitter electrode is formed on the semiconductor substrate and is connected to the base region and the The emitter region is electrically connected.

That is, the first semiconductor device of the present invention is a lateral IGBT in which the impurity concentration of the collector region is set to be substantially the same low concentration as the impurity concentration of the top semiconductor layer. Therefore, the amount of excess carriers injected into the semiconductor substrate during the operation of the IGBT can be suppressed more than when the collector region is formed with a high impurity concentration layer. As a result, the amount of excess carriers remaining in the semiconductor substrate at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

In the case of forming the collector region with a high impurity concentration layer, it is necessary to provide a second conductivity type buffer layer with an impurity concentration higher than that of the RSU region between the collector region and the RSU region to reduce injection from the collector region. hole injection efficiency into the region of reduced surface electric field. In contrast, in the first semiconductor device of the present invention, since the collector region is formed with a low impurity concentration, there is no need to provide a second conductivity type buffer layer, and the process can be simplified.

As a supplementary note, in the specification of this case, "having substantially the same impurity concentration" means that the impurity concentration difference is about 1×10 ¹ /cm ³ or less (that is, when expressed as an index, both are within the range of the same index order ), "located at substantially the same depth" means that the depth difference is about 1 μm or less.

The second semiconductor device involved in the present invention includes: a second conductivity type RESURF region, a first conductivity type base region, a second conductivity type emitter and source region, a first gate insulating film, a first gate electrode, a top semiconductor layer of a first conductivity type, a collector region of a first conductivity type, a drain region of a second conductivity type, a collector-cum-drain electrode, and an emitter-cum-source electrode, the second conductivity type reducing the surface electric field A region is formed in a surface portion of a first conductivity type semiconductor substrate; the first conductivity type base region is formed in the semiconductor substrate in a manner adjacent to the resurf region; the second conductivity type emits a pole-cum-source region formed in the base region in a manner of being isolated from the RESURF region; the first gate insulating film is formed to cover the emitter-cum-source region in the base region; The portion between the electrode region and the RESURF region; the first gate electrode is formed on the first gate insulating film; the first conductivity type top semiconductor layer is formed on the surface of the RESURF region and is electrically connected to the base region; the collector region of the first conductivity type is formed in a surface portion of the RESURF region in isolation from the top semiconductor layer, and has a The same impurity concentration of the top semiconductor layer is located at a position substantially as deep as the top semiconductor layer; the second conductivity type drain region is formed in the RESURF region in a manner of being isolated from the top semiconductor layer In the surface portion; the collector and drain electrode is formed on the semiconductor substrate, and is electrically connected to the collector region and the drain region respectively; the emitter and source electrode is formed on the semiconductor substrate bottom, and are electrically connected to the base region and the emitter-source region respectively.

That is, the second semiconductor device of the present invention is a semiconductor device that performs MOSFET operation or IGBT operation according to the amount of collector current. In this semiconductor device, the impurity concentration in the collector region is set to be substantially the same low concentration as the impurity concentration in the top semiconductor layer. Therefore, the amount of excess carriers injected into the semiconductor substrate during the operation of the IGBT can be suppressed more than when the collector region is formed with a high impurity concentration layer. As a result, the amount of excess carriers remaining in the semiconductor substrate at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

In the case of forming the collector region with a high impurity concentration layer, it is necessary to provide a second conductivity type buffer layer with an impurity concentration higher than that of the RSU region between the collector region and the RSU region to reduce injection from the collector region. hole injection efficiency into the region of reduced surface electric field. In contrast, in the second semiconductor device of the present invention, since the collector region is formed with a low impurity concentration, there is no need to provide a second conductivity type buffer layer, and the process can be simplified. Furthermore, it is possible to avoid the occurrence of a situation in which switching from MOSFET operation to IGBT operation becomes more difficult due to the provision of the second conductivity type buffer layer.

In the second semiconductor device of the present invention, it is preferable that the collector region and the drain region are respectively composed of a plurality of isolated parts; Each part of the collector region and each part of the drain region are alternately arranged in a direction perpendicular to the direction of the source region.

In this way, in a semiconductor device that performs MOSFET operation or IGBT operation according to the amount of collector current, by changing the length of each part of the collector region, it is possible to easily adjust the switching from MOSFET operation to IGBT operation. Collector voltage Vch.

In the first or second semiconductor device of the present invention, it is preferable that the semiconductor device further includes a second gate insulating film and a second gate electrode, the second gate insulating film being formed on the lower The surface electric field region extends from the collector region to the top semiconductor layer; the second gate electrode is formed on the second gate insulating film.

In this way, the second gate electrode is turned on when the first or second semiconductor device is turned off, so that excess carriers can be further extracted from the top semiconductor layer, and thus the required time for extraction of carriers can be further shortened. time. Therefore, the switching speed can be further improved.

In this case, it is more preferable that the semiconductor device further includes a first conductivity type buried semiconductor layer formed on the top semiconductor layer in contact with the top semiconductor layer. In the RESURF region, and electrically connected to the base region.

In this way, since the buried semiconductor layer is also formed in the region for reducing the surface electric field, when the IGBT is turned off, not only from the top semiconductor layer, but also from the buried semiconductor layer can be efficiently extracted The excess carrier in the surface electric field area is reduced, and thus the time required for extraction of the carrier can be further shortened. Therefore, the switching speed can be further improved. Compared with the case where only the top semiconductor layer is formed in the RESURF region, since the depletion layer can be formed from the buried semiconductor layer in both upper and lower directions, the impurity concentration in the RESURF region can be made higher, thereby Improvement in switching speed and reduction in on-resistance can be achieved.

The first semiconductor device manufacturing method of the present invention is a method for manufacturing the first or second semiconductor device of the present invention, at least including forming the top semiconductor layer and the collector region through the same impurity implantation process process.

According to the first semiconductor device manufacturing method of the present invention, since the top semiconductor layer and the collector region are formed by the same impurity implantation process, the number of steps can be made smaller compared with the case of separately forming the semiconductor layer and the collector region, thereby Cost reduction can be achieved.

The third semiconductor device according to the present invention includes: a second conductivity type reduced surface electric field region, a first conductivity type base region, a second conductivity type emitter region, a gate insulating film, a gate electrode, a first conductivity type The buried semiconductor layer, the collector region of the first conductivity type, the collector contact region of the first conductivity type, the collector electrode, and the emitter electrode, and the surface electric field reduction region of the second conductivity type are formed on the semiconductor substrate of the first conductivity type In the surface portion; the first conductivity type base region is formed in the semiconductor substrate in a manner adjacent to the reduced surface electric field region; is formed in the base region in a region isolation manner; the gate insulating film is formed to cover a portion of the base region between the emitter region and the RESURF region; the gate electrode formed on the gate insulating film; the first conductive type buried semiconductor layer is formed in the reduced surface electric field region, and is electrically connected to the base region; the first conductive type collector region is connected with the The buried semiconductor layer is isolated in the RESURF region, has substantially the same impurity concentration as the buried semiconductor layer, and is located substantially as deep as the buried semiconductor layer. the first conductivity type collector contact region is formed in the surface portion of the RESURF region in contact with the collector region; the collector electrode is formed on the semiconductor substrate, and The collector contact region is electrically connected; the emitter electrode is formed on the semiconductor substrate and is electrically connected to the base region and the emitter region.

That is, the third semiconductor device of the present invention is a lateral IGBT. In this IGBT, since the impurity concentration of the collector region is set to be substantially the same low concentration as that of the buried semiconductor layer, compared with the case where the collector region is formed with a high impurity concentration layer, the IGBT The amount of excess carriers injected into the semiconductor substrate during operation is suppressed more. As a result, the amount of excess carriers remaining in the semiconductor substrate at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

According to the third semiconductor device of the present invention, since the buried semiconductor layer is formed in the RESURF region, the depletion layer can be formed in both vertical directions from the buried semiconductor layer. Therefore, the impurity concentration of the resurf region can be made high, and the switching speed can be improved and the on-resistance can be reduced.

In the case where the collector region is formed with a high impurity concentration layer, it is necessary to set a second conductivity type buffer layer with an impurity concentration higher than that of the RESURF region between the collector region and the RESURF region to reduce the noise from the collector region. The efficiency of hole injection into the region of reduced surface electric field. In contrast, in the third semiconductor device of the present invention, since the collector region is formed with a low impurity concentration, it is not necessary to provide a second conductivity type buffer layer, and the process can be simplified.

The fourth semiconductor device according to the present invention includes: a second conductivity type RESURF region, a first conductivity type base region, a second conductivity type emitter and source region, a gate insulating film, a gate electrode, a second conductivity type A conductive type buried semiconductor layer, a first conductive type collector region, a first conductive type collector contact region, a second conductive type drain region, a collector-cum-drain electrode, and an emitter-cum-source electrode, the The second conductivity type resurf region is formed in a surface portion of the first conductivity type semiconductor substrate; the first conductivity type base region is formed in the semiconductor substrate adjacent to the resurf region The second conductivity type emitter and source region is formed in the base region in a manner of being isolated from the reduced surface electric field region; the gate insulating film is formed to cover the base region located in the base region The portion between the emitter and source region and the reduced surface electric field region; the gate electrode is formed on the gate insulating film; the first conductivity type buried semiconductor layer is formed on the reduced surface electric field region, and is electrically connected to the base region; the collector region of the first conductivity type is formed in the reduced surface electric field region in a manner of being isolated from the buried semiconductor layer, and has a The buried semiconductor layer has the same impurity concentration and is located substantially as deep as the buried semiconductor layer; the first conductivity type collector contact region is formed in the lowered portion in contact with the collector region. In the surface portion of the surface electric field region; the drain region of the second conductivity type is formed in the surface portion of the reduced surface electric field region in a manner of being isolated from the buried semiconductor layer; the collector and drain electrode is formed in the surface portion of the surface electric field region on the semiconductor substrate, and are respectively electrically connected to the collector contact region and the drain region; the emitter and source electrode is formed on the semiconductor substrate, and are respectively connected to the base region and the drain region The emitter and source regions are electrically connected.

That is, the fourth semiconductor device of the present invention is a semiconductor device that performs MOSFET operation or IGBT operation depending on the amount of collector current. In this semiconductor device, the impurity concentration of the collector region is set to be substantially the same low concentration as that of the buried semiconductor layer. Therefore, compared with the case where the collector region is formed with a high impurity concentration layer, the The amount of excess carriers injected into the semiconductor substrate during IGBT operation is suppressed more. As a result, the amount of excess carriers remaining in the semiconductor substrate at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

According to the fourth semiconductor device of the present invention, since the buried semiconductor layer is formed in the RESURF region, depletion layers can be formed from the buried semiconductor layer in both upper and lower directions. Therefore, the impurity concentration of the resurf region can be made high, and the switching speed can be improved and the on-resistance can be reduced.

In the case of forming the collector region with a high impurity concentration layer, it is necessary to provide a second conductivity type buffer layer with an impurity concentration higher than that of the RSU region between the collector region and the RSU region to reduce injection from the collector region. hole injection efficiency into the region of reduced surface electric field. In contrast, in the fourth semiconductor device of the present invention, since the collector region is formed with a low impurity concentration, there is no need to provide a second conductivity type buffer layer, and the process can be simplified. Furthermore, it is possible to avoid the occurrence of a situation in which switching from MOSFET operation to IGBT operation becomes more difficult due to the provision of the second conductivity type buffer layer.

In the fourth semiconductor device of the present invention, it is preferable that the collector region and the drain region are respectively composed of a plurality of isolated parts; Each part of the collector region and each part of the drain region are alternately arranged in a direction perpendicular to the direction of the source region.

In this way, in a semiconductor device that performs MOSFET operation or IGBT operation according to the amount of collector current, by changing the length of each part of the collector region, it is possible to easily adjust the switching from MOSFET operation to IGBT operation. Collector voltage Vch.

The second semiconductor device manufacturing method of the present invention is a method for manufacturing the third or fourth semiconductor device of the present invention, at least including forming the buried semiconductor layer and the collector electrode through the same impurity implantation process. regional processes.

According to the second semiconductor device manufacturing method of the present invention, since the buried semiconductor layer and the collector region are formed by the same impurity implantation process, the process can be simplified compared with the case of separately forming the buried semiconductor layer and the collector region. The number is small, and cost reduction can be aimed at.

As an additional note, in the first to fourth semiconductor devices of the present invention, if the gate insulating film (in the first and second semiconductor devices of the present invention, the first gate insulating film) is formed to the emitter region ( In the second and fourth semiconductor devices of the present invention, the gate electrode and the emitter region can be prevented from being short-circuited.

-The effect of the invention-

According to the present invention, since it is possible to reduce the amount of excess carriers remaining in the semiconductor substrate when it is turned off, the time required for extracting the carriers can be shortened, and thus the switching speed can be improved, thereby reducing the switching loss. . Therefore, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

Description of drawings

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

2 is a sectional view showing one step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

3 is a sectional view showing one step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

4 is a sectional view showing one step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

5 is a cross-sectional view showing one step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

6 is a cross-sectional view showing one step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

7 is a sectional view showing one step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

Fig. 8(a) is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention (a cross-sectional view along line CC' in Fig. 8(b)); Fig. 8(b) is a cross-sectional view of the semiconductor device according to the present invention A plan view of a semiconductor device according to the second embodiment of the present invention.

Fig. 9 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention (a cross-sectional view taken along line D-D' in Fig. 8(b) ).

FIG. 10 is a graph showing the results of measuring the dependence of fall time tf on temperature for a semiconductor device according to a second example of the present invention and a semiconductor device according to a comparative example.

FIG. 11 is a graph showing the results of measuring the dependence of on-resistance Ron on temperature for a semiconductor device according to a second example of the present invention and a semiconductor device according to a comparative example.

Fig. 12(a) is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention (a cross-sectional view along line EE' in Fig. 12(b)); Fig. 12(b) is a cross-sectional view of the semiconductor device according to the present invention A plan view of a semiconductor device according to the third embodiment.

13 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

14 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

15 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

16 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

17 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

18 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 19 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

20 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

21 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

22 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

23 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

24 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

25 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 26 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.

27 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.

28 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.

29 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.

30 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.

31 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.

32 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.

Fig. 33(a) is a cross-sectional view of a semiconductor device according to a comparative example (a cross-sectional view taken along line AA' in Fig. 33(b)); Fig. 33(b) is a cross-sectional view of a semiconductor device according to a comparative example floor plan.

Fig. 34 is a cross-sectional view of a semiconductor device according to a comparative example (a cross-sectional view along line B-B' in Fig. 33(b)).

35 is a graph showing the relationship between the collector voltage and the collector current in the semiconductor device according to the comparative example.

FIG. 36 is a diagram showing an example of a circuit configuration of a conventional switching power supply device.

Fig. 37 is a graph showing the results of comparing the relationship between load and loss when MOSFET (lateral, drift region has a resurf structure) and IGBT (lateral) are used in switching power supplies, respectively.

Fig. 38 is a cross-sectional view showing an example of a conventional anode-short-circuited lateral IGBT.

Symbol Description

101-semiconductor substrate; 102-reduced surface electric field region; 103-gate insulating film; 104-electric field insulating film; 105-top semiconductor layer; 106-base region; 107-gate electrode; 108-emitter and source 109-collector region; 110-contact region; 111-interlayer film; 112-collector and drain electrode; 113-emitter and source electrode; 114-protective film; 116-drain electrode; 201 - semiconductor substrate; 202 - RESURF region; 203 - gate insulating film (first gate insulating film); 204 - electric field insulating film; 205 - top semiconductor layer; 206 - base region; 207 - gate electrode (first gate electrode); 208-emitter region (emitter and source region); 209-collector contact region; 210-contact region; 211-interlayer film; 212-collector electrode (collector and drain electrode); 213-emitter electrode (emitter and source electrode); 214-protective film; 215-collector region; 216-drain region; 217-buried semiconductor layer; 218-collector region; 219 - collector contact region; 220 - second gate insulating film; 221 - second gate electrode; 222 - top semiconductor layer.

Detailed ways

(first embodiment)

Next, a semiconductor device according to a first embodiment of the present invention, specifically, a high withstand voltage semiconductor switching element will be described with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a semiconductor device according to a first embodiment. As shown in FIG. 1, in the surface portion of, for example, a P ^- type semiconductor substrate 201 (with an impurity concentration of 1×10 ¹⁴ /cm ³ ), for example, an N-type RESURF region 202 (with an impurity concentration of For example, 1×10 ¹⁶ /cm ³ and a depth of 7 μm). In addition, a P-type base region 206 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 4 μm) is formed adjacent to the RESURF region 202 in the surface portion of the semiconductor substrate 201 . ).

In the base region 206, a contact region 210 of, for example, P ⁺ type (for example, an impurity concentration of 1×10 ¹⁹ /cm ³ , and a depth of 2 μm) and a contact region of, for example, N ⁺ type emitter region 208 (the impurity concentration is, for example, 1×10 ²⁰ /cm ³ , and the depth is 0.5 μm). Furthermore, a gate insulating film 203 is formed covering a portion of the base region 206 between the emitter region 208 and the resurf region 202 , and a gate electrode 207 is formed on the gate insulating film 203 .

In addition, if the gate insulating film 203 is formed on the emitter region 208, it is possible to prevent the gate electrode 207 and the emitter region 208 from being short-circuited.

In the surface portion of the resurf region 202, there is formed, for example, a P-type top semiconductor layer 205 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 1 μm). Although not shown in the drawings, the top semiconductor layer 205 is electrically connected to the base region 206 via a predetermined portion of the resurf region 202 or wiring in an upper layer.

In the surface portion of the RESURF region 202 , a P-type collector region 215 (for example, impurity concentration of 1×10 ¹⁶ /cm ³ , depth of 1 μm) is formed in isolation from the top semiconductor layer 205 . Here, the collector region 215 has substantially the same impurity concentration as that of the top semiconductor layer 205 and is positioned substantially as deep as the top semiconductor layer 205 .

In the surface portion of the collector region 215, a collector contact region 209 of, for example, P ⁺ type (with an impurity concentration of, for example, 1×10 ¹⁹ /cm ³ and a depth of 0.5 μm) is formed. As a supplementary note, the collector contact region 209 may not be formed.

An interlayer film 211 is formed on the semiconductor substrate 201 on which the impurity regions and the like described above are formed via the electric field insulating film 204 formed on the surface of the resurf region 202 .

On the semiconductor substrate 201, a collector electrode 212 and an emitter electrode 213 are formed. The collector electrode 212 penetrates the interlayer film 211 and is electrically connected to the collector contact region 209 (ie, the collector region 215); The pole electrode 213 penetrates the interlayer film 211 and is electrically connected to both the contact region 210 (ie, the base region 206 ) and the emitter region 208 .

A protective film 214 is formed on the interlayer film 211 on which the collector electrode 212 and the emitter electrode 213 are formed.

In the semiconductor device of this embodiment, a forward bias voltage is applied between the collector electrode 212 and the emitter electrode 213 (making the collector electrode 212 side a high potential), and then a positive voltage is applied to the gate electrode. 207, when the potential difference between the potential of the collector region 215 and the potential of the portion surrounding the collector region 215 in the resurf region 202 reaches approximately 0.6 V, holes are injected from the collector region 215 into the By reducing the surface electric field region 202, the semiconductor device starts to perform IGBT operation.

That is, the semiconductor device (switching element) of this embodiment is a lateral IGBT. In this IGBT, the impurity concentration of the collector region 215 is set to be substantially the same low concentration as the impurity concentration of the top semiconductor layer 205 . Therefore, compared with the case where the collector region is formed with a high impurity concentration layer (P ⁺ layer), it is possible to reduce the excess current that is injected into the semiconductor substrate 201 including the resurf region 202 when the IGBT is in operation. Quantum suppressed more. As a result, the amount of excess carriers remaining in the semiconductor substrate 201 at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

In the case where the collector region is formed with a high impurity concentration layer, it is necessary to provide an N-type buffer layer with an impurity concentration higher than that of the RESURF region between the collector region and the RESURF region to reduce the voltage from the collector. The electrode region is injected into the region to reduce the surface electric field for hole injection efficiency. In contrast, in the semiconductor device of this embodiment, since the collector region 215 is formed with a low impurity concentration, it is not necessary to provide an N-type buffer layer, and the process can be simplified.

Next, an example of the method of manufacturing the switching element of this embodiment shown in FIG. 1 will be described with reference to the sectional views of FIGS. 2 to 7 .

First, in the process ^shown in FIG ^. 2 , ^for example, phosphorus ion implantation is used to selectively form, for example, N-type The RESURF region 202 of . The impurity concentration of the resurf region 202 is, for example, about 1×10 ¹⁶ /cm ³ , and the formation depth of the resurf region 202 is, for example, about 7 μm.

Next, in the process shown in FIG. 3 , a top semiconductor layer 205 such as a P-type and a collector region such as a P-type are simultaneously and selectively formed in the surface portion of the RESURF region 202 by boron ion implantation. 215. Here, the top semiconductor layer 205 and the collector region 215 are formed to be separated from each other. The impurity concentration of the top semiconductor layer 205 and the impurity concentration of the collector region 215 are respectively about 1×10 ¹⁶ /cm ³ , and the formation depths of the top semiconductor layer 205 and the collector region 215 are respectively about 1 μm.

In addition, although not shown in the drawings, the top semiconductor layer 205 is formed to be electrically connected to the base region 206 described later.

Next, in the process shown in FIG. 4 , for example, a P-type base region 206 is formed in the surface portion of the semiconductor substrate 201 by boron ion implantation. The base region 206 is formed adjacent to the resurf region 202 . The impurity concentration of the base region 206 is, for example, about 1×10 ^{16 /} cm ³ , and the formation depth of the base region 206 is, for example, 4 μm. Further, an electric field insulating film 204 having a thickness of, for example, 500 nm is selectively formed on the surface of the resurf region 202 by, for example, wet oxidation or the like. At this time, the impurity of the top semiconductor layer 205 diffuses, so that the impurity concentration of the top semiconductor layer 205 drops a little.

It should be added that in this embodiment, the sequence of ion implantation performed to form the impurity regions is not limited.

Next, in the step shown in FIG. 5 , a gate insulating film 203 covering a portion of the base region 206 between the emitter region 208 and the resurf region 202 described later is formed, for example, by thermal oxidation. Thereafter, a gate electrode 207 made of, for example, polysilicon is selectively formed on the gate insulating film 203 . In addition, using the gate electrode 207 as a mask, an emitter region 208 of, for example, N ⁺ type is selectively formed in the base region 206 by self-alignment, for example, by arsenic ion implantation or the like. The emitter region 208 is formed to be isolated from the resurf region 202 . The impurity concentration of the emitter region 208 is, for example, about 1×10 ²⁰ /cm ³ , and the formation depth of the emitter region 208 is, for example, about 0.5 μm.

Next, in the process shown in FIG. 6 , for example, a P ⁺ -type contact region 210 is formed in the base region 206 by, for example, boron ion implantation. The contact region 210 is formed to be isolated from the RESURF region 202 . The impurity concentration of the contact region 210 is, for example, about 1×10 ¹⁹ /cm ³ , and the formation depth of the contact region 210 is, for example, 2 μm. Thereafter, a collector contact region 209 of, for example, P ⁺ type is formed in a surface portion of the collector region 215 by, for example, boron ion implantation. The impurity concentration of the collector contact region 209 is, for example, about 1×10 ¹⁹ /cm ³ , and the formation depth of the collector contact region 209 is, for example, 0.5 μm. As a supplementary note, the collector contact region 209 may not be formed.

Next, in the process shown in FIG. 7 , an interlayer film is formed on the semiconductor substrate 201 including the electric field insulating film 204 and the gate electrode 207 by, for example, an atmospheric pressure CVD (chemical vapor deposition) method. 211, and then open a predetermined part of the interlayer film 211, and then form a collector electrode 212 and an emitter electrode 213 on the semiconductor substrate 201, respectively. ) is electrically connected; the emitter electrode 213 is electrically connected to both the contact region 210 (ie, the base region 206 ) and the emitter region 208 . Finally, after forming a protective film 214 made of, for example, a plasma silicon nitride film on the interlayer film 211, a spacer formation region in the protective film 214 is opened. Thus, the switching element of this embodiment shown in FIG. 1 is formed.

According to the manufacturing method of this embodiment described above, since the top semiconductor layer 205 and the collector region 215 are formed through the same impurity implantation process, compared with the case where the top semiconductor layer 205 and the collector region 215 are formed separately, the process can be simplified. Fewer quantities can reduce costs.

(comparative example)

As a semiconductor device that uses high-voltage and high-power electric power, has a low on-resistance and a fast turn-off speed, the following device has been proposed, that is, a device that combines a lateral double-diffused metal oxide semiconductor (LDMOS) and a lateral insulated gate double A device in which both structures of a LIGBT and LIGBT are formed in the same substrate (for example, refer to Patent Document 7).

The semiconductor device disclosed in Patent Document 7 has a double-gate structure, that is, a structure in which the gate of LIGBT and the gate of LDMOS are separately provided, and the anode of LIGBT and the drain of LDMOS are separated by a trench well.

The inventor of the present case has proposed in Patent Document 8 a structure different from that of the semiconductor device disclosed in Patent Document 7. This structure is capable of performing MOSFET operation and IGBT operation with a simple structure without using trench well isolation. Both work with single-gate lateral IGBT structures.

Next, as a comparative example, a semiconductor device having an IGBT structure disclosed by the inventor of the present application will be described with reference to the drawings. 33( a ) and 34 are cross-sectional views of a semiconductor device according to a comparative example, and FIG. 33( b ) is a plan view of a semiconductor device according to a comparative example. As an additional note, Fig. 33(a) is a sectional view along the A-A' line in Fig. 33(b); Fig. 34 is a sectional view along the B-B' line in Fig. 33(b). In FIG. 33(b), illustration of some structural elements is omitted.

As shown in Fig. 33(a), Fig. 33(b) and Fig. 34, in the surface portion of the P ^- type semiconductor substrate 101 (the impurity concentration is, for example, 1×10 ¹⁴ /cm ³ ), an N-type reduced surface is formed. Electric field region 102 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 7 μm). In addition, a P-type base region 106 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 4 μm) is formed adjacent to the resurf region 102 in the surface portion of the semiconductor substrate 101 .

In the base region 106, a P ⁺ type contact region 110 (with an impurity concentration of, for example, 1×10 ¹⁹ /cm ³ and a depth of 2 μm) and an N ⁺ type emitter and source are formed in a manner isolated from the RESURF region 102 . Pole region 108 (with an impurity concentration of, for example, 1×10 ²⁰ /cm ³ , and a depth of 0.5 μm). In addition, a gate insulating film 103 is formed to cover a portion of the base region 106 between the emitter and source region 108 and the resurf region 102 , and a gate electrode 107 is formed on the gate insulating film 103 .

In the surface portion of the resurf region 102, a P-type top semiconductor layer 105 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 1 μm) electrically connected to the base region 106 is formed.

In the surface portion of the RESURF region 102, a P ⁺ -type contact region 109 (with an impurity concentration of, for example, 1×10 ¹⁹ /cm ³ and a depth of 1 μm) is formed in a manner to be isolated from the top semiconductor layer 105 (see FIG. 33 in particular). (a)). Here, the contact region 109 is formed with an impurity concentration much higher than that of the top semiconductor layer 105 to reduce the on-resistance.

Furthermore, in the surface portion of the RESURF region 102, an N ⁺ -type drain region 116 (with an impurity concentration of, for example, 1×10 ²⁰ /cm ^3. The depth is 0.5 μm) (especially refer to FIG. 34 ).

Here, as shown in FIG. 33( b ), the collector region 109 and the drain region 116 are each composed of a plurality of isolated parts. Each part of the collector region 109 and each part of the drain region 116 are alternately provided in a direction perpendicular to the direction from the collector region 109 toward the emitter-source region 108 .

An interlayer film 111 is formed on the semiconductor substrate 101 on which the impurity regions and the like described above are formed via the electric field insulating film 104 formed on the surface of the resurf region 102 .

On the semiconductor substrate 101, a collector and drain electrode 112 and an emitter and source electrode 113 are formed. Both are electrically connected; the emitter and source electrode 113 penetrates the interlayer film 111 and is electrically connected to both the contact region 110 (ie, the base region 106 ) and the emitter and source region 108 .

A protective film 114 is formed on the interlayer film 111 on which the collector/drain electrode 112 and the emitter/source electrode 113 are formed.

In the semiconductor device related to the comparative example, when a forward bias voltage is applied between the collector and drain electrode 112 and the emitter and source electrode 113 (hereinafter, the forward bias voltage is sometimes referred to as the collector voltage), and when a positive voltage is applied to the gate electrode 107, the electron flow (hereinafter, the electron flow is also referred to as the collector current in some places) flows from the drain region 116 to the emitter and source electrode 113, the semiconductor device MOSFET operation is thereby performed. When the flow of electrons flowing to the emitter and source electrode 113, that is, the magnitude of the collector current, reaches a certain level, the potential difference between the potential of the collector region 109 and the potential of the portion surrounding the collector region 109 in the reduced surface electric field region 102 is about At 0.6 V, holes are injected from the collector region 109 into the resurf region 102, whereby the semiconductor device is shifted from MOSFET operation to IGBT operation. FIG. 35 shows the relationship between the collector voltage and the collector current in the semiconductor device according to this comparative example.

In this way, in the semiconductor device according to the comparative example, when the collector current flowing through the element is small, the semiconductor device can be operated as a MOSFET, and the semiconductor device can be operated after the collector current flowing through the element reaches a certain level. Do IGBT work. That is, it is possible to realize a semiconductor device that performs MOSFET operation or IGBT operation according to the amount of collector current flowing through the element.

As a supplementary note, in the semiconductor device according to the comparative example, the collector region 109 and the drain region 116 are respectively composed of a plurality of isolated parts, and in the direction from the collector region 109 toward the emitter-source region 108 In the vertical direction, each part of the collector region 109 and each part of the drain region 116 are alternately arranged. In this way, the length of the collector region 109 in the vertical direction (ie, the direction in which the collector region 109 and the drain region 116 are aligned) can be made short. Therefore, the collector voltage (i.e., the potential difference between the potential of the collector region and the potential of the portion surrounding the collector region in the region where the surface electric field is reduced) can be easily reduced due to the drop in voltage. And the collector voltage (for example, about 1V) at about 0.6V increases. Therefore, by adjusting the value of the collector voltage for switching from MOSFET operation to IGBT operation, a more practical design can be performed, such as expanding the range of collector voltage capable of performing MOSFET operation with high-speed switching performance (that is, designing to have The MOSFET with the high-speed switching function operates until the collector voltage reaches, for example, a voltage value greater than about 1 V). That is, for example, it is possible to freely design the distribution of MOSFET operation with excellent switching characteristics and IGBT operation with low on-resistance.

However, in the semiconductor device performing MOSFET operation or IGBT operation described above as the semiconductor device according to the comparative example, there are the following problems during the operation of the IGBT.

As with bipolar transistors, conductivity modulation occurs in IGBTs, so the conduction loss can be reduced, and the power loss of IGBTs can be made smaller than that of MOSFETs whose chip size is approximately the same as that of IGBTs.

However, in the semiconductor device according to the comparative example, the impurity concentration of the collector region 109 is much higher than that of the top semiconductor layer 105 to reduce the on-resistance. Therefore, when switching from the on state to the off state, it takes a long time to extract the excess carriers remaining inside the semiconductor substrate 101 . Therefore, there occurs a problem that the switching speed of the IGBT is slower than that of the MOSFET, and as a result, the switching loss is large, and the power loss cannot be sufficiently reduced.

In order to cope with the above-mentioned problems, it is conceived as a method of improving the switching speed of the IGBT, such as adopting a technology to limit the service life. However, when this technique is adopted, sacrifices such as an increase in cost and deterioration in characteristics follow. Therefore, this approach is not a good solution.

In addition, in the semiconductor device according to the comparative example, since the collector region 109 is formed at a high impurity concentration much higher than that of the top semiconductor layer 105, it is necessary An N-type buffer layer whose impurity concentration is higher than that of the RESURF region 102 is disposed between them to reduce the efficiency of hole injection from the collector region 109 to the RESURF region 102 . This leads to an increase in the number of process steps, and also creates a new problem of difficulty in switching from MOSFET operation to IGBT operation.

The semiconductor device according to the second embodiment of the present invention described below solves various problems of the semiconductor device according to the above-mentioned comparative example without causing an increase in cost or deterioration of characteristics.

(second embodiment)

Next, a semiconductor device, specifically a high withstand voltage semiconductor switching element, according to a second embodiment of the present invention will be described with reference to the drawings.

8( a ) and FIG. 9 are sectional views of the semiconductor device according to the second embodiment; FIG. 8( b ) is a plan view of the semiconductor device according to the second embodiment. To add an explanation, Fig. 8(a) is a sectional view along the line C-C' in Fig. 8(b); Fig. 9 is a sectional view along the line D-D' in Fig. 8(b). In FIG. 8( b ), illustration of some structural elements is omitted.

As shown in FIG. 8(a), FIG. 8(b) and FIG. 9, in the surface portion of, for example, a P ^- type semiconductor substrate 201 (the impurity concentration is, for example, 1×10 ¹⁴ /cm ³ ), for example It is an N-type resurf region 202 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 7 μm). In addition, a P-type base region 206 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 4 μm) is formed adjacent to the RESURF region 202 in the surface portion of the semiconductor substrate 201 . ).

In the base region 206, a contact region 210 of, for example, P ⁺ type (for example, an impurity concentration of 1×10 ¹⁹ /cm ³ , and a depth of 2 μm) and a contact region of, for example, N ⁺ type emitter and source region 208 (for example, the impurity concentration is 1×10 ²⁰ /cm ³ , and the depth is 0.5 μm). In addition, a gate insulating film 203 is formed covering a portion of the base region 206 between the emitter-source region 208 and the resurf region 202 , and a gate electrode 207 is formed on the gate insulating film 203 .

In addition, if the gate insulating film 203 is formed on the emitter-source region 208, it is possible to prevent the gate electrode 207 and the emitter-source region 208 from being short-circuited.

In the surface portion of the resurf region 202, there is formed, for example, a P-type top semiconductor layer 205 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 1 μm). Although not shown in the drawings, the top semiconductor layer 205 is electrically connected to the base region 206 via a predetermined portion of the resurf region 202 or wiring in an upper layer.

In the surface portion of the RESURF region 202 , a P-type collector region 215 (for example, impurity concentration of 1×10 ¹⁶ /cm ³ , depth of 1 μm) is formed in isolation from the top semiconductor layer 205 . Here, the collector region 215 has substantially the same impurity concentration as that of the top semiconductor layer 205 and is positioned substantially as deep as the top semiconductor layer 205 .

In the surface portion of the collector region 215, a collector contact region 209 of, for example, P ⁺ type (with an impurity concentration of, for example, 1×10 ¹⁹ /cm ³ and a depth of 0.5 μm) is formed. As a supplementary note, the collector contact region 209 may not be formed.

In addition, in the surface portion of the RESURF region 202, an N ⁺ -type drain region 216 (with an impurity concentration of, for example, 1×10 ²⁰ /cm ³ and a depth of 0.5 μm).

Here, as shown in FIG. 8( b ), the collector region 215 and the drain region 216 are each composed of a plurality of isolated parts. In a direction perpendicular to the direction from the collector region 215 toward the emitter-source region 208 (hereinafter, the vertical direction may be referred to as the vertical direction in some places), each part of the collector region 215 and the drain region are alternately arranged. Portions of pole region 216. The length of each part of the collector region 215 in the vertical direction (the length X shown in FIG. 8( b )) is, for example, about 60 μm; The length Y) shown in (b) is, for example, about 30 μm.

An interlayer film 211 is formed on the semiconductor substrate 201 on which the impurity regions and the like described above are formed via the electric field insulating film 204 formed on the surface of the resurf region 202 .

On the semiconductor substrate 201, a collector and drain electrode 212 and an emitter and source electrode 213 are formed. The collector and drain electrode 212 penetrates the interlayer film 211 and contacts the collector contact region 209 (that is, the electrode region 215) and the drain region 216 are electrically connected; the emitter and source electrode 213 penetrates the interlayer film 211, and is electrically connected to the contact region 210 (that is, the base region 206) and the emitter and source region 208. connect.

A protective film 214 is formed on the interlayer film 211 on which the collector/drain electrode 212 and the emitter/source electrode 213 are formed.

In the semiconductor device according to the present embodiment, when a forward bias voltage is applied between the collector-cum-drain electrode 212 and the emitter-source electrode 213 (hereinafter, the forward bias voltage is sometimes referred to as collector electrode voltage), and when a positive voltage is applied to the gate electrode 207, electron flow (hereinafter, the electron flow is also referred to as collector current in some places) flows from the drain region 216 to the emitter and source electrode 213, the semiconductor The device thus performs MOSFET operation. When the flow of electrons flowing to the emitter and source electrode 213, that is, the magnitude of the collector current, reaches a certain level, the potential difference between the potential of the collector region 215 and the potential of the portion surrounding the collector region 215 in the reduced surface electric field region 202 is about At 0.6V, holes are injected from the collector region 215 into the resurf region 202, thereby transferring the semiconductor device from MOSFET operation to IGBT operation.

In this way, in the semiconductor device according to this embodiment, the semiconductor device can be operated as a MOSFET when the collector current flowing through the element is small, and the semiconductor device can be operated after the collector current flowing through the element reaches a certain level. device for IGBT operation. That is, it is possible to realize a semiconductor device that performs MOSFET operation or IGBT operation according to the amount of collector current flowing through the element. In the semiconductor device according to the present embodiment described above, since the impurity concentration of the collector region 215 is set to be substantially the same low concentration as the impurity concentration of the top semiconductor layer 205, it is different from forming a layer with a high impurity concentration (P ⁺ layer). Compared with the case where the collector region is removed (comparative example), the amount of excess carriers injected into the semiconductor substrate 201 including the resurf region 202 during IGBT operation can be suppressed more. As a result, the amount of excess carriers remaining in the semiconductor substrate 201 at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

Fig. 10 is the semiconductor device of this embodiment shown in Fig. 8(a), Fig. 8(b) and Fig. 9 (using a P-type semiconductor layer (with an impurity concentration of 1×10 ¹⁶ /cm ³ and a depth of 1 μm) The device in which the collector region 215 is formed) and the semiconductor device according to the comparative example shown in FIG. 33(a), FIG. 33( ^b ) and ^FIG . cm ³ , the depth is 1 μm) to measure the fall time tf (after the gate is turned off, the collector current drops from 90% of the value immediately before the cutoff to 10% of the value of the element with the collector region 109 formed) The graph obtained by graphing the dependence of the time taken for the process) on the temperature (K), and then graphing the results of the measurement. In addition, in FIG. 10 , the horizontal axis represents the temperature (K), and the vertical axis represents the fall time tf. Assuming that the fall time tf (nsec) at the temperature of 398K in the semiconductor device according to the comparative example is 100%, the fall time is expressed as a percentage of the fall time tf value at 100% for each fall time value tf.

As shown in FIG. 10 , in the semiconductor device of this embodiment in which the collector region 215 is formed at a low impurity concentration substantially the same as that of the P-type top semiconductor layer 205, and the collector region 215 is formed with the P ⁺ -type semiconductor layer. Compared with the comparative example in the electrode region, the fall time tf was significantly improved at various temperatures.

Fig. 11 is the semiconductor device of this embodiment shown in Fig. 8(a), Fig. 8(b) and Fig. 9 (using a P-type semiconductor layer (with an impurity concentration of 1×10 ¹⁶ /cm ³ and a depth of 1 μm) The device in which the collector region 215 is formed) and the semiconductor device according to the comparative example shown in FIG. 33(a), FIG. 33( ^b ) and ^FIG . cm ³ and a depth of 1 μm) to measure the dependence of on-resistance Ron on temperature (K) and to graph the results of the measurement. As a supplementary note, in FIG. 11 , the horizontal axis represents the temperature (K), and the vertical axis represents the on-resistance Ron. Assuming that the on-resistance Ron (Ω) at the temperature of 223K in the semiconductor device of the present example is 100%, it is expressed in terms of the percentage of the on-resistance Ron value at 100% for each on-resistance value On-resistance Ron.

As shown in FIG. 11 , in the semiconductor device of this embodiment in which the collector region 215 is formed at a low impurity concentration substantially the same as that of the P-type top semiconductor layer 205, the P ⁺ -type semiconductor layer can also be obtained. The on-resistance values of the comparative examples in the collector region were substantially the same. Although the on-resistance value of the semiconductor device of this embodiment is slightly higher in the temperature range below 250K, the actual use range of the semiconductor device is about 250K to 400K (-20°C to 140°C), so there is no question.

As can be seen from the measurement results in FIGS. 10 and 11 described above, in the semiconductor device of this embodiment in which the collector region 215 is formed at a low impurity concentration substantially the same as that of the P-type top semiconductor layer 205, it is possible to obtain The effect of greatly reducing the switching loss without increasing the loss caused by the on-resistance Ron.

In the comparative example in which the collector region was formed with a high impurity concentration layer (P ⁺ -type semiconductor layer), it is necessary to provide an N-type buffer layer whose impurity concentration is higher than that of the resurf region between the collector region and the resurf region , to reduce the efficiency of hole injection from the collector region to the RESURF region. In contrast, in the semiconductor device of this embodiment, since the collector region 215 is formed with a low impurity concentration, it is not necessary to provide an N-type buffer layer, and the process can be simplified. Furthermore, it is possible to avoid a situation in which switching from MOSFET operation to IGBT operation becomes more difficult due to the provision of the N-type buffer layer as in the comparative example.

As a supplementary explanation, in the manufacturing method of the semiconductor device (switching element) of the present embodiment shown in FIG. 8(a), FIG. 8(b) and FIG. Each process shown in 7 is carried out in the same manner to be used to make each process of the structure along the CC' line of Fig. 8 (b) (that is, Fig. 8 (a)) each process, thus omit these processes illustrate. If you want to carry out the process of making the structure of the cross-sectional view (that is, FIG. 9 ) along the DD' line of FIG. In the process shown in FIG. 5 in the embodiment, the N ⁺ -type drain region 216 is formed simultaneously with the formation of the N ⁺ -type emitter region 208 . In addition, the impurity concentration of the drain region 216 is, for example, about 1×10 ²⁰ /cm ³ , and the formation depth of the drain region 216 is, for example, about 0.5 μm.

(third embodiment)

Next, a semiconductor device, specifically a high withstand voltage semiconductor switching element, according to a third embodiment of the present invention will be described with reference to the drawings.

12(a) is a cross-sectional view of the semiconductor device according to the third embodiment; FIG. 12(b) is a plan view of the semiconductor device according to the third embodiment. As an additional note, Fig. 12(a) is a cross-sectional view along line E-E' in Fig. 12(b). The sectional view along the FF' line in Fig. 12(b) is the same as the following figure, that is, the second embodiment shown in Fig. 8(a), Fig. 8(b) and Fig. 9 The cross-sectional view of the semiconductor device is equivalent to FIG. 9 , in which an embedded semiconductor layer 217 described later is formed instead of the top semiconductor layer 205 . In FIG. 12( b ), illustration of some structural elements is omitted.

As shown in FIG. 12(a), FIG. 12(b) and FIG. 9, in the surface portion of, for example, a P ^- type semiconductor substrate 201 (the impurity concentration is, for example, 1×10 ¹⁴ /cm ³ ), for example The resurf region 202 is N-type (for example, the impurity concentration is 2×10 ¹⁶ /cm ³ , and the depth is 7 μm). In addition, a P-type base region 206 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 4 μm) is formed adjacent to the RESURF region 202 in the surface portion of the semiconductor substrate 201 . ).

In the base region 206, a contact region 210 of, for example, P ⁺ type (for example, an impurity concentration of 1×10 ¹⁹ /cm ³ , and a depth of 2 μm) and a contact region of, for example, N ⁺ type emitter and source region 208 (for example, the impurity concentration is 1×10 ²⁰ /cm ³ , and the depth is 0.5 μm). In addition, a gate insulating film 203 is formed covering a portion of the base region 206 between the emitter-source region 208 and the resurf region 202 , and a gate electrode 207 is formed on the gate insulating film 203 .

In addition, if the gate insulating film 203 is formed on the emitter region 208, it is possible to prevent the gate electrode 207 and the emitter region 208 from being short-circuited.

In the RESURF region 202 , for example, a P-type buried semiconductor layer 217 (with an impurity concentration of, for example, 2×10 ¹⁶ /cm ³ ) is formed. The buried semiconductor layer 217 is formed along the depth direction from, for example, a depth of about 1 μm (Z in FIG. 12( a )) based on the surface of the substrate 201 . The width (W in FIG. 12( a )) of the buried semiconductor layer 217 is, for example, about 1 μm. Although not shown in the drawings, the buried semiconductor layer 217 is electrically connected to the base region 206 via a predetermined portion of the resurf region 202 or wiring in an upper layer.

In the resurf region 202 , for example, a P-type collector region 218 (with an impurity concentration of, for example, 2×10 ¹⁶ /cm ³ ) is formed so as to be isolated from the buried semiconductor layer 217 . Here, the collector region 218 has substantially the same impurity concentration as that of the buried semiconductor layer 217 and is positioned substantially as deep as the buried semiconductor layer 217 . In addition, in the surface portion of the resurf region 202, a collector contact region 219 of, for example, P ⁺ type (with an impurity concentration of, for example, 1×10 ¹⁹ /cm ³ and a depth of 1 μm).

In addition, in the surface portion of the RESURF region 202, for example, an N ⁺ -type drain region 216 (with an impurity concentration of, for example, 1×1020/cm ³ and a depth of 0.5 μm).

Here, as shown in FIG. 12( b ), the collector region 218 and the drain region 216 are each composed of a plurality of isolated parts. In a direction perpendicular to the direction from the collector region 218 toward the emitter-source region 208 (hereinafter, the vertical direction may be referred to as the vertical direction in some places), each part of the collector region 218 and the drain region are alternately arranged. Portions of pole region 216. The length of each part of the collector region 218 in the vertical direction (the length X shown in FIG. 12( b )) is, for example, about 60 μm; The length Y) shown in (b) is, for example, about 30 μm.

An interlayer film 211 is formed on the semiconductor substrate 201 on which the impurity regions and the like described above are formed via the electric field insulating film 204 formed on the surface of the resurf region 202 .

On the semiconductor substrate 201, a collector and drain electrode 212 and an emitter and source electrode 213 are formed. The collector and drain electrode 212 penetrates the interlayer film 211 and contacts the collector contact region 219 (that is, the electrode region 218) and the drain region 216 are electrically connected; the emitter and source electrode 213 penetrates the interlayer film 211, and is electrically connected to the contact region 210 (that is, the base region 206) and the emitter and source region 208. connect.

A protective film 214 is formed on the interlayer film 211 on which the collector/drain electrode 212 and the emitter/source electrode 213 are formed.

In the semiconductor device according to the present embodiment, when a forward bias voltage is applied between the collector-cum-drain electrode 212 and the emitter-source electrode 213 (hereinafter, the forward bias voltage is sometimes referred to as collector electrode voltage), and when a positive voltage is applied to the gate electrode 207, electron flow (hereinafter, the electron flow is also referred to as collector current in some places) flows from the drain region 216 to the emitter and source electrode 213, the semiconductor The device thus performs MOSFET operation. When the magnitude of the electron current flowing to the emitter and source electrode 213, that is, the collector current, reaches a certain level, the potential difference between the potential of the collector region 218 and the potential of the portion surrounding the collector region 218 in the reduced surface electric field region 202 is about At 0.6V, holes are injected from the collector region 218 into the resurf region 202, thereby transferring the semiconductor device from MOSFET operation to IGBT operation.

In this way, in the semiconductor device according to this embodiment, the semiconductor device can be operated as a MOSFET when the collector current flowing through the element is small, and the semiconductor device can be operated after the collector current flowing through the element reaches a certain level. device for IGBT operation. That is, it is possible to realize a semiconductor device that performs MOSFET operation or IGBT operation according to the amount of collector current flowing through the element. In the semiconductor device according to the above-mentioned embodiment, since the impurity concentration of the collector region 218 is set to be substantially the same low concentration as the impurity concentration of the buried semiconductor layer 217, it is different from the high impurity concentration layer (P ⁺ layer). ) in which the collector region is formed (comparative example), the amount of excess carriers injected into the semiconductor substrate 201 including the resurf region 202 during IGBT operation can be suppressed more. As a result, the amount of excess carriers remaining in the semiconductor substrate 201 at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

In particular, in the semiconductor device (switching element) of this embodiment, since the buried semiconductor layer 217 is formed in the RESURF region 202 in the semiconductor device, it is possible to form power dissipation devices in both upper and lower directions from the buried semiconductor layer. Do the best. Therefore, the impurity concentration of the resurf region 202 can be made higher than in the case where the top semiconductor layer 205 is formed (the second embodiment), and the switching speed can be improved and the on-resistance can be reduced.

In the case where the collector region is formed with a high impurity concentration layer (P ⁺ -type semiconductor layer), it is necessary to provide an N-type buffer layer whose impurity concentration is higher than that of the resurf region between the collector region and the resurf region, To reduce the efficiency of hole injection from the collector region to the RESURF region. In contrast, in the semiconductor device of this embodiment, since the collector region 218 is formed with a low impurity concentration, it is not necessary to provide an N-type buffer layer, and the process can be simplified. Furthermore, it is possible to avoid a situation in which switching from MOSFET operation to IGBT operation becomes more difficult due to the provision of the N-type buffer layer as in the comparative example.

As a supplementary note, this embodiment describes the structure in which the drain region 216 is formed, that is, the structure in which the MOSFET operation is switched to the IGBT operation. However, as described in the first embodiment, even in the case where the drain region 216 is not provided, that is, when the lateral IGBT is configured, the same effect as that of the present embodiment can be obtained. This effect reduces the loss in the entire range from a small load to a heavy load.

Next, an example of a method of manufacturing the switching element of this embodiment shown in FIGS. 12(a), 12(b) and 9 will be described with reference to the sectional views of FIGS. 13 to 18. FIG.

First, in the process shown in FIG. 13, a P ^- type semiconductor substrate 201 having an impurity concentration of, for example, about 1×10 ¹⁴ /cm ³ is prepared.

Next, in the process shown in FIG. 14 , for example, an N-type resurf region 202 is selectively formed in the surface portion of the semiconductor substrate 201 by, for example, phosphorus ion implantation. The impurity concentration of the resurf region 202 is, for example, about 2×10 ¹⁶ /cm ³ , and the formation depth of the resurf region 202 is, for example, about 7 μm. Thereafter, a base region 206 of, for example, P-type is formed in the surface portion of the semiconductor substrate 201 by, for example, boron ion implantation. The base region 206 is formed adjacent to the resurf region 202 . The impurity concentration of the base region 206 is, for example, about 1×10 ¹⁶ /cm ³ , and the formation depth of the base region 206 is, for example, 4 μm. Further, an electric field insulating film 204 having a thickness of, for example, 500 nm is selectively formed on the surface of the resurf region 202 by, for example, wet oxidation or the like.

Next, in the process shown in FIG. 15 , for example, a P-type buried semiconductor layer 217 and, for example, a P-type collector electrode are simultaneously and selectively formed in the RESURF region 202 by high-energy boron ion implantation. Area 218. Here, the buried semiconductor layer 217 and the collector region 218 are formed to be separated from each other. The impurity concentration of the buried semiconductor layer 217 and the impurity concentration of the collector region 218 are, for example, about 2×10 ¹⁶ /cm ³ , respectively. The buried semiconductor layer 217 and the collector region 218 are respectively formed in the depth direction from a depth of about 1 μm (Z in FIG. 12( a )) based on the surface of the substrate 201 . The width (W in FIG. 12( a )) of the buried semiconductor layer 217 and the collector region 218 is, for example, about 1 μm. At this time, since the buried semiconductor layer 217 is formed by ion implantation through the electric field insulating film 204 , the formation depth of the collector region 218 is slightly greater than the formation depth of the buried semiconductor layer 217 .

In addition, although not shown in the drawings, the buried semiconductor layer 217 is formed to be electrically connected to the base region 206 .

In this embodiment, the order of ion implantation performed to form the respective impurity regions is not limited.

Next, in the step shown in FIG. 16 , the gate insulating film 203 is formed to cover a portion of the base region 206 between the emitter-source region 208 described later and the resurf region 202 , for example, by thermal oxidation. . Thereafter, a gate electrode 207 made of, for example, polysilicon is selectively formed on the gate insulating film 203 . In addition, using the gate electrode 207 and an unshown resist pattern as a mask, for example, an N ⁺ -type emitter-source electrode is selectively formed in the base region 206 by self-alignment, for example, by arsenic ion implantation. region 208 , and at the same time selectively form, for example, an N ⁺ -type drain region 216 in the RESURF region 202 by self-alignment (for the drain region 216 , refer to FIG. 12( b ) and FIG. 9 ). The emitter-source region 208 is formed to be isolated from the RESURF region 202 , and the drain region 216 is formed to be isolated from the buried semiconductor layer 217 . The impurity concentrations of the emitter-source region 208 and the drain region 216 are, for example, about 1×10 ²⁰ /cm ³ , and the formation depths of the emitter-source region 208 and the drain region 216 are, for example, about 0.5 μm.

Next, in the process shown in FIG. 17 , for example, a P ⁺ -type contact region 210 is formed in the base region 206 by, for example, boron ion implantation. The contact region 210 is formed to be isolated from the RESURF region 202 . The impurity concentration of the contact region 210 is, for example, about 1×10 ¹⁹ /cm ³ , and the formation depth of the contact region 210 is, for example, 2 μm. Thereafter, a collector contact region 219 of, for example, P ⁺ type, in contact with the collector region 218 is formed in the surface portion of the resurf region 202 by, for example, boron ion implantation. The impurity concentration of the collector contact region 219 is, for example, about 1×10 ¹⁹ /cm ³ , and the formation depth of the collector contact region 219 is, for example, 1 μm.

Next, in the process shown in FIG. 18, an interlayer film 211 is formed on the semiconductor substrate 201 including the electric field insulating film 204 and the gate electrode 207 by, for example, atmospheric pressure CVD, and then the interlayer film 211 is formed. The prescribed part of the opening is opened, and then the collector and drain electrode 212 and the emitter and source electrode 213 are respectively formed on the semiconductor substrate 201. The collector and drain electrode 212 is connected to the collector contact region 219 (that is, the collector region 218 ) and drain region 216 ; the emitter-source electrode 213 is electrically connected to contact region 210 (ie, base region 206 ) and emitter-source region 208 . Finally, after forming a protective film 214 made of, for example, a plasma silicon nitride film on the interlayer film 211, the spacer formation region in the protective film 214 is opened. Thus, the switching element of this embodiment shown in Fig. 12(a), Fig. 12(b) and Fig. 9 is completed.

According to the manufacturing method of this embodiment described above, since the buried semiconductor layer 217 and the collector region 218 are formed through the same impurity implantation process, compared with the case where the buried semiconductor layer 217 and the collector region 218 are formed separately , the number of processes can be reduced, and the cost can be reduced.

(fourth embodiment)

Next, a semiconductor device according to a fourth embodiment of the present invention, specifically a high withstand voltage semiconductor switching element, will be described with reference to the drawings.

FIG. 19 shows a cross-sectional structure of a semiconductor device according to the fourth embodiment. As shown in FIG. 19, in the surface portion of, for example, a P ^- type semiconductor substrate 201 (with an impurity concentration of 1×10 ¹⁴ /cm ³ ), for example, an N-type RESURF region 202 (with an impurity concentration of For example, 1×10 ¹⁶ /cm ³ and a depth of 7 μm). In addition, a P-type base region 206 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 4 μm) is formed adjacent to the RESURF region 202 in the surface portion of the semiconductor substrate 201 . ).

In the base region 206, a contact region 210 of, for example, P ⁺ type (for example, an impurity concentration of 1×10 ¹⁹ /cm ³ , and a depth of 2 μm) and a contact region of, for example, N ⁺ type emitter region 208 (the impurity concentration is, for example, 1×10 ²⁰ /cm ³ , and the depth is 0.5 μm). Further, a first gate insulating film 203 covering a portion of the base region 206 between the emitter region 208 and the resurf region 202 is formed, and a first gate electrode is formed on the first gate insulating film 203 . 207.

As an additional note, if the first gate insulating film 203 is formed on the emitter region 208 , it is possible to prevent the short circuit between the first gate electrode 207 and the emitter region 208 .

In the surface portion of the resurf region 202, there is formed, for example, a P-type top semiconductor layer 205 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 1 μm). Although not shown in the drawings, the top semiconductor layer 205 is electrically connected to the base region 206 via a predetermined portion of the resurf region 202 or wiring in an upper layer.

In the surface portion of the RESURF region 202 , a P-type collector region 215 (for example, impurity concentration of 1×10 ¹⁶ /cm ³ , depth of 1 μm) is formed in isolation from the top semiconductor layer 205 . Here, the collector region 215 has substantially the same impurity concentration as that of the top semiconductor layer 205 and is positioned substantially as deep as the top semiconductor layer 205 .

In the surface portion of the collector region 215, a collector contact region 209 of, for example, P ⁺ type (with an impurity concentration of, for example, 1×10 ¹⁹ /cm ³ and a depth of 0.5 μm) is formed. As a supplementary note, the collector contact region 209 may not be formed.

On the resurf region 202, a second gate insulating film 220 extending from the collector region 215 to the top semiconductor layer 205 is formed. On a portion of the second gate insulating film 220 between the collector region 215 and the top semiconductor layer 205 , a second gate electrode 221 is formed. Although not shown in the drawings, the second gate electrode 221 is electrically connected to the first gate electrode 207 via a wiring for a gate electrode, a wiring located in an upper layer, or the like.

An interlayer film 211 is formed on the semiconductor substrate 201 on which the aforementioned impurity regions, gate electrodes, and the like are formed.

On the semiconductor substrate 201, a collector electrode 212 and an emitter electrode 213 are formed. The collector electrode 212 penetrates the interlayer film 211 and is electrically connected to the collector contact region 209 (ie, the collector region 215); The pole electrode 213 penetrates the interlayer film 211 and is electrically connected to both the contact region 210 (ie, the base region 206 ) and the emitter region 208 .

A protective film 214 is formed on the interlayer film 211 on which the collector electrode 212 and the emitter electrode 213 are formed.

In the semiconductor device of this embodiment, a forward bias is applied between the collector electrode 212 and the emitter electrode 213 (to make the potential on the side of the collector electrode 212 higher), and on the first gate electrode 207 When a positive voltage is applied, when the potential difference between the potential of the collector region 215 and the potential of the portion surrounding the collector region 215 in the resurf region 202 reaches approximately 0.6 V, holes flow from the collector region 215 Implanted into the RESURF region 202, the semiconductor device starts IGBT operation. That is, the semiconductor device (switching element) of this embodiment is a lateral IGBT.

According to the semiconductor device (switching element) of this embodiment, because when the switching element is turned off (if the voltage of the emitter electrode 213 is 0V, the voltages of the first gate electrode 207 and the second gate electrode 221 are both changed from 6V to 0V), the electric potential of the portion between the collector region 215 and the top semiconductor layer 205 in the reduced surface electric field region 202 (hereinafter, the potential is also referred to as the collector potential in some places) rises, so the collector The P-channel MOSFET formed in a part of the electrode region 215 is turned on. In this way, excess carriers remaining in the RESURF region 202 can be extracted from the collector region 215 through the path passing through the P-channel MOSFET, the top semiconductor layer 205 , the base region 206 and the contact region 210 . Furthermore, excess carriers remaining in the resurf region 202 can also be extracted from the top semiconductor layer 205 . Therefore, the fall time (tf) can be shortened, in other words, the time required to extract carriers can be shortened to improve the switching speed. Therefore, it is possible to reduce the switching loss.

As a supplementary note, in this embodiment, after the collector potential is raised to extract the excess carriers (holes) remaining in the resurf region 202 when it is turned off, the depletion layer flows from the top semiconductor layer 205 to The resurf region 202 expands so that hole current flowing from the collector electrode 212 through the path including the P-channel MOSFET can be blocked. Therefore, the withstand voltage characteristics of the element do not deteriorate.

According to the semiconductor device of this embodiment, since the impurity concentration of the collector region 215 is set to be substantially the same low concentration as the impurity concentration of the top semiconductor layer 205, it is different from that in which the collector region is formed with a high impurity concentration layer (P ⁺ layer). Compared with the case, the amount of excess carriers injected into the semiconductor substrate 201 including the resurf region 202 during the operation of the IGBT can be suppressed more. As a result, the amount of excess carriers remaining in the semiconductor substrate 201 at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

In the case where the collector region is formed with a high impurity concentration layer, it is necessary to provide, for example, an N-type buffer layer whose impurity concentration is higher than that of the resurf region between the collector region and the resurf region to reduce the The collector region is injected to reduce the surface electric field region for hole injection efficiency. In contrast, in the semiconductor device of this embodiment, since the collector region 215 is formed with a low impurity concentration, it is not necessary to provide an N-type buffer layer, and the process can be simplified.

As a supplementary note, in this embodiment, a structure without forming a drain region is described, that is, a structure without switching from MOSFET operation to IGBT operation. However, as described in the second and third embodiments, even when the drain region is provided, the same effect as that of the present embodiment can be obtained. The effect of reducing loss in the entire range from hours to heavy loads. In this case, it may also be such that the collector region 215 and the drain region are each composed of separate parts, and in the direction from the collector region 215 towards the emitter region 208 (in this case, Each part of the collector region 215 and each part of the drain region are alternately arranged in a direction perpendicular to the direction of the emitter and source region).

Next, an example of the method of manufacturing the switching element of the present embodiment shown in FIG. 19 will be described with reference to the sectional views of FIGS. 20 to 25 .

First, in the process shown in ^{FIG .} 20 , for example, phosphorus ion implantation is used to selectively ^form , for example, N-type The RESURF region 202 of . The impurity concentration of the resurf region 202 is, for example, about 1×10 ¹⁶ /cm ³ , and the formation depth of the resurf region 202 is, for example, about 7 μm.

Next, in the process shown in FIG. 21, a top semiconductor layer 205 such as a P-type and a collector electrode such as a P-type are simultaneously and selectively formed in the surface portion of the RESURF region 202 by, for example, boron ion implantation. Area 215. Here, the top semiconductor layer 205 and the collector region 215 are formed to be separated from each other. The impurity concentration of the top semiconductor layer 205 and the impurity concentration of the collector region 215 are respectively about 1×10 ¹⁶ /cm ³ , for example. The formation depths of the top semiconductor layer 205 and the collector region 215 are, for example, about 1 μm.

In addition, although not shown in the drawings, the top semiconductor layer 205 is formed to be electrically connected to the base region 206 described later.

Next, in the process shown in FIG. 22 , for example, a P-type base region 206 is formed in the surface portion of the semiconductor substrate 201 by, for example, boron ion implantation. The base region 206 is formed adjacent to the resurf region 202 . The impurity concentration of the base region 206 is, for example, about 1×10 ¹⁶ /cm ³ , and the formation depth of the base region 206 is, for example, 4 μm. Further, second gate insulating film 220 extending from collector region 215 onto top semiconductor layer 205 to a thickness of, for example, 500 nm is selectively formed on the surface of resurf region 202 by, for example, wet oxidation or the like. At this time, the impurity of the top semiconductor layer 205 diffuses, so that the impurity concentration of the top semiconductor layer 205 drops a little.

It should be added that in this embodiment, the sequence of ion implantation performed to form the impurity regions is not limited.

Next, in the step shown in FIG. 23 , the first gate insulating film 203 is formed to cover a portion of the base region 206 between the emitter region 208 and the resurf region 202 described later, for example, by thermal oxidation. After that, a first gate electrode 207 made of, for example, polysilicon is selectively formed on the first gate insulating film 203 . At this time, a second gate electrode made of polysilicon, for example, is selectively formed on a portion of the second gate insulating film 220 between the collector region 215 and the top semiconductor layer 205 simultaneously with the formation of the first gate electrode 207 . gate electrode 221 . In addition, using the first gate electrode 207 as a mask, an emitter region 208 of, for example, N ⁺ type is selectively formed in the base region 206 by self-alignment, for example, by arsenic ion implantation or the like. The emitter region 208 is formed to be isolated from the resurf region 202 . The impurity concentration of the emitter region 208 is, for example, about 1×10 ²⁰ /cm ³ , and the formation depth of the emitter region 208 is, for example, about 0.5 μm.

Next, in the process shown in FIG. 24 , for example, a P ⁺ -type contact region 210 is formed in the base region 206 by, for example, boron ion implantation. The contact region 210 is formed to be isolated from the RESURF region 202 . The impurity concentration of the contact region 210 is, for example, about 1×10 ¹⁹ /cm ³ , and the formation depth of the contact region 210 is, for example, 2 μm. Thereafter, a collector contact region 209 of, for example, P ⁺ type is formed in a surface portion of the collector region 215 by, for example, boron ion implantation. The impurity concentration of the collector contact region 209 is, for example, about 1×10 ¹⁹ /cm ³ , and the formation depth of the collector contact region 209 is, for example, 0.5 μm. As a supplementary note, the collector contact region 209 may not be formed.

Next, in the process shown in FIG. 25 , an interlayer film 211 is formed on the semiconductor substrate 201 on which the impurity regions and gate electrodes and the like are formed, for example, by atmospheric pressure CVD, and then the interlayer film 211 is made to have a defined thickness. part of the opening, and then form a collector electrode 212 and an emitter electrode 213 on the semiconductor substrate 201, the collector electrode 212 is electrically connected to the collector contact region 209 (that is, the collector region 215); the emitter electrode 213 is connected to the contact Both region 210 (ie, base region 206 ) and emitter region 208 are electrically connected. Finally, after forming a protective film 214 made of, for example, a plasma silicon nitride film on the interlayer film 211, the spacer formation region in the protective film 214 is opened. Thus, the switching element of this embodiment shown in FIG. 19 is formed.

According to the manufacturing method of this embodiment described above, since the top semiconductor layer 205 and the collector region 215 are formed through the same impurity implantation process, compared with the case where the top semiconductor layer 205 and the collector region 215 are formed separately, the process can be simplified. Fewer quantities can reduce costs.

(fifth embodiment)

Next, a semiconductor device according to a fifth embodiment of the present invention, specifically a high withstand voltage semiconductor switching element, will be described with reference to the drawings.

FIG. 26 shows a cross-sectional structure of a semiconductor device according to the fifth embodiment. As shown in FIG. 26, in the surface portion of, for example, a P ^- type semiconductor substrate 201 (with an impurity concentration of 1×10 ¹⁴ /cm ³ ), for example, an N-type RESURF region 202 (with an impurity concentration of For example, 2×10 ¹⁶ /cm ³ and a depth of 7 μm). In addition, a P-type base region 206 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 4 μm) is formed adjacent to the RESURF region 202 in the surface portion of the semiconductor substrate 201 . ).

In the base region 206, a contact region 210 of, for example, P ⁺ type (for example, an impurity concentration of 1×10 ¹⁹ /cm ³ , and a depth of 2 μm) and a contact region of, for example, N ⁺ type emitter region 208 (the impurity concentration is, for example, 1×10 ²⁰ /cm ³ , and the depth is 0.5 μm). Further, a first gate insulating film 203 covering a portion of the base region 206 between the emitter region 208 and the resurf region 202 is formed, and a first gate electrode is formed on the first gate insulating film 203 . 207.

As an additional note, if the first gate insulating film 203 is formed on the emitter region 208 , it is possible to prevent the short circuit between the first gate electrode 207 and the emitter region 208 .

In the surface portion of the resurf region 202, a top semiconductor layer 222 of, for example, P-type (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 1 μm) is formed.

On the lower side of the top semiconductor layer 222 in the RESURF region 202, a P-type buried semiconductor layer 217 (with an impurity concentration of, for example, 2×10 ¹⁶ /cm ³ ) is formed in contact with the top semiconductor layer 222. ). The buried semiconductor layer 217 is formed along the depth direction from a depth of about 1 μm based on the surface of the substrate 201 . The width of the buried semiconductor layer 217 is, for example, about 1 μm. Although not shown in the drawings, the buried semiconductor layer 217 is electrically connected to the base region 206 via a predetermined portion of the resurf region 202 or wiring in an upper layer. That is to say, the top semiconductor layer 222 and the base region 206 are electrically connected to each other via the buried semiconductor layer 217 .

In the surface portion of the RESURF region 202 , a P-type collector region 215 (with an impurity concentration of, for example, 1×10 ¹⁶ /cm ³ and a depth of 1 μm) is formed in isolation from the top semiconductor layer 222 . Here, the collector region 215 has substantially the same impurity concentration as that of the top semiconductor layer 222 and is positioned substantially as deep as the top semiconductor layer 222 .

It should be added that the buried semiconductor layer 217 is formed in the portion from the vicinity of the collector region 215 to the vicinity of the base region 206 in the RESURF region 202 , while the top semiconductor layer 222 is formed only in the RESURF region 202 around the collector region 215 only. In a direction perpendicular to the direction from the collector region 215 toward the base region 206 , the top semiconductor layer 222 is composed of a plurality of portions isolated from each other. This is arranged to secure a path for extracting carriers described later.

In the surface portion of the collector region 215, a collector contact region 209 of, for example, P ⁺ type (with an impurity concentration of, for example, 1×10 ¹⁹ /cm ³ and a depth of 0.5 μm) is formed. As a supplementary note, the collector contact region 209 may not be formed.

On the resurf region 202, a second gate insulating film 220 extending from the collector region 215 to at least the top semiconductor layer 222 is formed. On a portion of the second gate insulating film 220 between the collector region 215 and the top semiconductor layer 222 , a second gate electrode 221 is formed. Although not shown in the drawings, the second gate electrode 221 is electrically connected to the first gate electrode 207 via a wiring for a gate electrode, a wiring located in an upper layer, or the like.

An interlayer film 211 is formed on the semiconductor substrate 201 on which the aforementioned impurity regions, gate electrodes, and the like are formed.

On the semiconductor substrate 201, a collector electrode 212 and an emitter electrode 213 are formed. The collector electrode 212 penetrates the interlayer film 211 and is electrically connected to the collector contact region 209 (ie, the collector region 215); The pole electrode 213 penetrates the interlayer film 211 and is electrically connected to both the contact region 210 (ie, the base region 206 ) and the emitter region 208 .

A protective film 214 is formed on the interlayer film 211 on which the collector electrode 212 and the emitter electrode 213 are formed.

The operation of the switching element in the semiconductor device of this embodiment is basically the same as that of the fourth embodiment. That is, when a forward bias voltage is applied between the collector electrode 212 and the emitter electrode 213 (to make the potential on the side of the collector electrode 212 higher), and a positive voltage is applied to the first gate electrode 207 Next, when the potential difference between the potential of the collector region 215 and the potential of the portion surrounding the collector region 215 in the resurf region 202 reaches approximately 0.6 V, holes are injected from the collector region 215 into the resurf region 202 . In region 202, the semiconductor device starts to perform IGBT operation. In other words, the semiconductor device (switching element) of this embodiment is a lateral IGBT.

According to the semiconductor device (switching element) of this embodiment, because when the switching element is turned off (if the voltage of the emitter electrode 213 is 0V, the voltages of the first gate electrode 207 and the second gate electrode 221 are both changed from 6V to 0V), the electric potential of the portion between the collector region 215 and the top semiconductor layer 222 in the reduced surface electric field region 202 (hereinafter, the potential is also referred to as the collector potential in some places) rises, so the collector The P-channel MOSFET formed in a part of the electrode region 215 is turned on. Like this, just can use the path that passes through described P channel MOSFET, top semiconductor layer 222, buried type semiconductor layer 217, base region 206 and contact region 210 to extract from collector region 215 remaining in the reduced surface electric field region 202. excess carriers. Furthermore, excess carriers remaining in the resurf region 202 can be extracted from the top semiconductor layer 222 and the buried semiconductor layer 217 . Therefore, the fall time (tf) can be shortened, in other words, the time required to extract carriers can be shortened to improve the switching speed. Therefore, it is possible to reduce the switching loss.

As a supplementary note, in this embodiment, after the collector potential is raised to extract the excess carriers (holes) remaining in the RESURF region 202 when it is turned off, the depletion layer is removed from the top semiconductor layer 222 and The buried semiconductor layer 217 expands into the resurf region 202 so that the hole current flowing from the collector electrode 212 through the path including the P-channel MOSFET can be blocked. Therefore, the withstand voltage characteristics of the element do not deteriorate.

According to the semiconductor device of this embodiment, since the impurity concentration of the collector region 215 is set to be substantially the same low concentration as that of the top semiconductor layer 222, it is different from the case where the collector region is formed with a high impurity concentration layer (P ⁺ layer). Compared with the case, the amount of excess carriers injected into the semiconductor substrate 201 including the resurf region 202 during the operation of the IGBT can be suppressed more. As a result, the amount of excess carriers remaining in the semiconductor substrate 201 at the time of off can be reduced. Therefore, the time required for extracting the carriers can be shortened, the switching speed can be improved, and the switching loss can be reduced. In other words, it is possible to realize a high withstand voltage semiconductor device capable of reducing loss over the entire range from a small load to a heavy load.

In the case where the collector region is formed with a high impurity concentration layer, it is necessary to provide, for example, an N-type buffer layer whose impurity concentration is higher than that of the resurf region between the collector region and the resurf region to reduce the The collector region is injected to reduce the surface electric field region for hole injection efficiency. In contrast, in the semiconductor device of this embodiment, since the collector region 215 is formed with a low impurity concentration, it is not necessary to provide an N-type buffer layer, and the process can be simplified.

According to the semiconductor device of the present embodiment, since the embedded semiconductor layer 217 is also formed in the RESURF region 202, a depletion layer can be formed from the embedded semiconductor layer 217 in both upper and lower directions, and thus is different from that in the RESURF region 202. Compared with the case where only the top semiconductor layer 205 is formed in the electric field region 202 (fourth embodiment), the impurity concentration of the resurf region 202 can be made higher, thereby improving the switching speed and reducing the on-resistance.

As a supplementary note, in this embodiment, a structure without forming a drain region is described, that is, a structure without switching from MOSFET operation to IGBT operation. However, as described in the second and third embodiments, even when the drain region is provided, the same effect as that of the present embodiment can be obtained. The effect of reducing loss in the entire range from hours to heavy loads. In this case, it may also be such that the collector region 215 and the drain region are each composed of separate parts, and in the direction from the collector region 215 towards the emitter region 208 (in this case, Each part of the collector region 215 and each part of the drain region are alternately arranged in a direction perpendicular to the direction of the emitter and source region).

Next, an example of the method of manufacturing the switching element of the present embodiment shown in FIG. 26 will be described with reference to the sectional views of FIGS. 27 to 32 .

First, in the process ^shown in FIG ^{. 27} , for example, phosphorus ion implantation is used to selectively form, for example, N-type The RESURF region 202 of . The impurity concentration of the resurf region 202 is, for example, about 2×10 ¹⁶ /cm ³ , and the formation depth of the resurf region 202 is, for example, about 7 μm.

Next, in the process shown in FIG. 28 , for example, boron ion implantation is used to simultaneously and selectively form, for example, a P-type top semiconductor layer 222 and, for example, a P-type collector electrode in the surface portion of the RESURF region 202 . Area 215. Here, the top semiconductor layer 222 and the collector region 215 are formed to be separated from each other. The impurity concentration of the top semiconductor layer 222 and the impurity concentration of the collector region 215 are respectively about 1×10 ¹⁶ /cm ³ , for example. The formation depths of the top semiconductor layer 222 and the collector region 215 are, for example, about 1 μm.

Next, in the process shown in FIG. 29 , for example, a P-type base region 206 is formed in the surface portion of the semiconductor substrate 201 by, for example, boron ion implantation. The base region 206 is formed adjacent to the resurf region 202 . The impurity concentration of the base region 206 is, for example, about 1×10 ¹⁶ /cm ³ , and the formation depth of the base region 206 is, for example, 4 μm. Further, second gate insulating film 220 extending from collector region 215 to at least top semiconductor layer 222 to a thickness of, for example, 500 nm is selectively formed on the surface of resurf region 202 by, for example, wet oxidation or the like. At this time, the impurity of the top semiconductor layer 222 diffuses, so that the impurity concentration of the top semiconductor layer 222 drops a little.

Afterwards, a P-type buried semiconductor layer 217 is selectively formed on the lower side of the top semiconductor layer 222 in the RESURF region 202 adjacent to the top semiconductor layer 222 by, for example, high-energy boron ion implantation. The impurity concentration of the buried semiconductor layer 217 is, for example, about 2×10 ¹⁶ /cm ³ . The buried semiconductor layer 217 is formed along the depth direction from a depth of about 1 μm based on the surface of the substrate 201 . The width of the buried semiconductor layer 217 is, for example, about 1 μm. In addition, although not shown in the drawings, the buried semiconductor layer 217 is formed to be electrically connected to the base region 206 described later.

It should be added that in this embodiment, the sequence of ion implantation performed to form the impurity regions is not limited.

Next, in the step shown in FIG. 30 , the first gate insulating film 203 is formed to cover a portion of the base region 206 between the emitter region 208 and the resurf region 202 described later, for example, by thermal oxidation. After that, a first gate electrode 207 made of, for example, polysilicon is selectively formed on the first gate insulating film 203 . At this time, a second gate electrode made of polysilicon, for example, is selectively formed on a portion of the second gate insulating film 220 between the collector region 215 and the top semiconductor layer 222 simultaneously with the formation of the first gate electrode 207 . gate electrode 221 . In addition, using the first gate electrode 207 as a mask, for example, an N ⁺ -type emitter region 208 is selectively formed in the base region 206 by self-alignment by, for example, arsenic ion implantation. The emitter region 208 is formed to be isolated from the resurf region 202 . The impurity concentration of the emitter region 208 is, for example, about 1×10 ²⁰ /cm ³ , and the formation depth of the emitter region 208 is, for example, about 0.5 μm.

Next, in the process shown in FIG. 31 , for example, a P ⁺ -type contact region 210 is formed in the base region 206 by, for example, boron ion implantation. The contact region 210 is formed to be isolated from the RESURF region 202 . The impurity concentration of the contact region 210 is, for example, about 1×10 ¹⁹ /cm ³ , and the formation depth of the contact region 210 is, for example, 2 μm. Thereafter, a collector contact region 209 of, for example, P ⁺ type is formed in a surface portion of the collector region 215 by, for example, boron ion implantation. The impurity concentration of the collector contact region 209 is, for example, about 1×10 ¹⁹ /cm ³ , and the formation depth of the collector contact region 209 is, for example, 0.5 μm. As a supplementary note, the collector contact region 209 may not be formed.

Next, in the process shown in FIG. 32 , an interlayer film 211 is formed on the semiconductor substrate 201 on which the impurity regions, gate electrodes, etc. are formed, for example, by atmospheric pressure CVD, and then the interlayer film 211 is defined to part of the opening, and then form a collector electrode 212 and an emitter electrode 213 on the semiconductor substrate 201, the collector electrode 212 is electrically connected to the collector contact region 209 (that is, the collector region 215); the emitter electrode 213 is connected to the contact Both region 210 (ie, base region 206 ) and emitter region 208 are electrically connected. Finally, after forming a protective film 214 made of, for example, a plasma silicon nitride film on the interlayer film 211, the spacer formation region in the protective film 214 is opened. Thus, the switching element of this embodiment shown in FIG. 26 is formed.

According to the manufacturing method of this embodiment described above, since the top semiconductor layer 222 and the collector region 215 are formed by the same impurity implantation process, compared with the case where the top semiconductor layer 222 and the collector region 215 are formed separately, the process can be simplified. Fewer quantities can reduce costs.

-Industrial applicability-

The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, when the present invention is used for a high withstand voltage semiconductor switching element used in a switching power supply device, it can reduce It is very useful to shorten the time required to extract carriers by reducing the amount of excess carriers, thereby improving the switching speed.

Claims (10)

1. A semiconductor device, characterized in that: include: a second conductivity type resurf region formed in a surface portion of the first conductivity type semiconductor substrate, a first conductivity type base region formed in the semiconductor substrate adjacent to the resurf region, a second conductivity type emitter region formed in the base region in isolation from the resurf region, a first gate insulating film formed to cover a portion of the base region between the emitter region and the resurf region, a first gate electrode formed on the first gate insulating film, a first conductivity type top semiconductor layer formed in a surface portion of the resurf region and electrically connected to the base region, A first conductivity type collector region is formed in a surface portion of the RESURF region in isolation from the top semiconductor layer and has substantially the same impurity concentration as that of the top semiconductor layer, and is located substantially at the same distance from the top semiconductor layer. position as deep as the top semiconductor layer, a collector electrode formed on the semiconductor substrate and electrically connected to the collector region, and An emitter electrode is formed on the semiconductor substrate and is electrically connected to the base region and the emitter region. 2. A semiconductor device, characterized in that: include: a second conductivity type resurf region formed in a surface portion of the first conductivity type semiconductor substrate, a first conductivity type base region formed in the semiconductor substrate adjacent to the resurf region, a second conductivity type emitter-source region formed in the base region in isolation from the resurf region, a first gate insulating film formed to cover a portion of the base region between the emitter-source region and the resurf region, a first gate electrode formed on the first gate insulating film, a first conductivity type top semiconductor layer formed in a surface portion of the resurf region and electrically connected to the base region, A first conductivity type collector region is formed in a surface portion of the RESURF region in isolation from the top semiconductor layer and has substantially the same impurity concentration as that of the top semiconductor layer, and is located substantially at the same distance from the top semiconductor layer. position as deep as the top semiconductor layer, a second conductivity type drain region formed in a surface portion of the resurf region in isolation from the top semiconductor layer, a collector-cum-drain electrode formed on the semiconductor substrate and electrically connected to the collector region and the drain region, respectively, and An emitter-and-source electrode is formed on the semiconductor substrate, and is electrically connected to the base region and the emitter-source region, respectively. 3. The semiconductor device according to claim 2, wherein: The collector region and the drain region are respectively composed of a plurality of isolated parts; Each part of the collector region and each part of the drain region are alternately arranged in a direction perpendicular to a direction from the collector region toward the emitter-source region. 4. The semiconductor device according to any one of claims 1 to 3, characterized in that: Also includes: a second gate insulating film formed on said resurf region extending from above said collector region onto said top semiconductor layer, and A second gate electrode is formed on the second gate insulating film. 5. The semiconductor device according to claim 4, wherein: A buried semiconductor layer of a first conductivity type is also included, formed in the resurf region in contact with the top semiconductor layer, and electrically connected to the base region. 6. A method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device is used to manufacture the semiconductor device according to any one of claims 1 to 3, characterized in that: At least including the step of forming the top semiconductor layer and the collector region through the same impurity implantation process. 7. A semiconductor device, characterized in that: include: a second conductivity type resurf region formed in a surface portion of the first conductivity type semiconductor substrate, a first conductivity type base region formed in the semiconductor substrate adjacent to the resurf region, a second conductivity type emitter region formed in the base region in isolation from the resurf region, a gate insulating film formed to cover a portion of the base region between the emitter region and the resurf region, a gate electrode formed on the gate insulating film, a first conductivity type buried semiconductor layer formed in the RESURF region and electrically connected to the base region, The collector region of the first conductivity type is formed in the RESURF region in such a manner as to be isolated from the buried semiconductor layer, and has substantially the same impurity concentration as that of the buried semiconductor layer, and is located substantially as deep as the buried semiconductor layer, a first conductivity type collector contact region formed in a surface portion of the resurf region in contact with the collector region, a collector electrode formed on the semiconductor substrate and electrically connected to the collector contact region, and An emitter electrode is formed on the semiconductor substrate and is electrically connected to the base region and the emitter region. 8. A semiconductor device, characterized in that: include: a second conductivity type resurf region formed in a surface portion of the first conductivity type semiconductor substrate, a first conductivity type base region formed in the semiconductor substrate adjacent to the resurf region, a second conductivity type emitter-source region formed in the base region in isolation from the resurf region, a gate insulating film formed to cover a portion of the base region between the emitter-source region and the resurf region, a gate electrode formed on the gate insulating film, a first conductivity type buried semiconductor layer formed in the RESURF region and electrically connected to the base region, The collector region of the first conductivity type is formed in the RESURF region in such a manner as to be isolated from the buried semiconductor layer, and has substantially the same impurity concentration as that of the buried semiconductor layer, and is located substantially as deep as the buried semiconductor layer, a first conductivity type collector contact region formed in a surface portion of the resurf region in contact with the collector region, a second conductivity type drain region formed in a surface portion of the resurf region in isolation from the buried semiconductor layer, a collector-cum-drain electrode formed on the semiconductor substrate and electrically connected to the collector contact region and the drain region, respectively, and An emitter-and-source electrode is formed on the semiconductor substrate, and is electrically connected to the base region and the emitter-source region, respectively. 9. The semiconductor device according to claim 8, wherein: The collector region and the drain region are respectively composed of a plurality of isolated parts; Each part of the collector region and each part of the drain region are alternately arranged in a direction perpendicular to a direction from the collector region toward the emitter-source region. 10. A method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device is used to manufacture the semiconductor device according to any one of claims 7 to 9, characterized in that: At least including the step of forming the buried semiconductor layer and the collector region through the same impurity implantation process.

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