CN101151801A

CN101151801A - Normalized Least Mean Square Chip Level Equalization Advanced Diversity Receiver

Info

Publication number: CN101151801A
Application number: CNA2005800380160A
Authority: CN
Inventors: 艾利拉·莱尔; 菲利普·J·佩特拉斯基; 凯尔·俊霖·潘; 米海拉·贝露里; 杨陆
Original assignee: InterDigital Technology Corp
Current assignee: InterDigital Technology Corp
Priority date: 2004-11-05
Filing date: 2005-10-18
Publication date: 2008-03-26
Also published as: NO20072828L

Abstract

A receiver which includes at least one equalizer filter and a tap coefficients generator for implementing receive diversity. The equalizer filter processes a signal derived from signals received by a plurality of antennas. In one embodiment, sample data streams from the antennas are merged into one sample data stream. The merged sample data stream is processed by a single extended equalizer filter, whereby filter coefficients are adjusted in accordance with a joint error signal. A filter coefficient correction term used by the equalizer filter is generated by the tap coefficients generator using a normalized least mean square (NLMS) algorithm. In another embodiment, a plurality of equalizer filters are utilized, whereby each equalizer receives a sample data stream from a specific one of the antennas. In yet another embodiment, the sample data streams are combined after being processed by a plurality of matched filters based on respective estimated channel impulse responses.

Description

Normalized least mean square chip-level equalization advanced diversity receiver

Technical Field

The present invention relates to a wireless communication system using receiver diversity, and more particularly, to a receive diversity technique for a Normalized Least Mean Square (NLMS) chip-level equalization (CLE) receiver.

Background

While on-chip equalizers are well suited for advanced receiver systems such as those used in wireless transmit/receive units (WTRUs) and base stations, an NLMS-based CLE receiver provides superior performance for high data rate services such as High Speed Downlink Packet Access (HSDPA) through a Rake receiver. A typical NLMS receiver consists of an equalizer filter, typically a Finite Impulse Response (FIR) filter, and an NLMS algorithm.

The NLMS algorithm is used as a tap coefficient generator that generates tap coefficients used by the equalizer filter and updates them iteratively, as appropriate and in time. Traditionally, tap coefficient generation involves error signal calculation, vector length (norm) calculation, and leaky integration, in order to g generate and update the tap coefficients.

Although the NLMS CLE has been successfully validated in a single antenna receiver, no extension of the NLMS algorithm is provided in terms of receiver diversity, a simple extension would be to provide an NLMS CLE for each antenna and combine each result, which is less than ideal.

Disclosure of Invention

The invention relates to a receiver comprising at least one equalizer filter and a tap coefficient generator for implementing receive diversity, the equalizer filter processing a signal derived from signals received by a plurality of antennas. In one embodiment, the sample data streams from the antennas are combined into a sample data stream, the combined sample data stream is processed by a single extended equalizer filter, whereby filter coefficients are adjusted based on a joint error signal, and a filter coefficient correction term used by the equalizer filter is generated by the tap coefficient generator using an NLMS algorithm. In another embodiment, a plurality of equalizer filters are used, whereby each equalizer receives a sample data stream from a particular one of the antennas. In yet another embodiment, the sample data streams are combined after being processed by a plurality of matched filters according to respective estimated cirs.

Drawings

The invention may be understood in more detail by reference to the following description of a preferred embodiment, given as an example, and the accompanying drawings, in which:

FIG. 1 is a block diagram of an NLMS CLE receiver configured in accordance with a first embodiment of the present invention;

FIG. 2 is a block diagram of an NLMS CLE receiver configured in accordance with a second embodiment of the present invention;

fig. 3 is a block diagram of a simplified version of the NLMS CLE receiver of fig. 2; and

fig. 4 is a block diagram of an NLMS CLE receiver configured in accordance with a third embodiment of the present invention.

Detailed Description

The preferred embodiments of the present invention will be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.

Hereinafter, the term "wireless transmit/receive unit (WTRU)" is used generically to include, but is not limited to, a User Equipment (UE), a mobile station, a laptop computer, a Personal Digital Assistant (PDA), a fixed or mobile subscriber unit, a pager, or any other type of device capable of operating in a wireless environment. When referred to hereafter, the terminology "base station" includes but is not limited to an Access Point (AP), a node B, a site controller, or any other type of interfacing device in a wireless environment.

The features of the present invention may be integrated into an Integrated Circuit (IC) or may be configured in a circuit comprising a multitude of interconnecting components.

Hereinafter, the present invention will be explained with reference to the NLMS algorithm, however, it should be noted that any other adaptive equalization algorithm may be used.

The invention will be explained with reference to the method of receiver diversity for an NLMS algorithm, however, it should be noted that any form of adaptive equalizer or filter may be used, such as Least Mean Square (LMS), goldenafil's algorithm, channel estimation based NLMS (CE-NLMS), and other iterative or recursive algorithms.

Fig. 1 is a block diagram of an NLMS CLE receiver 100 configured in accordance with a first embodiment of the present invention. The NLMS CLE receiver 100 is a joint processing NLMS receiver that uses a single equalizer filter, the NLMS CLE receiver 100 includes a plurality of antennas 102A, 102B, a plurality of samplers 104A, 104B, a multiplexer 106, and an NLMS equalizer 108, and the NLMS equalizer 108 further includes an equalizer filter 110 and a tap coefficient generator 112.

The signals received by the antennas 102A, 102B are input to samplers 104A, 104B, respectively, to generate respective

sample data streams

105A, 105B, which are sampled at twice (2 x) the chip rate. The

sample data streams

105A, 105B are combined by the multiplexer 106 into a single sample data stream 114, which is input to the equalizer filter 110 of the NLMS equalizer 108, with samples appearing at twice the chip rate per

sample data stream

105A, 105B, so that samples appear at four times (4 x) the chip rate of the sample data stream 114. Each sample occurring on the sample data stream 114, either from

sample data stream

105A or 105B, the efficiency of the equalizer filter 106 is four times (4 x) r chip rate.

Although fig. 1 illustrates that the NLMS CLE receiver 100 can be used to sample signals received from two (2) antennas at twice (2 x) the chip rate, it is noted that the NLMS CLE receiver 100 can include any number of antennas and the signals received from the antennas can be sampled at any desired rate.

The equalizer filter 110 includes a plurality of taps having filter coefficients, and a FIR filter may be used as the equalizer filter 110. The number of taps in the equalizer filter 110 may be optimized for a particular multipath channel for different power delay data and tool rates. The tap coefficient generator 112 includes a vector length square estimator 116, a tap correction unit 118,

multipliers

120, 122, 124, and an adder 126.

The equalizer filter 110 outputs an equalizer output signal 130, which is a chip rate signal, the equalizer output signal 130 is multiplied by an encrypted code conjugate signal 134 via the multiplier 120 to generate a decrypted equalizer output signal 142 (which is an estimate of the unencrypted transmit chip), the decrypted equalizer output signal 142 is input to a first input of the adder 126, and the equalized input signal 130 is determined based on an equalized delay line (TDL) signal 132 and a tap correction signal 152.

A pilot amplitude reference signal 144 is used to adjust the average output power of the equalizer 108 by varying the amplitude of a pilot reference signal 148 generated by the multiplier 122, which is multiplied by a once quantized pilot (i.e., common pilot channel (CPICH)) channelization code 146. The pilot reference signal 148 is input to a second input of the adder 126, and the pilot reference signal 148 is the decrypted equalizer output signal 142 subtracted by the adder 126 to generate an error signal 150 that is input to a first input of the tap correction unit 118, and the

external signals

134, 144, and 146 are configured and generated based on signal information transmitted from higher layers.

The equalizer TDL signal 132 is multiplied by the encrypted code conjugate signal 134 via the multiplier 124 to generate a vector signal 136 having a value X. Which is a decrypted version of the signal 132. The vector signal 136 is input to the vector length squares estimator 116, and a second input of the tap correction unit 118, the vector length squares estimator 116 generates a signal 138 having a value equal to | | X | | survival ² (i.e., the length squared of the value X of the vector signal 136 or equivalent equalizer TDL signal 132), the vector length squared estimator outputs the signal 138 to a third input of the tap correction unit 118. Based on the

signals

136, 138 and 150, the tap correction unit 118 outputs the tap correction signal 152 having a value w which is input to the equalizer filter 110.

The tap correction signal 152 represents the tap value used by the equalizer filter 110, and at a given time, the next value w of the tap correction signal 152 is calculated by adding the current value of the tap correction signal 152 (possibly weighted by a leakage factor), the product of the normalization signal (signal 130 divided by signal 140), and the error signal 150, as well as a stage size parameter defined in the tap correction unit 118, as described in more detail below.

The tap correction signal 152 is updated by the tap correction unit 118 as follows:

equation (1)

Wherein,

a weight vector defined for the equalizer filter 110;

is a vector based on samples received from the antennas 102A, 102B; μ, α, ε are parameters chosen to control the adaptation phase size, tap leakage, and the number of divisions by zero (or near zero) to prevent; ε is a small number to prevent division by zero from occurring. The leakage parameter α is a weighting parameter, and is generally not greater than 1. The phase size parameter mu is a factor of a metrology error. The equalizer filter 110 is a FIR structure that computes the inner product of w and X<w，X>And the inner product result is the equalizer output signal 130.

The present invention incorporates an adaptive equalizer to implement receive diversity, which greatly improves the receiver performance. A joint equalizer filter coefficient vector adaptation mechanism in accordance with the present invention is described below.

Defining a joint weight vector for an equalizer filter

As a union of multiple element weight vectors, each corresponding to data collected by a different antenna, any permutation combination of elements from the element vectors can include the combining weight vector, provided that the permutation appropriately reflects the order in which data enters the combining NLMS equalizer, although these are mathematical equations, but the permutation can be chosen according to the tag aspect, e.g., combining weight vectors in both antenna aspects

The following can be defined:

equation (2)

Wherein] ^T Representing a transpose operation, the total number of taps of the equalizer filter is represented by L,

is a line vector.

For the tag selected by equation (2), the splice update vector

Is defined as follows:

equation (3)

Wherein

Is based on the vectors of samples received from antenna 1 and antenna 2

Is a column vector.

The filter coefficient adaptation of the joint NLMS equalizer can then be processed in the general way of NLMS equalizers, for example, the update coefficient vector can be obtained as follows:

equation (4)

Wherein] ^H Representing a conjugate transpose operation, d [ n ]]Is the reference signal for NLMS and epsilon is a small number to prevent division by zero from occurring. The parameter α is a weighting parameter and μ is an error signal metric, μ can be estimated based on tool velocity and signal-to-interference-and-noise ratio (SINR), and interpolated to obtain a continuous estimate.

For guided dominant NLMS, d [ n ]]May be a pilot signal, training signal, or the likeA signal of a known pattern, a signal spread by a predetermined spreading factor, or a signal that is not spread. Similarly, for data-dominated NLMS, d [ n ]]May be full, partial, or non-expanded data symbols. The tapping correction items

Is calculated as follows:

equation (5)

Wherein the factor e _n，joint Is a joint error signal and is derived from the reference signal d [ n ]]The equalized filter output is subtracted, which is calculated as follows:

equation (6)

The new tap coefficient of the next iteration is obtained by dividing the tap coefficient term

Added to (weighted) tap coefficients of a previous iterationThe weighting mechanism can be obtained as described below with the parameter α:

equation (7)

The splice tap update vector in equation (4) may simply be in the standard NLMS equation

Replacement stitching weight vector

And with

Replacement join update vectorThus, the compound (I) is obtained. Equation (4) uses the joint equalizer output and subtracts the joint equalizer output from the desired signal or pilot signal to generate a joint estimate error. The vector length squared of the input signal is a joint vector length squared. The joint estimation error and the conjugate of the input signal mu, and the square of the vector length of the input signal, generate a correction term that is added to the tap weight vector for iteration n to generate the tap weight vector for iteration n +1, i.e., update the tap weight vector.

Fig. 2 is a block diagram of an NLMSCLE receiver 200 configured in accordance with a second embodiment of the invention. The NLMSCLE receiver 200 is a spread-guided joint processing NLMS receiver that uses a plurality of equalizers. The NLMSCLE receiver 200 includes a plurality of antennas 202A, 202B, a plurality of

samplers

204A, 204B, and an NLMS equalizer 206. The NLMS equalizer 206 includes a plurality of

equalizer filters

208A, 208B and a tap coefficient generator 210. The signals received from the antennas 202A, 202B are input to

samplers

204A, 204B, respectively, which generate respective sample data streams 205A, 205B, (X) ¹ 、X ² )。

Although fig. 2 illustrates that the NLMS CLE receiver 200 can be used to sample signals received from two (2) antennas at twice (2 x) the chip rate, it must be understood that the NLMS CLE receiver 200 can include any number of antennas and equalizer filters, and that the signals received from the antennas can be sampled at any desired rate.

The sample data streams 205A, 205B from the

samplers

204A, 204B enter the corresponding equalizer filters 208A, 208B and the tap coefficient generator 210. The sample data streams 205A, 205B are processed and down-sampled (in this embodiment, 2 down-sampled) by the equalizer filters 208A, 208B to produce equalized

signals

212A, 212B at one (1 x) chip rate.

The tap coefficient generator 210 includes series-to-parallel (S → P) to vector converters 213A, 213B, multipliers 214A, 214B, 222, vector accumulators 216A, 216B, correction term generators 218A, 218B,

adders

220 and 226, and a chip accumulator 224. The S → P to vector converters 213A, 213B are similar to a TDL, whereby the output of the S → P to vector converters 213A, 213B indicates the state of the TDL, which is used to generate the signal output by the equalizer filter 110 in fig. 1.

Each 2x chip rate sample data stream 205A, 205B is converted by an S → P to vector converter 213A, 213B into a 1x chip rate length L vector signal 231A, 231B. The length L vector signals 231A, 231B are then multiplied by an encryption code conjugate signal 232 (P) via the multipliers 214A, 214B, respectively, each of which outputs a decrypted vector signal 234A, 234B to a respective vector accumulator 216A, 216B to generate respective update vector signals 217A, 217B. The vector accumulators 216A, 216B perform a despreading operation during a time period (i.e., the same time period as the chip accumulator 224), which may be different from the pilot signals received by the antennas 202A and 202B. The update vector signals 217A, 217B are forwarded to the correction term generators 218A, 218B.

The equalized signals 212A, 212B are summed by adder 220, which outputs a summed equalized signal 221, the summed equalized signal 221 is then multiplied by the encrypted code conjugate signal 232 via multiplier 222, which then outputs a decrypted signal 223. The decrypted signal 223 is input to the chip accumulator 224, which performs a despreading operation during a period that may be different from the spreading factor of a pilot signal received by the antennas 202A and 202B. The accumulated result signal 225 output by the chip accumulator 224 is subtracted by an adder with a pilot reference signal 230 to generate a joint error signal 227.

Each of the correction term generators 218A, 218B includes a vector length square estimator (not shown, but similar to block 116 of fig. 1) for generating a vector length square of the update vector signals 217A, 217B, and for generating

correction terms

219A, 219B for the equalizer filters 208A, 208B to be added to filter coefficients of a previous iteration to generate the update filter coefficients for a next iteration based on the update vector signals 217A, 217B, the vector length squares of the update vector signals 217A, 217B, and the joint error signal 227.

The correction term generator 218A can generate the correction term according to the correction term

The correction term 219A is generated which is added to the filter coefficients of the previous iteration within the equalizer filter 208A to generate updated filter coefficients for the next iteration. Similarly, the correction term generator 219B can generate the correction term according to the correction termThe correction term 218B is generated, which is added to the filter coefficients of the previous iteration within the equalizer filter 208B to generate updated filter coefficients for the next iteration.

Alternatively, the correction term generator may generate the correction term based on the correction term

The correction term 219A is generated, and the correction term generator 218B generates the correction term according to the correction term

The correction term 219B is generated, and the variable η is a relatively small number for improving the numerical characteristics and preventing when the correction term is generatedAnd (5) making fixed point operation overflow.

Fig. 3 is a block diagram of a simplified version of the NLMS CLE receiver 200 of fig. 2. The NLMS CLE receiver 300 is a non-despread pilot-based joint processing NLMS receiver that uses a plurality of equalizers. The NLMS CLE receiver 300 includes a plurality of

antennas

302A, 302B, a plurality of

samplers

304A, 304B, and an NLMS equalizer 306. The NLMS equalizer 306 includes a plurality of

equalizer filters

308A, 308B and a tap coefficient generator 310. The signals received by the

antennas

302A, 302B are input to the

samplers

304A, 304B, respectively, which generate respective sample data streams 305A, 305B.

Although fig. 3 illustrates that the NLMS CLE receiver 300 can be used to sample signals received from two (2) antennas at twice (2 x) the chip rate, it must be understood that the NLMS CLE receiver 300 can include any number of antennas and equalizer filters, and that the signals received from the antennas can be sampled at any desired rate.

The NLMS CLE receiver 300 of fig. 3 is similar to the NLMS CLE receiver 200 of fig. 2, except that the sample data stream and the outputs from the filter coefficients are not summed.

The sample data streams 305A, 305B from the

samplers

304A, 304B are input to corresponding equalizer filters 308A, 308B and the tap coefficient generator 310. The sample data streams 305A, 305B are processed and down-sampled (in this embodiment, down-sampled by 2) by the equalizer filters 308A, 308B to produce equalized

signals

312A, 312B at one (1 x) chip rate.

The tap coefficient generator 310 includes S → P to vector converters 313A, 313B,

multipliers

314A, 314B and 322, correction term generators 318A, 318B, and

adders

320, 326. Each of the sample data streams 305A, 305B is converted by the S → P to vector converters 313A, 313B into length L vector signals 331A, 331B, which perform a despreading operation over a period of time that may be different from the spreading factor of the pilot signals received by the

antennas

302A and 302B. The length L vector signals 331A, 331B are then multiplied by the encryption code conjugate signal 332 (P) via the

multipliers

314A, 314B, respectively, to generate decrypted

vector signals

334A, 334B, which decrypted

vector signals

334A, 334B are forwarded to the correction term generators 318A, 318B, respectively.

The equalized signals 312A, 312B are summed by the adder 320, which outputs a summed equalized signal 321, the summed equalized signal 321 is then multiplied by an encrypted code conjugate signal 332 via the multiplier 322, (P), which then outputs a decrypted signal 323, the decrypted signal 323 is subtracted (e.g., quantized pilot) by the adder 326 with a reference pilot signal 325 to generate a joint error signal 327.

The correction generators 318A, 318B are similar to the correction term generators 318A, 318B described above, each correction term generator 318A, 318B including a vector length square estimator (not shown, but similar to block 116 shown in fig. 1) for generating a vector length square of the decrypted

vector signals

334A, 334B, and generating

correction terms

319A, 319B for the equalizer filters 308A, 308B to add to the filter coefficients of the previous iteration to generate updated filter coefficients for the next iteration based on the decrypted vector 317A, 317B, the vector length squares of the decrypted

vector signals

334A, 334B, and the join error signal 327.

The updated filter coefficients used by the

NLMS CLE receivers

200 and 300 are generated as follows:

equation (8)

Wherein e _n，joint The joint estimation error generated by the joint process from two antennas is defined as follows:

equation (9)

A diversity receiver performs the NLMS equalization independently for each of the receive antennas as follows:

equation (10)

Wherein

And

the tap weight vector and the input update vector for the NLMS equalizer i corresponding to the receive antenna i at the iteration n. The equalizer i generates its own error signal and independently updates the tap weight vector, and the equalizer outputs are despread and combined together. For the pilot-based approach, the despread data for multiple antennas are soft combined to produce the final output for performance enhancement, while for the data-based approach, the despread data for multiple antennas are soft combined to produce the final output for hard decision, and the resulting hard signal is used as a reference signal.

The tap correction term if equation (10)

Another variant is obtained if the following calculation is made:

equation (11)

And

equation (12)

Fig. 4 is a block diagram of an NLMS CLE receiver 400 configured in accordance with a third embodiment of the present invention, the NLMS CLE receiver 400 using pre-equalized combining of the signals received from the diversity antenna. The NLMS CLE receiver 400 includes

multiple antennas

402A, 402B,

multiple samplers

403A, 403B, multiple matched filters (NFs) 404A, 404B,

multiple channel estimators

405A, 405B, a combiner 406, and an NLMS equalizer 408. The NLMS equalizer 408 includes an equalizer filter 410 and a tap coefficient generator 412.

A signal is received by the antenna 402 and a sample data stream is generated from the received signal by the sampler 403. For example, fig. 4 illustrates two antennas and sampling at 2x chip rate, however, it is noted that the receiver 400 may include any number of antennas and the samples may be generated at any rate. The samples are processed by the matched filter 404 and channel estimator 405 and combined by the combiner 406 to produce a combined sample data stream 407. The combiner 406 can be a simple adder with or without weighting, or a matched filter can be used as the combiner 406 to perform the diversity signal combining. The combined sample data stream 407 maintains the same rate as the sample rate.

The combined sample data stream 407 is then input to the equalizer filter 408 and the tap coefficient generator 410. Assuming that two antennas are used, the combined signal can be represented as follows:

equation (13)

Wherein H ⁱ To estimate the channel response matrix for the receiving antenna i, where, for example, the NLMSCLE receiver 400 with two antennas, i =1,2. The(Vector)

Is the combined signal vector after the receive diversity combination at iteration n.

After performing diversity combining, a combined sample data stream 407 is generated and forwarded to the equalizer filter 410 for processing to perform equalization to mitigate interference such as Inter Symbol Interference (ISI) and Multiple Access Interference (MAI). In this embodiment, the equalizer filter 410 is performed at twice (2 x) the chip rate, and the processing result is down-sampled by 2 to produce a chip rate output, which is then decrypted with an encryption code sequence.

The NLMS may tap weight vector updates as described below:

equation (14)

Wherein

For tapping the weight vector, for equalizing the combined received signal, and d [ n ]]Is a reference signal at time n.

The tap coefficient generator 412 includes

multipliers

411, 420, a chip accumulator 413, an adder 414, a correction term generator 417, a vector accumulator 422, a multiplier 420, and an S → P to vector converter 418. The output from the equalizer filter 410 is decrypted by the multiplier 411, and the output of the multiplier 411 is accumulated by the chip accumulator 413, which performs a despreading operation at a time that may be different from the spreading factors of the pilot signals received from the

antennas

402A and 402B. The accumulated result output by the chip accumulator 413 is subtracted by the adder 414 with a pilot reference signal 415 to generate a joint error signal 416.

The combined data sample stream 407 is converted into length L vectors by the S → P to vector converter 418 and decrypted by the multiplier 420. The decrypted output vector is accumulated by the vector accumulator 422 to generate the update vector 423. The vector accumulator 422 performs a despreading operation over a period of time (i.e., the same period of time as the chip accumulator 413), which may be different from the spreading factor of the pilot signals received from the

antennas

402A and 402B. The update vector 423 is forwarded to the correction term generator 417, and the correction term generator 417 generates the correction term 425 of the equalizer filter 410, which is added to the filter coefficients of the previous iteration to generate the updated filter coefficients for the next iteration.

The correction term generated by the correction term generator 417 is the product of the normalization signal (signal 423 divided by the length of signal 423), the error signal 416, and a step size parameter (mu) defined in 417. A new filter value is generated by adding the correction term to the previous filter value, the filter output being the inner product of the filter value and the TDL state vector.

The correction term generator 417 can be based on the correction term

The correction term 425 is generated in the equalizer filter 410 that is added to the filter coefficients of the previous iteration to generate updated filter coefficients for the next iteration, or the correction term generator 417 may generate the correction term based on the correction term

The correction terms 425 are generated.

The third embodiment shown in fig. 4 is described with respect to a despread pilot-master receiver, however, the receiver may be a non-despread pilot-master receiver as shown in fig. 3, in which case the decrypted samples are not accumulated and the stream of received samples must be executed to generate an update vector.

Although the features and elements of the present invention are described in the embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the preferred embodiments or in various combinations with or without other features and elements of the present invention. While the invention has been described in terms of preferred embodiments, other variations which do not depart from the scope of the invention as claimed will become apparent to those skilled in the art. The foregoing description is for the purpose of illustration and is not intended to limit the particular invention in any way.

Claims

1. A receiver comprising:

Multiple antennas for receiving signals;

a plurality of samplers connected to individual antennas of the antennas for generating a plurality of sample data streams, wherein each of the samplers generates an individual sample data stream according to the signal received by the individual antenna;

a multiplexer for combining the sample data streams generated by the sampler into a combined sample data stream; and

an equalizer for processing the combined sample data stream.

2. The receiver of claim 1, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, wherein the sample data stream is sampled by the individual sampler at twice the chip rate, And, the combined sample data stream is processed by the equalizer at a quadruple chip rate.

3. The receiver according to claim 1, wherein the equalizer comprises:

an equalizer filter for processing the combined sample stream with filter coefficients; and

A tap coefficient generator for generating at least one filter coefficient correction term for use by the equalizer filter.

4. The receiver of claim 3, wherein the filter coefficient correction item is generated according to a de-expanded pilot sequence.

5. The receiver of claim 3, wherein the filter coefficient correction item is generated according to a non-de-expanded pilot sequence.

6. The receiver of claim 3, wherein the filter coefficient correction item is generated by the tap coefficient generator using a normalized least mean square (NLMS) algorithm.

7. The receiver according to claim 3, wherein the tap coefficient generator comprises:

a first multiplier connected to a first output of the equalizer filter, the first multiplier being configured to receive an equalizer output signal from the first output of the equalizer filter, and multiplying the equalizer output signal by an encrypted code conjugate signal to generate a decrypted equalizer output signal;

a second multiplier connected to a second output of the equalizer filter, the second multiplier configured to receive an equalizer tapped delay line from the second output of the equalizer filter (TDL) signal, and the equalizer TDL signal is multiplied by the encryption code conjugate signal to generate a vector signal with a value X;

an adder for subtracting the first decrypted signal from a pilot reference signal to generate an error signal;

a vector length square estimator for receiving the vector signal and generating a signal having a value equal to ^∥X∥2 ; and

A tap correction unit that generates a vector signal representing tap values used by the equalizer filter to generate the equalizer output signal and the equalizer TDL signal.

8. A receiver comprising:

a plurality of receivers for receiving signals;

a plurality of samplers connected to individual ones of the antennas for generating a plurality of sample data streams, wherein each of the samplers generates an individual sample data stream based on the signal received by the individual antenna; and

an equalizer for processing the sample data stream.

9. The receiver of claim 8, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, and wherein the sample data stream is generated by the individual sampler at twice the chip rate sampling.

10. The receiver according to claim 8, wherein the equalizer comprises:

a plurality of equalizer filters connected to individual ones of the samplers for processing the sample data stream using filter coefficients; and

11. The receiver of claim 10, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, wherein the sample data stream is sampled by the individual sampler at twice the chip rate , and downsampled to chip rate by the individual equalizer filter.

12. The receiver of claim 10, wherein the filter coefficient correction item is generated according to a de-expanded pilot sequence.

13. The receiver of claim 10, wherein the filter coefficient correction item is generated according to a non-de-expanded pilot sequence.

14. The receiver of claim 10, wherein the filter coefficient correction item is generated by the tap coefficient generator using a normalized least mean square (NLMS) algorithm.

15. The receiver according to claim 10, wherein the tap coefficient generator comprises:

a plurality of series-to-parallel (S→P)-to-vector converters connected to the individual sampler and equalizer filters for converting each of the individual sample data streams into a length L vector signal;

a plurality of vector decryption multipliers connected to individual S→P-to-vector converters of the S→P-to-vector converters, each vector decryption multiplier configured to convert the output from an individual S→P-to-vector converter The length L vector signal is multiplied by an encrypted code conjugate signal to generate a decrypted vector signal;

a first adder connected to each of the equalizer filters for adding the equalized output signals generated by each of the equalizer filters to generate a summed equalizer output signal;

an equalizer output multiplier connected to the adder for multiplying the summed equalizer output signal by the encrypted code conjugate signal to generate a decrypted summed equalizer signal;

a second adder for subtracting the decrypted sum equalizer signal from a pilot reference signal to generate a splice error signal; and

a plurality of correction term generators connected to the adder, an individual vector decryption multiplier, and an individual equalizer filter, wherein each correction term generator is multiplied according to the joint error signal and by an individual vector decryption An individual deciphered vector signal produced by an individual equalizer to output a correction object used by an individual equalizer filter.

16. The receiver according to claim 15, wherein the tap coefficient generator further comprises:

a plurality of vector accumulators connected between individual vector decryption multipliers and individual correction term generators;

An on-chip accumulator connected between the equalizer output multiplier and the second adder.

17. A receiver comprising:

Multiple antennas for receiving signals;

a plurality of samplers connected to individual ones of the antennas for generating a plurality of sample data streams, wherein each of the samplers generates an individual sample data stream based on the signal received by the individual antenna;

a plurality of channel estimators for estimating a channel impulse response;

a plurality of matched filters (MFs) connected to individual ones of the samplers, and the MFs process the sample data stream according to the estimated channel impulse response;

a combiner for combining the combined outputs of the MFs; and

an equalizer for processing the output of the MFs.

18. The receiver of claim 17, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, and wherein the sample data stream is generated by the individual sampler at twice the chip rate sampling.

19. The receiver of claim 17, wherein the combiner combines multiple multipath components of the signal received by the antenna.

20. The receiver of claim 17, wherein the equalizer comprises:

an equalizer filter using filter coefficients to process the combined output of the MFs; and

21. The receiver of claim 17, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, and wherein the sample data stream is generated by the individual sampler at twice the chip rate sampled and down-sampled to chip rate by the equalizer filter.

22. The receiver of claim 20, wherein the filter coefficient correction item is generated according to a de-expanded pilot sequence.

23. The receiver of claim 20, wherein the filter coefficient correction object is generated according to a non-de-expanded pilot sequence.

The receiver of 24.15, wherein the filter coefficient correction term is generated by the tap coefficient generator using a normalized least mean square (NLMS) algorithm.

25. The receiver according to claim 20, wherein the tap coefficient generator comprises:

a series-to-parallel (S→P)-to-vector converter connected to the combiner and the equalizer filter for converting the combined output of the MFs into a length L vector signal;

A vector decryption multiplier, which is connected to the S→P to vector converter, is used to multiply the length L vector signal output by the S→P to vector converter by an encryption code conjugate signal to generate a decrypt vector signal;

an equalizer output multiplier connected to the equalizer filter for multiplying an equalizer output signal generated by the equalizer filter by an encrypted conjugate signal to generate a decrypt the equalizer signal;

an adder for subtracting the decrypted equalizer signal from a pilot reference signal to generate an error signal; and

a correction term generator connected to the adder, the vector decryption multiplier and the equalizer filter, wherein the correction term generator generates the decryption vector according to the error signal and the vector decryption multiplier signal to output the correction term used by the equalizer filter.

26. The receiver according to claim 25, wherein the tap coefficient generator further comprises:

a vector accumulator connected between the vector decryption multiplier and the correction term generator; and

An on-chip accumulator is connected between the equalizer output multiplier and the adder.

27. An integrated circuit (IC) for connection to a receiver having multiple antennas for receiving signals, the IC comprising:

a plurality of samplers connected to individual ones of the antennas for generating a plurality of sample data streams, wherein each of the samplers generates an individual sample data from the signal received by a respective one of the antennas streaming;

a multiplexer for combining the sample data stream generated by the sampler into a combined sample data stream; and

an equalizer for processing the combined sample data stream.

28. The IC of claim 27, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, and wherein the sample data stream is sampled by the individual sampler at twice the chip rate , and, the combined sample data stream is processed by the equalizer at a quadruple chip rate.

29. The IC of claim 27, wherein the equalizer comprises:

30. The IC of claim 29, wherein the filter coefficient correction item is generated according to a de-expanded bootstrap sequence.

31. The IC of claim 29, wherein the filter coefficient correction item is generated according to a non-de-expanded bootstrap sequence.

32. The IC of claim 29, wherein the filter coefficient correction item is generated by the tap coefficient generator using a normalized least mean square (NLMS) algorithm.

33. The IC of claim 29, wherein the tap factor generator comprises:

34. An integrated circuit (IC) for use in connection with a receiver having multiple antennas for receiving signals, the IC comprising:

a plurality of samplers connected to individual ones of the antennas for generating a plurality of sample data streams, wherein each sampler generates an individual sample data stream based on the signal received by an individual one of the antennas ;as well as

an equalizer for processing the sample data stream.

35. The IC of claim 34, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, and the sample data stream is sampled by the individual sampler at twice the chip rate.

36. The IC of claim 34, wherein the equalizer comprises:

37. The IC of claim 36, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, and the sample data stream is sampled by the individual sampler at twice the chip rate, and Downsampled to chip rate by the individual equalizer filter.

38. The IC of claim 36, wherein the filter coefficient correction item is generated according to a de-expansion bootstrap sequence.

39. The IC of claim 36, wherein the filter coefficient correction item is generated according to a non-de-expanded bootstrap sequence.

40. The IC of claim 36, wherein the filter coefficient correction term is generated by the tap coefficient generator using a normalized least mean square (NLMS) algorithm.

41. The IC of claim 36, wherein the tap factor generator comprises:

a plurality of series-to-parallel (S→P)-to-vector converters connected to individual samplers and equalizer filters of the samplers for converting each of the individual sample data streams into a vector signal of length L;

a plurality of vector decryption multipliers connected to individual S→P-to-vector converters of the S→P-to-vector converter, each of the vector decryption multipliers being configured to convert the output from an individual S→P-to-vector converter The length L vector signal is multiplied by an encrypted code conjugate signal to generate a decrypted vector signal;

a first adder connected to each of the equalizer filters for adding an equalizer output signal generated by each of the equalizer filters to generate a summed equalizer output signal;

a plurality of correction term generators connected to the adder, the respective vector decryption multipliers of the equalizer filters, and the respective equalizer filters of the equalizer filters, wherein each correction term generator The correction term used by an individual equalizer filter of the equalizer filters is output based on the joint error signal and an individual decrypted vector signal generated by an individual vector decryption multiplier.

42. The IC according to claim 41, wherein the tap coefficient generator further comprises:

a plurality of vector accumulators connected between individual ones of the vector decryption multipliers and individual ones of the correction term generators; and

43. An integrated circuit (IC) for connection to a receiver having multiple antennas for receiving signals, the IC comprising:

a plurality of samplers connected to individual ones of the antennas for generating a plurality of sample data streams, wherein each of the samplers generates an individual sample data stream based on the signal received by an individual one of the antennas flow;

a plurality of channel estimators for estimating a channel impulse response;

a combiner for combining the outputs of the MFs; and

an equalizer for processing the combined output of the MFs.

44. The IC of claim 43, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, and the sample data stream is sampled by the individual sampler at twice the chip rate.

45. The IC of claim 43, wherein the combiner combines multiple multipath components of a signal received by the antenna.

46. The IC of claim 43, wherein the equalizer comprises:

an equalizer filter for processing the combined output of the MFs using filter coefficients; and

47. The IC of claim 43, wherein the receiver is a Code Division Multiple Access (CDMA) receiver, and wherein the sample data stream is sampled by the individual sampler at twice the chip rate, And it is down-sampled to the chip rate by the equalizer filter.

48. The IC of claim 46, wherein the filter coefficient correction item is generated according to a de-expanded bootstrap sequence.

49. The IC of claim 46, wherein the filter coefficient correction item is generated according to a non-de-expanded bootstrap sequence.

50. The IC of claim 46, wherein the filter coefficient correction item is generated by the tap coefficient generator using a normalized least mean square (NLMS) algorithm.

51. The IC of claim 46, wherein the tap factor generator comprises:

an equalizer output multiplier connected to the equalizer filter for multiplying an equalizer output signal generated by the equalizer filter by an encryption code conjugate signal to generate a decryption equalizer signal;

a correction term generator connected to the adder, the vector decryption multiplier, and the equalizer filter, wherein the correction term generator is based on the error signal and the decryption generated by the vector decryption multiplier Vector signal to output the correction mesh used by this equalizer filter.

52. The IC according to claim 51, wherein the tap coefficient generator further comprises:

53. A method for processing signals received by a plurality of antennas, the method comprising:

(a) generating a plurality of sample data streams, each of the sample data streams being generated based on the signal received by a respective one of the antennas;

(b) combining the sample data streams into a combined sample data stream; and

(c) processing the merged sample data stream.

54. The method of claim 53, wherein a Code Division Multiple Access (CDMA) receiver is used to perform steps (a)-(c), the method further comprising:

(d) sampling the sample data stream at twice the chip rate; and

(e) Processing the combined sample data stream at quadruple chip rate.

55. The method of claim 53, further comprising:

(d) processing the combined sample stream using filter coefficients; and

(e) generating at least one filter coefficient correction item.

56. The method of claim 55, wherein the filter coefficient correction item is generated according to a de-expansion guide sequence.

57. The method of claim 55, wherein the filter coefficient correction item is generated according to a non-de-expanded bootstrap sequence.

58. The method of claim 55, wherein the filter coefficient correction item is generated using a normalized least mean square (NLMS) algorithm.

59. The method of claim 55, further comprising:

(f) receiving an equalized output signal and multiplying the equalized output signal by an encrypted code conjugate signal to generate a decrypted equalized output signal;

(g) receiving an equalizer tapped delay line (TDL) signal and multiplying the equalizer TDL signal by the encrypted code conjugate signal to generate a vector signal having a value X;

(h) subtracting the first decrypted signal from a pilot reference signal to generate an error signal;

(i) generating a signal having a value equal to ^∥X∥2 from the vector signal; and

(j) generating a vector signal representing a tap value for generating the equalizer output signal and the equalizer TDL signal.

60. A method for processing signals received by a plurality of antennas, the method comprising:

(a) generating a plurality of sample data streams, wherein each of the sample data streams is generated based on the signal received by a respective one of the antennas; and

(b) Process the sample data stream.

61. The method of claim 60, wherein a Code Division Multiple Access (CDMA) receiver is used to perform steps (a) and (b), the method further comprising:

(c) Sampling the sample data stream at double chip rate sampling.

62. The method of claim 60, further comprising:

(c) processing the sample data stream using filter coefficients; and

(d) generating at least one filter coefficient correction item.

63. The method of claim 60, wherein a Code Division Multiple Access (CDMA) receiver is used to perform steps (a)-(d), the method further comprising:

(e) sampling the sample data stream at twice the chip rate; and

(f) Downsampling the sample data stream to chip rate.

64. The method of claim 62, wherein the filter coefficient correction item is generated according to a de-expansion guide sequence.

65. The method of claim 62, wherein the filter coefficient correction item is generated according to a non-de-expanded bootstrap sequence.

66. The method of claim 62, wherein the filter coefficient correction item is generated using a normalized least mean square (NLMS) algorithm.

67. The method of claim 62, further comprising:

(e) converting each individual sample data stream into a vector signal of length L;

(f) multiply each length L vector signal by an encryption code conjugate signal to generate an individual decryption vector signal;

(g) adding a plurality of equalizer output signals to produce a summed equalizer output signal;

(h) multiplying the summed equalizer output signal by the encrypted code conjugate signal to generate a decrypted summed equalized signal;

(i) subtracting the deciphered sum-equalized signal from a pilot reference signal to generate a joint error signal; and

(j) generating correction objects based on the joint error signal and an individual decryption vector signal.

68. A method for processing signals received by multiple antennas, the method comprising:

(a) generating a plurality of sample data streams, wherein each sample data stream is generated based on the signal received by individual ones of the antennas;

(b) estimating a channel impulse response;

(c) processing the sample data stream according to the estimated channel impulse response to generate a plurality of processed signals;

(d) combining the processed signal; and

(e) Processing the sample data stream.

69. The method of claim 68, wherein a Code Division Multiple Access (CDMA) receiver is used to perform steps (a)-(e), the method further comprising:

(f) Sample the sample data stream at twice the chip rate.

70. The method of claim 68, wherein step (d) comprises:

Multiple multipath components of the signal received by the antenna are combined.

71. The method of claim 68, further comprising:

(f) processing the combined processed signal using filter coefficients; and

(g) generating at least one filter coefficient correction item.

72. The method of claim 68, wherein a Code Division Multiple Access (CDMA) receiver is used to perform steps (a)-(e), the method further comprising:

(f) sampling the sample data stream at twice the chip rate; and

(g) Downsampling the sample data stream to chip rate.

73. The method of claim 71, wherein the filter coefficient correction item is generated according to a de-expanded bootstrap sequence.

74. The method of claim 71, wherein the filter coefficient correction item is generated according to a non-de-expanded bootstrap sequence.

75. The method of claim 71, wherein the filter coefficient correction item is generated using a normalized least mean square (NLMS) algorithm.

76. The method of claim 71, further comprising:

(h) converting the combined processing signal into a length L vector signal;

(i) multiplying the length L vector signal output by the S→P to vector converter by an encryption code conjugate signal to generate a decryption vector signal;

(j) multiplying an equalizer output signal by an encrypted code conjugate signal to generate a decrypted equalizer signal;

(k) subtracting the decrypted equalizer signal from a pilot reference signal to generate an error signal; and

(1) Generate a correction item according to the error signal and the decrypted vector signal.