CN101145762B - Amplifier capable of increasing bandwidth by injecting current and method thereof - Google Patents

Abstract

The present invention discloses an amplifier and a method thereof that can increase bandwidth by injecting current. The amplifier includes an input stage for receiving a first input signal; a load stage coupled to the input stage for outputting a first output signal; a predetermined current source coupled to the input stage for allowing a fixed current to flow; and a first current source coupled to the input stage for injecting a first current into the input stage to output the first output signal.

Description

Amplifier capable of increasing bandwidth by injecting current and method thereof

technical field

The invention relates to an amplifier, in particular to an amplifier with increased bandwidth and a method thereof.

Background technique

Operational amplifiers are one of the most widely used devices, ranging from buffers, filters, analog/digital converters to digital/analog converters. When high performance is required, such as high-speed or high-resolution, analog-to-digital converters, an operational amplifier with high gain and high bandwidth is required.

Please refer to FIG. 1 , which is a schematic diagram of a conventional amplifier 10 . The components within the amplifier 10 are arranged in a telescopic topology. Amplifier 10 includes a plurality of transistors M1-M9. The transistors M1 and M2 are transistors with the same characteristics, and are used as an input stage 12 to respectively receive an input voltage V _ip and an inverse input voltage V _in , and the transistors M3-M8 are used as a load stage 14 , For example, an active load, and the respective bias voltages of the transistors M3 - M8 are V _hn , V _bp1 , V _bp2 . Transistor M9 is biased at V _cmfb and is a tail transistor in amplifier 10, used as a current source to limit currents I ₁ and I ₂ to a fixed reference current I _Q , and is turned on To the ground terminal, since the transistors M5 and M6 are transistors with the same characteristics, and the transistors M7 and M8 are transistors with the same characteristics, the currents _I1 and _I2 correspond to the same current value. If the transistors M1 and M2 are both on, the current I ₁ is equal to half of the current I _Q , and the current I ₁ is equal to the current I ₂ . As shown in FIG. 1 , both the input voltage V _on and the reverse input voltage V _op are coupled to an output capacitor C ₀ . The components in the amplifier 10 are usually configured in a sleeve structure. Compared with other configurations, the amplifier adopting this configuration not only consumes less power, but also can operate at high speed. Because the configuration of the sleeve structure is existing in the industry.

The frequency response of an amplifier is the response of the circuit in the frequency domain, in other words, if the circuit is given a sine wave input, then its response should be a sine wave output with the same frequency, and the sine wave input is otherwise It is amplified by an open loop gain (open loop gain) A ₀ . Such a frequency response can be expressed using a low-pass function.

$h\left(\mathrm{the\; s}\right)=\frac{A_0}{1+\frac{\mathrm{the\; s}}{{\mathrm{\ω}}_p}}$ where, ω _p is a dominant pole (dominate pole), and s=jω

Equation (1)

For frequencies much larger than ω _p , such as ω>>ω _p , the gain A can be estimated as:

$A\left(\mathrm{j\ω}\right)=\frac{A_0{\mathrm{\ω}}_p}{\mathrm{j\ω}}$ Equation (2)

$\left|A\left(\mathrm{j\ω}\right)\right|=\frac{A_0{\mathrm{\ω}}_p}{\mathrm{\ω}}$ Equation (3)

Therefore, by substituting the above results into equation (1), a unity-gain bandwidth (unity-gain bandwidth-h) ω _u can be obtained:

ω _u ＝ A ₀ ω _p Equation (4)

The unity-gain bandwidth can also be expressed by a device's transconductance gm and an output resistance _r0 , so equation (4) can be transformed into the following equation (5):

${\mathrm{\ω}}_u=\frac{\mathrm{gm}\×r_0}{r_0{C}_0}=\frac{\mathrm{gm}}{C_{\mathrm{op}}+C_{\mathrm{load}}}$ Equation (5)

It can be known from equation (5) that the unity gain bandwidth ω _u is a function of the transconductance gm and the overall output capacitance C ₀ , and the overall output capacitance C ₀ includes the parasitic junction capacitance C _op and the value determined by the amplifier 10 The driven capacitive load (capacitive load) C _load , therefore, the way to increase the bandwidth is to increase the transconductance value gm of the device or reduce the output capacitance value C ₀ . The value of the capacitive load C _load is determined by the circuit specification, so it cannot be reduced arbitrarily for a specific application. In addition, if the influence of the parasitic capacitance C _op is much greater than that of the capacitive load C _load , the effect of reducing the capacitive load C _load is not significant. If the value gm is to be transduced, a device with a larger size is required, but this will lead to a larger parasitic capacitance value, so the size of the device cannot be increased without limit. As such, the relationship between gain and bandwidth creates an upper bandwidth limit.

Contents of the invention

Therefore, one of the objectives of the present invention is to provide an amplifier and its method that can increase the bandwidth by injecting current, so as to solve the above problems.

One of the objects of the present invention is an amplifier with current injection and its method, which can increase its bandwidth.

One of the objects of the present invention is an amplifier with current injection and its method, which can maintain the gain.

One of the objects of the present invention is an amplifier with current injection and its method without increasing power consumption or circuit area.

Description of drawings

Figure 1 is a schematic diagram of an existing amplifier.

Fig. 2 is a schematic diagram of a first embodiment of the amplifier of the present invention.

FIG. 3 is a schematic diagram of a second embodiment of the amplifier of the present invention.

Description of reference symbols

10, 20, 30 Amplifier 12, 22 input stage 14, 24, 32 load level 26, 28 Battery 33, 34, 35, 36 gain unit

Detailed ways

FIG. 2 is a schematic diagram of a first embodiment of an amplifier 20 of the present invention. Amplifier 20 can increase bandwidth and maintain high gain under current injection conditions. The amplifier 20 includes an input stage 22 and a load stage 24 . The input stage 22 includes two transistors M1 and M2, and the load stage 24 includes a plurality of transistors M31, M41, M51, M61, M71, M81. The transistor M9 is used as a current source for drawing a fixed reference current I _Q to control the current values of the multiple currents I _a -I _d . If the transistors M1 and M2 are both on, the sum of the currents I _a and I _c is equal to the current I ₁ shown in FIG. 1 , and the sum of the currents I _b and I _d is equal to the current I ₂ shown in FIG. 1 . In one embodiment, the circuit structures of the input stage 22 and the load stage 24 are the same as the circuit structures of the input stage 12 and the load stage 14 shown in FIG. 1 .

As shown in FIG. 2 , the current source 26 includes a series of transistors M72, M52 and M32 electrically connected to each other and coupled to the drain of the transistor M1, and the current source 28 includes a series of transistors M82, M62 and M42 electrically connected to each other. The drain of the transistor M2 injects the currents I _c and I _d into the input stage 22 respectively. In one embodiment, the transistors M72 and M82 have the same bias voltage V _bp1 , the transistors M52 and M62 have the same bias voltage V _bp2 , and the transistors M32 and M42 have the same bias voltage V _bp3 . In addition, the reverse output voltage V _on coupled to an output capacitor C ₀ is coupled to the drain of the transistor M31 , and the output voltage V _op coupled to an output capacitor C ₀ is coupled to the drain of the transistor M41 . In this embodiment, the transistors M32, M42, M51, M52, M61, M62, M71, M72, M81, M82 are PMOS transistors, while the transistors M1, M2, M9, M31, M41 are NMOS transistors. Please note that the configuration of the amplifier of the present invention is not limited to the configuration in this embodiment.

In one embodiment of the present invention, the current sources 26 and 28 are p-type current sources. Since the transistor M9 can still conduct the fixed reference current I _Q to ground, the currents I ₁ , I ₂ shown in FIG. 1 change due to the injected currents I _c , I _d . In order to maintain the same bias state, the size of each device must be adjusted according to the current change of each device. Assuming that the current I _a is set to k*I ₁ , therefore, the channel aspect ratio (W/L) must be adjusted accordingly, in other words, the transistor M71 and the transistor M7 of FIG. 1 The channel width-to-length ratio of is:

${\left(\frac{W}{L}\right)}_{m71}=k*{\left(\frac{W}{L}\right)}_{m7}$ Among them, 0<k<1 Equation (6)

Similarly, the channel width-to-length ratio of the transistor M81 and the transistor M8 in FIG. 1 is:

${\left(\frac{W}{L}\right)}_{m81}=k*{\left(\frac{W}{L}\right)}_{m8}$ Among them, 0<k<1 Equation (7)

The frequency response of the amplifier 20 can be represented by a low-pass function like the aforementioned equation (1). However, the dominant pole ω _p now becomes:

${\mathrm{\&omega;}}_p=\frac{1}{r_0{C}_0}=\frac{1}{r_0(k{C}_{\mathrm{op}}+C_{\mathrm{load}})}$ Equation (eight)

Since the size of the device decreases due to a coefficient k, wherein 0<k<1, the parasitic capacitance C _op also decreases due to the coefficient k.

Putting the above results into the previous equation gives the unity gain bandwidth ω _u as:

${\mathrm{\&omega;}}_u=\frac{\mathrm{gm}\&times;r_0}{r_0{C}_0}=\frac{\mathrm{gm}}{r_0(k{C}_{\mathrm{op}}+C_{\mathrm{load}})}$ Formula (9)

Since the parasitic capacitance C _OP of the device is small, the unity gain bandwidth ω _u is increased by a factor (C _op +C _load )/(kC _op +C _load ) compared with the unity gain bandwidth of FIG. 1 . Note that the circuit dimensions of amplifier 20 are similar to those of amplifier 10 shown in FIG. 1 .

FIG. 3 is a schematic diagram of a second embodiment of an amplifier 30 of the present invention. The amplifier 30 has both a gain boosting mechanism and a current injection structure, which can increase bandwidth and gain simultaneously. Amplifier 30 is similar in structure to amplifier 20 . As shown in Figure 3, a load stage 32 of the amplifier 30 includes: a plurality of gain units 33, 34, 35, 36 for increasing the gain, because the above-mentioned technology of increasing the gain by using the gain units is existing in the industry, Therefore, its related description is omitted here. Compared with the amplifier 20, the amplifier 30 has a larger DC gain (DC gain) A ₀ due to the increased gain, and the bandwidth of the amplifier 30 is increased due to the current injected into the input stage 22 from the current sources 26 and 28 .

Please note that in the above-mentioned embodiments, the current is injected into a differential pair, however, the configurations of the current injection shown in FIG. 2 and FIG. 3 are just examples, that is, this The configuration of the current injection of the invention is not limited to the above embodiments, and can also be implemented in single-ended circuits or other circuits using amplifiers.

The inventive amplifier achieves a higher bandwidth without sacrificing gain, circuit area, or power loss.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (15)

1. amplifier comprises:

One input stage is in order to receive one first input signal;

One load stage is coupled to this input stage, in order to export one first output signal;

One scheduled current source is coupled to this input stage, in order to allow the circulation of a scheduled current; And

One first current source is coupled to this input stage, in order to one first electric current is injected this input stage, and exporting this first output signal,

Wherein, this load stage is an active load, and it includes a plurality of transistors and at least one gain unit that is one another in series and is electrically connected, and this at least one gain unit is coupled at least one transistorized source electrode and the grid in these a plurality of transistors.

2. amplifier as claimed in claim 1, wherein, this first current source, this input stage and this load stage are coupled to a node.

3. amplifier as claimed in claim 1, wherein, this input stage, this load stage and this scheduled current source are disposed in the mode of a tube-in-tube structure.

4. amplifier as claimed in claim 1, wherein, this input stage includes a transistor, and this first input signal inputs to this transistorized grid, and this first electric current is injected into this transistor drain.

5. amplifier as claimed in claim 1, wherein, this first current source is a p type current source.

6. amplifier as claimed in claim 1, wherein, this input stage receives one second input signal in addition, and this load stage is exported one second output signal in addition, and this amplifier comprises in addition:

One second current source is coupled to this input stage, in order to one second electric current is injected this input stage, to export this second output signal.

7. amplifier as claimed in claim 6, wherein, this input stage comprises:

One the first transistor is coupled to this first current source, in order to receive this first input signal; And

One transistor seconds is coupled to this second current source, in order to receive this second input signal.

8. amplifier as claimed in claim 7, wherein, this load stage comprises:

A plurality of the 3rd transistors, being one another in series is electrically connected and is coupled to this first transistor, in order to produce this first output signal; And

A plurality of the 4th transistors, being one another in series is electrically connected and is coupled to this transistor seconds, in order to produce this second output signal.

9. amplifier as claimed in claim 8, wherein, this input stage, this load stage and this scheduled current source are disposed in the mode of a tube-in-tube structure.

10. bandwidth increase method that is used for an amplifier, this amplifier comprises an input stage, a load stage, a scheduled current source and one first current source, this bandwidth increase method comprises:

Use an input stage of this amplifier to receive one first input signal;

Use this scheduled current source of this amplifier to allow the circulation of a scheduled current;

Use this first current source that one first electric current is provided, and this first electric current is injected this input stage; And

Use a load stage of this amplifier to export one first output signal,

Wherein, this load stage is an active load, and it includes a plurality of transistors and at least one gain unit that is one another in series and is electrically connected, and this at least one gain unit is coupled to an at least one transistorized source electrode and the grid in these a plurality of transistors.

11. bandwidth increase method as claimed in claim 10, wherein, this input stage, this load stage and this scheduled current source are disposed in the mode of a tube-in-tube structure.

12. bandwidth increase method as claimed in claim 10, wherein, this input stage includes a transistor, and wherein this first input signal inputs to this transistorized grid, and this first electric current is injected into this transistor drain.

13. bandwidth increase method as claimed in claim 10, wherein, this first current source is a p type current source.

14. bandwidth increase method as claimed in claim 10, other comprises:

One second electric current is provided, and this second electric current is injected this input stage.

15. bandwidth increase method as claimed in claim 14, wherein this input stage, this load stage and this scheduled current source are disposed in the mode of a tube-in-tube structure.

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