CN1011084B - Testing-measuring system and method for variant electronic device - Google Patents

Abstract

A system and method for adjusting various electronic devices. Each electronic device has an internal busbar. When an electronic device with multiple software packages inside is installed or maintained after transportation, each software package stores information related to Each specific electronic device test and adjustment related command data. Usually, various electronic devices are connected to the computer through the bus in the machine, and the various electronic devices are tested according to the information stored in the software package.

Description

The present invention relates generally to a testing system and method suitable for electronic devices in which internal circuitry is digitally controlled, such as televisions, video tape recorders, and tape recorders. In fact, it involves a testing system and method, the adjustment of which is performed externally by a computer through the built-in busbars in these electronic devices.

Video recording equipment or recording equipment such as digital televisions, video tape recorders (VTRs) and tape recorders have recently been commercialized. Most of these digital electronic devices use on-board buses to simultaneously connect the central processing unit (CPU), memory and other control circuits. During normal work, the CPU takes out the control signals of each circuit of each electronic device stored in the read-only memory (ROM), and sends the taken out data to the corresponding circuit through the bus inside the machine to control the machine. work of the internal circuit. In addition, the CPU can also directly control the circuit of the device by manually controlling an external keyboard or remote control input signal.

The above-mentioned internal busbar can generally be a two-wire type or a three-wire type. The two-wire type internal bus is composed of a data transmission line and a clock transmission line. The communication system disclosed in Japanese Patent Laid-Open Showa 57-106262 can also be used for the two-wire type bus. On the other hand, the three-wire type built-in bus consists of a data transmission line, a clock transmission line and a so-called identification signal for identifying the nature of each data group to which the data transmission line is uploaded.

If the testing of the internal circuits of those electronic devices with internal busbars can be standardized, centralized and simplified during the installation and maintenance process, the overall results including manufacturing costs will be reduced.

The task of the present invention is to provide a testing system and method suitable for a digital electronic device with an internal bus.

The above-mentioned inventive task can be realized by the testing system and method of the present invention, which is characterized in that the computer is simultaneously connected to each electronic device with an internal bus. The computer then tests each circuit of the electronic devices with software means storing test semaphores and predicts the test results for each electronic device.

Electronic devices with internal busbars can be tested with an external general-purpose computer. Therefore, the test systems for various electronic devices can be centralized and standardized, resulting in an integrated test system.

The invention can be understood more comprehensively through the following description in conjunction with the accompanying drawings. Reference numerals in the drawings indicate corresponding component parts.

Figure 1 is a simplified block diagram of an electronic device to which the present invention is applied.

Figure 2 shows a simplified block diagram of a preferred embodiment of a test television.

Fig. 3 is a simplified connection diagram of another preferred embodiment for testing various electronic devices according to the present invention.

Figure 4 is a diagrammatic illustration of the two-wire serial bus protocol.

Figure 5 is a diagrammatic illustration of the three-wire serial bus protocol.

Figure 6 is a simplified block diagram of a bus converter.

FIG. 7 is a graphical illustration of a timing diagram for the operation of the circuit shown in FIG. 6. FIG.

In order to facilitate the understanding of the present invention, it will be described with reference to the accompanying drawings.

Fig. 1 is a circuit block diagram of an electronic device applied to the present invention.

In Fig. 1, an electronic device 1 is equipped with a first integrated circuit (IC) device 2, a second integrated circuit (IC) device 3, a central processing unit (CPU) 4, and a memory 5, and these circuit blocks pass through a bus 6 interconnections. The bus bar 6 terminates at an outgoing connector 7 of the electronic device 1 . An external computer 8 for testing the device 1 is connected to the connector 7 through another bus 22 . The computer 8 is connected with a display device 9, such as a CRT monitor, to display the test results.

The above-mentioned first IC device 2 is composed of a bus interface 10 , a digital-to-analog (D/A) converter 11 , analog circuits A-E, a conversion circuit 12 , a conversion control circuit 13 and an analog-to-digital (A/D) converter 14 . The bus interface 10 sends the digital control data received from the CPU 4 through the bus 6. The control signal is given to the D/A converter 11 and the conversion control circuit 13. The control signal both identifies whether the A-E circuit is under control and determines the operation of a specific circuit in the A-E circuit. The D/A converter 11 converts the received signal into an analog signal and uses the latter to control a given one of the circuits A-E. Switching control circuit 13 connects the output of a given one of circuits A-E to A/D converter 14 and drives switch 12 to the corresponding position of contact positions a-e. The A/D converter 14 converts the analog output signal into a corresponding digital signal, and the digital signal returns to the bus 6 through the bus interface 10 . Said above A to E circuit is controlled by CPU4, and tests with computer 8. In this embodiment, five different circuits to be controlled are incorporated in the IC device 2 .

The second IC device 3 is composed of a bus interface 15, an analog-to-digital converter (A/D) 16, a conversion circuit 17, a conversion control circuit 18 and input terminals 19, 20, 21 connecting the conversion circuit with external circuits. The bus interface 15 mentioned above is connected to the bus 6 . The inputs 19 , 20 , 21 are connected to the outputs of the three peripheral circuits F, G, H. These external device circuits F, G, and H are separate circuits rather than integrated circuits, and are controlled by the CPU 4 . The input signals from the external equipment circuits F, G, H are selected by the converter 17 and the conversion controller 18, and then added to the bus 6 through the A/D converter 16 and the bus interface 15.

The following paragraphs describe the operation of the system during installation and maintenance of electronic devices. It will be appreciated that a separate computer 8 will be used for testing during installation and maintenance.

The test during installation was to use a keyboard as a manual input device operated by the computer 8 to generate digital data representing the control signals. The data is fed into the first and second IC devices 2,3 via the bus bar 22, the connector 7 and the bus bar 6.

Data is registered in the first IC device 2 through the bus interface 10 . The registered data are converted into corresponding analog control signals by D/A converter 11 and sent to circuits A to E. The circuits A to E are controlled by control signals which are related to the characteristics of the output signals which are to be adjusted according to the task with the control signal quantities. The received output signal is converted into a digital signal, Then return to the computer 8 through the bus interface 10 and the bus 6,22. The display unit 9 displays the test results of the circuits A to E on a fluorescent screen. These results can be compared to known design characteristics by the operator, who can, if necessary, adjust the input control signals via the keyboard to obtain the desired output.

After confirming that the circuit A-E works normally through the displayed situation, the operator can operate the keyboard to store the input control quantity of the circuit A-E in the memory 5 as a reference value used in normal operation. When the electronic device 1 is in operation, the CPU 4 reads out the reference value recorded in the memory 5, and each A-E circuit performs an operation required according to the read data.

On the other hand, the external equipment circuits F, G, H must be externally controlled and show changes in the output signals of these operating states. These output signals are received by the second IC device 3 , that is, via the input terminals 19 , 20 , 21 by the corresponding contacts f, g, h of the switching circuit 17 .

The switching control circuit 17 selects one of the contacts f, g, and h sequentially or arbitrarily on the basis of the control signal output by the computer 8 . From the circuit F-H, the selected input signal is converted into a digital signal by the A/D converter 16, and then sent to the computer 8 through the bus interface 15 and the buses 6, 22. The display device 9 displays the test results of the external equipment circuits F, G, H on a fluorescent screen.

In the maintenance process, it is necessary to discriminate the situation of the failure. A computer 8 for maintenance and adjustment is connected to the busbar 22. The operator uses the keyboard to type in the specific address of each circuit of the circuits A-E, and selects the circuit to be tested. When the corresponding circuit is selected After going out, computer 8 takes out the appropriate input control quantity stored when installing from memory 5, and outputs a control signal to the designated circuit. As far as circuits A-E are concerned, it is to output a control signal to conversion control circuit 13 or 18 , and then the keyboard operator commands the computer 8 to sample the output current of the specified circuit through the bus 22,6. The computer 8 keeps the previously prepared output level patterns in the corresponding software package, indicating the correct operation of the corresponding circuits A-H. The computer 8 compares the circuit output received on the bus 22 with the stored corresponding level pattern, thereby judging The working state of the circuit is specified, and the comparison result is displayed on the display device 9 . Assuming that the work discussed above is performed on all circuits, any faulty circuits will be detected.

Although in the shown embodiment a computer 8 is used to test circuits A-H during installation and maintenance, the test program and all required reference data stored in the memory can be input remotely into an operating unit. Simultaneously memory 5 and circuits A-H are accessed via bus 6 with this special remote tester as described above.

Fig. 2 is a circuit block diagram of a TV set with an internal bus that can be applied to the present invention. CPU4 among Fig. 2, storer 5, busbar 6, 22 and the numbering of computer 8 are identical with the numbering among Fig. 1.

In the embodiment shown in FIG. 2, corresponding to the control circuits A-E shown in FIG. 1 is an audio processing circuit 25, video control circuit 26, video processing circuit 27, and deflection control circuit 28. In normal operation, CUP4 controls the PLL (Phase Locked Loop) circuit, which is synchronized with each circuit of the above-mentioned 25 to 28, and the tuner 31 tunes with the instructions sent by the keyboard 29 or the remote controller. Manually selected frequency tuning values, volume adjustments, graphic adjustments and similar parameters can be displayed on the display device 33 . The number 34 in Figure 2 represents the remote control signal receiver, the number 35 represents the intermediate frequency amplifier, the number 36, and 37 represent the deflection coil of CRT40, the number 38 represents the audio power amplifier, the number 39 represents the video power amplifier, and the number 40 represents the cathode ray tube (CRT ).

Computer 8 or controller 30 can be used for testing or adjustment during installation and maintenance, as described with reference to FIG. 1 . Operational factors such as linearity, width, pincushion distortion in both directions, horizontal and vertical, etc., within the range to be adjusted can be included, as well as color adjustments such as white balance, R (red), G ( Green) and B (blue) signal off position and start position, grid bias adjustment of CRT40.

In addition, various data obtained by testing during maintenance can be recorded in a memory, recorded on an external recording medium, etc., or sent to a central collection control computer through a telephone line. The central computer can prepare information based on the data obtained by each maintenance station, and Distribute this information to design, development, manufacturing, materials, and maintenance.

Fig. 3 has shown the equipment disposition diagram that is applied to the present invention, and the TV set 45 in this figure, video tape recorder (VTR) 46, and tape recorder 47 all have an internal bus shown in Fig. 1 each, They are simultaneously connected to a computer 8 for testing and adjustment. A commercially available personal computer was used as the computer 8 at this time. According to various devices 45, 46, and 47 that need to be tested, the TV test box 48 selected, the tape video recorder test box 49, and/or the tape recorder test box 50 are connected with the computer 8. The test boxes 48, 49, 50 each have a data storage medium such as magnetic tape, floppy disk, or ROM to store a set of programs, and the stored data are dedicated to the testing and adjustment of the corresponding equipment. In addition, the dedicated device keyboard covers 52, 53, 54 may be prepared for the keyboard of the computer 8. The computer 8 is connected to the bus 6 (not shown in FIG. 3 ) of each device through the bus 22 and the connector 7 .

Because in this embodiment the common computer 8 can be used to test many different electronic devices, it only needs to be used according to the appropriate exchange of the software package for each device, and the testing and adjustment work can be done completely like the relevant computer hardware and interconnection. standardization.

Now that testing has been discussed, the data conversion between the two-wire bus specification and the three-wire bus specification is discussed next. Recently, two-wire and three-wire busbars have been quite commonly used as the above-mentioned built-in busbars.

Figure 4 shows the data packet form of the signal transmission on the two-wire bus. The first transmission line of the two-wire bus transmits the serial data (bit serial) D ₂ , and the second transmission line transmits the clock signal CL ₂ . Each data packet includes: a) the first signal indicating the start of the data packet; b) a 7-bit address signal indicating an address assigned to the controlled circuit; c) indicating that the following data is input to the designated controlled circuit or slave A one-bit R/W (read/write) signal taken out of the designated controlled circuit; d) a one-bit ACK (answer) signal that notifies the computer to specify the controlled circuit to receive the data; e) eight-bit data representing the adjustment amount; f) the desired n subsequent packets, with one bit of ACK signal per eight bit pulse; and g) one bit of stop signal.

Figure 5 shows the signal form transmitted through the three-wire bus.

Its first transmission line transmits serial data D ₃ , the second transmission line transmits clock signal CL ₃ , and the third transmission line transmits identification signal ID, address or data identifying the type of information, often encoded in serial data D ₃ .

Each data packet is started with a one-bit start signal, which drives the identification signal ID to a low potential, indicating that the eight-bit data representing the address enters _D3 . An eight-bit address followed by two octets of data appears. During the entire transmission process of the following 16-bit data, the identification signal is always at a high level, and a short low level will appear according to the stop signal on the _D3 line before finally returning to its higher level, which indicates that the data Packet signal ended.

Figure 6 shows a preferred embodiment of a bus converter for converting transmission signals on a two-wire bus into signals compatible with the three-wire specification. FIG. 7 is a timing chart of the bus converter shown in FIG. 6 .

In FIGS. 6 and 7 , the serial data line D ₂ is connected to the input terminal 61 , and the clock line CL ₂ in FIG. 4 is connected to the other input terminal 62 . First, when a one-bit start signal is detected by the start/stop detection circuit 63 in the data _D2 , the Q output of the flip-flop (F/F) circuit 64 rises to "H" (high) level. The reset terminal (R) of the shift register 65 and the counter 66 are connected to the Q output of the flip-flop 64, and are reset according to the rising edge of the Q output. When these circuits 65 and 66 are reset, the shift register 65 starts to read through the gate circuit 67 receives serial bits of data _D2 at its data terminal D in a manner synchronous with clock _CL2 , while counter 66 starts counting clock pulses _CL2 . Decoder 68 receives the parallel count value of 5-bit width that comes up by counter 66, and output pulse indication important bit-counting position in the data packet D ₂ , particularly corresponding to R/W position respectively, the first ACK bit, the second 8th, 9th, 17th and 18th bit pulses for ACK bit and stop bit. These four output lines are connected in various logic circuits in the bus converter. In particular, the control circuit 69 receives the 8th bit pulse directly and receives the 9th bit pulse and the 18th bit pulse through a common OR circuit 70 . The control circuit 69 generates a gate signal _S0 to make the sequencing "gate" 67 conductive during the 9th bit pulse or the 18th bit pulse, and non-conductive during the 8th bit pulse. This is used to identify the output of the R/W bit and 1st ACK bit of packet _D2 .

The 17th bit pulse from the decoder 68 is sent to the AND gate circuit 72, which also receives the inverted clock pulse _CL2 generated by the inverter 71 connected to the clock terminal C of the shift register 65. The output signal of the AND gate is sent to the set terminal of the latch 73 as the set signal S ₁ . Under the setting signal, the latch 73 locks 15 bits of meaningful serial data, that is, 7 bits of address data and 8 bits of data stored in the shift register 65 . The 15-bit data is then converted into the 16-bit form of the three-wire bus using a data conversion memory ROM (read only memory) 74.

The eighteen-bit pulse from decoder 68 is also applied to another AND gate 75 which also receives the inverted clock pulse _CL2 from inverter 71. The "AND" output signal of the "AND" gate 75, together with the clock signal CL ₃ and the identification ID signal of the generator 77, is sent to the setting terminal S of another shift register 76 as a group of signals S ₂ , and the shift register 76 The data converted by the ROM 74 is latched according to the set signal _S2 .

When the start/stop detection circuit 63 detects a stop signal, the Q output of the flip-flop circuit 64 falls to "L" (low) level. The above-mentioned signal generator 77 generates the clock pulse _CL3 and the identification signal ID of the three-wire bus. The clock pulse _CL3 is output from the output terminal 79 at a desired frequency, and the contents of the shift register 76 are sequentially read out. The identification signal ID is output through another output terminal 80 directly connected to the signal generator 77 . Finally, the contents of the shift register 76 , that is, the 8-bit address and 8-bit data are serially output through another output terminal 78 .

In addition to the bus converter example that converts the data form of the two-wire system into the data form of the three-wire system discussed above, there is also a bus converter that converts the data form of the three-wire system into the data form of the three-wire system; the two can be selected application. It will also be noted that the bus 22 connecting the external computer 8 and the internal bus 6 of various electronic devices must be a two-wire system. system or a three-wire system. Furthermore, the signal generator using the two-wire system shown in FIG. 4 and the signal generator using the three-wire system shown in FIG. 5 may be disposed between the computer 8 and the electronic device to be used. Advanced computers can alternately optionally use two-wire or three-wire signaling systems as well as other signaling systems. A signal converter designed for two-wire/three-wire conversion is available. The bus converters discussed above may be housed in electronic devices.

Claims (5)

1, in order to the device of the various parts of testing apparatus in the installation of digital electronic device and maintenance process, the described parts of electronic equipment are multiple classes, and the described parts of each of electronic equipment comprise a plurality of circuit to be tested, it is characterized in that, described device comprises:

Bus in a plurality of machines that in each described parts of electronic equipment, connect respectively;

Respectively described circuit to be tested in each described parts of electronic equipment selectively is connected to a plurality of conversion equipments of bus in the machine wherein;

Storage is exclusively used in a plurality of software packages of the instruction and data of described multiple class of electronic devices respectively:

And

Computing machine can be connected to the described various parts of electronic equipment in order to according to some selected circuit in the various parts of the content test electronic equipment of described conversion equipment and software package simultaneously by bus in some relevant described machines, and each parts of electronic equipment comprise a storer corresponding to the instruction and data of operate as normal that is connected to bus in its machine and storage from described computing machine;

Thereby described computing machine is used to set up the initial conditions of the operate as normal of each the described parts that is enough to satisfy electronic equipment at the beginning, be included in the described condition of memory stores in each described parts of electronic equipment, and the condition of described storage after this is cancelled from relevant storer.

2, according to the device of claim 1, it is characterized in that this device also comprises the CRT monitor that is connected on the described computing machine, in order to the test result of display electronics assemblies, the operator can be compared test result and known design characteristic.

3,, it is characterized in that bus is a bus in the two-wire type machine in the machine according to the device of claim 1.

4,, it is characterized in that bus in the machine has one two-wire type conversion of signals become the converter of three line style signals according to the device of claim 1.

5, a kind of method of using the various parts of the described equipment of the described device to test of claim 1, the described parts of electronic equipment are multiple classes, the described parts of each of electronic equipment comprise a plurality of circuit to be tested, and respectively have bus in the machine and will circuit to be tested selectively be connected to the conversion equipment of the interior bus of machine; It is characterized in that this method comprises the following steps:

Bus in the machine separately of the various parts of computing machine by electronic equipment is connected with various parts simultaneously and is connected with the circuit of selecting to be tested by the conversion equipment in each described parts of electronic equipment;

But make the described computing machine of a plurality of characteristic software package accesses;

With described computer programming with by bus in the described machine of appointment to the output of the appearance of the circuit of appointment in described electronic equipment sampling;

The output of the described appearance of described specified circuit and particular data in the described software package that is stored in appointment are compared;

Regulate the input of described specified circuit by this way, so that the output of the described appearance of described specified circuit is consistent with the described particular data in the described software package that is stored in described appointment;

To be stored in the storer that is connected to bus in the described appointment machine for the described input of using in the future.

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