CN101089940B - Display apparatus having data compensating circuit - Google Patents

Abstract

In the data compensating circuit and the display device having the same, previously compressed data into which previous frame data is compressed is stored in a memory in advance, a decoder decompresses the previously compressed data from the memory to output previously decompressed data, an encoder— The decoder compresses the current frame data into current compressed data to store the current compressed data in the memory, and decompresses the current compressed data to output the current decompressed data. The first processor outputs a difference between the previously decompressed data and the current decompressed data, and the second processor adds the current frame data and the difference to generate the previously re-decompressed data. The compensator outputs current compensated data based on the previously re-decompressed data and the current frame data. Therefore, the size of the memory can be reduced while avoiding corruption of data.

Description

Display device with data compensation circuit

This application claims the benefit of Korean Patent Application No. 2006-52607 filed on June 12, 2006 and Korean Patent Application No. 2006-73457 filed on August 3, 2006, which are hereby disclosed in their entirety for reference. refer to.

technical field

The present invention relates to a display device, and more particularly, to a display device with a data compensation circuit capable of avoiding data corruption.

Background technique

Generally, a liquid crystal display (LCD) includes two display substrates and a liquid crystal layer interposed between the substrates. The LCD applies an electric field to a liquid crystal layer to control transmission of light passing through the liquid crystal layer by adjusting the strength of the electric field, thereby displaying a desired image.

Recently, LCDs have been widely used as display devices for computers, televisions, and the like to display moving images. However, conventional LCDs are not suitable for displaying moving images because of the slow response speed of liquid crystals.

The slow response of the liquid crystal molecules is due to the time required to charge the liquid crystal capacitor to a sufficient voltage to obtain the desired display brightness. In particular, when the voltage difference between the previous voltage charged in the liquid crystal capacitor and the target voltage is large, the liquid crystal capacitor is not charged to the target voltage during the 1H period when the switching element is turned on. This is the case even if the target voltage is applied to the capacitor from the beginning of the 1H cycle.

To avoid this problem, conventional LCDs employ a dynamic capacitance compensation (DCC) method in order to speed up the response speed of liquid crystals. According to the DCC method, based on the target voltage of the current frame and the previous voltage of the previous frame, a compensation voltage is applied to the pixels during the current frame in order to speed up the response speed of the liquid crystal.

However, in order to store the voltage of the previous frame, an additional frame memory is necessary in the conventional LCD employing the DCC method. As a result, the yield of the LCD decreases due to the number and size of the frame memories, and the manufacturing cost increases.

Contents of the invention

The present invention provides a data compensation circuit capable of improving the yield of a memory by reducing its size and avoiding data corruption.

The present invention also provides a display device with the above-mentioned data compensation circuit.

In an aspect of the present invention, a data compensation circuit includes: a memory, a decoder, an encoder-decoder, a first processor, a second processor, and a compensator. The memory stores compressed data from previous frames, and during the current frame, the decoder decompresses the previously compressed data read from the memory. During the current frame, the encoder-decoder compresses the current frame data, stores the current compressed data in memory, and decompresses the current compressed data to output decompressed data.

The first processor outputs a first difference value indicating a difference between the previously decompressed data and the current decompressed data, and the second processor outputs the previously re-decompressed data based on the first difference value and the current frame data. The compensator compensates the current frame data based on the previously re-decompressed data and the current frame data to output the current compensated data.

In another aspect of the present invention, the data compensation circuit includes: a first memory, a second memory, an encoder, a comparator, a decoder, a compensator, and a data selector.

The (n-2)th compressed data from the (n-2)th frame data (where n represents the current frame) is pre-stored in the first memory, and the (n-1)th compressed data from the (n-1)th frame data 1) The compressed data is pre-stored in the second memory. The encoder converts the nth frame data into the nth compressed data during the nth frame, and the comparator compares the (n-2)th compressed data, the (n-1)th compressed data, and the nth compressed data with each other to output the selected Signal.

The decoder decompresses the nth compressed data, the (n-1)th compressed data, and the (n-2)th compressed data into the nth decompressed data, the (n-1)th decompressed data, and the (n-2)th decompressed data, respectively. ) to decompress the data. The compensator outputs first compensation data based on the nth decompressed data, the (n-1)th decompressed data, and the (n-2)th decompressed data, and the data selector outputs the nth frame data or the first compensated data in response to the selection signal data as output data.

In another aspect of the present invention, the data compensation circuit includes: a first memory, a second memory, a first decoder, a second decoder, an encoder-decoder, a first processor, a second processor, a third processing processor, fourth processor and compensator. The first memory stores the (n-2) compressed data from the (n-2) frame data during the (n-1) frame, and outputs the pre-stored (n-2) compressed data during the n frame, And store the (n-1)th compressed data from the (n-1)th frame data. The second memory stores the (n-1)th compressed data during the (n-1)th frame, and outputs the pre-stored (n-1)th compressed data during the nth frame.

The first decoder decompresses the (n-2)th compressed data during the nth frame to output the (n-2)th decompressed data, and the second decoder decompresses the (n-1)th compressed data during the nth frame to output the (n-1)th decompressed data. The encoder-decoder compresses the nth frame data into nth compressed data to store the nth compressed data in the second memory, and decompresses the nth compressed data into nth decompressed data during the nth frame.

The first processor outputs a first difference indicating the difference between the (n-2)th decompressed data and the nth decompressed data, and the second processor outputs the (n-2)th frame data based on the first difference and the nth frame data. 2) Decompress the data again. The third processor outputs the second difference value indicating the difference between the (n-1)th decompressed data and the nth decompressed data, and the fourth processor generates the (n-th)th frame data based on the second difference value and the nth frame data. 1) Decompress the data again. The compensator compensates the (n-1)-th re-decompressed data based on the (n-2)-th re-decompressed data, the (n-1)-th re-decompressed data, and the n-th frame data to output the (n-1)-th compensated data.

In another aspect of the present invention, a display device includes: a data compensation circuit, a data driving circuit, a gate driving circuit, and a display part. The data compensation circuit receives the nth frame data, and compensates the nth frame data during the nth frame as output data. The data driving circuit converts the compensated data into a data voltage in response to the data control signal to output the data voltage. The gate driving circuit outputs a gate voltage in response to a gate control signal. The display part displays an image in response to the data voltage and the gate voltage.

The data compensation circuit includes: a first memory, a second memory, an encoder, a comparator, a decoder, a compensator and a data selector.

Pre-store the (n-2)th compressed data compressed from the (n-2)th frame data in the first memory, and pre-store the (n-1)th compressed data compressed from the (n-1)th frame data stored in the second memory. The encoder converts the nth frame data into the nth compressed data during the nth frame, and the comparator compares the (n-2)th compressed data, the (n-1)th compressed data, and the nth compressed data with each other to output the selected Signal.

The decoder decompresses the nth compressed data, the (n-1)th compressed data, and the (n-2)th compressed data into the nth decompressed data, the (n-1)th decompressed data, and the (n-2)th decompressed data, respectively. ) to decompress the data. The compensator outputs first compensation data based on the nth decompressed data, the (n-1)th decompressed data, and the (n-2)th decompressed data, and the data selector outputs the nth frame data or the first compensated data in response to the selection signal data as output data.

According to the above description, since the compressed data is stored in the memory, the size of the memory can be reduced. Also, in the case of displaying a freeze frame image, current frame data that is neither compressed nor decompressed is output, thereby avoiding data corruption.

Description of drawings

The above and other advantages of the present invention will become more apparent from the following detailed description considered in conjunction with the accompanying drawings, in which:

1 is a block diagram illustrating an exemplary embodiment of a data compensation circuit according to the present invention;

2 and 3 are graphs showing brightness and voltage corresponding to a current frame compensated by the data compensation circuit shown in FIG. 1;

4 is a block diagram illustrating another exemplary embodiment of a data compensation circuit according to the present invention;

Fig. 5 is an internal block diagram of the compensator shown in Fig. 4;

6 is a block diagram illustrating another exemplary embodiment of a data compensation circuit according to the present invention;

Figure 7 is an internal block diagram of the compensator shown in Figure 6; and

FIG. 8 is a block diagram showing a liquid crystal display device having the data compensation circuit shown in FIG. 1 .

Detailed ways

It will be understood that when an element or layer is referred to as being "on," "connected to," or "joined to" another element or layer, that element or layer can be directly on the other element or layer. On, connected to, or joined to another element or layer, or with intervening elements or layers present. In contrast, when an element is referred to as being "on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, or region without departing from the teachings of the present invention. second layer and/or second section.

For the convenience of description, terms related to space can be used here, such as "under", "under", "below", "on", "above", etc., To describe the relationship of one element or feature shown in the drawings to another (or more) element or feature. It will be understood that the spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented over the other elements or features. Thus, the exemplary term "beneath" can encompass both an orientation of "above" and "beneath". The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, singular forms are intended to include plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the term "comprises" and/or "comprises", when used in this specification, means the existence of the described features, integers, steps, operations, elements and/or components, but does not exclude the existence or addition of an or multiple other features, integers, steps, operations, elements, components and/or groups thereof.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an exemplary embodiment of a data compensation circuit according to the present invention.

Referring to FIG. 1 , the data compensation circuit 100 includes: a memory 110 , a decoder 120 , an encoder-decoder 130 , a first processor 140 , a second processor 150 and a compensator 160 .

In the memory 110, the data Fc(n-1) compressed from the previous frame data F(n-1) is stored in advance. In this embodiment, if the previous frame data F(n-1) includes 24 bits, the previous compressed data Fc(n-1) includes 8 bits compressed to one third of the previous frame data F(n-1). bit. Therefore, the memory 110 is smaller than 2 ^m (m represents the number of bits of the previous frame data F(n-1)). That is, when the previous frame data F(n-1) includes 24 bits, the size of the memory 110 is 2 ⁸ . Also, compressed data having a data amount less than the amount of one frame is stored in the memory 110, so that the size of the memory 110 can be reduced.

During the current frame, the decoder 120 reads out the previously compressed data Fc(n-1) previously stored in the memory 110, and decompresses the previously compressed data Fc(n-1) to output the previously decompressed data Fd(n-1). 1). Specifically, the decoder 120 decompresses m/3-bit previously compressed data Fc(n-1) into m-bit previously decompressed data Fd(n-1).

During the current frame, the encoder-decoder 130 receives the current frame data F(n), and compresses the current frame data F(n) into the current compressed data Fc(n) to store the current compressed data Fc(n) in the memory 110 in. The current frame data F(n) includes m bits, and the current compressed data Fc(n) includes m/3 bits of data. The frame encoder-decoder 130 decompresses the current compressed data Fc(n) during the current frame to output the current decompressed data Fd(n).

The first processor 140 outputs the first difference ΔFd(n) between the previous decompressed data Fd(n-1) and the current decompressed data Fd(n), and the second processor 150 based on the first difference ΔFd(n ) and the current frame data F(n) to generate the previously decompressed (re-decompressed) data Fd'(n-1). Specifically, the second processor 150 adds the first difference ΔFd(n) to the current frame data F(n) to generate the previously re-decompressed data Fd'(n-1). For a free-frame image, the current decompressed data Fd(n) is the same as the previous decompressed data Fd(n-1), so that the first difference ΔFd(n) is equal to zero. Therefore, the second processor 150 may output the same previously re-decompressed data Fd'(n-1) as the current frame data F(n).

The compensator 160 compensates the current frame data F(n) based on the previously re-decompressed data Fd'(n-1) and the current frame data F(n) to output the current compensated data F'(n). Specifically, when the second difference between the previously re-decompressed data Fd'(n-1) and the current frame data F(n) is smaller than the predetermined first reference value, the output of the compensator 160 is the same as the current frame data F (n) The same current compensation data F'(n). Therefore, for a freeze-frame image, the first difference ΔFd(n) is equal to zero, so that the previously re-decompressed data Fd'(n-1) is the same as the current frame data F(n).

During the current frame, current frame data F(n) that is neither compressed nor decompressed is output. Therefore, the current frame data F(n) that has not been processed is used to display the image, thereby avoiding damage to the freeze frame image.

When the second difference is greater than the first reference value, the compensator 160 outputs the current compensation data F'(n) which is increased by a predetermined compensation value compared with the current frame data F(n).

Hereinafter, the current compensation data overdriven (increased or decreased) by the compensator 160 will be described in detail with reference to FIGS. 2 and 3 .

2 and 3 are graphs showing luminance and voltage corresponding to current compensation data compensated by the data compensation circuit shown in FIG. 1 . In Figure 2 and Figure 3, the x-axis represents time, and the y-axis represents voltage and brightness. The voltage represents a voltage applied to the liquid crystal layer at each frame, and the brightness represents the brightness of light transmitted through the liquid crystal layer.

Referring to FIG. 2, previous frame data corresponds to a first target voltage Vt1, and current frame data corresponds to a second target voltage Vt2 higher than the first target voltage Vt1. When the voltage difference between the first target voltage Vt1 and the second target voltage Vt2 is greater than a predetermined reference value, a desired target luminance Lt cannot be obtained within one frame even if the second target voltage is applied to the liquid crystal layer. To solve this problem, the compensator 160 (shown in FIG. 1 ) overdrives (increases) the second target voltage Vt2 to a third target voltage Vt3 higher than the second target voltage Vt2 during the current frame n. Thus, the third target voltage Vt3 is applied to the liquid crystal layer during the current frame n, so the rising time of the voltage of the liquid crystal layer can be reduced, and a desired target luminance Lt can be obtained within one frame.

Referring to FIG. 3, previous frame data corresponds to a first target voltage Vt1, and current frame data corresponds to a second target voltage Vt2 lower than the first target voltage Vt1. When the voltage difference between the first target voltage Vt1 and the second target voltage Vt2 is greater than a predetermined reference value, a desired target luminance Lt cannot be obtained within one frame even if the second target voltage Vt2 is applied to the liquid crystal layer. To solve this problem, the compensator 160 (shown in FIG. 1 ) overdrives (decreases) the second target voltage Vt2 to a third target voltage Vt3 lower than the second target voltage Vt2 during the current frame n. Thus, the third target voltage Vt3 is applied to the liquid crystal layer during the current frame n, so that the falling time of the voltage of the liquid crystal layer can be reduced and a desired target luminance Lt can be obtained within one frame.

As described above, an overdriven (increased or decreased) voltage is applied to the liquid crystal layer, thereby increasing the response speed of the liquid crystal molecules of the liquid crystal layer.

FIG. 4 is a block diagram illustrating another exemplary embodiment of a data compensation circuit according to the present invention. FIG. 5 is an internal block diagram of the compensator shown in FIG. 4 .

4, the data compensation circuit 200 includes: a first memory 210, a second memory 220, a first decoder 230, a second decoder 240, an encoder-decoder 250, a first processor 260, a second processor 270 , a third processor 280 , a fourth processor 290 and a compensator 295 .

In the first memory 210, the (n-2)th compressed data Fc(n-2) from the (n-2)th frame data F(n-2) is stored in advance, and the (n-1)th frame data from the (n-1)th frame data The (n-1)th compressed data Fc(n-1) of F(n-1) is stored in the second memory 220 in advance. The first memory 210 outputs the pre-stored (n-2)th compressed data Fc(n-2) during the nth frame, and stores the (n-1)th compressed data Fc(n-1). The second memory 220 outputs the pre-stored (n-1)th compressed data Fc(n-1) during the nth frame. In this embodiment, if each of the (n-2)th frame data and the (n-1)th frame data includes m bits, then the (n-2)th compressed data and the (n-1)th compressed data Each consists of m/3 bits. Each of the first memory 210 and the second memory 220 is smaller than 2 ^m . As an example of the present embodiment, each of the first memory 210 and the second memory 220 has a size of about 2 ^m/3 .

The first decoder 230 decompresses the (n-2)th compressed data Fc(n-2) during the nth frame to output the (n-2)th decompressed data Fd(n-2), and the second decoder 240 The (n-1)th compressed data Fc(n-1) is decompressed during the nth frame to output the (n-1)th decompressed data Fd(n-1). In this embodiment, the first decoder 230 and the second decoder 240 respectively convert the (n-2)th compressed data Fc(n-2) and the (n-1)th compressed data Fc(n -1) Decompressed into m-bit (n-2)th decompressed data Fd(n-2) and (n-1)th decompressed data Fd(n-1).

The encoder-decoder 250 receives the nth frame data F(n) during the nth frame, and compresses the nth frame data F(n) into the nth compressed data Fc(n) so that the nth compressed data Fc(n) ) is provided to the second memory 220. The encoder-decoder 250 decompresses the nth compressed data Fc(n) during the nth frame to output the nth decompressed data Fd(n).

The first processor 260 outputs the first difference ΔFd(n-2) between the (n-2)th decompressed data Fd(n-2) and the nth decompressed data Fd(n), and the second processor 270 The (n-2)th re-decompressed data Fd'(n-2) is generated based on the first difference ΔFd(n-2) and the n-th frame data F(n). The second processor 270 adds the first difference ΔFd(n-2) to the nth frame data F(n) to generate the (n-2)th re-decompressed data Fd'(n-2).

The third processor 280 outputs the second difference ΔFd(n-1) between the (n-1)th decompressed data Fd(n-1) and the nth decompressed data Fd(n), and the fourth processor 290 The (n-1)th re-decompressed data Fd'(n-1) is generated based on the second difference ΔFd(n-1) and the n-th frame data F(n). The fourth processor 290 adds the second difference ΔFd(n-1) to the nth frame data F(n) to generate the (n-1)th re-decompressed data Fd'(n-1).

The compensator 295 compensates based on the (n-2)th re-decompressed data Fd'(n-2), the (n-1)th re-decompressed data Fd'(n-1) and the n-th frame data F(n) The (n-1)th decompresses the data Fd'(n-1) again to output the (n-1)th compensation data F'(n-1).

As shown in FIG. 5 , the compensator 295 includes: a first compensator 296 and a second compensator 297 . The first compensator 296 generates the (n-1)th compensation solution based on the (n-2)th re-decompressed data Fd'(n-2) and the (n-1)th re-decompressed data Fd'(n-1) Compressed data F"(n-1). The second compensator 297 generates the (n-1)th compensated data Fd"(n-1) based on the (n-1)th compensated decompressed data Fd"(n-1) and the nth frame data F(n). Data F'(n-1).

Specifically, when the third difference between the (n-2)th re-decompressed data Fd'(n-2) and the (n-1)th re-decompressed data Fd'(n-1) is smaller than the predetermined When the first reference value is used, the first compensator 296 outputs the (n-1)th compensated decompressed data Fd"(n-1) identical to the (n-1)th re-decompressed data Fd'(n-1), And when the third difference is greater than the predetermined first reference value, the first compensator 296 outputs the (n-1)th compensation solution overdriven from the (n-1)th decompressed data Fd'(n-1) again Compressed data Fd"(n-1).

For a freeze frame image, each of the first difference ΔFd(n-2) and the second difference ΔFd(n-1) is equal to zero, so that the (n-2)th decompressed data Fd'(n-2) and Each of the (n-1)th re-decompressed data Fd'(n-1) is equal to the n-th frame data F(n). In addition, the third difference is equal to zero, and the first compensator 296 outputs the (n-1)th compensated decompressed data Fd"(n-1) which is the same as the n-th frame data F(n).

At the same time, when the (n-1)th compensated decompressed data Fd"(n-1) is smaller than the second reference value and the nth frame data F(n) is larger than the third reference value, the second compensator 297 generates a ratio higher than the ( n-1) The (n-1)th compensation data F'(n-1) that compensates the second compensation value greater than the decompressed data Fd"(n-1). When the (n-1)th compensated decompressed data Fd"(n-1) is greater than the second reference value or the nth frame data F(n) is less than the third reference value, the second compensator 297 generates the same value as the (n-th 1) The (n-1)th compensation data F'(n-1) that is the same as the decompressed data Fd"(n-1) is compensated.

For a freeze frame image, the second compensator 297 generates the (n-1)th compensated data F'(n-1) identical to the (n-1)th compensated decompressed data Fd"(n-1). Because the ( n-1) compensated decompressed data Fd”(n-1) is the same as the nth frame data F(n), so the (n-1)th compensated data F’(n-1) is equal to the nth frame data F(n ).

Likewise, when a freeze frame image is displayed, each of the first compensator 296 and the second compensator 297 outputs n-th frame data F(n) that is neither compressed nor decompressed. Therefore, the n-th frame data F(n) that has not been processed is used to display the image, thereby avoiding damage to the freeze frame image.

FIG. 6 is a block diagram illustrating another exemplary embodiment of a data compensation circuit according to the present invention, and FIG. 7 is an internal block diagram of the compensator illustrated in FIG. 6 .

Referring to FIG. 6 , the data compensation circuit 900 includes: a first memory 910 , a second memory 920 , an encoder 930 , a comparator 940 , a decoder 950 , a compensator 960 and a data selector 970 .

In the first memory 910, the (n-1)th compressed data Fc(n-1) compressed from the (n-1)th frame data F(n-1) is stored in advance, and the (n-2)th frame The (n-2)th compressed data Fc(n-2) compressed by the data F(n-2) is stored in the second memory 920 in advance. Each of the first memory 910 and the second memory 920 is less than 2m/i (m represents the bit of the (n-1)th frame data F(n-1) and the (n-2)th frame data F(n-2) number, i represents the value obtained by dividing m bits by the number of bits to be compressed).

In this embodiment, when the (n-1)th frame data F(n-1) includes 24 bits, the (n-1)th compressed data Fc(n-1) includes the compressed (n-1th) 1) Eight bits of one-third of the frame data F(n-1). Accordingly, the size of each of the first memory 910 and the second memory 920 is 2 ⁸ . Also, compressed data having a data amount smaller than the amount of one frame is stored in each of the first memory 910 and the second memory 920, so that the sizes of the first memory 910 and the second memory 920 can be reduced.

The encoder 930 receives the nth frame data F(n) during the nth frame period, and compresses the nth frame data F(n) into nth compressed data Fc(n). The (n-1)th compressed data Fc(n-1) and the (n-2)th compressed data Fc(n-2) stored in the first memory 910 and the second memory 920 respectively in advance are read out during the nth frame. ).

The comparator 940 receives the nth compressed data Fc(n), the (n-1)th compressed data Fc(n-1) and the (n-2)th compressed data Fc(n-1) from the encoder 930, the first memory 910 and the second memory 920, respectively. Data Fc(n-2). When the nth compressed data Fc(n) is the same as the (n-1)th compressed data Fc(n-1) and the (n-2)th compressed data Fc(n-2), the comparator 940 output has a first state The selection signal S1. Also, when the n-th compressed data Fc(n) is different from the (n-1)-th compressed data Fc(n-1) and the (n-2)-th compressed data Fc(n-2) and the (n-1)-th compressed When the data Fc(n-1) is the same as the (n-2)th compressed data Fc(n-2), the comparator 940 outputs a selection signal S1 having a second state.

The decoder 950 includes: a first decoder 951 , a second decoder 952 and a third decoder 953 . The first decoder 951 receives the nth compressed data Fc(n) from the encoder 930, and decompresses the nth compressed data Fc(n) into the nth decompressed data Fd(n) to output the nth decompressed data Fd(n) n). The second decoder 952 receives the (n-1)th compressed data Fc(n-1), and decompresses the (n-1)th compressed data Fc(n-1) into the (n-1)th decompressed data Fd (n-1) to output the (n-1)th decompressed data Fd(n-1). The third decoder 953 receives the (n-2)th compressed data Fc(n-2), and decompresses the (n-2)th compressed data Fc(n-2) into the (n-2)th decompressed data Fd (n-2) to output the (n-2)th decompressed data Fd(n-2).

The compensator 960 receives the nth decompressed data Fd(n), the (n-1)th decompressed data Fd(n-1) and the (n-2) decompresses the data Fd(n-2). The compensator 960 outputs first compensation data based on the nth decompressed data Fd(n), the (n-1)th decompressed data Fd(n-1), and the (n-2)th decompressed data Fd(n-2) Fd"(n-1).

The data selector 970 receives the first compensation data Fd"(n-1), the nth frame data F(n) and the selection signal S1 from the comparator 940 to output data F'(n-1). Specifically, When the selection signal S1 with the first state is input, the data selector 970 outputs the nth frame data F(n) as the output data F'(n-1). When the selection signal S1 with the second state is input, the data selection The controller 970 outputs the first compensation data Fd"(n-1) as output data F'(n-1).

As shown in FIG. 7 , the compensator 960 includes: a first compensator 961 and a second compensator 962 .

The first compensator 961 outputs second compensation data Fd'(n-1) based on the (n-1)th decompressed data Fd(n-1) and the (n-2)th decompressed data Fd(n-2). The second compensator 962 outputs the first compensation data Fd"(n-1) based on the second compensation data Fd'(n-1) and the nth decompressed data Fd(n).

When the difference between the (n-2)th decompressed data Fd(n-2) and the (n-1)th decompressed data Fd(n-1) is smaller than a predetermined reference value, the first compensator 961 outputs the ( n-1) Decompresses the data Fd(n-1). When the difference is greater than the reference value, the first compensator 961 outputs the second compensation data Fd'(n- 1).

The second compensator 962 receives the second compensation data Fd'(n-1) and the nth decompressed data Fd(n) to output the first compensation data. As the present exemplary embodiment, the first compensation data Fd"(n-1) has an intermediate value between the second compensation data Fd'(n-1) and the nth decompressed data Fd(n).

According to another embodiment of the present invention, the data compensation circuit 900 further includes a look-up table (LUT, not shown). Accordingly, the second compensator 962 may output compensation data from the LUT based on the second compensation data Fd'(n-1) and the nth decompressed data Fd(n) as the first compensation data Fd"(n-1).

The data selector 970 outputs the first compensation data Fd"(n-1) or the nth frame data F(n) as the output data F'(n-1) according to the state of the selection signal S1.

Therefore, in order to display a freeze frame image, the data compensation circuit 900 outputs uncompressed nth frame data F(n), thereby avoiding data corruption. Also, when converting a freeze frame image to a moving image, the data compensation circuit 900 outputs an intermediate value based on data from the freeze frame image and data of the moving image, thereby avoiding data corruption at the time of conversion.

FIG. 8 is a block diagram showing a liquid crystal display device having the data compensation circuit shown in FIG. 1 .

8, the liquid crystal display device 1000 includes: a display part 300, displaying an image; a gate driving circuit 400, and a data driving circuit 500, driving the display part 300; a grayscale voltage generator 800, connected to the data driving circuit 500; The timing controller 600 controls the driving of the gate driving circuit 400 and the data driving circuit 500 .

A plurality of gate lines GL1˜GLn receiving gate voltages and a plurality of data lines DL1˜DLm receiving data voltages are arranged on the display part 300 . The gate lines GL1˜GLn and the data lines DL1˜DLm define a plurality of pixel regions in a matrix structure, and pixels 310 are arranged in each pixel region. The pixel 310 includes: a thin film transistor 311 , a liquid crystal capacitor (liquid crystal capacitor) C _LC and a storage capacitor (storage capacitor) C _ST .

As shown in FIG. 8, the thin film transistor 311 includes a gate electrode connected to the first gate line GL1, a source electrode connected to the first data line DL1, and a drain electrode connected to the liquid crystal capacitor _CLC and the storage capacitor _CST .

In this embodiment, the display part 300 includes: a lower substrate, an upper substrate facing the lower substrate, and a liquid crystal layer disposed between the lower substrate and the upper substrate.

The gate lines GL1˜GLn, the data lines DL1˜DLm, the thin film transistor 311, and a pixel electrode serving as a first electrode of the liquid crystal capacitor _CLC are formed on the lower substrate. Accordingly, the thin film transistor 311 applies the data voltage to the pixel electrode in response to the gate voltage.

A common electrode serving as a second electrode of the liquid crystal capacitor _CLC is formed on the upper substrate, and a common voltage is applied to the common electrode. A liquid crystal layer interposed between the pixel electrode and the common electrode serves as a dielectric. Thus, a voltage corresponding to a potential difference between the data voltage and the common voltage is charged in the liquid crystal capacitor C _LC .

The gate driving circuit 400 is electrically connected to the gate lines GL1˜GLn arranged on the display part 300 to supply gate voltages to the gate lines GL1˜GLn. The data driving circuit 500 is electrically connected to the data lines DL1˜DLm arranged on the display part 300, and selects a grayscale voltage from the grayscale voltage generator 800 to supply the grayscale voltage to the data lines DL1˜DLm as data voltage.

The timing controller 600 receives various control signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock MCLK, a data enable signal DE, and the like. The timing controller 600 outputs a gate control signal CONT1 and a data control signal CONT2 based on various control signals.

The gate control signal CONT1 is provided to the gate driving circuit 400 to control the driving of the gate driving circuit 400 . The gate control signal CONT1 includes a vertical start signal to start driving of the gate driving circuit 400 , a gate clock signal to determine an output time of the gate voltage, and an output enable signal to determine an ON pulse width of the gate voltage.

The gate driving circuit 400 outputs the gate voltage as a gate-on voltage Von or a gate-off voltage Voff in response to a gate control signal CONT1 from the timing controller 600 .

The data control signal CONT2 is supplied to the data driving circuit 500 as a signal controlling driving of the data driving circuit 500 . The data control signal CONT2 includes: a vertical start signal for starting the driving of the data driving circuit 500 , a switching signal for switching the polarity of the data voltage, and an output instruction signal for determining an output time of the data voltage from the data driving circuit 500 .

The timing controller 600 is formed in a chip form, and the data compensation circuit 100 shown in FIG. 1 is built in the timing controller 600 . Specifically, compressed data is stored in the memory 110 (shown in FIG. 1 ), so that the size of the memory 110 can be reduced, and the memory 110 can be built in the timing controller 600 .

The data compensation circuit 100 receives current frame data F(n) from an external graphics controller (not shown), and compensates the current frame data F(n) into current compensation data F'(n) during the current frame. The data driving circuit 500 receives the current compensation data F'(n) in response to the data control signal CONT2 from the timing controller 600, and selects the gray level voltage corresponding to the current compensation data F' from the gray level voltage generator 800. (n) gray-scale voltage. Then, the data driving circuit 500 converts the selected gray scale voltage into a data voltage to output the data voltage.

Accordingly, the display part 300 displays an image in response to the data voltage and the gate voltage. Specifically, in the case of freezing the frame image, the current compensation data F'(n) is changed to a data voltage corresponding to the current frame data F(n) that is neither compressed nor decompressed, so that the display part 300 Images can be displayed using uncorrupted data.

According to the above description, the frame data is compressed and stored in the memory, and after decompressing the frame data read from the memory, the decompressed frame data is supplied to the compensator. Therefore, the size of the memory can be reduced, and the memory can be built in the timing controller, thereby reducing the manufacturing cost and increasing the yield. Furthermore, in the case of displaying a freeze-frame image, current frame data that is neither compressed nor decompressed is used to display the image, thereby avoiding data corruption.

The data compensation circuit compares the compressed data corresponding to three consecutive frames, and outputs the uncompressed current frame data or the intermediate value between the current frame data and the first compensation data according to the comparison result. As a result, display devices can improve responsiveness and avoid data corruption due to compression.

Although exemplary embodiments of the present invention have been described, it should be understood that the present invention should not be limited to these exemplary embodiments, and those of ordinary skill in the art can Various changes and modifications are made thereto.

Claims (28)

1. A data compensation circuit, comprising: a memory for storing previously compressed data into which the previous frame data is compressed; a decoder for decompressing previously compressed data read from memory during a current frame to output previously decompressed data; an encoder-decoder that compresses the current frame data into current compressed data during the current frame to store the current compressed data in a memory, and decompresses the current compressed data to output the current decompressed data; a first processor, outputting a first difference value indicative of a difference between the previously decompressed data and the current decompressed data; a second processor, outputting previously re-decompressed data based on the first difference and the current frame data; and a compensator that compensates the current frame data based on the previously re-decompressed data and the current frame data to output the current compensated data, Wherein, when the second difference indicating the difference between the previously re-decompressed data and the current frame data is smaller than a predetermined first reference value, the compensator outputs the current compensation data having the same value as the current frame data, and when the When the second difference is greater than the first reference value, the compensator outputs the current compensation data with a predetermined compensation value increased compared with the current frame data, Wherein, when the first difference is equal to zero, the second processor outputs the same previously re-decompressed data as the current frame data, and the current compensation data is equal to the current frame data. 2. The data compensation circuit according to claim 1, wherein the previous re-decompressed data is the sum of the current frame data and the first difference. 3. The data compensation circuit according to claim 1, wherein the size of the memory is smaller than 2 ^m , wherein m represents the number of bits of the current frame data. 4. The data compensation circuit according to claim 3, wherein the size of the memory is 2 ^m/3 . 5. The data compensation circuit of claim 4, wherein the decoder decompresses m/3 bits of previously compressed data into m bits of previously decompressed data, and the encoder-decoder compresses m bits of current frame data is the current compressed data of m/3 bits. 6. A data compensation circuit, comprising: The first memory stores in advance the (n-2) compressed data compressed from the (n-2) frame data, where n represents the current frame; The second memory stores in advance the (n-1)th compressed data compressed from the (n-1)th frame data; The first decoder decompresses the (n-2)th compressed data during the nth frame to output the (n-2)th decompressed data; The second decoder decompresses the (n-1)th compressed data during the nth frame to output the (n-1)th decompressed data; an encoder-decoder that compresses the nth frame data into nth compressed data during the nth frame to provide the nth compressed data to the second memory, and decompresses the nth compressed data to output the nth decompressed data; a first processor, outputting a first difference value indicative of a difference between the (n-2)th decompressed data and the nth decompressed data; The second processor outputs (n-2) decompressed data again based on the first difference and the nth frame data; a third processor, outputting a second difference indicating a difference between the (n-1)th decompressed data and the nth decompressed data; The fourth processor outputs the (n-1)th decompressed data again based on the second difference value and the nth frame data; a compensator that compensates the (n-1)th re-decompressed data based on the (n-2)th re-decompressed data, the (n-1)-th re-decompressed data, and the n-th frame data to output the (n-1)th re-decompressed data ) compensation data. 7. The data compensation circuit as claimed in claim 6, wherein the (n-2) decompressed data is the sum of the nth frame data and the first difference, and the (n-1) decompressed data again is the sum of the nth frame data and the second difference. 8. The data compensation circuit according to claim 6, wherein each of the first memory and the second memory is smaller than 2 ^m , wherein m represents the number of bits of the nth frame data. 9. The data compensation circuit of claim 8, wherein the first memory and the second memory each have a size of 2 ^m/3 . 10. A data compensation circuit comprising: The first memory stores in advance the (n-2)th compressed data compressed from the (n-2)th frame data, where n represents the current frame; The second memory stores in advance the (n-1)th compressed data compressed from the (n-1)th frame data; An encoder that converts the nth frame data into the nth compressed data during the nth frame; A comparator is used to compare (n-2) compressed data, (n-1) compressed data and n compressed data to output a selection signal; A decoder for decompressing the nth compressed data, the (n-1)th compressed data, and the (n-2)th compressed data into the nth decompressed data, the (n-1)th decompressed data, and the (n-th)th decompressed data, respectively. 2) Decompress the data; a compensator that outputs first compensation data based on the nth decompressed data, the (n-1)th decompressed data, and the (n-2)th decompressed data; and The data selector outputs the nth frame data or the first compensation data as its output data in response to the selection signal. 11. The data compensation circuit of claim 10, wherein the compensator comprises: a first compensator that outputs second compensation data based on the (n-1)th decompressed data and the (n-2)th decompressed data; and The second compensator outputs the first compensation data based on the second compensation data and the nth decompressed data. 12. The data compensation circuit of claim 11, wherein the second compensator outputs an intermediate value between the second compensation data and the n-th decompressed data as the first compensation data. 13. The data compensation circuit according to claim 11, wherein when the difference indicating the difference between the (n-2)th decompressed data and the (n-1)th decompressed data is smaller than a predetermined reference value, the th A compensator outputs the (n-1)th decompressed data, and when the difference is greater than the predetermined reference value, the output of the first compensator is increased by a predetermined compensation value compared with the (n-1)th decompressed data The second compensation data. 14. The data compensation circuit according to claim 10, wherein when the nth compressed data is equal to the (n-2)th compressed data and the (n-1)th compressed data, the comparator outputs a selection signal having a first state, When the n-th compressed data is different from the (n-2)-th compressed data and the (n-1)-th compressed data, and the (n-1)-th compressed data is the same as the (n-2)-th compressed data, the comparator output has Select signal for the second state. 15. The data compensation circuit according to claim 14 , wherein the data selector outputs the nth frame data as output data in response to a selection signal having a first state, and outputs the first compensation data in response to a selection signal having a second state as output data. 16. The data compensation circuit of claim 10, wherein each of the first memory and the second memory has a size smaller than 2 ^m , where m represents the number of bits of the nth frame data. 17. A display device comprising: A data compensation circuit that generates current compensation data based on previous frame data and current frame data; a data driving circuit, outputting a data voltage corresponding to the current compensation data in response to the data control signal; a gate drive circuit that outputs a gate voltage in response to a gate control signal; and a display part that displays an image in response to the data voltage and the gate voltage, The data compensation circuit includes: a memory that pre-stores previously compressed data compressed from previous frame data; a decoder for decompressing previously compressed data read from memory during a current frame to output previously decompressed data; an encoder-decoder that compresses the current frame data into current compressed data during the current frame to store the current compressed data in a memory, and decompresses the current compressed data to output the current decompressed data; a first processor, outputting a first difference value indicative of a difference between the previously decompressed data and the current decompressed data; a second processor, outputting previously re-decompressed data based on the first difference and the current frame data; and a compensator that compensates the current frame data based on the previously re-decompressed data and the current frame data to output the current compensated data, Wherein, when the second difference indicating the difference between the previously re-decompressed data and the current frame data is smaller than a predetermined first reference value, the compensator outputs the current compensation data having the same value as the current frame data, and when the When the second difference is greater than the first reference value, the compensator outputs the current compensation data with a predetermined compensation value increased compared with the current frame data, Wherein, when the first difference is equal to zero, the second processor outputs the same previously re-decompressed data as the current frame data, and the current compensation data is equal to the current frame data. 18. The display device according to claim 17, wherein the previously re-decompressed data is a sum of current frame data and the first difference value. 19. The display device according to claim 17, wherein the size of the memory is smaller than ^2m , wherein m represents the number of bits of the current frame data. 20. The display device of claim 17, further comprising: a timing controller to apply the data control signal and the gate control signal to the data driving circuit and the gate driving circuit, respectively, in response to an external control signal. 21. The display device according to claim 20, wherein the timing controller is formed in a chip form, and the data compensation circuit is built in the timing controller. 22. The display device as claimed in claim 17, wherein the display part comprises a plurality of pixels arranged in a matrix structure thereon, each of said pixels comprising: a thin film transistor outputting a data voltage in response to a gate voltage; and The liquid crystal capacitor is charged with a potential difference between the data voltage and a predetermined reference voltage. 23. A display device comprising: The data compensation circuit receives the nth frame data during the nth frame period to compensate the nth frame data as output data; a data driving circuit, which converts the compensated data into a data voltage in response to a data control signal, so as to output the data voltage; a gate drive circuit that outputs a gate voltage in response to a gate control signal; and a display part that displays an image in response to the data voltage and the gate voltage, The data compensation circuit includes: The first memory stores in advance the (n-2)th compressed data compressed from the (n-2)th frame data; The second memory stores in advance the (n-1)th compressed data compressed from the (n-1)th frame data; An encoder that converts the nth frame data into the nth compressed data during the nth frame; a comparator for comparing the (n-2)th compressed data, the (n-1)th compressed data, and the nth compressed data with each other to output a selection signal; A decoder for decompressing the nth compressed data, the (n-1)th compressed data, and the (n-2)th compressed data into the nth decompressed data, the (n-1)th decompressed data, and the (n-th)th decompressed data, respectively. 2) Decompress the data; a compensator that outputs first compensation data based on the nth decompressed data, the (n-1)th decompressed data, and the (n-2)th decompressed data; and The data selector outputs the nth frame data or the first compensation data as output data in response to the selection signal. 24. The display device of claim 23, wherein the compensator comprises: a first compensator that outputs second compensation data based on the (n-1)th decompressed data and the (n-2)th decompressed data; and The second compensator outputs the first compensation data based on the second compensation data and the nth decompressed data. 25. The display device as claimed in claim 23, wherein when the nth compressed data is equal to the (n-2)th compressed data and the (n-1)th compressed data, the comparator outputs a selection signal having a first state, When the n-th compressed data is different from the (n-2)-th compressed data and the (n-1)-th compressed data, and the (n-1)-th compressed data is the same as the (n-2)-th compressed data, the comparator output has Select signal for the second state. 26. The display device as claimed in claim 25, wherein the data selector outputs the nth frame data as the output data in response to the selection signal having the first state, and outputs the first compensation data as the output data in response to the selection signal having the second state. Output Data. 27. The display device of claim 23, further comprising a timing controller to apply the data control signal and the gate control signal to the data driving circuit and the gate driving circuit, respectively, in response to an external control signal. 28. The display device according to claim 27, wherein the timing controller is formed in a chip form, and the data compensation circuit is built in the timing controller. the

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