CN101060135A - A double silicon nanowire wrap gate field-effect transistor and its manufacture method - Google Patents

Abstract

The invention provides a double-silicon nanowire-enclosed gate field-effect transistor and a preparation method thereof, belonging to the technical field of metal-oxide-semiconductor field-effect transistors in ultra-large-scale integrated circuits (ULSI). The field-effect transistor is based on a bulk silicon substrate, and the channel is a double-silicon nanowire with the same cross-sectional structure as a circle. The double-silicon nanowire is surrounded by a gate oxide and a polysilicon gate to form a surrounding gate structure. The source and drain are connected to the bulk The silicon substrate is connected, and there is a thick silicon dioxide insulating layer directly below the channel and between the bulk silicon substrate, forming a structure in which the channel is on the insulating layer. The invention has obvious advantages and broad application prospects in the application of low power consumption and high-speed logic circuits. The present invention also provides a preparation method of the above-mentioned field effect transistor, which is fully compatible with conventional CMOS technology, does not require SOI substrate and high-cost epitaxy process, and can reduce substrate cost and process preparation cost.

Description

A double-silicon nanowire-enclosed gate field-effect transistor and its preparation method

technical field

The invention belongs to the technical field of metal oxide semiconductor field effect transistor (MetalOxide Silicon Field Effect Transistor-MOSFET) in ultra-large-scale integrated circuit (ULSI), and in particular relates to a double-silicon nanowire-enclosed gate field-effect transistor and a preparation method thereof.

Background technique

With the wide application and high-speed development of VLSI, MOSFET technology has entered the nanometer field (<100nm). However, when the gate length of a conventional single-gate MOSFET (which can be referred to as a device) is scaled down to sub-50nm, problems such as poor gate control capability, deterioration of short-channel effect, large leakage current, and insufficient on-state drive current will become more apparent. It's getting serious. In order to improve the gate control ability of MOSFET as much as possible, reduce the leakage current, increase the on-state drive current, increase the switching ratio, and suppress the short-channel effect, many double-gate or multi-gate devices have been proposed, such as FinFET double-gate devices (along The cross-sectional structure in the vertical direction of the channel is shown in Fig. 1(a), a tri-gate device (as shown in Fig. 1(b)), an Ω-gate device (as shown in Fig. 1(c)) and a surrounding gate (Gate- all-around, referred to as GAA, as shown in Figure 1(d)) devices, etc. Under the same conditions, the gate-enclosed device has the strongest gate control ability and the best characteristics. As the gate length of the device is scaled down, in order to maintain good electrical characteristics, enhance gate control capability, and reduce leakage current, the channel cross-section size of double-gate or multi-gate devices will be reduced to about 10nm. It becomes a silicon nanowire (Si nanowire) device. Silicon nanowire multi-gate or surrounding gate devices have attracted great attention and research enthusiasm due to their strong gate control ability, obvious short-channel effect suppression, and excellent device characteristics.

However, the silicon nanowire multi-gate or surrounding gate devices that have been reported are either limited by the structure itself, or will bring difficulties in process preparation, etc., so that the advantages of silicon nanowire multi-gate or surrounding gate devices are often not fully reflected. .

For example, the nanowire Ω-gate device shown in Document 1 (F.L.Yang, D.H.Lee, H.Y. Chen, et al., "5nm-gate nanowire FinFET", in Symp.VLSl Tech.Dig, 2004, pp:196-197) (As shown in Figure 2(a)-(d)), there are the following problems: (1) it is prepared on an SOI substrate, and the cost is very high; (2) because the preparation of silicon nanowires requires a very thin top silicon film, SOI The channel on the substrate has the same thickness as the silicon film of the source and drain, as shown in Figure 2(c), which increases the parasitic series resistance of the source and drain and limits the on-state drive current; (3) at the same time, the silicon nanowire device The cross-sectional structure along the vertical direction of the channel is an Ω gate structure, as shown in Figure 2(b) and (d), which is not a surrounding gate structure, and the gate control capability needs to be further improved.

In response to the problems in Document 1, Document 2 (S.D.Suk, S.Y. Lee, et al., "High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability", in IEDM Tech.Dig., 2005, pp: 717-720) proposed a silicon nanowire-enclosed gate field-effect transistor as shown in Figure 3(a)-(c), which is based on a bulk silicon substrate, reducing the substrate cost; both source and drain Connected to the bulk silicon substrate, a deeper source-drain junction can be used to reduce the parasitic series resistance of the source and drain and increase the on-state drive current; as shown in Figure 3(b) and (c), in the bulk silicon substrate The upper channel is a double-silicon nanowire with the same cross-sectional structure as a circle, and is surrounded by gate oxide and polysilicon gate to form a double-silicon nanowire gate-enclosed device; it can significantly improve the gate control capability, suppress the short channel effect, and The on-state drive current is nearly doubled.

However, there is still a very serious problem in the device with this structure: as shown in Figure 3 (b) and (c), there is a parasitic tube on the surface of the bulk silicon substrate directly below the double silicon nanowire, which is formed by It consists of parasitic gate oxide, parasitic channel and common source, drain and polysilicon gate. That is to say, the device with this structure shown in Document 2 has two field effect transistors at the same time, one is the double silicon nanowire gate device field effect transistor (which can be called an intrinsic transistor) required by the design, and the other is a bulk silicon Parasitic tubes on the substrate surface (need to be avoided or eliminated as much as possible). Therefore, the device with this structure shown in Document 2 has the following disadvantages: (1) The parasitic tube increases the leakage current of the entire device and reduces the switching ratio, which increases the power consumption of the device and is not suitable for low-power logic ( Low-power Logic) application; (2) The gate capacitance of the parasitic tube also increases the total gate capacitance, which deteriorates the AC characteristics of the device and reduces the switching speed of the device, which is not suitable for high-speed logic (High-speed Logic) applications; (3) At the same time, in the process preparation, the SiGe etching sacrificial layer in Document 2 and the silicon channel as the nanowire are both epitaxially grown, and the process cost is still high.

Therefore, how to further optimize the device structure and process preparation method of the silicon nanowire gate device, improve the device performance, and fully reflect the advantages of the silicon nanowire gate device are the difficulties and hot spots in the field of MOSFET research in the world.

Contents of the invention

Aiming at the problems existing in the above silicon nanowire gate-enclosed device, in order to further optimize the DC characteristics and AC characteristics of the device and increase the switching speed of the device, the present invention proposes a dual silicon nanowire-enclosed gate field effect transistor.

A double-silicon nanowire-enclosed gate field-effect transistor, based on a bulk silicon substrate, the channel is a double-silicon nanowire with the same cross-sectional structure as a circle, and the double-silicon nanowire is surrounded by a gate oxide and a polysilicon gate to form a surrounding gate Structure, the source and drain are connected to the bulk silicon substrate, and there is a thick silicon dioxide insulating layer directly below the channel and between the bulk silicon substrate, forming a structure in which the channel is on the insulating layer.

The diameter of the double silicon nanowire is ≤10nm.

The junction depth of the source and the drain is greater than the diameter of the double silicon nanowire, which is 30-50nm.

The silicon dioxide insulating layer directly below the channel and between the bulk silicon substrate has a thickness of 200-300nm.

Another object of the present invention is to provide a method for preparing the above-mentioned double silicon nanowire gate-enclosed device. The preparation method, as shown in Figure 6(a)-(n), comprises the following steps:

1) On the bulk silicon substrate, deposit silicon dioxide and silicon nitride, lithography the active area, etch silicon nitride and silicon dioxide to form a double-layer hard mask;

2) Etching the silicon in the field region, the etched size self-aligns to define the height H of the cross-sectional structure of the double silicon nanowire; depositing silicon dioxide, etching the silicon dioxide to form sidewalls to protect the channel;

3) Etching the silicon in the field area again to form a shallow groove; etching the silicon isotropically so that the silicon directly below the channel is etched;

4) Remove the silicon dioxide sidewall, and wet-etch silicon nitride; the lateral etching size self-alignment of silicon nitride defines the width W of the cross-sectional structure of the double-silicon nanowire; for the circular double-silicon nanowire, the height H equal to the width W;

5) Deposit silicon dioxide, planarize, and form shallow trench isolation; at the same time, form a structure in which the channel is on the insulating layer, and the source and drain are still connected to the bulk silicon substrate;

6) deposition of silicon nitride layer, grid photolithography; grid and the coverage of the position of silicon nitride lateral etching in the above step 4), self-alignment defines the position of double silicon nanowires; etching two layers of silicon nitride ;

7) Etching silicon dioxide, then etching silicon, and self-aligning the double silicon nanowires formed on the insulating layer;

8) Wet etching silicon dioxide, so that the double silicon nanowires are suspended in the air; using an optimized process, the double silicon nanowires are rounded and thinned, and dry oxygen is oxidized to form gate oxide;

9) Depositing polysilicon as the gate material, doping and activating, and planarizing to form a polysilicon gate, both the gate oxide and the polysilicon gate surround the double silicon nanowires to form a surrounding gate structure;

10) Remove silicon nitride, doping to form n+ source and drain.

In the step 1), the width of the channel region of the active region plate is 50-80nm.

The etching size of silicon in the field region in step 2) is equal to the lateral etching size of silicon nitride in step 4, both of which are 15-20 nm.

In the step 3), the etching size of silicon in the field region is 250-350 nm, which is the depth of the shallow groove; the isotropic etching of silicon is 30-50 nm, which is larger than the active region as claimed in claim 6 Half the width of the channel region of the plate.

In said step 5), the thickness of the deposited silicon dioxide is 350-500 nm, which is greater than the depth of the shallow groove as claimed in claim 8.

Some key structural parameters of the double-silicon nanowire gate-enclosed device of the BOI structure obtained at last, such as the thickness of the silicon dioxide insulating layer of the BOI structure, the diameter D of the double-silicon nanowire, the gate length L _G , and the gate oxide thickness The doping concentration and distribution of channels, sources and drains can all be adjusted according to the needs of the design. The preparation method of the present invention adopts conventional CMOS preparation techniques, such as oxidation, deposition, etching and corrosion, etc., and can be self-aligned on a bulk silicon substrate through a new process integration (Process Integration, i.e. a combination of processes) BOI structure (body on insulating layer) double silicon nanowire gate device. The preparation method is fully compatible with the existing conventional CMOS technology, does not require SOI substrates, and does not require high-cost epitaxy and other processes. While achieving optimized device characteristics, it can also reduce substrate costs and process preparation costs.

The double silicon nanowire fence field effect transistor of the present invention, the advantage of adopting this BOI structure is: (1) can eliminate the parasitic tube on the bulk silicon substrate surface directly below the channel, block the leakage channel of the parasitic tube, Reduce the leakage current, increase the switching ratio of the device, and reduce the power consumption of the device; (2) Eliminate the parasitic tube while reducing the parasitic gate capacitance, which can reduce the total gate capacitance and optimize the AC of the double silicon nanowire gate device characteristics, increasing device switching speed. Therefore, the double-silicon nanowire-enclosed gate field effect transistor of the present invention has obvious advantages in the application of low power consumption and high-speed logic circuits.

Compared with Document 2, the technical effect of the present invention is (as shown in Figure 5(a) and (b)): (1) The parasitic tube on the substrate can be eliminated, the leakage current (I _off ) is reduced by 25 times, and the on-state The driving current (I _on ) is approximately equal, that is, the switching ratio (I _on /I _off ) can be increased by more than one order; (2) the gate capacitance (C _G ) can be reduced by 36%; (3) the switching speed of the device (in I _on /C _G V _dd , V _dd is the operating voltage) can be increased by 38%; (4) on the bulk silicon substrate, the double silicon nanowire surrounding gate device with the body on the insulating layer can be formed by self-alignment, The preparation method is simple and fully compatible with the existing conventional CMOS technology.

Therefore, the body-on-insulator (BOI structure) double-silicon nanowire gate-enclosed device proposed by the present invention has obvious advantages in DC characteristics, AC characteristics and device switching speed, and is effective in low power consumption and high-speed logic circuits There are obvious advantages and broad application prospects in the application.

Description of drawings

Figure 1 is a schematic cross-sectional structure diagram of several conventional double-gate and multi-gate devices (along the vertical direction of the channel): Figure 1(a) is a FinFET double-gate device, Figure 1(b) is a triple-gate device, Figure 1( c) is an Ω-gate device, and Figure 1(d) is a surrounding-gate device.

In Figure 1(a)-(d), the same reference numerals represent the same components:

101-SOI silicon wafer substrate back silicon 102-SOI silicon wafer substrate silicon dioxide buried layer (Buried-Oxide)

103-Polysilicon gate (Poly-Si Gate) of FinFET double gate device

104-SiO2 Hard Mask for FinFET Dual-Gate Devices

105-Fin (fin type) channel of FinFET double-gate device 106-Gate oxide of FinFET double-gate device

107-polysilicon gate of tri-gate device 108-gate oxide of tri-gate device 109-channel of tri-gate device

Polysilicon gate for 110-Ω gate devices Gate oxide for 111-Ω gate devices Channel for 112-Ω gate devices

113-The polysilicon gate of the gate-enclosed device 114-The gate oxide of the gate-enclosed device 115-The channel of the gate-enclosed device

Figure 2 is the layout and structural diagram of the silicon nanowire Ω-gate device in Document 1: Figure 2(a) is a schematic diagram of the layout of the device, M1 is the active region plate, and M2 is the gate plate; Figure 2(b) is the device The schematic diagram of the cross-sectional structure of the device along the vertical direction (A1A2 direction) of the channel; Figure 2(c) is a schematic diagram of the cross-sectional structure of the device along the direction of the channel (B1B2 direction); Figure 2(d) is the schematic diagram of Figure 2(b) Corresponding SEM images.

In Figure 2(b)-(d), the same reference numerals represent the same components:

Back silicon of 201-SOI silicon wafer substrate Silicon dioxide buried layer of 202-SOI silicon wafer substrate

203-Polysilicon gate (Poly-Si Gate) of silicon nanowire Ω gate device

204-Gate oxide of silicon nanowire Ω-gate device 205-Channel of silicon nanowire Ω-gate device

206-Source of silicon nanowire Ω-gate device 207-Drain of silicon nanowire Ω-gate device

Figure 3 is the layout and structural schematic diagram of the double silicon nanowire gate device in Document 2: Figure 3(a) is a schematic layout diagram of the device, M1 is the active region plate, M2 is the gate plate, and the dark part is double silicon Nanowire; Figure 3(b) is a schematic cross-sectional structure diagram of the device along the vertical direction (A1A2 direction) of the channel, it can be seen that the channel is a double silicon nanowire, and there is a parasitic tube directly below the double silicon nanowire; Fig. 3(c) is a schematic cross-sectional structure diagram of the device along the channel direction (B1B2 direction).

In Figure 3(b) and (c), the same reference numerals represent the same components:

301-Bulk silicon substrate (p-doped) 302-STI isolated field silicon dioxide

303-Poly-Si Gate 304-Gate oxide of double silicon nanowire gate device

305-Double silicon nanowire (channel)

306-Gate oxide of the parasitic tube on the surface of the bulk silicon substrate directly below the double silicon nanowire (channel)

307-Channel of parasitic tube 308-Source of double silicon nanowire gate device 309-Drain of double silicon nanowire gate device

Fig. 4 is the layout and structural representation of the body on the insulating layer (BOI structure) double-silicon nanowire surrounding gate device provided by the present invention: Fig. 4 (a) is the layout schematic diagram of this device, M1 is the active region version, M2 is the gate plate, and the dark part is double silicon nanowires; Figure 4(b) is a schematic cross-sectional structure diagram of the device along the vertical direction (A1A2 direction) of the channel, it can be seen that the channel is double silicon nanowires, At the same time, there is a thick silicon dioxide insulating layer directly below the channel and between the bulk silicon substrate, which can eliminate the parasitic tubes on the surface of the bulk silicon substrate; Figure 4(c) shows the direction of the device along the channel (B1B2 direction ), it can be seen that the position of the channel is a BOI structure, and the source and drain are still connected to the bulk silicon substrate.

In Figure 4(b) and (c), the same reference numerals represent the same components:

401-Bulk silicon substrate (p-doped) 402-STI isolated field silicon dioxide

403-Poly-Si Gate 404-Gate Oxide

405-Double silicon nanowire (channel)

406 - thick insulating layer of silicon dioxide directly under the double silicon nanowire (channel) and between the bulk silicon substrate

407-source 408-drain

Figure 5(a) and (b) are the drain current (including leakage current I _off , on-state drive current I _on ), gate capacitance (C _G ) and Comparison chart of Document 2.

Figure 6(a)-(n) is the process flow of the preparation method of the double-silicon nanowire gate-enclosed device based on the body-on-insulator (BOI structure) of the bulk silicon substrate and its steps according to an embodiment of the present invention. Schematic diagram of the corresponding product structure.

In Figure 6(a)-(n), the same reference numerals represent the same components:

601 - Bulk silicon substrate (p-doped) 602 - SiO ₂ layer as hard mask

603-Si ₃ N ₄ layers for hard mask 604-SiO ₂ sidewalls to protect silicon channel

605-suspended silicon channel (its thickness can define the height H of the cross-sectional structure of the double silicon nanowire)

606-The floating position directly below the silicon channel (used to fill SiO ₂ as an insulating layer)

The position of 607-Si ₃ N ₄ layer being etched laterally (defining the position of the double silicon nanowire, the size of the lateral etching defines the width W of the cross-sectional structure of the double silicon nanowire, for the circular silicon nanowire, the height H and the width W equal)

608-STI isolated field silicon dioxide

609-Silicon dioxide insulating layer directly below the channel and between the bulk silicon substrate

610 - Si ₃ N ₄ layer used as planarization stop layer

611-Double silicon nanowire (channel) 612-Gate oxide 613-Poly-Si Gate

614-source 615-drain

Detailed ways

The double silicon nanowire gate field effect transistor provided by the present invention and its preparation method will be described in detail below with reference to the accompanying drawings, but this does not constitute a limitation to the present invention.

As shown in FIG. 4 , it is the double silicon nanowire gate device of this embodiment. Figure 4(a) shows the layout of the device. The part of the M1 active region plate covered by the M2 gate plate is the channel region, and the uncovered part is the source region and drain region. The width of the channel region (A1A2 direction) is 50nm, and the length of the channel region (B1B2 direction), that is, the gate length is 30nm. Figure 4(b) and (c) respectively show the cross-sectional structure of the device along the vertical direction of the channel (A1A2 direction) and along the channel direction (B1B2 direction). As shown in Figure 4(b): the cross section of the double silicon nanowire 405 as a channel is circular, with a diameter of 10nm, surrounded by a gate oxide 404 with a thickness of 1.2nm, and surrounded by a polysilicon gate 403 with a thickness of 150nm. Polysilicon with a thickness of 100nm, polysilicon with a thickness of 40nm underneath; a layer of silicon dioxide insulating layer 406 with a thickness of 250nm directly under the double silicon nanowire 405, forming a BOI structure on the insulating layer. As shown in Figure 4 (c): the silicon dioxide 002 in the field region of STI isolation is 400nm thick; due to the BOI structure, the double silicon nanowire 405 and the polysilicon gate 403 are all formed on the insulating layer; the source 407 and the drain 408 are still connected to the body The silicon substrate 401 is connected, and a larger junction depth of 30nm can be used to reduce the parasitic series resistance of the source and drain and increase the on-state driving current. The thick silicon dioxide insulating layer 406 can eliminate possible parasitic tubes on the surface of the bulk silicon substrate 401 directly below the channel, reduce leakage current, increase switching ratio, reduce gate capacitance, optimize AC characteristics, and improve device performance. switching speed.

The double-silicon nanowire-enclosed gate device of the present invention is based on a bulk silicon substrate (Bulk Si Wafer). From the cross-sectional structure along the vertical direction of the channel, as shown in Figure 4(b), the channel is two identical circular silicon nanowires (Twin Si Nanowire), that is, double silicon nanowires, whose diameter is ≤ 10nm; double silicon nanowires are surrounded by gate oxide (Gate Oxide), and then surrounded by gate (Gate), forming a gate-enclosed device; between the channel, that is, directly below the double silicon nanowires and the substrate, there is a layer with a thickness of 200 ~300nm silicon dioxide insulating layer, forming a structure (Body-on-Insulator, BOI structure) of a double silicon nanowire channel (referred to as body) on the insulating layer; from the cross-sectional structure along the direction of the channel, such as As shown in Figure 4(c), the body is on the insulating layer, and the source and drain are connected to the substrate. The junction depth of the source and drain is greater than the diameter of the double silicon nanowire, which can reach 30-50nm, so as to reduce the source and drain of parasitic series resistance.

The DC characteristics and AC characteristics of the double silicon nanowire gate device with BOI structure in this embodiment are compared with Document 2, as shown in Figure 5(a) and (b) respectively. The gate length, gate oxide thickness, threshold voltage, junction depth, silicon nanowire diameter and other parameters of the two devices are the same. Figure 5(a) is a comparison of the drain current (including leakage current I _off and on-state drive current I _on ) of DC characteristics: the abscissa in the figure is the gate voltage (V _G ), and the ordinate is the drain current (I _D ), when the drain voltage is 1.1V (volts), the _ID when the gate voltage is 0V is defined as the leakage current I _off , and the device of the present invention can reduce I _off by 25 times compared with the device of Document 2; when the gate voltage is 1.1V _ID of is defined as the on-state drive current I _on , and the two devices are approximately equal; therefore, the device provided by the present invention can also increase the switching ratio I _on /I _off by more than one order of magnitude. Fig. 5 (b) is the comparison of the gate capacitance (C _G ) of AC characteristics: the abscissa in the figure is the gate voltage (V _G ), and the ordinate is the gate capacitance (C _G ). It can be seen that the device of the present invention eliminates the The parasitic tube of the substrate reduces the parasitic gate capacitance, which can significantly reduce the total gate capacitance. At a gate voltage of 1.1V, the gate capacitance can be reduced by 36%. Since the switching speed of the device is measured by _Ion / _CG · _Vdd , _{and Vdd} is the operating voltage, which is 1.1V, the switching speed of the device of the present invention can be increased by 38% compared with the device of Document 2.

The present invention prepares the method for double-silicon nanowire-enclosed gate field-effect transistor, and this preparation method comprises the following steps:

Step 1: On the bulk silicon substrate, deposit silicon dioxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ); implant boron into the channel; photolithography of the active area, the channel area of the active area The width is 50-80nm, and the silicon nitride and oxide layer are etched to form a double-layer hard mask.

Step 2: Etching 15-20 nm of silicon in the field region, this size self-aligns to define the height H of the cross-sectional structure of the silicon nanowire; depositing SiO ₂ , etching the SiO ₂ to form sidewalls to protect the channel.

Step 3: Etch 250-350nm of silicon in the field area again to form a shallow groove; etch 30-50nm of silicon isotropically, which is greater than half the width of the channel area of the active area plate, so that the silicon below the channel area is all Carved out.

Step 4: remove the SiO ₂ sidewall, and wet etch Si ₃ N ₄ 15-20nm (wet etching is isotropic). The dimensional self-alignment of the lateral etching defines the width W of the cross-sectional structure of the silicon nanowire; for a circular silicon nanowire, the height H and the width W are equal.

Step 5: Deposit SiO ₂ with a thickness of 350-500nm, which is greater than the depth of the shallow groove; use Si ₃ N ₄ as a stop layer, and planarize it with chemical mechanical polishing (CMP) to form shallow trench isolation (STI); simultaneously form a BOI structure, trench The track is on the silicon dioxide insulating layer, while the source and drain are still connected to the bulk silicon substrate.

Step 6: Deposit Si ₃ N ₄ layer for the second time; grid plate photolithography; cover the grid plate and the position of silicon nitride lateral etching in the above step 4, self-align to define the position of double silicon nanowire; etch two Layer Si ₃ N ₄ .

Step 7: Etching SiO ₂ , and then etching silicon, using SiO ₂ as a mask to self-align the double silicon nanowires formed on the insulating layer.

Step 8: Etching the silicon dioxide by 50-80 nm, so that the double silicon nanowires are suspended in the air; using an optimized process, the silicon nanowires are rounded and thinned to form circular double silicon nanowires with a diameter D≤10 nm. Dry oxygen oxidation forms gate oxide.

Step 9: Deposit polysilicon as gate material, phosphorus doping and RTP (rapid thermal annealing) activation, CMP planarization. A channel in which both the gate oxide and the polysilicon gate surround the double silicon nanowires is formed, that is, a gate-enclosed structure.

Step 10: removing Si ₃ N ₄ , doping source and drain with As (arsenic), forming n+ source and drain with a junction depth of 30-50 nm.

As shown in Figure 6. Each structure shown in Fig. 6(a)-(n) corresponds to each step in the preparation method.

Below in conjunction with accompanying drawing this preparation method is described in detail:

Step 1: On the p(100) bulk silicon substrate, deposit SiO ₂ layer 30nm and Si ₃ N ₄ layer 100nm; channel implantation of boron; M1 active area plate photolithography, the width of the channel area of the active area plate 60nm; Si ₃ N ₄ and SiO ₂ are etched to form a double-layer hard mask. A cross-sectional structure as shown in FIG. 6(a) is formed (along the vertical direction of the channel, such as the A1A2 direction shown in 4(a)).

Step 2: Etch 15nm of silicon in the field region, this height self-aligns to define the height H of the cross-sectional structure of the silicon nanowire; then deposit SiO ₂ and etch to form sidewalls to protect the silicon channel. A cross-sectional structure (along A1A2 direction) as shown in FIG. 6(b) is formed.

Step 3: Etch 300 nm of silicon in the field region again; etch 40 nm of silicon isotropically, so that the silicon below the position of the channel region is etched empty. A cross-sectional structure (along A1A2 direction) as shown in FIG. 6(c) is formed.

Step 4: Remove the SiO ₂ sidewall, and wet etch Si ₃ N ₄ about 15nm. The position of the etched Si ₃ N ₄ and the position covered by the M2 grid plate can be self-aligned to define the position of the double silicon nanowire; the size of the lateral etching can be self-aligned to define the width W of the cross-sectional structure of the silicon nanowire; for circular Silicon nanowires with equal height H and width W. A cross-sectional structure (along A1A2 direction) as shown in FIG. 6(d) is formed.

Step 5: Deposit SiO ₂ about 500nm, use Si ₃ N ₄ of the hard mask as a stop layer, chemical mechanical polishing (CMP) planarization, and form shallow trench isolation; at the same time, form a BOI structure, the channel is on the insulating layer, and The source and drain are still connected to the bulk silicon substrate. A cross-sectional structure (along the A1A2 direction) as shown in FIG. 6(e) is formed, and a corresponding cross-sectional structure in the B1B2 direction is shown in FIG. 6(f).

Step 6: Deposit the Si ₃ N ₄ layer for the second time, as shown in Figure 6(g) (along the direction A1A2). M2 grid plate photolithography, etching two layers of Si ₃ N ₄ to form gate grooves.

Step 7: Etching SiO ₂ for about 30 nm, and then etching silicon, using SiO ₂ as a mask to self-align the double silicon nanowires formed on the insulating layer. A cross-sectional structure (along A1A2 direction) as shown in FIG. 6(h) is formed.

Step 8: Etch 60nm of SiO ₂ , so that the double silicon nanowires are suspended (but there is a thicker silicon dioxide insulating layer directly below the double silicon nanowires); form a cross-sectional structure as shown in Figure 6(i) (along A1A2 direction), the corresponding cross-sectional structure of B1B2 direction is shown in Fig. 6(j). The process optimizes the structure of the double-silicon nanowires, and anneals them in a high-temperature furnace at 950°C for about 2 hours in _H2 environment, and sacrificially oxidizes them many times, so that the double-silicon nanowires become round and thin, and the diameter is reduced to 10nm. Then dry oxygen oxidation at 850°C to generate gate oxide 1.2nm, forming the cross-sectional structure (along A1A2 direction) as shown in Figure 6(k).

Step 9: Deposit polysilicon with a thickness of about 250nm, dope phosphorus (P) about 1×10 ¹⁶ cm ^-2 /40KeV, activate RTP (rapid thermal annealing) at 950°C for 10s, and planarize with CMP. Both the gate oxide and the polysilicon gate surround the channel of the double silicon nanowire, forming a gate-around device. A cross-sectional structure (along B1B2 direction) as shown in Fig. 6(1) is formed.

Step 10: removing Si ₃ N ₄ , doping source and drain with As (arsenic) about 5×10 ¹⁵ cm ⁻² /40KeV. A cross-sectional structure (along the A1A2 direction) as shown in FIG. 6(m) is formed, and a corresponding cross-sectional structure in the B1B2 direction is shown in FIG. 6(n).

Step 11: Further carry out conventional follow-up processes, depositing a low-oxygen layer, RTP annealing to activate impurities, photolithography and etching lead holes, sputtering metal, photolithography and etching to form metal lines, alloys, and passivation.

Finally, a double-silicon nanowire gate device that can be used for testing is obtained on the insulating layer (BOI structure). The silicon dioxide insulating layer has a thickness of 250nm.

The double-silicon nanowire gate-enclosed device and its preparation method provided by the present invention have been described above through detailed embodiments. Those skilled in the art should understand that within the scope not departing from the essence of the present invention, certain modifications can be made to the device structure of the present invention. Variation or modification; its preparation method is not limited to the content disclosed in the examples.

Claims (9)

1. A double-silicon nanowire-enclosed gate field-effect transistor, based on a bulk silicon substrate, the channel is a double-silicon nanowire with the same cross-sectional structure as a circle, and the double-silicon nanowire is surrounded by a gate oxide and a polysilicon gate to form The surrounding gate structure, the source and the drain are connected to the bulk silicon substrate, which is characterized in that there is a thick silicon dioxide insulating layer directly below the channel and between the bulk silicon substrate, forming a channel on the insulating layer structure. 2. The double silicon nanowire gate field effect transistor according to claim 1, characterized in that the diameter of the double silicon nanowire is ≤ 10 nm. 3. The double silicon nanowire gate field effect transistor according to claim 1, wherein the junction depth of the source and the drain is greater than the diameter of the double silicon nanowire, which is 30-50nm. 4. The double silicon nanowire fenced gate field effect transistor according to claim 1, characterized in that the silicon dioxide insulating layer directly below the channel and between the bulk silicon substrate has a thickness of 200-300 nm . 5. A method for preparing the double silicon nanowire gate field effect transistor according to claim 1, comprising the following steps: 1) On the bulk silicon substrate, deposit silicon dioxide and silicon nitride, lithography the active area, etch silicon nitride and silicon dioxide to form a double-layer hard mask; 2) Etching the silicon in the field region, the etched size self-aligns to define the height H of the cross-sectional structure of the double silicon nanowire; depositing silicon dioxide, etching the silicon dioxide to form sidewalls to protect the channel; 3) Etching the silicon in the field area again to form a shallow groove; etching the silicon isotropically so that the silicon directly below the channel is etched; 4) Remove the silicon dioxide sidewall, and wet-etch silicon nitride; the lateral etching size self-alignment of silicon nitride defines the width W of the cross-sectional structure of the double-silicon nanowire; for the circular double-silicon nanowire, the height H equal to the width W; 5) Deposit silicon dioxide, planarize, and form shallow trench isolation; at the same time, form a structure in which the channel is on the insulating layer, and the source and drain are still connected to the bulk silicon substrate; 6) deposition of silicon nitride layer, grid photolithography; grid and the coverage of the position of silicon nitride lateral etching in the above step 4), self-alignment defines the position of double silicon nanowires; etching two layers of silicon nitride ; 7) Etching silicon dioxide, then etching silicon, and self-aligning the double silicon nanowires formed on the insulating layer; 8) Wet etching silicon dioxide, so that the double silicon nanowires are suspended in the air; using an optimized process, the double silicon nanowires are rounded and thinned, and dry oxygen is oxidized to form gate oxide; 9) Depositing polysilicon as the gate material, doping and activating, and planarizing to form a polysilicon gate, both the gate oxide and the polysilicon gate surround the double silicon nanowires to form a surrounding gate structure; 10) Remove silicon nitride, doping to form n+ source and drain. 6. The preparation method according to claim 5, characterized in that, in the step 1), the width of the channel region of the active region plate is 50-80 nm. 7. The preparation method according to claim 5 or 6, characterized in that, both the height H and the width W are 15-20 nm. 8. The preparation method according to claim 5 or 6, characterized in that, in step 3), the etching size of the silicon in the field region is 250-350 nm, which is the depth of the shallow groove; isotropic etching The etching silicon is 30~50nm. 9. The preparation method according to claim 5 or 8, characterized in that, in the step 5), the thickness of the deposited silicon dioxide is 350-500 nm.

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