CN101016630A - Plasma etching of tapered structures - Google Patents

Abstract

The present invention relates to a method of plasma etching a substrate, in particular a wedge-shaped channel through a substrate, using a process gas comprising at least one halide and oxygen.

Description

Plasma etching of wedge-shaped structures

technical field

The present invention relates to methods of plasma etching substrates, and more particularly to microelectronic semiconductor substrates.

Background technique

Plasma etching processes are commonly used to etch layers in the manufacture of integrated circuits. Reactive ion etching is the mainstream technology, but current advanced technologies such as electron cyclotron resonance (ECR) and the use of magnetic fields to enhance plasma density to introduce inductively coupled plasma (ICP).

It is believed that plasma etching is based in part on chemical etching. This means that a chemical reaction occurs between the atoms of the bulk material and the gas atoms to form molecules that are subsequently removed from the substrate. Due to the applied DC voltage, there is also some sputtering effect which is believed to be smaller than the effect of chemical etching. Additionally, ion bombardment is believed to augment or support the chemical etch process. Combining the two effects results in a synergistic effect that provides enhanced etch rates.

The main steps in the etch process are:

1. Formation of reactive particles,

2. The reaction particles reach the surface to be etched,

3. Adsorption of reaction particles on the surface to be etched,

4. Chemical adsorption of reaction particles on the surface,

5. Molecular formation,

6. Desorption of molecules,

With increasing device density on or within a chip, there is more and more integral functionality in applications such as MEMS, RF circuits where micro sensors, micro actuators are often also integrated with digital and analog electronic components. This increased complexity leads to smaller pads on the device and challenges with advanced packaging.

One of the fundamental features of image sensor packages as well as MEMS or solar cells is the back contact. In one aspect, optics require an interface to the environment without any constraints due to packaging. On the other hand, however, optics also require protection against environmental influences. Even for AeroMEMS that require an interface with the environment to probe or modify flow behavior, precisely defined openings or channels are critical to the functionality of these devices.

One problem with prior art etching methods is the bending of the etch channel. This means that the diameter of the etched channel increases under the mask, and after removal of the mask, a small collar extends along the edge of the etched structure. Thus, bowing presents a significant disadvantage for the dimensions of etched structures and causes problems in subsequent manufacturing process steps.

Contents of the invention

It is an object of the present invention to provide a method of etching at least a part of a substrate which is reliable and improves the accuracy of microscale configurations.

Furthermore, it is an object of the invention to reduce the curvature of the etched channel or at least to control the magnitude of the curvature based on the parameters of the etching method.

Another object of the present invention is to provide a method that allows etching of wedge-shaped channels and based on the etching method to determine the sidewall angle of the wedge-shaped channels.

This object is achieved using a method for plasma etching of at least a portion of a substrate according to independent claims 1 and 41-50.

Advantageous refinements are the object of the respective dependent claims.

According to the invention, a substrate is provided and at least one mask is applied to the substrate. The mask can be structured after deposition on the substrate, or a structured mask can be applied.

The structures define or include openings in the mask. These openings may have different shapes, such as circular structures to form circular channels or rectangular structures to define strip-shaped conduits or channels.

Material is removed from the substrate at least in the openings by performing a plasma etch process.

According to the invention, a process gas comprising at least one halide and oxygen is used.

The inventors have found that it is possible to etch microscale structures, especially vias of backside contacting electronic devices, using a gas mixture. The inventive method provides wedge-shaped channels with sidewall angles substantially independent of substrate material. This means that the sidewall angle is neither defined by the crystal structure nor follows the crystal texture.

Furthermore, it is possible to form channels with substantially no overhangs (bends) under the mask.

According to a preferred embodiment of the invention, the amount of oxygen in the process gas in volume percent is less than 40%, preferably less than 20%, particularly preferably less than 25%, of the defined portion. The ratio of the oxygen to the halide is less than 30%, preferably less than 25%, particularly preferably less than 20% (ratio by volume). The inventors have found that with an amount of oxygen less than 30% of the SF ₆ /O ₂ mixture, it is possible to etch micro-sized channels substantially without overhangs or bends. The volume of a gas is measured in standard ^cm3 (sccm).

Particularly provided halides are sulfur halides, especially SF ₆ .

According to the present invention, halides are defined as molecules or atoms comprising one or more halogen atoms. Furthermore, the halogen atoms may be chemically bonded in the molecule or may be provided as ions, for example in a plasma.

The method according to the invention involves various substrates, especially semiconductor materials such as silicon wafers.

According to a preferred embodiment of the present invention, a photoresist is used as the mask.

Such masks can be constructed with photolithographic processes, especially using steppers that allow structures with an accuracy of 10 μm or even better, ie a precision of a fraction of a micron, such as 0.2 μm or even 0.1 μm.

The inventors have found that the choice of _SiOx is very good. Etching on photoresist is possible.

After etching the substrate, the mask can be easily removed.

According to an embodiment of the invention, the substrate is etched in at least two etching steps.

In particular, the first etching step can be performed with a higher etching rate than the subsequent second etching step. By means of said first etching step it is possible to etch deep structures in a fast manner. Due to the fact that a high etch rate may result in reduced accuracy, the process will be terminated in one or several additional etch steps with a lower etch rate.

The inventors have found that by reducing the fraction of oxygen in the second etch step, accuracy can be improved.

In the final step, it is possible to perform etching with only a halide gas as a gas, ie, as a single process gas.

Alternatively, at least one channel (via) can also be etched in the substrate in a single etching step. Especially by means of additive gases for passivation, such as CHF ₃ or C ₄ F ₈ , it is possible to etch channels with high precision substantially without any overhangs or bends.

By means of the method according to the invention, various etching rates are possible, in particular between 5 and 500 μm/min, preferably between 7 and 100 μm/min, particularly preferably between 8 and 20 μm/min Vary the etch rate.

The addition of passivating gases such as CHF ₃ and C ₄ F ₈ to the process gas improves fabrication accuracy and also reduces overhang formation under the mask. Preferably, these passivating gases comprise at least one carbon-containing compound.

The sidewall angle can be controlled by the parameters of the etch process. It is possible to form side wall angles of 50° to nearly 90°. The inventors found that with the etching method according to the invention, the sidewall angles do not follow the crystal structure of the substrate.

For most applications, steep passages are desired. But a sidewall angle of 90° is too steep to allow deposition of conductive or non-conductive material in further process steps. Therefore, preferably, the side wall angle is kept between 75° and 85°.

The roughness of the side walls of the channel can be reduced below 200 nm, preferably below 100 nm, particularly preferably below 50 nm (peak to valley), so that the standard surface roughness R of the side walls _is below 100 nm , preferably below 30 nm, particularly preferably below 10 nm (R _a ).

It is possible to form very small diameter channels or vias of 10 μm to 500 μm, preferably 15 to 100 μm, particularly preferably 18 to 70 μm.

According to the invention, the interpretation of diameter is not limited to substantially circular channels. It can be applied to channels of substantially any shape, where the diameter is defined as the distance between opposing side walls of the channel.

According to the terminology of this specification, a channel defines an overhang under the mask when the diameter of the channel in the vicinity of the mask opening is larger than the diameter of the mask opening.

According to the invention, it is possible to form channels in which the difference between the diameter of the opening and the diameter of the channel in the vicinity of the mask opening is smaller than 10 μm, preferably smaller than 5 μm, particularly preferably smaller than 2 μm.

Wherein electrical control of the overhang by the plasma source is possible.

Especially for removing residual overhangs, the substrate can be thinned.

By means of the method according to the invention, the substrate can be etched to a depth of between 5 μm and 500 μm, preferably between 20 and 200 μm, particularly preferably between 80 and 160 μm.

Almost all types of plasma sources can be used as plasma sources for generating the plasma, in particular inductively coupled plasma (ICP) sources are suitable.

By constructing the mask using steppers, accuracies better than 10 μm can be obtained.

In order to improve the surface roughness of the substrate, the substrate can be smoothed in a further process step.

During the plasma etching process, the temperature of the substrate is kept below 200°C, preferably below 150°C, particularly preferably below 120°C. Therefore, the method according to the invention is suitable for microelectronics.

In order to reduce the substrate temperature, the etching process can be performed discontinuously, in particular pulsed.

In particular, the substrate may be etched in a KOH etching process.

After etching of the substrate, conductive strips may be formed, for example by depositing at least one conductive layer on the substrate.

Finally, the substrate can be applied with a passivation layer.

The invention is suitable for a variety of applications such as electronic components, especially wafer-level packaging, image sensors, such as CCD chips, microelectromechanical systems (MEMS) or also in microfluidic systems.

Due to the fact that the side wall angle is not or only slightly affected by the substrate material, filters, especially molecular sieves, can also be produced. Such filters may be provided with side wall angles approaching 90° to form substantially upright channels.

The invention is suitable for photosensitive devices with back contacts, especially charge-coupled photosensitive devices (CCD).

By directly contacting each pixel, the signal noise of the image device can be significantly reduced.

The signal for each pixel can be amplified by cascaded amplifiers or photomultipliers, especially secondary electron multipliers.

The amplified signal may be routed through a bucket brigade circuit. Due to the fact that the barrel circuit processes the amplified signal, the signal noise can be significantly reduced.

Preferably, the above-mentioned electronic components are provided as integrated circuits, in particular as thin film integrated circuits.

Description of drawings

1 to 6 show steps of etching a substrate according to an exemplary embodiment of the present invention;

7 to 10 schematically show a method of contacting a wafer-level packaged image sensor;

Figures 11 and 12 show images of two channels etched with the same recipe but with different etch times;

Figures 13 to 15 show a multi-step etching method;

Figure 16 shows the results of the multi-step etching method according to Figures 13 to 15;

Figure 17 shows a picture of the results of the etching method of the present invention;

Figure 18 schematically shows a plasma source for plasma etching according to the present invention;

Figure 19 schematically shows a cross-section of a region of a photosensitive device;

Figures 20 to 25 schematically show flow diagrams of exemplary methods of wafer-level chip-scale packaging in which a wafer is packaged or contacted using an etching method according to the present invention;

Figure 26 schematically shows an inductively coupled plasma source.

Detailed ways

1 to 6 schematically show steps of etching a portion of a substrate according to an exemplary embodiment of the present invention.

As shown in Fig. 1, a substrate 1 is provided. The substrate 1 according to this embodiment of the invention is a wafer comprising electronic components 2 on its front side. The electronic component 2 may comprise, for example, an image sensor or a general electronic, optoelectronic, microfluidic, or micromechanical structure.

As shown in Figure 2, a photolithographic mask 3 is applied on the back side of the substrate.

In a next step according to FIG. 3 , a mask 3 is constructed to define openings 4 on said substrate 1 . Using a photolithographic layout or a stepper device (not shown), it is possible to apply micro-sized structures with an accuracy of 10 μm or to apply sub-micron-sized structures with an accuracy of 0.1 μm, respectively.

Referring to FIG. 4 , channels 5 are etched in the substrate 1 through the openings of the mask 3 . According to the invention, etching is performed using a process gas comprising _SF6 and up to 30% _O2 . These channels may extend through the entire substrate like vias, or may terminate at a predefined depth in the substrate 1 .

The inventors have discovered that the sidewall angle of the tapered channel is substantially independent of the substrate material and can be controlled based on process parameters.

Furthermore, the size of the overhang bend can be controlled with the inventive etching method.

The basic idea of this plasma anisotropic etching method is the balance between sidewall passivation and bottom etching.

Plasma etching of wedge-shaped channels can be performed on HR (High Speed) ICP (Inductively Coupled Plasma) plasma kits. Etch rates as high as 25 μm/min in silicon are obtained when using the etching gas SF ₆ . C ₄ F ₈ , O ₂ and CHF ₆ were used as passivation gases.

The plasma etching process depends to some extent on the chemical reaction between the plasma gas and the substrate 1 . The etch rate depends on the rate of diffusion of plasma-generated reactive species to the etch front and also on the rate of diffusion of formed etch products out of the etch front. The rate of diffusion to and from the etch front is reduced relative to shallow silicon structures. This reduces the etch rate as the etch depth increases.

Low temperature plasma etching can also be used as an alternative to etch the wedge-shaped channel 5 . The mechanism used in low temperature etching is a combination of barrier layer formation and reduced reaction probability of free radicals at the silicon surface. The disadvantage of this method is the cryogenic temperature. Due to various temperature limitations, this reduced temperature is not suitable for many applications.

7 to 10 schematically illustrate a method of contacting a WLP image sensor.

Figure 7 shows plasma etching of wedge-shaped via and channel structures in silicon. The substrate comprises a silicon layer 11 on which a resist layer 13 is applied as an etch stop. Under the etching channel 5, there is also a layer 14 of conductive material. The glass sheet 10 is preferably attached to the silicon layer 11 using a glue layer 12 . A glass sheet 10 covers the active components (ICs/sensors) of a silicon layer 11 .

Figure 8 shows the passivation and deposition of the IDL layer (internal dielectric layer). Two passivation layers 15 , 16 are applied to the silicon layer 11 , the first passivation layer 15 being deposited and the second passivation layer 16 sprayed on in a CVD process. A resist layer 17 is applied as a final layer. In a subsequent process step, the resist layer 17 is opened above the layer of conductive material 14 .

FIG. 9 shows plasma etching of the passivation and glue layers 12 , 13 and 14 , 15 in order to form vias to the conductive material 14 . In a subsequent step, the outer resist layer (17 of Figure 8) is stripped.

As shown in Figure 10, the contact layer 18 is finally covered, preferably sputtered with a metal layer and redistributed. A solder mask and bumps 19 for contacts are applied.

These processes include plasma etching of vias that make electrical contact with the front-end pads and scribed vias, sputtering to create contact windows in the vias, and metallization of the redistribution pad connections.

In order to have good uniformity and step coverage in spraying, in the photolithography process and metallization inside the channel, tapered sidewalls are required.

Channels with vertical sidewalls commonly seen in cryogenic processes are not suitable for use because it is difficult to obtain good step coverage at steep corners in the subsequent sputtering process.

KOH and TMAH are the most common methods used to create wedge-shaped channels in silicon because these are cheap and easy-to-use techniques. However, these techniques are limited by the low etch rate (1 μm/min) and the invariance of different designs (54°, fixed angle of 70°).

For microfluidic applications, channels with tapered sidewalls can be used as diffusers and nozzles.

The use of channels with tapered side walls has clear advantages, such as computationally simple geometry, higher possible flow rates, and reduced thermal time constants.

It has been found that wedge-shaped channels with a depth of up to 30 μm are easily formed in silicon with a SF ₆ /O ₂ gas mixture. For channels deeper than 30 μm, the sidewalls tend to overhang, ie bend.

Figures 11 and 12 show two channels etched with the same recipe but with different etch times.

The channels according to FIG. 11 are etched at short time intervals. The etch depth is about 17 μm. The channel has substantially no overhangs or bends.

The channel according to FIG. 12 was etched for a longer time and had an etch depth of about 54 μm and an overhang of about 20 μm.

This overhang or bow is very critical for the next process steps shown in Figures 8 to 10 such as spraying, deposition of passivation layer and metallization as it leads to reduced or defective coverage in this area

The SF ₆ /O ₂ -Si system is considered as an ion suppression process. In this gas system, oxygen induces the formation of a passivation layer with silicon dioxide on the silicon surface.

SF ₅ ⁺ ions etch the passivator or passivation layer, allowing F- radicals to etch the silicon substrate.

Possible causes of this overhang are thought to be:

Due to the fact that the passivation layer is an insulator ( _SiO2 ) ions colliding with the sidewalls will leave their charges causing sidewall charging, which is difficult to compensate with electrons. This charge repels subsequent ions;

The ion deflection is most pronounced for the SF ₆ /O ₂ etch gas mixture. The negative potential of the channel walls deflects ions towards the side walls.

Ion shadowing when ions reach the uppermost layer of the channel at an angle prevents the ion from etching the area below the mask layer.

Ion deflection is considered to be the main driving force for overhang formation (bending) in the via profile.

13 to 15 show a multi-step etching method.

As shown in FIG. 13 , channels 5 with overhangs 20 are etched in the substrate as a first step. In this first initial step, a profile with a curvature has been produced with SF ₆ /O ₂ plasma (10% O ₂ ). In this step, typical etch rates are higher than 10 μm/min (for 5% etched area).

The sidewall angle α is defined as the angle between the surface of the substrate and the sidewall of the channel 5 .

As shown in FIG. 14, the mask layer (3 in FIG. 11) was removed with pure oxygen plasma.

Referring to FIG. 15 , as a final step, an isotropic etch using SF ₆ plasma is performed to remove the overhang ( 20 of FIGS. 11 and 12 ) and obtain the final channel geometry.

Stress-containing silicon layers with crystal dislocations that may be generated during the mechanical thinning step can be avoided to ensure improved and reliable packaging performance.

In a further step, the etch mask is removed in a pure oxygen plasma.

In the final etching step, the final profile is obtained in an isotropic etching step (SF ₆ plasma).

Figure 16 shows a graph of the results of a multi-step etch process performed in accordance with the embodiment of the invention shown in Figures 13-15.

The side wall angle is adjustable at least in the range of 55-75°.

The roughness within the channel is excellent (<<200nm peak to valley).

The selectivity of silicon to the resist layer is higher than 50.

Ion deflection can be minimized by increasing passivation of the sidewalls, wall charging, and/or energy of the ions prior to entering the channel. This effect can be obtained by adding an additional passivating gas (eg C ₄ F ₈ or CHF ₃ ).

_{The C4F8} glow discharge produces a chemically reactive polymer precursor species that can be used to isotropically deposit barrier polymer films over the wafer surface.

Due to the fact that the passivation material is an FC polymer, effects such as ion charging and ion deflection can be avoided.

With this gas chemistry, wedge-shaped profiles can be obtained in one step.

FIG. 17 schematically shows the etching of a channel 5 in a silicon substrate 1 using a SF ₆ /O ₂ /C ₄ F ₈ gas mixture. An undercut 21 is formed under the mask, but almost no overhang is seen.

Figure 16 shows the results of this etching method. Using 8 inch wafer material, the roughness in the channel is about 3 μm (peak to valley). The selectivity of silicon to resist is about 80.

The SF ₆ /O ₂ /C ₄ F ₈ gas mixture offers basically easy design improvements. However, for some applications, the roughness within the channel is critical. A typical roughness with this gas mixture is around 3 μm.

For applications requiring good roughness qualities such as microfluidics or electronic packaging, an additional smoothing step is required.

As an alternative, a SF ₆ /O ₂ /CHF ₃ gas mixture can be used. This gas chemistry allows the passivation of silicon surfaces with silicon dioxide and polymers (FC fluorocarbons).

The gaseous CHF ₃ is not only the source of the fluorocarbon polymer passivating the silicon surface, but also the source of CF- ions, which in turn are responsible for the removal of the SiO _x F _y layer at the bottom of the channel, forming volatile CO _x F _y . In this case the F:C _ratio is 3, so the FC polymer is not as stable as the FC polymer deposited from _C4F8 discharge (F:C ratio is 2) and can be completely removed with _O2 .

Figure 18 schematically shows a plasma source 30 for plasma etching according to the invention.

The plasma source 30 includes a lower electrode 31 and an upper electrode 32 connected to a generator (not shown), a gas inlet 33 and a pump 34 .

Preferably, instead of the direct etch plasma chamber according to Fig. 18, an inductively coupled plasma chamber is used.

Inductively coupled plasma source 35 is shown schematically in FIG. 26 . This type of plasma source is powered by electromagnetic induction, that is, an electrical current generated by a time-varying magnetic field. An inductively coupled plasma source 35 includes a coil 36 outside a plasma chamber 37 and electrodes 38 inside. When an alternating current is passed through the coil 36, it induces a time-varying magnetic field, which in turn leads to the formation of a plasma.

A so-called dark sheath forms in the vicinity of all grounded surfaces, electrodes and walls in the reactor. The dark sheath can be thought of as some type of dielectric or some type of capacitor. It can therefore be assumed that the applied power is delivered to the plasma via the capacitor. Process gases may be introduced into the plasma source through a gas inlet 33 .

According to the invention, all known types of plasma sources such as HF, microwave etc. can be used.

FIG. 19 schematically shows a cross-section of a photosensitive device 40 , in particular an image sensor composed of pixels 41 . Each pixel 41 includes a photosensitive charge-coupled device and is back contacted by a channel. The channels are filled with conductive material 6 and etched using the etching method according to the invention.

Each pixel 41 is connected to an amplifier 43 via said channel. The amplifier 43 is provided as an integrated circuit layer 44 comprising a single IC. The integrated circuit layer 44 is bonded to the substrate 2 by an adhesive material 42 . A contact layer 45 is provided as integrated circuit layer 44 . The contact layer is connected to the amplifier 43 .

Because the amplifiers 43 are placed close to the pixels 41, the signals are amplified substantially directly or immediately after their formation. The amplified signal is less sensitive to normal noise.

The signal of the amplifier 43 is transmitted via the contact layer 45 . For transmitting the signals of the amplifier, the contact layer includes a barrel circuit.

Due to the fact that the barrel circuit processes the amplified signal, the signal is less sensitive to noise, eg induced by said barrel circuit.

The noise of the photosensitive device is thus substantially reduced.

The barrel team circuit is connected to solder contacts (not shown).

Optionally, according to another embodiment of the invention (not shown), the pixels are in contact with the amplifier, and the amplifier is in direct contact. Without any barrel-chaining circuitry, the repetition rate of the sensor would increase significantly.

FIG. 20 shows a flowchart of a wafer-level chip-scale packaging method according to an example embodiment of the present invention. This method is particularly useful in the manufacture of packaged CCD image sensors.

As shown in Figure 20, the silicon wafer is bonded to a glass sheet at its front side. As a next step, the silicon layer supported by the glass sheet is thinned.

In order to contact the pixels of eg a CCD sensor, vias are formed in the silicon layer. Wires are used to contact the pixels to the solder ball grid array. A solder ball grid array allows contacting of the sensor package.

As a final step, the chips are singulated by dicing.

Referring to Figure 21, the step of bonding the glass sheet and silicon layer is shown in more detail.

The glass sheet is treated with a plasma including oxygen to activate the glass surface.

As a next step, the silicon and glass layers are pretreated in a CVD process. HMDS (hexamethyldisilazane) is used as an example of the precursor gas.

The glass and silicon layers are aligned and bonded with adhesive. The adhesive is cured with UV radiation and heat.

Glass sheets serve as optical components for example in image sensors and as protection when transporting silicon wafers.

Referring to FIGS. 22 and 23 , the step of forming a via is shown in more detail according to an exemplary embodiment of the present invention.

Fig. 22 exemplarily shows the steps of thinning the silicon layer. The wafer is laminated to the foil, and the silicon layer is thinned to a thickness of 50 to 180 μm by grinding. Grinding can be performed in several steps with different abrasives to achieve the final precision.

Due to the fact that a glass layer is used as a carrier for the silicon layer, it is possible to produce a substantially homogeneous silicon layer with a thickness of less than 10 μm.

After grinding, the wafer is rinsed, the foil is removed, and the wafer is rinsed again.

Referring to FIG. 23, the steps of applying photolithography to the silicon structure are shown in detail. Spin coat the wafer with primers. The photoresist was heated at 90°C for 30 minutes, exposed and developed.

After rinsing and drying, the vias and channels of the electronic structure are etched with the etching method according to the invention. The plasma etch process is performed in one-step and two-step strategies. By etching in a one-step strategy, the etch rate is typically set lower. Therefore, a second etching step for reducing the overhang (bow) may be unnecessary.

The sidewall angle of the etched structure is typically 70°. The thickness of the silicon layer can be further reduced in the etching process. Using this steep sidewall angle, backside contacting of small structures such as image sensors such as CCD chips is possible.

The wafer after performing these steps is shown in FIG. 7 .

Photoresist stripping is performed with an oxygen-containing plasma.

Referring to FIG. 24, an insulating layer is deposited onto the surface of the structured wafer using a low temperature PECVD (Plasma Enhanced Chemical Vapor Deposition) process. The SiO insulating layer has a typical thickness of 2 μm on top and 1 μm inside the vias.

For photolithography, more layers are applied in a spraying process. These layers have a typical thickness of 20 μm on top and 1-2 μm inside the vias.

The wafer now corresponds to FIG. 8 .

Referring to FIG. 25, a flow chart shows in detail the steps of contacting a pixel such as a chip. Through a plasma etch process, using CF ₄ /C ₄ F ₈ /He plasma, the insulating layer is removed to contact the pixels (as shown in FIG. 9 ).

To ash the hardened resist layer on top, an oxygen-containing plasma is applied.

The resist is now stripped.

The wafer now corresponds to FIG. 8 .

As a next step, Al leads are sputtered to fill the vias (redistribution). It is not explicitly shown that the formation of the Al via holes providing the electronic structure is performed with conventional thin film methods including wet etching processes.

The wafer now corresponds to FIG. 9 .

To provide contact to the CCD chip, a solder ball grid array (forming bumps) is applied.

The wafer now corresponds to FIG. 10 . Finally, the chips are singulated.

It will be apparent to those skilled in the art that modifications and variations of the methods and apparatus described above are possible without departing from the inventive concepts disclosed herein.

label:

1 Substrate

2 chips

3 mask

4 opening

5 channels

6 Conductive material

10 glass pieces

11 Silicon layer

12 glued layer

13 resist layer

14 Conductive material

15 The first passivation layer

16 Second passivation layer

17 resist layer

20 Overhang

21 Undercut

30 Plasma source

31 Lower electrode

32 Upper electrode

33 Gas inlet

34 pump

40 photosensitive device

41 pixels

42 Adhesive layer

43 amplifier

44 IC layer

45 Contact layer

Claims (59)

1. the method for the plasma etching of at least a portion of substrate comprises:

Substrate is provided,

On described substrate, apply at least one the structurizing mask that comprises opening,

On described substrate, apply at least one mask, and

In described mask, limit opening by constructing described mask,

Use comprises that the process gas of at least a halogenide and oxygen passes through plasma etch process and removes material from described substrate at least in described opening.

2. according to the method for the plasma etching of at least a portion of the substrate of claim 1, when it is characterized in that being expressed as the volume percent of gas in the described process gas amount of oxygen be preferably lower than 30% less than 40%, particularly preferably be lower than 25%.

3. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described oxygen with respect to described halid ratio less than 30%, preferably less than 25%, particularly preferably less than 20% (volume percent).

4. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described halogenide is provided as sulfur halide.

5. according to the method for the plasma etching of at least a portion of the substrate of claim 2, it is characterized in that described sulfur halide is provided as SF ₆

6. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described substrate comprises semiconductor material.

7. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described substrate comprises silicon.

8. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described substrate is a wafer.

9. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described mask comprises photoresist material.

10. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described mask is a mask.

11. the method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim also comprises the step of peeling off described mask.

12., wherein at least two etch step, carry out the etching of described substrate according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

13. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, wherein first etch step has than the higher etch rate of second etch step subsequently.

14., wherein in second etch step, reduce the amount of described oxygen according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

15. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, wherein etched substrate in the etch step is in the end used the technology that does not comprise oxygen in this last etch step.

16., wherein in an etch step, carry out the etching of at least one passage in described substrate according to the method for the plasma etching of at least a portion of the substrate of claim 1～11.

17. method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim, the etch rate that it is characterized in that described etching technics is between 5 to 500 μ m/min, preferably between 7 to 100 μ m/min, particularly preferably between 8 to 20 μ m/min.

18., it is characterized in that described process gas also comprises CHF according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim ₃

19., it is characterized in that described process gas also comprises C according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim ₄H ₈

20., it is characterized in that etching passes through at least one passage of described substrate according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

21., it is characterized in that etching passes through at least one wedgy passage of described substrate according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

22. method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described wedgy passage limits the side wall angle of described relatively substrate surface, wherein said side wall angle is regulated between 50 ° and 90 °, preferably between 60 ° and 85 °, regulate, particularly preferably between 65 ° and 80 °, regulate.

23. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described passage sidewall the peak to the paddy roughness less than 200nm, preferably less than 100nm, particularly preferably less than 50nm.

24., it is characterized in that if described surfaceness is expressed as the standard surface roughness R of sidewall according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim _a, the surfaceness of the sidewall of described passage is less than 100nm, preferably less than 30nm, particularly preferably less than 10nm.

25., it is characterized in that formation has 10 μ m to 500 μ m, preferably 15 to 100 μ m, particularly preferably at least one passage of the diameter of 18 to 70 μ m according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

26. method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim, wherein said passage is limited to overhanging below the described mask, the diameter of wherein said passage is greater than the diameter of described opening, the difference of described diameter that it is characterized in that the described diameter of opening and described passage is less than 10 μ m, preferably less than 5 μ m, particularly preferably less than 2 μ m.

27. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, wherein said sidewall is at least by the part passivation.

28., wherein obtain described passivation by adding passivation gas for described process gas according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

29. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, wherein said passivation gas comprises at least a carbon compound.

30. according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim, wherein said passivation gas comprises C ₄F ₈And/or CHF ₃

31., it is characterized in that controlling described overhanging by the power of plasma source according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

32., also comprise the step of the described substrate of attenuate according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

33. method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that the removed degree of depth of described material in the described substrate is between 5 μ m to the 500 μ m, preferably between 20 to the 200 μ m, particularly preferably between 80 to the 160 μ m.

34., it is characterized in that producing described plasma body with induction coupled plasma body (ICP) source according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

35., it is characterized in that constructing described mask with step unit according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

36., also comprise the step on smooth substrate surface according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

37. the method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim is characterized in that the etching by substrate surface, carries out the step of smooth substrate especially by the KOH etching.

38., also be included at least one conductive layer of deposition on the described substrate according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

39., also comprise with at least one passivation layer coated substrate at least in part according to the method for the plasma etching of at least a portion of the substrate of any in the aforementioned claim.

40. method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim, when it is characterized in that being expressed as the volume percent of gas in the described process gas amount of oxygen between 3 to 40%, preferably between 5 to 30%, particularly preferably between 10 to 20%.

41. method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim, it is characterized in that described substrate temperature is lower than 200 ℃ during described plasma etch process, be preferably lower than 150 ℃, particularly preferably be lower than 120 ℃.

42. the method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim is characterized in that discontinuously, particularly described plasma etch process is carried out on pulsed ground.

43. the method according to the plasma etching of at least a portion of the substrate of any in the aforementioned claim comprises:

Substrate is provided,

On described substrate, apply at least one mask,

In described mask, limit opening by constructing described mask,

At least in described opening, remove material by plasma etch process from described substrate.

44. can make, especially according to the electronic unit of any manufacturing in the preceding method claim.

45. can make, use the wafer-class encapsulation of making according to the method for any in the preceding method claim especially.

46. can make, use the MEMS (micro electro mechanical system) of making according to the method for any in the preceding method claim (MEMS) especially.

47. can make, use the microfluidic device of making according to the method for any in the preceding method claim especially.

48. can make, use the strainer, particularly molecular sieve made according to the method for any in the preceding method claim especially.

49. can make, use the microprocessor of making according to the method for any in the preceding method claim especially.

50. can make, use the transmitter, particularly pressure transmitter made according to the method for any in the preceding method claim especially.

51. can make, use the water cooler that is used for microprocessor especially according to the method manufacturing of any in the preceding method claim.

52. can make, use the sensor devices of making according to the method for any in the preceding method claim especially, particularly electric charge coupling sensor devices (CCD) or complementary metal oxide semiconductor (CMOS).

53. according to any sensor devices in the aforementioned claim, comprise at least one light-sensing element array of the pixel that limits described sensor devices, wherein said photo-sensitive cell is contacted by the back side.

54., it is characterized in that described pixel is contacted by the back side and be electrically connected with amplifier according to any sensor devices in the aforementioned claim.

55., it is characterized in that described at least one amplifier is with each alignment of pixels according to any sensor devices in the aforementioned claim.

56. according to the sensor devices of aforementioned claim, wherein said amplifier is contacted by the back side and/or connects with bucket team circuit (Eimerkette).

57. according to the sensor devices of aforementioned claim, wherein said amplifier is the cascade type amplifier.

58. according to the sensor devices of aforementioned claim, wherein said sensor devices comprises photomultiplier cell, is used for the secondary electron multiplier of photomultiplier transit especially.

59. sensor devices, especially according to any sensor devices in the aforementioned claim, at least one light-sensing element array that comprises the pixel that limits described sensor devices, described photo-sensitive cell is characterized in that with the contact of the amplifier back side at least one amplifier is with each alignment of pixels.

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