CN101009836A - Embedded video playing device based on the dual processor - Google Patents

Abstract

The invention discloses an embedded video playback device based on dual processors. The playback device is provided with two processors, which are the embedded processor responsible for reading the video code stream from the video data source device and the DSP decoding processor for decoding and playing video code stream; by setting two processors, data reading and decoding display are completed by different processors, and the respective advantages of the processors can be used at the same time. Compared with single-core processors, they have More powerful performance. At the same time, the data reading performance requirements from low-end to high-end can be realized by replacing the embedded processor. By replacing the DSP processor, audio and video codec algorithms with low bit rate and low complexity can be realized to audio and video with high bit rate and high complexity. Compared with multi-core processors, video codec algorithms have more processor choices, and processor combinations can be customized according to different performance requirements.

Description

Embedded Video Playing Device Based on Dual Processors

technical field

The invention relates to the technical field of digital video processing, in particular to an embedded video playback device based on dual processors.

Background technique

With the rapid development of information technology, the rapid popularization of the Internet, and the acceleration of the integration of 3C (computer, communication, consumer electronics), the digital age has come. Digital products with embedded network multimedia system as the technical core have become mainstream products in the digital age. Typical embedded network multimedia system embedded video surveillance system (DVR), IP set-top box (IP-STB), portable media player (PMP) and other products all include embedded video playback system. The embedded video playback system is divided into single-core single-processor architecture, multi-core single-processor architecture and multi-processor architecture according to the architecture. The single-core architecture usually cannot meet the computational load of encoding and decoding data processing and code stream sending and receiving processing, and there are relatively large limitations in capacity. The multi-core single-processor architecture has strong processing capabilities, but the structure is limited and difficult to customize and expand. The multi-processor architecture has the characteristics of flexible structure and powerful performance, but it needs to solve the problems of communication and coordination between processors.

Contents of the invention

The invention provides an embedded video playing device based on dual processors. The system divides decoding and playing and reading video data sources into two processors for processing. The video data source is read by the embedded processor, and decoded and played by the DSP processor. It has the advantages of powerful processing performance, flexible function customization, flexible upgrade, and wide application range.

A kind of embedded video playing device based on dual processors, described playing device is provided with two processors, is the embedded processor that is responsible for reading the video code stream from the video data source device and is responsible for video code stream DSP decoding processor for decoding and playing;

One end of the embedded processor is connected to the video data source device, and the other end is connected to the DSP decoding processor through a dual-port RAM device, and the DSP decoding processor is connected to the display;

Among them, the embedded processor includes a code stream reader and a code stream transmitter,

Dual-port RAM devices include shared registers and stream registers,

DSP decoding processor includes code stream buffer, decoder and playback controller;

The code stream reader reads the video code stream from the video data source device, the code stream transmitter checks the remaining space information of the buffer of the shared register, obtains the video code stream from the code stream reader, and sends it to the code stream buffer through the code stream register The code stream buffer buffers the received video code stream, updates the buffer status information in the shared register, the decoder obtains the video code stream from the code stream buffer, and decodes it, and the video data is received by the playback controller And control its playback speed, output to the monitor for video display.

The shared register buffer is set with upper and lower limit marks. When the code flow in the shared register buffer is lower than the lower limit, the sending is started, and when the to-code flow is higher than the upper limit, the sending is stopped.

The video data source device may be a network video server or a local disk.

The present invention can realize the data reading performance requirements from low-end to high-end by replacing the embedded processor, and can realize audio and video encoding and decoding algorithms with low code stream and low complexity to audio and video with high code stream and high complexity by replacing the DSP processor. Video codec algorithm.

In the present invention, by setting two processors, data reading and decoding and displaying are respectively completed by different processors. Since the embedded processor has powerful network functions and storage operation functions, it cooperates with the embedded operating system and rich The application program can realize multiple audio and video data acquisition methods, so the present invention uses an embedded processor to complete the data reading process; and the DSP processor has powerful audio and video data processing capabilities, and can realize the decoding of multiple audio and video codes display, so the decoding and display process of the present invention is completed using a DSP processor.

The video playback process is divided into two processors, and the respective advantages of the two processors can be used at the same time, and it has more powerful performance than a single-core processor. At the same time, the present invention can achieve data reading performance requirements from low-end to high-end by replacing the embedded processor, and can realize audio and video encoding and decoding algorithms with low bit rate and low complexity to high bit rate and high complexity by replacing the DSP processor The advanced audio and video codec algorithm has a wide range of performance and is easy to customize, which is conducive to the multiplexing of software and hardware resources. Compared with multi-core processors, it has more processor options, and the processor combination can be customized according to different performance requirements.

In the video playback device of the present invention, the playback control is dominated by the DSP processor responsible for video data decoding and playback, and the embedded processor obtains the buffer situation of the decoding DSP processor through the shared register, and sends code streams to it as required. At the same time, the present invention sets the upper and lower limit marks on the buffer zone. When the code flow in the buffer zone is lower than the lower limit, the transmission is started, and when the code flow is higher than the upper limit, the transmission is stopped, so that the code stream transmission can be completed in a centralized manner. Compared with the previous method of simply setting the sending threshold, the playback performance will not be affected because the buffer code flow fluctuates around the threshold.

Description of drawings

Fig. 1 is a structural schematic block diagram of the present invention;

Fig. 2 is a schematic block diagram of the functional structure of the present invention;

Fig. 3 is a flow chart of the operation of video playback in the present invention.

Detailed ways

As shown in Figure 1, a kind of embedded video playback device based on dual processors is provided with two processors, which are responsible for reading the embedded video code stream from video data source devices such as network video server 110 or local disk 160. Formula processor 120 and the DSP decoding processor 140 that is responsible for decoding and playing the video code stream;

One end of the embedded processor 120 is connected to the video data source device, and the other end is connected to the DSP decoding processor 140 through the dual-port RAM device 130, and the DSP decoding processor 140 is connected to the display 150;

As shown in Figure 2, the embedded processor 120 includes a code stream reader 210 and a code stream transmitter 220;

The dual-port RAM device 130 includes a shared register 230 and a code stream register 280;

The DSP decoding processor 140 includes a code stream buffer 240 , a decoder 250 and a playback controller 260 .

As shown in Figure 3, when utilizing the video playback device of the present invention to play video, the code stream reader 210 reads the video code stream from the video data source device; the code stream transmitter 210 first checks the code stream buffer in the shared register 230 Status information, if the remaining space of the buffer is not greater than the upper limit, then wait in a loop until the code stream is consumed until the remaining space of the buffer is greater than the upper limit, then read the video code stream from the code stream reader 210, and pass the code stream register 280 to the code stream Stream buffer 240 sends video code stream, continues to check the state information of code stream buffer in shared register 230, if buffer remaining space is not less than lower limit, then continues to send video code stream to code stream buffer 240, until shared register 230 The remaining space of code stream buffer is less than the lower limit; code stream, and decode it, the playback controller 260 receives the video data and controls its playback speed, and outputs it to the display 150 for video display.

In the actual application process, the video playback device of the present invention can be customized according to different performance requirements. Realize audio and video encoding and decoding algorithms with low bit rate and low complexity to high bit rate and high complexity audio and video encoding and decoding algorithms, with more processor choices.

Claims (4)

1. embedded video playing device based on dual processor, it is characterized in that: described playing device is provided with two processors, for be responsible for reading the flush bonding processor (120) and the responsible DSP decoding processor (40) that video code flow is decoded and play of video code flow from the video data source apparatus;

Flush bonding processor (120) one ends connect the video data source apparatus, and the other end is connected with DSP decoding processor (140) through dual port RAM device (130), and DSP decoding processor (140) connects display (150);

Wherein, flush bonding processor (120) comprises code stream reader (210) and code stream transmitter (220);

Dual port RAM device (130) comprises shared register (230) and code stream register (280);

DSP decoding processor (140) comprises bit stream buffer device (240), decoder (250) and playing controller (260);

Code stream reader (210) reads video code flow from the video data source apparatus, code stream transmitter (220) inspection is shared the buffering area remaining space information of register (230), obtain video code flow from code stream reader (210), send to bit stream buffer device (240) through code stream register (280), bit stream buffer device (240) cushions the video code flow that receives, upgrade the buffer status information of sharing in the register (230), decoder (250) obtains video code flow from bit stream buffer device (240), and it is decoded, by playing controller (260) receiving video data and control its broadcasting speed, export display (150) to and carry out video and show.

2. the embedded video playing device based on dual processor as claimed in claim 1, it is characterized in that: the bound mark is set sharing register (230) buffering area, code flow is lower than down in limited time in shared register (230) buffering area, startup sends, and is higher than to code flow then to stop in limited time sending.

3. the embedded video playing device based on dual processor as claimed in claim 1 is characterized in that: described video data source apparatus can be network video server (110) or local disk (160).

4. the embedded video playing device based on dual processor as claimed in claim 1, it is characterized in that: can realize from low side can realizing the audio/video encoding/decoding algorithm of the audio/video encoding/decoding algorithm of low code stream low complex degree by changing dsp processor by changing flush bonding processor to the high complexity of high code stream to high-end data read performance requirement.

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