CN101008921A - Embedded heterogeneous polynuclear cache coherence method based on bus snooping - Google Patents

Abstract

The invention discloses an embedded heterogeneous multi-core cache consistency method based on bus snooping. The method of the present invention adopts the advantages of the "write-through" and "write-back" strategies to realize a processor level-1 cache coherence method suitable for a bus-based heterogeneous multi-core processor system based on a write-once strategy, Its main function is to ensure the consistency of multiple copies of the same data in the multiprocessor core's local L1 cache and shared L2 cache. The method is suitable for bus-based heterogeneous multi-core system processors, combines the advantages of write-through and write-back strategies, reduces invalid operations, reduces bus traffic, and improves bus efficiency.

Description

Embedded heterogeneous multi-core cache coherency method based on bus snooping

technical field

The invention relates to the field of heterogeneous multi-core processor systems, in particular to an embedded heterogeneous multi-core cache consistency method based on bus snooping.

Background technique

Multi-core processor, that is, single-chip multi-processor refers to the integration of multiple microprocessor cores on one chip, which can execute program codes in parallel, reduce the power consumption of the processor without increasing the operating frequency of the processor, and obtain high polymerization performance. The heterogeneous multi-core processor means that the multiple microprocessor cores integrated on the chip are heterogeneous.

2006 is the year with the fastest processor replacement since computer history. Processor manufacturers represented by Intel and AMD released dual-core processors at the beginning of the year, and then released a variety of dual-core processors. At the end of 2006, they released Quad-core processors. On January 10, 2007, Intel demonstrated an eight-core computer equipped with two quad-core processors. Multi-core processors began to enter the market across the board. The era of multi-core computers has really come. By the end of 2006, multi-core processor shipments had reached more than 90% of the total processor shipments. In the next few years, the number of processing cores will increase. According to Intel's processor development roadmap, Intel's mainstream processors in 2010 will be 128 to 144 cores. In addition, some other chip manufacturers are also developing processors with more cores. Among them, Rapport, a start-up company in Silicon Valley, USA, announced that it plans to develop a chip that integrates 1,000 simple processors. The arrival of the multi-core era has undoubtedly opened a new chapter in the history of computer development.

In current multi-core processor systems, multiple cores each have a separate L1 cache and a shared L2 cache. In this multi-core processor system, the cache structure brings new problems: if processes in different processor cores need to share some data, then there may be multiple copies of the same data stored in each L1 cache In , when the data in a certain L1 cache is updated, and the copy of the same data in other L1 caches is not modified accordingly, what those processor cores read from the private L1 cache will be "Dirty" data causes multiple versions of the same data to coexist. This is the so-called L1 cache coherency problem.

There are roughly three reasons for data inconsistency:

1. Inconsistencies caused by sharing writable data. As mentioned earlier, copies of the same data exist in multiple L1 caches. Doing the same modification will result in data inconsistency in multiple L1 caches. In addition, after the data in a certain level-1 cache is updated, before it is written back to the level-2 cache, the data in the level-1 cache and the level-2 cache will also be inconsistent. If there is just a processor core process (assuming that there is no copy of the modified data in the private first-level cache of the processor core) that needs this data at this time, when reading the second-level cache data, a data error will result.

2. Inconsistencies caused by process migration. In a multiprocessor core system, processes can migrate between processor cores. If a process in a processor core modifies the data in the private L1 cache, but before writing it back to the L2 cache, it needs to be migrated to another processor core for some reason to continue running, and at this time the read What you get will be "stale" data.

3. Data inconsistency caused by input and output operations. Assuming that there are data copies of the same data block in the second-level cache in multiple first-level caches, when the system starts an I/O operation, the I/O processor (channel DMA) may update the data in the second-level cache. data, resulting in data inconsistencies between the first-level cache and the second-level cache.

The consistency requirement means that if a piece of data is modified in the first-level cache, then on the second-level cache (and higher), the copy of the data must be modified immediately or last, and ensure that it refers to the second-level The correctness of the data content in the cache without increasing the communication load too much is the problem to be solved by the cache coherence protocol. There are two broad categories of approaches to achieving cache coherency on multiprocessor systems. One is the software method, when the program is compiled, the data is divided into two types, available cache and unavailable cache, through software analysis. The writable data shared by each processor belongs to the unavailable cache category and cannot be placed in the cache. The other is the hardware method. When the program is running, the hardware will dynamically identify the conditions of inconsistency and deal with it in time, so that the use of the cache is highly efficient. Moreover, this method is transparent to programmers and system software developers, and reduces the burden of software development, so it is generally adopted.

At present, the strategies generally adopted in the cache coherency strategy include write-back (Write-Back) and write-through (Write-Through) strategies. In the Cache using the Write-Through strategy, data blocks have two states: valid and invalid. Valid means that the content of the data block is correct, and invalid means that the content of the data block is "outdated" or not in the Cache. The effective state in the Cache using the Write-Through strategy is further subdivided into two types here: read-write (read-write) state and read-only (read-only) state. The read-only state indicates that more than one copy of the data block is correct in the whole system, for example, one is in the cache and the other is in the memory. The read/write status indicates that the data block has been modified at least once, and the corresponding data block in the memory has not been modified, that is, only one copy of the data block in the entire system is correct.

Contents of the invention

The purpose of the present invention is to provide an embedded heterogeneous multi-core cache coherence method based on bus snooping.

The technical solution adopted by the present invention to solve its technical problems is as follows:

1) Data block state distinction

According to whether the data block in the read and write operation is the first write, the data block in the first-level cache is divided into four states: "valid", "invalid", "reserved" and "rewritten";

2) Transformation between the four states of the first-level cache data block

When the processor core accesses a data block in the L1 cache, the state of the data block changes among the four states. The events that trigger the transformation of the first-level cache data block are divided into read operations and write operations:

I. During the read operation, there are two possibilities: one possibility is that when there is a valid data block in the first-level cache, the processor directly reads the data, and the state of the first-level cache remains unchanged; the other possibility is If there is no valid data block in the first-level cache, a read miss event will be triggered, and the system will transfer the valid data block into the first-level cache, and set the status of the corresponding data block to "valid";

II. During the write operation, there are two possibilities of hit or miss: when the write is hit, when the state of the first-level cache data block is in the "valid" state, the state of the first-level cache data block is transferred to "reserved", At the same time, the state of the corresponding data blocks in the other processing cores' L1 cache is set to "invalid"; when the write miss occurs, the state of the local L1 cache data block is set to "Reserved", and the corresponding data blocks of other L1 caches are set to "Reserved". The data block status is set to "invalid";

3) Read and write operations according to the state of the data block

Processor core L1 cache access is divided into read and write operations:

I. During the read operation, there are two possibilities: one possibility is that the processor core directly reads the data when there is a valid data block in the first-level cache; the other possibility is that there is no block in the first-level cache For valid data blocks, the system tries to transfer valid data blocks into the first-level cache, and when the corresponding data blocks are in the rewriting state, the operation of the second-level cache is also prohibited at the same time; If the corresponding data block in the write state indicates that the data block in the second-level cache operation is a correct copy, then it is sufficient to read it directly from the second-level cache operation;

II. During the write operation, there are two possibilities of hit or miss: when the state of the data block in the first-level cache is in the "valid" state, the write-through strategy will be adopted to write the written content into the second-level cache at the same time; When the first-level cache data block is in the "reserved" or "rewrite" state, the write-back strategy is used; when the write misses, a write-miss event is triggered, and the system first transfers the correct data block into the first-level cache, and uses the write-back strategy. Write back the data block through the policy.

Compared with the background technology, the present invention has the beneficial effects that:

This method is suitable for bus-based heterogeneous multi-core system processors. It combines the advantages of the two strategies of write-through and write-back. Since the first write and subsequent write operations adopt the write-through and write-back strategies respectively , reducing invalid operations, reducing bus traffic, and improving bus efficiency.

Description of drawings

Fig. 1 is overall flowchart;

Fig. 2 is a data block state transition diagram;

In Fig. 2, Rl represents the local processor core read; Rr represents the non-local processor core read; Wl represents the local processor core write; Wr represents the non-local processor core read.

Specific implementation method

The specific implementation process of the present invention is shown in FIG. 1 .

Step 1: Data block status distinction

According to whether the data block in the read and write operation is the first write, the data block in the first-level cache is divided into four states:

"Valid": the first-level cache data block read from the second-level cache and consistent with the copy of the second-level cache;

"Invalid": not found in the first-level cache or the content of the data block in the first-level cache is "obsolete";

"Reserved": The data is only written once after being read from the L2 cache into the L1 cache, the copy in the L1 cache is consistent with the copy in the L2 cache, and it is a correct copy;

"Rewrite": the data block in the first-level cache has been written more than once, and it is the only correct data block. At this time, the data block in the second-level cache is not a correct data block either.

Step 2: Transformation between the four states of the first-level cache data block

This step describes the transformation of the data block state of the first-level cache in terms of different operations of the processor on the first-level cache, as shown in FIG. 2 . The events that trigger the transformation of the first-level cache data block are divided into read operations and write operations. In Figure 2, Rl represents the local processor core read; Rr represents the non-local processor core read; Wl represents the local processor core write; Wr represents the non-local Processor core reads:

For read operations, there are two possibilities. One possibility is that when there is a valid data block in the L1 cache, it can be valid, reserved or rewritten, in which case the state of the corresponding data block does not change. Another possibility is that there is no valid data block in the L1 cache, that is, the data block is in an invalid state. At this time, a read miss event will be triggered, and the system will try to transfer valid data blocks into the first-level cache. In any case, the corresponding data blocks in the latter level-1 cache will enter the "valid" state.

When writing, there are also two possibilities: write hit and write miss. When a write hits, when the status of the first-level cache data block is in the "valid" state, the status of the first-level cache data block is transferred to "reserved", and the corresponding data block status of the other processing core first-level cache is set to is "invalid"; when the first-level cache data block is in the "reserved" or "rewrite" state, the state transfers to the "rewrite" state, and at this time, other first-level cache data blocks with the same content must be is in the "inactive" state;

When a write miss occurs, a write miss event is triggered. The system first transfers the correct data block into the first-level cache. Write through policy while writing to L2 cache. At this time, the status is transferred as follows: the status of the local first-level cache is set to "reserved", and the corresponding data block status of other first-level cache is set to "invalid".

Step 3: Perform read and write operations according to the state of the data block

Processor core L1 cache access is divided into read and write operations:

When the processor checks a L1 cache read, there are two possibilities. One possibility is that there are valid, reserved or rewritten data blocks in the L1 cache, and the processor core reads the data directly, and the status of the L1 cache remains unchanged. Another possibility is that there is no valid data block in the L1 cache, that is, the data block is in an invalid state. At this time, a read miss event will be triggered, and the system will try to transfer valid data blocks into the first-level cache. It is transferred into the local first-level cache; when the corresponding data block is in the rewriting state, the second-level cache operation is also prohibited at the same time. If there is no corresponding data block in the valid, reserved or rewritten state in the system, it means that the data block in the secondary cache is the correct copy (and the only copy), and at this time, it is directly read from the secondary cache That's it.

When the processor checks the L1 cache write operation, there are two possibilities similar to the read operation. Either hit, or miss. When a write hits, it will cause a transfer of the L1 cache state. Specifically, when the state of the first-level cache is in the "valid" state, the write-through strategy will be adopted to write the content written into the first-level cache into the second-level cache at the same time, and the state of the first-level cache will be transferred to "Reserve", and at the same time set the state of corresponding data blocks in other first-level caches to "invalid"; At this time, other first-level caches with the same content must be in the "invalid" state, so these first-level caches do not need to perform state transfer. When a write miss occurs, a write miss event is triggered. The system first transfers the correct data block into the first-level cache. Wear policy while writing to the L2 cache. At this time, the status is transferred as follows: the status of the local first-level cache is set to "reserved", and the corresponding data block status of other first-level cache is set to "invalid".

Claims (1)

1. An embedded heterogeneous multi-core cache consistency method based on bus snooping, characterized in that: 1) Data block state distinction According to whether the data block in the read and write operation is the first write, the data block in the first-level cache is divided into four states: "valid", "invalid", "reserved" and "rewritten"; 2) Transformation between the four states of the first-level cache data block The access of the processor core to the data block of the first-level cache causes the state of the data block to change among four states; the events that trigger the transformation of the data block of the first-level cache are divided into read operations and write operations: I. During the read operation, there are two possibilities: one possibility is that when there is a valid data block in the first-level cache, the processor directly reads the data, and the state of the first-level cache remains unchanged; the other possibility is If there is no valid data block in the first-level cache, the system transfers the valid data block into the first-level cache, and sets the state of the corresponding data block to "valid"; II. During the write operation, there are two possibilities of hit or miss: when the write is hit, when the state of the first-level cache data block is in the "valid" state, the state of the first-level cache data block is transferred to "reserved", At the same time, the state of the corresponding data blocks in the other processing cores' L1 cache is set to "invalid"; when the write miss occurs, the state of the local L1 cache data block is set to "Reserved", and the corresponding data blocks of other L1 caches are set to "Reserved". The data block status is set to "invalid"; 3) Read and write operations according to the state of the data block Processor core L1 cache access is divided into read and write operations: I. During the read operation, there are two possibilities: one possibility is that the processor core directly reads the data when there is a valid data block in the first-level cache; the other possibility is that there is no block in the first-level cache For valid data blocks, the system tries to transfer valid data blocks into the first-level cache, and when the corresponding data blocks are in the rewriting state, the operation of the second-level cache is also prohibited at the same time; If the corresponding data block in the write state indicates that the data block in the second-level cache operation is a correct copy, then it is sufficient to read it directly from the second-level cache operation; II. During the write operation, there are two possibilities of hit or miss: when the state of the data block in the first-level cache is in the "valid" state, the write-through strategy will be adopted to write the written content into the second-level cache at the same time; When the first-level cache data block is in the "reserved" or "rewrite" state, the write-back strategy is used; when the write misses, a write-miss event is triggered, and the system first transfers the correct data block into the first-level cache, and uses the write-back strategy. Write back the data block through the policy.

Images