CN100578814C - thin film transistor and thin film transistor array substrate - Google Patents

Abstract

A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, a spiral source electrode, and a spiral drain electrode. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer above the gate electrode. The spiral source electrode is arranged on the channel layer above the grid electrode, the spiral drain electrode is arranged on the channel layer above the grid electrode, and the spiral source electrode and the spiral drain electrode are arranged in a mutually winding state. By designing the spiral source electrode and the spiral drain electrode, the W/L ratio of a channel can be improved, and the parasitic capacitance C of a grid electrode and the drain electrode can be reduced_gd。

Description

Thin film transistor and thin film transistor array substrate

technical field

The present invention relates to a thin film transistor, and in particular to a thin film transistor capable of increasing channel W/L ratio and reducing gate-drain parasitic capacitance C _gd , thereby effectively reducing feedthrough voltage (ΔVp) .

Background technique

The display has become an important human-machine communication interface. Users can read information through the display and then control the operation of the device. Among them, the liquid crystal display is the focus of development. Generally speaking, a liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer between the two substrates. Among them, the thin film transistor (Thin Film Transistor, TFT) is mainly used to control the data writing of the liquid crystal display, which includes gate (gate), channel layer (channel) and source/drain (source/drain) and other components.

FIG. 1 is a schematic top view of a known TFT array substrate. Referring to FIG. 1 , a plurality of pixel structures 110 arranged in an array are mainly disposed on a thin film transistor array substrate 100 . Each pixel structure 110 is composed of a scan line 112, a data line 114, a thin film transistor 116 and a pixel electrode 118 corresponding to the thin film transistor 116.

Please continue to refer to FIG. 1, the thin film transistor 116 is used as a switching element of the pixel structure 110, and the scan wiring 112 and the data wiring 114 are used to provide the appropriate operating voltage for the selected pixel structure 110, respectively. Each pixel structure 110 is driven to display an image.

It should be noted that the thin film transistor 116 uses a part of the scan line 112 as the gate 116a, and after forming the semiconductor layer 116b directly on the scan line 112, the source 116c and the drain 116d are formed on the semiconductor layer 116b. A part of the semiconductor layer 116b between the source 116c and the drain 116d is the channel, and the channel has a channel width W (channel width, W) and a channel length L (channel length, L). When the channel width W is wider and the channel length L is shorter, the operation speed of the thin film transistor 116 is faster. However, since the channel layer 116b formed on the scanning line 112 has only a certain area, it is not easy to increase the channel width W within the limited area.

In addition, please continue to refer to FIG. 1. When the display is intended to display a predetermined picture, the thin film transistor 116 must be turned on to control the voltage applied to the pixel electrode 118, so that the voltage between the pixel electrode 118 and the color filter substrate (not shown) The liquid crystal molecules (not shown) between the common electrodes (commonelectrode) (not shown) on the top are deflected. Therefore, the light passing through the liquid crystal molecules will change the polarization direction along with the deflection of the liquid crystal molecules, and part of the polarized light will pass through the polarizing plate arranged on the color filter to achieve the purpose of display. It should be noted that, during the above voltage application process, the liquid crystal molecules will have a liquid crystal capacitance C _LC , which is formed by the coupling between the _pixel electrode 118 and the common electrode (not shown) on the color filter substrate. become.

Based on the above, when the thin film transistor 116 is turned off, the voltage applied to the liquid crystal capacitor C _LC still maintains a certain value, but since there is an overlapping area between the gate 116a and the drain 116d of the thin film transistor 116, the gate There will be a gate-drain parasitic capacitance C _gd between the drain 116a and the drain 116d, and due to the existence of the gate-drain parasitic capacitance C _gd , the voltage held on the liquid crystal capacitance C _LC will be As the signal on the data wiring 114 changes, the voltage held on the liquid crystal capacitor C _LC deviates from the originally set value. This voltage variation is called feed-through voltage (feed-through voltage) ΔVp, which can be expressed as:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; st</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; LC</span>}}}\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein ΔVg is the amplitude of the pulse voltage applied to the scanning wire 112 , and C _st is the storage capacitance.

Therefore, if the gate-drain parasitic capacitance C _gd can be reduced, ΔVp can be reduced, that is, the fluctuation of the feed-through voltage can be reduced, which can cause display unevenness (mura) or flicker (flicker) in the display screen. The situation improved.

Japanese Patent Publication No. JP2004-48036 discloses a technical solution close to the present application, which is to design the gate into a ring shape, and design one of the source and the drain into a ring shape and design the other is a straight line shape. This design is mainly to solve the leakage current problem, but it cannot effectively reduce the gate-drain parasitic capacitance Cgd.

Contents of the invention

In view of this, the object of the present invention is to provide a thin film transistor, which can increase the channel W/L ratio and reduce the gate-drain parasitic capacitance C _gd .

Another object of the present invention is to provide a thin film transistor array substrate, which includes thin film transistors that can increase channel W/L ratio and reduce gate-drain parasitic capacitance C _gd .

Based on the above and other objectives, the present invention provides a thin film transistor, which includes a gate, a gate insulating layer, a channel layer, a spiral source and a spiral drain. A gate insulating layer covers the gate. The channel layer is disposed on the gate insulating layer above the gate. The spiral source is arranged on the channel layer above the gate, and the spiral drain is arranged on the channel layer above the gate, wherein the spiral source and the spiral drain are arranged in a state of mutual winding.

Based on the above purpose or other purposes, the present invention further proposes a thin film transistor array substrate, which includes a substrate, scan lines, data lines, thin film transistors and pixel electrodes. A plurality of scanning lines are arranged on the substrate. A plurality of data lines are disposed on the substrate, wherein the scan lines and the data lines divide the substrate into a plurality of pixel regions. A plurality of thin film transistors are arranged on the substrate, and each thin film transistor is located in one of the pixel regions, and the thin film transistor is driven by a scan line and a data line, wherein each thin film transistor includes a gate, a gate insulating layer, a channel layer, spiral source, and spiral drain. A gate insulating layer covers the gate. The channel layer is disposed on the gate insulating layer above the gate. The spiral source is arranged on the channel layer above the gate, and the spiral drain is arranged on the channel layer above the gate, wherein the spiral source and the spiral drain are arranged in a state of mutual winding. The pixel electrodes are disposed on the substrate, and each pixel electrode is located in one of the pixel areas, and each pixel electrode is electrically connected to a corresponding thin film transistor.

In an embodiment of the present invention, the above-mentioned spiral source and spiral drain are arranged counterclockwise.

In an embodiment of the present invention, the above-mentioned spiral source and spiral drain are arranged in a clockwise direction.

In an embodiment of the present invention, the above-mentioned gate and the scan line are of the same metal layer.

In an embodiment of the present invention, the aforementioned spiral source is electrically connected to one of the data lines.

In an embodiment of the present invention, the aforementioned spiral drain is electrically connected to one of the pixel electrodes.

Because the present invention adopts the design of the spiral source and the spiral drain, the channel width (W) between the spiral source and the spiral drain can be widened on the channel layer with a limited area, and the channel length (L) can be kept almost constant, and therefore, the ratio of channel width to channel length (W/L) can be increased accordingly. In addition, the design of this thin film transistor can reduce the gate-drain parasitic capacitance C _gd , thus reducing the feed-through voltage ΔVp. Therefore, applying this thin film transistor to a display panel can improve problems such as display unevenness (mura) or flicker (flicker).

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of a known TFT array substrate.

FIG. 2 is a schematic top view of a thin film transistor in a preferred embodiment of the present invention.

Fig. 2A is a schematic cross-sectional view along line A-A' in Fig. 2 .

FIG. 3 is a schematic top view of another thin film transistor in a preferred embodiment of the present invention.

FIG. 4 is a schematic top view of a thin film transistor array substrate in a preferred embodiment of the present invention.

Description of main component marking

100, 300: TFT array substrate

110: Pixel structure

112, 270: scan line

114, 280: data line

116, 200: thin film transistor

116a, 210: grid

116b: semiconductor layer

116c: source

116d: drain

118, 290: pixel electrode

220: gate insulating layer

230: Channel layer

240a, 240b: spiral source

250a, 250b: spiral drains

260: protective layer

262: opening

310: Substrate

312: pixel area

A-A': hatching

W: channel width

L: channel length

Detailed ways

FIG. 2 is a schematic top view of a thin film transistor in a preferred embodiment of the present invention. Fig. 2A is a schematic cross-sectional view along line A-A' in Fig. 2 .

Please refer to FIG. 2 and FIG. 2A together. The thin film transistor 200 includes a gate 210 , a gate insulating layer 220 , a channel layer 230 , a spiral source 240 a and a spiral drain 250 a. The gate insulating layer 220 covers the gate 210 . The channel layer 230 is disposed on the gate insulating layer 220 above the gate 210 . The spiral source 240a is disposed on the channel layer 230 above the gate 210, and the spiral drain 250a is disposed on the channel layer 230 above the gate 210, wherein the spiral source 240a and the spiral drain 250a are wound around each other. It is set according to the state of rotation.

Referring to FIG. 2 and FIG. 2A, the thin film transistor 200, the scan line 270, the data line 280, the pixel electrode 290 and the like form a pixel structure. Moreover, generally, a protective layer 260 is covered on the thin film transistor 200 , and an opening 262 is formed on the protective layer 260 , and then the pixel electrode 290 is electrically connected to the thin film transistor 200 through the opening 262 .

It should be noted that, in an embodiment of the present invention, the spiral source 240 a and the spiral drain 250 a are arranged counterclockwise, as shown in FIG. 2 . However, in another embodiment of the present invention, the spiral-shaped source 240 b and the spiral-shaped drain 250 b are arranged in a clockwise direction, as shown in FIG. 3 . It can be seen from FIG. 2 and FIG. 3 that since the spiral source 240a and the spiral drain 250a, as well as the spiral source 240b and the spiral drain 250b are arranged in a manner of winding each other, even in a limited area On the channel layer 230, the present invention can also effectively increase the channel width W, and keep the channel length L almost unchanged. In this way, the ratio (W/L) of the channel width W to the channel length L can be increased. It is worth noting that the present invention can be wound by spiral source electrodes 240a, 240b and spiral source electrodes 250a, 250b. The number of turns, and then appropriately adjust the ratio of the channel width W to the channel length L.

Please refer to FIG. 2 again. In addition, since the spiral source 240a can form channels for the spiral drains 250a on both sides thereof, the operation speed of the thin film transistor 200 can be improved. Furthermore, in the thin film transistor 200 of the present invention, the shape of the spiral source 240a, 240b and the spiral drain 250a, 250b is not limited to the square shown in FIG. 2 and FIG. shape or polygon etc.

In addition, the thin film transistor 200 of the present invention can reduce the parasitic capacitance (hereinafter referred to as Cgd) between the gate and the drain. According to the formula of the feed-through voltage (hereinafter referred to as ΔVp),

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; st</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; LC</span>}}}\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Since Cgd is reduced, ΔVp is also reduced.

To further prove that the thin film transistor 200 of the present invention has lower Cgd and ΔVp, therefore, the ratio (W/L) of the channel width W to the channel length L of the thin film transistor 200 of the present invention is compared with that of the known thin film transistor 110 The ratio (W/L) of the width W to the channel length L is close, and comparing the Cgd and ΔVp of the two, the results in Table 1 can be obtained.

Table 1

Known Thin Film Transistor The thin film transistor of the present invention W/L 35/3 36/3 Cgd(F) 2.04E-14 1.7E-14 ΔVp(V) 0.486 0.406

It can be seen from Table 1 that the Cgd of the thin film transistor 200 of the present invention is reduced by about 16.65%, and ΔVp is reduced by about 16.48%. Design can effectively reduce Cgd and ΔVp. An embodiment of applying the thin film transistor 200 of the present invention to a thin film transistor array substrate will be described below.

FIG. 4 is a schematic top view of a thin film transistor array substrate in a preferred embodiment of the present invention. Please refer to FIG. 4 and FIG. 2A simultaneously, the TFT array substrate 300 includes a substrate 310 , scan lines 270 , data lines 280 , TFTs 200 and pixel electrodes 290 . A plurality of scan lines 270 are disposed on the substrate 310 . A plurality of data lines 280 are disposed on the substrate 310 , wherein the scan lines 270 and the data lines 280 divide the substrate 310 into a plurality of pixel regions 312 . A plurality of thin film transistors 200 are disposed on the substrate 310, and each thin film transistor 200 is located in one of the pixel regions 312, and the thin film transistor 200 is driven by the scan line 270 and the data line 280, wherein each thin film transistor 200 has been It is described in FIG. 2 , FIG. 2A or FIG. 3 and will not be repeated here. The pixel electrodes 290 are disposed on the substrate 310 , and each pixel electrode 290 is located in one of the pixel regions 312 , and each pixel electrode 290 is electrically connected to the corresponding thin film transistor 200 .

Please continue to refer to FIG. 4 and FIG. 2A. In an embodiment of the present invention, the gate 210 and the scan line 270 are the same metal layer, that is, the thin film transistor 200 uses the metal of the scan line 270 itself as the gate 210. . In addition, the spiral source 240 a is electrically connected to one of the data lines 280 , and the spiral drain 250 a is electrically connected to one of the pixel electrodes 290 .

Based on the above, the thin film transistor array substrate 300 with the above thin film transistor 200, because the design of the thin film transistor 200 can effectively reduce Cgd, thereby reducing ΔVp, so this thin film transistor array substrate 300 has better operating characteristics, and it can be applied When used in a display panel, problems such as display unevenness or flicker caused by excessive feed-through voltage ΔVp can be improved.

In summary, the thin film transistor and thin film transistor array substrate of the present invention have the following advantages:

(1) The present invention adopts the design of the spiral source and the spiral drain, so the W/L ratio of the channel can be increased on the channel layer with a limited area.

(2) Since the helical source can form channels for the helical drains on both sides, the operation speed of the thin film transistor can be improved.

(3) Since the thin film transistor of the present invention can effectively reduce the parasitic capacitance Cgd between the gate and the drain, it can further reduce the feed-through voltage ΔVp. Therefore, when the thin film transistor array substrate is manufactured by using the thin film transistor design and applied to a display panel, problems such as display unevenness or flicker caused by excessive feed-through voltage ΔVp can be improved.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (9)

1. A thin film transistor, characterized in that it comprises: grid; a gate insulating layer covering the gate; a channel layer disposed on the gate insulating layer above the gate; a spiral source disposed on the channel layer above the gate; and The spiral drain is disposed on the channel layer above the gate, wherein the spiral source and the spiral drain are disposed in a state of mutual winding. 2 . The thin film transistor according to claim 1 , wherein the spiral source and the spiral drain are arranged counterclockwise. 3 . 3. The thin film transistor according to claim 1, wherein the spiral source and the spiral drain are arranged in a clockwise direction. 4. A thin film transistor array substrate, characterized in that it comprises: Substrate; A plurality of scanning lines are arranged on the substrate; A plurality of data lines are arranged on the substrate, wherein the plurality of scanning lines and the plurality of data lines divide the substrate into a plurality of pixel regions; A plurality of thin film transistors are arranged on the substrate, and each thin film transistor is located in one of the plurality of pixel regions, and each thin film transistor passes through the plurality of scanning lines and the plurality of data line-driven, where each TFT consists of: grid; a gate insulating layer covering the gate; a channel layer disposed on the gate insulating layer above the gate; a spiral source disposed on the channel layer above the gate; The spiral drain is arranged on the channel layer above the grid, wherein the spiral The spiral source and the spiral drain are arranged in a state of mutual winding; and A plurality of pixel electrodes are arranged on the substrate, and each pixel electrode is located in one of the plurality of pixel regions, and each pixel electrode is electrically connected to the corresponding thin film transistor. 5 . The thin film transistor array substrate according to claim 4 , wherein the spiral source and the spiral drain are arranged counterclockwise. 6 . 6 . The thin film transistor array substrate according to claim 4 , wherein the spiral source and the spiral drain are arranged in a clockwise direction. 7. The thin film transistor array substrate according to claim 4, wherein the gate and the scan line are of the same metal layer. 8. The thin film transistor array substrate according to claim 4, wherein the spiral source is electrically connected to one of the plurality of data lines. 9. The thin film transistor array substrate according to claim 4, wherein the spiral drain is electrically connected to one of the plurality of pixel electrodes.

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