CN100561813C - Suppression method of hot-swapping inrush current in post-stage circuit and its buffered asynchronous start-up circuit - Google Patents

Abstract

The invention discloses a post-circuit hot-swapping surge current suppression method and its buffer asynchronous start-up circuit. The buffer asynchronous start-up circuit is based on the surge current suppression circuit, and a saturated conduction trigger circuit is added to detect the output voltage of the surge current suppression circuit. , to determine its working state, only after detecting that the inrush current suppression circuit is saturated and conducting, will it give a start signal to let the subsequent circuit start to work, so it can effectively prevent the subsequent stage circuit when the inrush current suppression circuit works in the linear region Start up, to avoid severe oscillation on the rising edge of the isolated output voltage, and effectively protect the entire system. The invention can be widely used in the hot-plug post-circuit of DC input to buffer the impact current of the post-circuit during hot-plug.

Description

Suppression method of hot-swapping inrush current in post-stage circuit and its buffered asynchronous start-up circuit

【Technical field】

The invention relates to a starting circuit, in particular to a starting circuit for preventing current impact.

【Background technique】

For circuit modules with large input capacitors, because the input stage has a large capacitive load, the impact current will be very large when the module is hot-swapped, which will easily cause the pins to ignite and reduce the performance and service life of the pins. ; At the same time, excessive inrush current may cause system shutdown, system power supply instability, or damage to system or internal components of the module. Therefore, a buffer startup circuit is often introduced to limit the current impact of the input capacitor on the system. In the prior art, the buffer startup circuit that suppresses the inrush current during hot swap adopts the following current limiting method:

Series resistance method: that is, a large resistance (usually a wire-wound resistance) is connected in series at the input end, but at this time, the power consumption on the resistance becomes larger, so a compromise resistance value should be selected so that the impact current and the power consumption on the resistance are equal. within the allowed range.

Thermistor method: The principle is the same as the series resistance method, but because of the negative temperature coefficient of the thermistor, as its own heating resistance becomes smaller, the power consumption is also reduced; It takes a while to reach its working state resistance value after startup, so low input may cause the power supply to work in a hiccup state.

Active inrush current limiting method: Utilizing the characteristics of low on-resistance and simple driving of MOS field effect transistors, an inrush current suppression circuit can be made by adding a small number of components around it. The basic idea is to incorporate a capacitor between the gate and drain of the MOS field effect transistor, which is to let the voltage of the gate and source of the MOSET rise slowly, so that the MOS field effect transistor is gradually turned on, and the hot swap of the module is realized. buffer.

Use ASIC to control the inrush current and realize the hot swap function: the existing LT1640 chip of Linear Technology Company provides a simple and effective inrush current control method. For detection, the current detected by the sampling resistor is used to control the turn-on degree of the MOS field effect transistor. As shown in Figure 1: at the moment of power-on, the MOS field effect transistor Q1 remains in the off state, which isolates the uncharged capacitor C3, the DC/DC power filter capacitor and the input power supply. As Q1 is turned on slowly, the capacitor Charge slowly under control, and only after the capacitor is fully charged, the chip gives a switch signal to make the DC/DC power supply start to work.

The circuit implementation of the series resistance method and the thermistor method in the above prior art greatly reduces the efficiency of the module, and the series connection of the resistance increases the input impedance of the module during normal operation, which is not conducive to the dynamic performance of the module. However, the buffer circuit using an ASIC, based on the control of the input current and the detection of the output voltage, has good performance, but the circuit is complicated and the cost is high; The reason for power consumption reduces the power supply efficiency of the system.

In the active inrush current limiting method that uses MOS field effect tubes to limit the inrush current, the MOS field effect tube linear amplification area is used to limit the inrush current, and when the input capacitor voltage rises to the start of the system, the MOS field effect The tube does not necessarily complete the transition to the linear amplification area. When the MOS field effect tube does not complete the transition to the linear amplification area, the startup of the system will cause the voltage on the input capacitor to sag, causing serious oscillations on the rising edge of the isolated output voltage.

【Content of invention】

The purpose of the present invention is to overcome the deficiencies in the prior art above, and provide a method for suppressing the surge current of hot-swapping in the subsequent stage circuit and its buffer asynchronous start-up circuit, which can effectively suppress the surge current during hot-swapping, and meet the requirements of the downstream circuit. The requirements for normal start-up inside the circuit and high working efficiency.

In order to achieve the above object, the present invention proposes a method for suppressing the inrush current of the post circuit hot swap, comprising the following steps: 1) using the inrush current suppression circuit to realize the slow rise of the output current and limit the maximum output value of the output current; 2 ) using a saturated conduction trigger circuit to monitor the conduction state of the inrush current suppression circuit in real time, and when the inrush current suppression circuit is saturated and conducted, the saturated conduction trigger circuit sends a power-on signal to start the subsequent circuit.

In the above method, the inrush current suppression circuit includes a MOS field effect transistor and a resistor and a capacitor connected in parallel between its gate and source, and the MOS field effect transistor can be selected to work in linear amplification according to the size of the input capacitance of the subsequent stage circuit. zone time. The saturated conduction trigger circuit judges the working state of the MOS field effect tube according to the monitoring of the voltage between the gate and the source of the MOS field effect tube, and provides a starting signal for the subsequent stage circuit to prevent the subsequent stage circuit from working in the MOS field effect tube. Start in the linear region. The maximum current limit value and current rising rate of the inrush current suppression circuit can be realized by selecting different capacitances connected in parallel between the gate and the source of the inrush current suppression circuit. The saturated conduction trigger circuit monitors the voltage between the gate and the source in real time through the voltage sampling circuit, and when the sampling voltage reaches a predetermined value, the switch circuit is started, and the switch circuit outputs a start signal to the subsequent circuit.

A buffered asynchronous startup circuit for hot-swap inrush current suppression, including an inrush current suppression circuit to realize a slow rise in output current; a saturated conduction trigger circuit that monitors the conduction state of the inrush current suppression circuit in real time, and when the When the inrush current suppression circuit is saturated and turned on, the saturated conduction trigger circuit sends a power-on signal to start the subsequent circuit.

In the buffered asynchronous starting circuit described above, the saturated conduction trigger circuit includes a voltage sampling circuit and a switch circuit; one end of the voltage sampling circuit is connected to the inrush current suppression circuit, and the sampling end is connected to the control end of the switch circuit; When the inrush current suppression circuit is saturated and turned on, the voltage at the sampling terminal of the voltage sampling circuit triggers the conduction of the switch circuit, sends a power-on signal, and starts the subsequent circuit.

In the buffered asynchronous starting circuit described above, the inrush current suppression circuit includes a MOS field effect transistor, a charging and discharging capacitor and a charging and discharging resistor, and the charging and discharging capacitor and the charging and discharging resistor are connected in parallel to the gate and source of the MOS field effect transistor Between, the gate and the source of the MOS field effect transistor are respectively coupled with the high and low potential terminals of the input voltage; the saturated conduction trigger circuit has two input terminals connected in parallel between the gate and the source of the MOS field effect transistor between.

In the buffered asynchronous startup circuit described above, the voltage sampling circuit includes a first voltage dividing resistor, a voltage stabilizing tube and a sampling resistor, and the three are connected in series successively between the grid and the source of the MOS field effect transistor; the stabilizing The common point of the pressure tube and the sampling resistor is the sampling terminal, which is connected to the control terminal of the switching circuit. The switch circuit includes a first switch tube, a second voltage dividing resistor and a second switch tube; the base of the first switch tube is connected to the sampling end of the voltage sampling circuit, and the emitter is connected to the low potential end; the second The voltage dividing resistor is connected between the collector of the first switch tube and the base of the second switch tube; the emitter of the second switch tube is connected to the high potential end, and its collector is used to connect to the subsequent circuit.

In the present invention, a saturated conduction trigger circuit is added to detect the output voltage of the inrush current suppression circuit, and its working state is judged. Only after the inrush current suppression circuit is detected to be saturated and conducted, a start signal is given to allow the subsequent stage circuit to start working, so it can be Effectively prevent the subsequent circuit from starting when the inrush current suppression circuit works in the linear region, avoid severe oscillation on the rising edge of the isolated output voltage, and effectively protect the entire system. The invention can be widely used in the hot-plug post-circuit of DC input to buffer the impact current of the post-stage circuit during hot plug-in.

Different from using a dedicated integrated chip to suppress the inrush current, the present invention does not perform buffer control based on the detection method of the inrush current, but realizes buffer startup by detecting the gate-source voltage of the MOS field effect transistor, that is, adopts the voltage detection method , It can be realized only by using ordinary transistors, MOS field effect transistors and voltage regulator tubes, plus resistors and capacitors. The components used are less, the circuit is simpler, and the cost is significantly reduced.

【Description of drawings】

Figure 1 is an example of an inrush current control circuit based on a control chip.

Figure 2 uses the block diagram of the buffer asynchronous start circuit of N-MOS field effect transistor.

Figure 3 uses the block diagram of the buffer asynchronous start circuit of the P-MOS field effect transistor.

Figure 4 N-MOS FET buffer asynchronous startup principle circuit.

【Detailed ways】

The present invention will be described in further detail below through specific embodiments and in conjunction with the accompanying drawings.

The principle block diagram of the present invention is shown in Figure 2 and Figure 3 respectively, at the output end of the surge current suppression circuit composed of MOS field effect transistor, charging and discharging capacitor, and charging and discharging resistor, a saturation conduction trigger circuit is added to monitor the surge current suppression in real time In the conduction state of the circuit, when the inrush current suppression circuit is saturated and conducted, the saturated conduction trigger circuit sends a power-on signal to start the subsequent circuit.

As shown in Fig. 4, it is a specific implementation manner. The saturation conduction trigger circuit includes a voltage sampling circuit and a switch circuit; one end of the voltage sampling circuit is connected to the surge current suppression circuit, and the sampling end is connected to the control end of the switch circuit; The trigger switch circuit is turned on, and a power-on signal is sent to start the subsequent stage circuit. The voltage sampling circuit includes the first voltage dividing resistor R3, the voltage regulator tube ZD1, and the sampling resistor R4, and the three are connected in series in sequence between the gate and the source of the MOS field effect transistor; the common contact point of the voltage regulator tube ZD1 and the sampling resistor R4 It is the voltage sampling terminal, which is connected with the control terminal of the switch circuit. The switching circuit includes a first switching tube Q2, a second voltage dividing resistor R5, and a second switching tube Q3; the base of the first switching tube Q2 is connected to the voltage sampling end of the voltage sampling circuit, and the emitter is connected to the low potential end; the second voltage dividing resistor R5 is connected between the collector of the first switching tube Q2 and the base of the second switching tube Q3; the emitter of the second switching tube Q3 is connected to the high potential end, and its collector is used to connect to the subsequent circuit.

The scheme works as follows:

As shown in Figure 4, the source S of the MOS field effect transistor Q1 is connected to the low potential end of the input, and the drain D is connected to the low potential pin of the input capacitor. Separated from the input power supply, a parallel network of charge and discharge capacitor C1 and charge and discharge resistor R2 is introduced between the gate G and source S of the MOS field effect transistor, and the drive of the MOS field effect transistor is connected by the input series resistor R1 to the gate Pole G; the circuit with this function can already realize the suppression of hot-swapping surge current.

At the moment of power-on, since the voltage across the input capacitor C2 cannot change abruptly, the input voltage is applied to both ends of the MOS field effect transistor Q1 at this time, and the drain D voltage of the MOS field effect transistor Q1 is equal to the input voltage; at the same time, the input power passes through the MOS The resistor R1 on the field effect transistor gate control circuit charges the charging and discharging capacitor C1 connected in parallel between the gate G and the source S, so that the voltage between the gate and the source of the MOS field effect transistor Q1 rises slowly at a set rate, Make the MOS field effect transistor transition from cut-off to linear conduction; in the linear working area, the MOS field effect transistor will limit the maximum current conducted between the drain D and the source S according to its own amplification characteristics, thus preventing hot plugging The inrush current when unplugging, choose different capacitors C1 for slow power-on, can obtain the rising rate of the gate-source voltage, and thus obtain different current limit values. When the gate and source voltages of the MOS field effect transistor Q1 are sufficiently high, the MOS field effect transistor Q1 enters saturation conduction. However, the selection of the capacitor C1 must also refer to the size of the input capacitor, so that the voltage on the capacitor C1 makes the MOS field effect transistor saturated and turned on, and the voltage of the input capacitor has reached more than 90% of the input voltage.

This design can change the saturated conduction trigger method to realize the function of buffer startup without changing the principle.

Claims (10)

1. A post-stage circuit hot-swapping inrush current suppression method, comprising the steps of: 1) using an inrush current suppression circuit to realize a slow rise in output current and limiting the maximum output value of the output current; 2) using a saturated conduction trigger The circuit monitors the conduction state of the inrush current suppression circuit in real time, and when the inrush current suppression circuit is saturated and turned on, the saturated conduction trigger circuit sends a power-on signal to start the subsequent circuit. 2. The method according to claim 1, characterized in that: the inrush current suppression circuit includes a MOS field effect transistor and a resistor and a capacitor connected in parallel between its gate and source, which can be input according to the capacitance of the subsequent circuit Size, select the time when the MOS field effect tube works in the linear amplification area. 3. The method according to claim 2, characterized in that: the saturated conduction trigger circuit judges the working state of the MOS field effect transistor according to the monitoring of the voltage between the gate and the source of the MOS field effect transistor, and gives the following The stage circuit start signal prevents the subsequent stage circuit from starting when the MOS field effect tube works in the linear region. 4. The method according to claim 2, characterized in that: the maximum current limit value and the current rising rate of the inrush current suppression circuit can be connected in parallel with the gate and source of the inrush current suppression circuit by selecting different Capacitance between to achieve. 5. The method according to claim 3, characterized in that: the saturated conduction trigger circuit monitors the voltage between the gate and the source in real time through the voltage sampling circuit, and when the sampling voltage reaches a predetermined value, the switch circuit is activated, and the The switching circuit outputs a starting signal to a subsequent stage circuit. 6. A buffered asynchronous startup circuit for hot-swapping inrush current suppression, including an inrush current suppression circuit to realize a slow rise in output current; it is characterized in that it also includes a saturated conduction trigger circuit to monitor the conduction of the inrush current suppression circuit in real time. In the on state, when the inrush current suppression circuit is saturated and turned on, the saturated conduction trigger circuit sends a power-on signal to start the subsequent circuit. 7. The buffered asynchronous starting circuit according to claim 6, characterized in that: the saturated conduction trigger circuit includes a voltage sampling circuit and a switch circuit; one end of the voltage sampling circuit is connected to the inrush current suppression circuit, and the sampling end Connected to the control terminal of the switch circuit; when the inrush current suppression circuit is saturated and turned on, the voltage at the sampling terminal of the voltage sampling circuit triggers the switch circuit to be turned on, and sends a power-on signal to start the subsequent circuit. 8. The buffer asynchronous starting circuit according to claim 7, characterized in that: the inrush current suppression circuit includes a MOS field effect transistor, a charging and discharging capacitor and a charging and discharging resistor, and the charging and discharging capacitor and the charging and discharging resistor are connected in parallel to the Between the gate and the source of the MOS field effect transistor, the gate and the source of the MOS field effect transistor are respectively coupled to the high and low potential ends of the input voltage; the saturated conduction trigger circuit has two input terminals connected in parallel to the Between the gate and source of the MOS field effect transistor. 9. The buffered asynchronous starting circuit according to claim 8, characterized in that: the voltage sampling circuit includes a first voltage dividing resistor (R3), a voltage regulator tube (ZD1) and a sampling resistor (R4), which are connected in series in sequence Afterwards, it is connected between the gate and the source of the MOS field effect transistor; the common contact point of the voltage regulator tube (ZD1) and the sampling resistor (R4) is the sampling terminal, which is connected to the control terminal of the switching circuit. 10. The buffered asynchronous starting circuit according to claim 9, characterized in that: the switch circuit includes a first switch tube (Q2), a second voltage dividing resistor (R5) and a second switch tube (Q3); The base of the first switching tube (Q2) is connected to the sampling end of the voltage sampling circuit, and the emitter is connected to the low potential end; the second voltage dividing resistor (R5) is connected to the collector of the first switching tube (Q2) and between the bases of the second switching tube (Q3); the emitter of the second switching tube (Q3) is connected to the high potential end, and its collector is used to connect to the subsequent stage circuit.

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