CN100565490C

CN100565490C - Active termination control through on-module registers

Info

Publication number: CN100565490C
Application number: CNB2003801089559A
Authority: CN
Inventors: J·W·扬岑
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2002-11-20
Filing date: 2003-11-12
Publication date: 2009-12-02
Anticipated expiration: 2023-11-12
Also published as: CN1809824A

Abstract

A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory. The module register monitors the system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory. The memory turns on active termination according to information programmed into one or more mode registers of the memory. The memory maintains the active termination in the on state for a predetermined time based on information programmed into one or more mode registers of the memory.

Description

Active termination control by register on the module

Related application

The application requires the right of priority of U.S. Provisional Application No.60/427917 that submitted on November 20th, 2002 and the U.S. Patent application No.10/383939 that submitted on March 7th, 2003.

Invention field

The present invention relates to memory storage.Specifically, it relates to the read and write order active termination control afterwards in memory storage.

Background of invention

Many electronic systems adopt controller and the memory storage that sends information each other back and forth.Information transmits on one or more system buss usually.These buses are as transmission line.Therefore, these bus requests are considered the design of the signal reflex related with the device that is coupled to transmission line.Transmission line adopts the resistance that is coupling between transmission line and the power supply node to stop usually.

For electronic system, as computing machine, provide termination by the non-essential resistance of operated by rotary motion on computer motherboard.Have with the non-essential resistance of the impedance of the impedance matching of transmission line and be selected to stop transmission line, for example to be connected the interconnect signal line of the bus of a plurality of integrated circuit.When the resistive component of non-essential resistance matched transmission line impedance, exist few or do not have signal reflex.But the non-essential resistance that is arranged on all signal wires on the system board uses a large amount of areas on these plates.

As a kind of alternatives of non-essential resistance, stop on the chip or tube core on stop, be called again on the integrated circuit that active termination can be used for system.Use and to stop the requiring device of system on the chip, as the additional interconnection between controller and the storer.This additional interconnection also requires other device of controller and system to use additional pin connector.The quantity that additional connecting line on the various devices is connected with pin depends on and is used to provide the global design that stops on the chip.

Needed is a kind of parts that the control of active termination control is provided, and it is flexibly, and does not require that electronic system is added a large amount of pins to be connected.

Summary of the invention

A solution to the problems referred to above is provided in the present invention.Provide the active termination control signal to provide a kind of method and apparatus by module register to storer for the control of the active termination in the storer.Read and write order on the module register monitors system command bus.Read or write order and respond detecting, module register produces the active termination control signal to storer.Storer starts active termination according to the information in the one or more mode registers that are programmed into storer.In one embodiment, memory column address strobe (CAS) stand-by period is used for determining turn-on time, and memory burst length (BL) is used for determining the trip time of active termination after connecting.Being set to the CAS stand-by period turn-on time deducts a plurality of clock period.After active termination was connected, it kept connecting in the amount of cycles that is set to approximate greatly the BL/2 that is equivalent to Double Data random access storage device (being called DDR) adds the time spans of 1.5 clock period.For the storer of a data bit of phase read and write weekly, active termination keeps connecting in the time span of the amount of cycles that is set to approximate greatly the BL that is equivalent to storer.

These and other embodiment of the present invention, aspect, advantage and feature will be set forth in the following description, implement the present invention by reaching with reference to the accompanying drawings or pass through with reference to following explanation of the present invention, those skilled in the art can know these contents to a certain extent.Realize and obtain of the present invention aspect these, advantage and feature by instrument, process and the combination that in claims, specifically indicates.

Summary of drawings

Fig. 1 represents an embodiment of information handling system, comprising theory according to the present invention, have the computer system of the controller of the memory module of being coupled to.

Fig. 2 represents according to theory of the present invention, has the embodiment of system of the controller of the memory module of being coupled to.

Fig. 3 represents according to theory of the present invention, has the embodiment of module register that decoding circuit, a plurality of input command port, chip are selected the active termination port of port and output active termination control signal.

Fig. 4 represents according to theory of the present invention, has an embodiment of decoding circuit who selects the module register of the active termination control port of the signal output active termination control signal that received on the port and a plurality of input command ports according to chip.

Fig. 5 represents an embodiment according to the storer of theory of the present invention, is used to receive the active termination control port of active termination control signal and the steering logic that is coupled to active termination comprising being coupled to.

Fig. 6 represents according to theory of the present invention, has an embodiment who controls the extended mode register of the bit location that information is provided for active termination.

Fig. 7 represents according to theory of the present invention, is adopted as the embodiment that active termination is controlled the mode register of the bit location that information is provided.

Fig. 8 represents according to theory of the present invention, is used for the process flow diagram of an embodiment of the method for active termination control.

Fig. 9 represents according to theory of the present invention, is used for the process flow diagram of another embodiment of the method for active termination control.

Figure 10 represents according to theory of the present invention, be used to expand the process flow diagram of another embodiment of the method for active termination control.

Figure 11 represents to have according to theory of the present invention, at an embodiment of the method that is used for active termination control the sequential chart to the write operation of storer of CAS stand-by period three and burst-length four.

Figure 12 represents according to theory of the present invention, has the sequential chart of read operation in the storer of CAS stand-by period three and burst-length four at an embodiment of the method for the active termination control that is used for comprising the control of expansion active termination.

DETAILED DESCRIPTION OF THE PREFERRED

In the following detailed description of preferred embodiment,, illustrate that by diagram some can implement specific embodiments of the invention in the accompanying drawing with reference to the accompanying drawing that constitutes its ingredient.These embodiment are described in detail, be enough to enable those skilled in the art to implement the present invention, and be appreciated that and adopt other embodiment, can carry out process, electric or mechanical change, and not deviate from scope of the present invention.Therefore, it is not restrictive below describing in detail, and scope of the present invention is only defined by claims and equivalent thereof.

System

Fig. 1 represents an embodiment of information handling system 100, comprising theory according to the present invention, have the computer system 110 of the controller 120 of memory module of being coupled to 130,140.Controller 120 also is coupled to memory module 130,140 by command line 150 except that other path.Memory module 130,140 comprises one or more memory storages, wherein has the active termination of design in each memory storage.In addition, information handling system 100 also can comprise and is coupled to computer system 110 so that receive input and to keyboard 160, mouse 170 and the monitor 180 of its display message from system user.

Fig. 2 represents according to theory of the present invention, has the embodiment of system 200 of the controller 220 of memory module of being coupled to 230,250.In the embodiment of Fig. 2, memory module 230 comprises module register 232 and memory storage 234-241, and wherein module register 232 is coupled to each storer 234-241 via many circuits 245.Similarly, memory module 250 comprises module register 252 and memory storage 254-261.Module register 252 is coupled to each storer 254-261 via many circuits 265.In addition, module register 232 on the memory module 230 and the module register 252 on the storer 250 are coupled to the generic command bus of the system command bus 260 that belongs to system 200, and controller 220 also is coupled to this bus.Except system command bus 260, controller 220 also selects (CS#0) line 262 and CS#1 line 264 to be coupled to module register 232 via chip, and is coupled to module register 252 via CS#2 line 266 and CS#3 line 268.As the skilled person will understand, system 200 also comprises unshowned other element, other bus and communication path except that these elements.Accompanying drawing focuses on those elements that are used to understand according to the various embodiment of theory of the present invention.

Module register 232 is worked as the impact damper on the module, and its control signal from system's control bus 260 is driven into eight memory storage 234-241 on the module 230 again.Address and control are routed to module register 232, are retimed to memory storage 234-241 in the next clock period then.Therefore, bigger load can be placed on the system bus 260, and does not make the load of address and control line excessive.Other embodiment comprises 16,32 or 36 memory storages on the single memory module.For the memory module of higher density, the quantity of memory storage changes usually.Module register 232 is coupled to memory storage 234-241 via control line 245, and wherein control line 245 is coupled to each memory storage, provides such as row address strobe (RAS), CAS and writes signal the permission (WE).Other signal such as CS and clock permission (CKE) has the circuit that is independent of register module 232.Memory storage 234-241 mainly monitors its chip and selects input, given memory storage is read or write so that determine whether.In addition, each memory storage 234-241 has been equipped with active termination, rather than allows termination be arranged on the mainboard.

Module register 232 is coupled to controller 220 by CS#0 line 262 and CS#1 line 264.Module register 252 disposes as module register 232, but is coupled to controller by CS#2 line 266 and CS#3 line 268.This configuration is used for visiting two groups of memory storages at different time, and wherein one group usually in a side of memory module 230, and another group is then at the opposite side of memory module 230.This configuration is called secondary.But, exist only to have the two-sided module that a chip is selected, be one-level therefore.How the level of module determines when memory storage is read or write termination signal.For one-level, in certain embodiments, memory storage stops voluntarily.For dual module system, if write or read is operated at module one, then module two is the module of actual termination.Therefore, the module register 232 of memory module 230 and the module register 252 of memory module 250 be the read and write order on the monitoring system control bus 260 all, making provides the information relevant with read/write activities each other to each memory module 230,250, stops so that proofread and correct.

Module register

Fig. 3 represents according to theory of the present invention, have decoding circuit 302, a plurality of input command port 304,306,308,310 and 312, chip selects

port

314 and 316 and an embodiment of the module register 300 of the active termination port 320 of output active termination control (ATC) signal.Clock signal (CLK) and inversion clock signal (CLK#) receive at port 304,306 respectively.Receive anti-phase row address strobe (RAS#), anti-phase column address strobe (CAS#) and anti-phasely write permission (WE#) signal at port 308,310 and 312 respectively, and respectively at

port

314 and 316 reception CS0# and CS1# signals.Module register 300 is retimed these signals, and CLK, CLK#, RAS#, CAS#, WE#, CS0# and the CS1# signal from port 322,324,326,328,330,332 and 334 respectively is driven into the memory storage that it is coupled to.Except control signal being retimed and be driven into the memory storage, module register 300 also provides a kind of parts that are used to control the active termination of the memory storage that it is coupled to.

Decoding circuit 302 employings are monitored from the control signal that system command bus received and are read or write any memory module reception whether order has been coupled to the identical systems command line.When detecting the write or read order, decoding circuit 302 provides ATC signal at port 320.If write order is decoded, then with on the memory module sends write order and provide ATC signal from port 320 simultaneously.If read command is decoded, send on memory module then that one-period provides ATC signal from port 320 after the read command.Module register 300 monitoring system bus send active termination control to memory storage then.Therefore, there is not extra pin in module or on chipset.Eliminated for the ATC port on each memory module and for the needs of the ATC port on the controller that is coupled to each memory module using module register 300 on each memory storage with a port or pin.Module register 300 surveillance command lines, and control is sent to the signal of the memory storage that it is coupled to, and the control of ATC signal is provided.

Fig. 4 represents according to theory of the present invention, has an embodiment of decoding circuit 400 who selects the module register of the active termination port 402 of the signal output active termination control signal that received on the port 404,406 and a plurality of input command port 408,410,412,414,416 according to chip.CLK that on

port

416 and 414, is received and CLK# and be respectively the input signal of decoding circuit 400 that the order of mailing to selected memory storage is decoded at port 408,410,412 WE# that received, CAS#, RAS#.CS1# on port 404,406 or CS0# are used for logical circuit and enable output ATC signal or pulse respectively.For dual module system, CS0# and CS1# enable the output of an ATC signal on the memory module, and on another memory module, memory storage is selected for the read and write operation.

Decoding circuit 400 is command decode structures, and it comprises one group of gate circuit to read command or write order decoding.If write order is through the decoding circuit 400 of module register, then the ATC signal will send the memory storage that is coupled to module register to from port 402.The decoding circuit 400 of process module register is so that must at first pass through latch 418 from the read command of port 402 transmission ATC signals.Latch 418 provides relatively from a clock cycle delay that sends of the read command of another module register.

Storer

Fig. 5 represents an embodiment according to the storer 500 of theory of the present invention, is used to the steering logic 502 that receives the active termination control port 504 of active termination control signal and be coupled to active termination 505 comprising being coupled to.Steering logic 502 logics comprise the timing circuit that switches on and off active termination.Steering logic 502 expression standard memory steering logics are together with the adjunct circuit or the state machine of the state that is used for the active termination on the control store.As the skilled person will understand, for simplicity, Fig. 5 does not comprise all elements of storer, and only comprises those elements of understanding the required storer of described embodiment.

Except receiving the ATC signal at port 504, steering logic 502 also receives CKE, CLK# and CLK respectively on port 506,508,510.Storer 500 also receives command signal CS#, WE#, CAS# and RAS# respectively on port 512,514,516 and 518, they are decoded in command decode 520.In addition, storer 500 also has as the ingredient of steering logic 502 or is coupled to one or more mode registers 522 of steering logic 502.Employing comprising CAS stand-by period, mode of operation, burst-length and outburst type, be used for operational store 500 information to one or more mode registers 522 programmings.According to specific memory, additional operations information can be included in one or more mode registers 522.

The memory circuit 528 that storer 500 also comprises address bus 524, data bus 526 and comprises the data of storage in the storer 500.Memory circuit 528 is coupled to address bus 524, so that receive the information that sign is used for reading or writing from data bus 526 unit of data.The A0-AX that the sign of unit is included in the BA0-BA1 that is used for the selection memory group and is used for the address of selection memory group.The management of read and write operation is being received from processor, is being carried out during as the order of the controller 220 of Fig. 2 by steering logic 502.The read and write operation utilization of storer 500 has the CLK input and controls with the delay locked loop that adjustment offers the timing of driver 532.The read and write operation is also controlled by data strobe pulse DQS, and wherein data strobe pulse DQS is by providing driver 532 to provide with the DQS generator 534 that control is located at the DQS on the DQS line 536.In addition, driver also is timed to data bus 526 DQ0-DQX of data bus position to the data that will shift 324 that received from memory circuit 314.

Storer 500 adopts one or more registers as mode register, wherein operation information usually when initialization or guiding (during system start-up) by controller programming in storer 500.As mentioned above, this information comprises CAS stand-by period, mode of operation, burst-length, outburst type.As everybody knows, burst-length is determined for the given maximum quantity that reads or writes the addressable column unit of order.Outburst type normally order or interweave, and the CAS stand-by period is read command by storer 500 records and from the clock period quantity between the primary availability of the output data of storer 500.Mode of operation can be routine operation or the routine operation that resets with delay locked loop (DLL).One or more mode registers 522 also can be programmed by the information that is used to control active termination.

Steering logic 502 is included in the timing circuit that the active termination control port receives active termination control signal schedule time connection active termination afterwards.The connection of active termination adopts one or more positions of definition CAS stand-by period to be provided with by storer 500.The connection of active termination also can be adjusted by the additional wait time (AL) that is programmed into equally in one or more mode registers.In one embodiment, the timing circuit of steering logic 502 is configured to deduct two clock period in the CAS stand-by period and adds the time of additional wait time and connect active termination.In one embodiment, the additional wait time is zero.Steering logic also is included in connects the timing circuit that the active termination device schedule time afterwards disconnects active termination.In one embodiment, steering logic 502 is configured to adopt the position that defines burst-length that be set the trip time of active termination.For simplicity, the amount of cycles that equals BL also is known as burst-length BL.Be set to the trip time of the timing circuit active termination of steering logic 502 burst-length after connecting an active termination divided by 2, add 1.5 clock period.The burst-length of DDR is divided by two, because a data bit is read out at the rising edge of clock, and another data bit is read out at the negative edge of same clock.Read the storer of a data bit for one of them clock period, will be that the burst-length after connecting an active termination adds 1.5 clock period the trip time of active termination.

In one embodiment, memory storage 500 has the active termination that comprises a plurality of stop values.One or more mode registers comprise selects one of them one or more positions of a plurality of active termination values.In one embodiment, a plurality of active termination values are 75 ohm and 150 ohm.In one embodiment, when storer is in the dual module system, use 75 ohm of stop values, and when storer is in the single module system, use 150 ohm of stop values.

In bimodulus piece or dual slot system, the command signal of the write or read of the memory storage on the module is accompanied by ATC connection signal to the memory storage on another module.But, in the system that only has a module, be not used in second module of active termination.In single module system, each storer stops voluntarily to write operation, does not then do any operation for read operation.In order to realize in the single module system that storer 500 comprises one or more positions in one or more mode registers 522 for thisly stopping voluntarily of writing, it shows that storer 500 is in single groove or the dual slot system.Storer 500 has logical circuit, makes when selecting single tank systems for one or more, makes storer 500 can ignore the active termination control signal that is received.When storer 500 is programmed to single tank systems during in initialization, the position of then having programmed is used for utilizing when receiving write order CAS stand-by period of one or more mode registers 522 and additional wait temporal information to connect voluntarily stopping.Active termination utilizes the burst length information that is programmed in one or more mode registers 522 to disconnect after connecting active termination.

In another embodiment, storer 500 comprises having and enables or one or more mode registers of the information of inactive active termination.

Like this, one or more mode register is used for being switched on or switched off active termination on the storer 500 according to the information that is programmed into these registers.Switch on and off active termination and compare with adopting external signal to connect active termination and adopt another external signal to disconnect active termination or two kinds of transformations by single active termination signal equivalently, this configuration provides more control able to programme.

Storer 500 and module register 300 and controller 220 all can be embodied as single integrated circuit.Storer 500 can use substrate to form on semiconductor element, and wherein substrate is material or other semiconductor material commonly used such as silicon, germanium, silicon on sapphire, gallium arsenide.The element of storer 500 adopts to form various circuit and provide in semiconductor material and is coupled to address bus, data bus and control line so that make with the traditional processing mode that is electrically connected of controller or processor communication.

The various embodiment of the various embodiment of storer 500 and the module register 300 of Fig. 3 can with the controller coupling of controller 220 of for example Fig. 2 and so on, thereby composition system 200 provides the system of the ability with its active termination control of management.In addition, one or more mode registers 522 of system 200 each storer 500 that it is coupled to that can adopt the one or more controllers of the various embodiment with controller 220 and other storer irrespectively to programme.

Data structure

Fig. 6 represents according to theory of the present invention, has an embodiment who controls the extended mode register of the bit location that information is provided for active termination.Extended mode register comprises the

bit location

0,1,2 that is used for respectively the information relevant with current control (QFC) with delay locked loop (DLL), drive strength (DS).Unit E0 provides for DLL enables/stops using.Unit E1 provides for the information about drive strength, and E2 provides for the QFC of current control is inactive.For example the extended mode register of the storer of storer 500 of Fig. 5 and so on is coupled to address bus 524 in operation, and the controller that is used for the controller 220 and so on by for example Fig. 2 is programmed.Controller 220 or middle controller utilize address bus that information is programmed in the extended mode register in initialization procedure.In general, the BA1 of address bus, BA2 unit are used for distinguishing the standard mode register and the extended mode register of programmable memory 500.BA1=0 and BA0=0 are commonly used to the standard mode register of programming, and simultaneously BA1=0 and BA0=1 are used for the standard mode register of programming.

Extended mode register can be used to programme one or more, is used for active termination control, is not provided with by standardisation bodies fully because be used for the position 3-11 of mode of operation.In one embodiment, the data structure of extended mode register comprises the field of the data that wherein comprise single groove of expression or dual slot memory system.This field comprises at least one position that is used to select single groove or dual slot system.In another embodiment, the data structure of extended mode register comprises the field of the data that wherein comprise a plurality of stop values of representing memory storage.This field comprises the one or more positions that are used to select 75 ohm of stop values or 150 ohm of stop values.In another embodiment, the data structure that is used for mode of extension comprises wherein having and comprises that expression is enabled or one or more field of the data of the automatic termination control of inactive storer.

Perhaps, active termination information is programmed into and is different from usually all in accordance with the standard mode register of the defined data structures of standardisation bodies such as for example JEDEC and one or more mode registers of extended mode register.CAS stand-by period and burst-length are programmed in the standard mode register usually.

Fig. 7 represents according to theory of the present invention, is adopted as the embodiment that active termination is controlled the mode register of the bit location that information is provided.Bit location 12,13 is coupled to address location BA0, BA1 respectively in operation, thus the sign of the mode register that will programme when providing to initialization.All the other bit location 0-11 are coupled to address bus unit A0-A11 respectively in operation.Bit location 0-11 can be used for active termination control.In one embodiment, the data structure of mode register comprises the field of the data that wherein comprise single groove of expression or dual slot memory system.This field comprises at least one position that is used to select single groove or dual slot system.In another embodiment, the data structure of mode register comprises the field of the data that wherein comprise a plurality of stop values of representing memory storage.This field comprises the one or more positions that are used to select 75 ohm of stop values or 150 ohm of stop values.In another embodiment, the data structure that is used for this pattern comprises wherein having and comprises that expression is enabled or one or more field of the data of the automatic termination control of inactive storer.

As previously described, the mode register of storer during the initialization of storer by controller programming.Perhaps, mode register can adopt specified command sequence to programme after initialization.In addition, the mode register of Fig. 6 and Fig. 7 is by providing the controller of data-signal to programme for storer, wherein data-signal is embodied by the one group of electric signal that comprises expression single groove or dual slot system, comprises the data of the data division that is used to select single groove or dual slot system.Data-signal comprises the data division that is used to select single groove or dual slot system, wherein has at least one position that is used to select single groove or dual slot system.For the data division that is configured to select single tank systems, this data division is to ignore the active termination control signal that is received with memory program.In another embodiment, data-signal also comprises the data of the selection of representing a plurality of active termination values, wherein has to comprise one or more data division selecting 75 ohm of stop values or 150 ohm of stop values.In another embodiment, data-signal comprise also that expression is enabled or inactive memory storage in the data of active termination control, wherein have to comprise and enable or one or more data division of inactive active termination control.

One or more mode registers are the programming when guiding or start by controller or processor in storer when initialize memory.Mode register adopts the data that comprise above-mentioned data division to programme.Controller is programmed to these mode registers with the instruction of being stored in the computer-readable media that obtains initialization directive to its visit according to controller.This computer-readable media can be the storage unit in the controller or other any computer-readable media that is coupled to controller in operation.Computer-readable media has the computer executable instructions that is used to carry out the position set that comprises one or more registers of determining to send and to be loaded into storer, arranges the method for position and carry-out bit set with predetermined format.In one embodiment, the position set comprises at least one position that is used to select single groove or dual slot system.When position set expression during to the selection of single tank systems, the output that storer is gathered in the position becomes to ignore the active termination control signal that is received with memory program.In addition, computer-readable media also can comprise the one or more positions that are used to select a plurality of stop values in the set on the throne.For example, one or more positions are provided for and select 75 ohm of stop values or 150 ohm of stop values.In another embodiment, position set also comprises and is used to enable or one or more positions of inactive active termination control.Person of skill in the art will appreciate that the computer-readable media that controller or processor are visited can belong to any computer-reader form, such as but not limited to CD-ROM, non-volatile ROM, ROM and RAM.

Operation

Fig. 8 represents according to theory of the present invention, is used for the process flow diagram of an embodiment of the method for active termination control.For example the module register of module register 300 of Fig. 3 and so on is used as

module register

232 and 252 in the system 200 of Fig. 2.At frame 802, module register 232 monitors system command bus 260.At frame 804, determine whether order is predetermined command.At frame 806, respond to determining that predetermined command is on the command line 260, send the active termination control signal.

In one embodiment, chip selection or anti-phase chip select signal that its slave controller 220 receives are also monitored in write order or read command on the module register 232 monitoring command lines simultaneously.In double flute or dual module system, module register 232 utilizes chip selection information to determine whether to export the ATC signal.For example, if the write or read order is used for the storer on the module one, then active termination is carried out on module two.Therefore, in Fig. 2, for the write or read to memory module 230, module register 252 is provided for the ATC signal of the active termination on the memory storage on the module 250.If detect the write order for the memory storage on the memory module 230, then module register 252 sends write order with module register 232 and produces the ATC signal simultaneously.The write order that ATC signal and module register produce was issued in a clock period that monitors from after the write order of system command bus 260.If detect the read command for the memory storage on the memory module 230, then the clock period of module register 252 after module register 232 sends write order produces the ATC signal.The read command that module register produces was issued in a clock period that monitors from after the read command of system command bus 260, and wherein the ATC signal was produced in two clock period that monitor from after the read command of system command bus 260.

Fig. 9 represents according to theory of the present invention, is used for the process flow diagram of another embodiment of the method for active termination control.At frame 902, receive the active termination control signal.At frame 904, connect active termination.For example the storer of storer 500 of Fig. 5 and so on is used for the memory module 230,250 of the system 200 of Fig. 2.Storer 500 receives the ATC signal, and connects active termination according to the information in one or more mode registers 522.Connect the schedule time generation of active termination after receiving the active termination control signal.In one embodiment, active termination according to one or more mode registers in CAS stand-by period of programming information relevant with the additional wait time connect.Being arranged to be approximately CAS stand-by period after receiving the ATC signal turn-on time deducts two clock period and adds the additional wait time.For example, for CAS stand-by period four of programming in standard mode register and additional wait time zero, active termination was connected in latter two clock period that receives the ATC signal.In another embodiment, for the storer that does not have the additional wait time, active termination is arranged to be approximately the CAS stand-by period that receives after the ATC signal and is deducted two clock period.Person of skill in the art will appreciate that, connect the schedule time of active termination and can adopt other parameter to be provided with.Comprise other predetermined turn-on time and adopt the CAS stand-by period to deduct additional clock amount of cycles, wherein additional clock amount of cycles can be any clock period quantity, comprises the mark clock period, less than the CAS stand-by period.Select the additional clock period just, make active termination before data are read or write, connect a short period.

Active termination length at the fixed time remains on-state.The schedule time adopts the information that is programmed in one or more mode registers to determine.In one embodiment, the schedule time is arranged to be approximately burst-length and adds 1.5 clock period divided by 2.For DDR, burst-length is divided by two.For reading or write one storer in the clock period, burst-length is not divided by two.For example, for the burst-length eight that is programmed in the standard mode register, five half clock cycles of active termination after active termination is switched on keep connecting.Person of skill in the art will appreciate that, keep the schedule time length of active termination can adopt other parameter to be provided with.Other schedule time length comprises and adopts burst-length or burst-length to add additional clock amount of cycles divided by two, and wherein clock period quantity can be 1,1.5,2,2.5 or other numerical value.Select the additional clock period just, make the short time interval of active termination data are read or write after still keep connection.

In one embodiment, the method that is used for the active termination control of storer comprise visit show active termination control the information enabling or stopping using, determine the turn-on time of active termination and the trip time of definite active termination.The information of enabling or stopping using that shows active termination control is provided by at least one position in the mode register.The one or more positions enabling or stop using that show active termination control combine with stand-by period information, so that be set to receive the ATC signal schedule time afterwards turn-on time.In one embodiment, the schedule time is set to CAS stand-by period after receiving the ATC signal and deducts two clock period and add the additional wait time.Perhaps, there are not additional wait time or additional wait time to be set to zero.Combine with burst length information to determine by the information of enabling or stopping using that will show active termination control trip time.In one embodiment, comprise that the burst-length that is set to trip time after the turn-on time of active termination adds the clock period multiple divided by two the trip time of determining active termination control.The suitable multiple of clock period is to equal about half clock cycle.

For example the storer of storer 500 of Figure 50 0 and so on adopts the ATC signal received, is programmed into the time that switches on and off that CAS stand-by period in the mode register and burst-length are provided with active termination.This operation is suitable for dual slot system, and wherein data are written into wherein or data are on the memory module the groove from the memory storage that wherein reads, and the memory storage that is used for active termination then is positioned at the memory module of another groove.For single tank systems, can use another kind of method.In one embodiment, the method that is used for the active termination control of storer comprises and receives the active termination control signal, ignores the active termination control signal and the response that are received and receive write order and connect active termination.The information that is used for ignoring the active termination control signal that is received is programmed into the mode register of storer.This information is stored in the mode register of storer as one or more positions usually.

For dual slot system, the time that switches on and off adopts stand-by period information and burst length information to be provided with respectively.Connecting the CAS stand-by period of active termination receiving write order after deducts two clock period and adds the time generation of additional wait time.In one embodiment, comprise the turn-on time that active termination is set and adopting for zero additional wait time.The schedule time of active termination after receiving write order is held.In one embodiment, the schedule time is approximately burst-length and adds a half clock cycle divided by two.In single tank systems, do not need to stop for read operation.

Figure 10 represents according to theory of the present invention, be used to expand the process flow diagram of another embodiment of the method for active termination control.For example the storer of storer 500 of Fig. 5 and so on is used for the memory module 230,250 of the system 200 of Fig. 2.At frame 1002, storer 500 receives the active termination control signal.At frame 1004, storer 500 is provided with the turn-on time of active termination.At frame 1006, storer 500 is provided with the trip time of active termination.At frame 1008, storer 500 determines whether another active termination control signal arrives.If another active termination control signal arrives, then storer 500 turns back to frame 1006, according to nearest active termination control signal new disconnection is set.At frame 1010, if another active termination control signal does not arrive, then storer 500 disconnects active termination in the trip time that was provided with the last time based on last the ATC signal that is received.Like this, storer 500 responses receive another ATC signal when active termination is connected, and make active termination keep connecting in the schedule time with respect to last the ATC signal setting that is received.Storer 500 adopts performed identical process and parameter trip time with its first ATC signal of reception by being provided with, and determines trip time according to last the ATC signal that is received.For example, receiving second and during last ATC signal, timer is reset, and makes active termination continue the turn-on time related with last active termination control signal burst-length afterwards and adds a half clock cycle divided by two.

Figure 11 represents according to theory of the present invention, at an embodiment of the method that is used for active termination control, the sequential chart 1100 to the write operation of storer with CAS stand-by period three and burst-length four.In order to discuss, sequential chart 1100 can be applicable to the system 200 of Fig. 2.1102, the write order on the system command bus 260 is detected by module register 232,252.Because this order is detected by the module register 232,252 of spying upon system command bus 260 effectively, therefore in Figure 11, be expressed as the order edge and connect.1102, WR RO represents the writing of zero level shown the write order of the storer that is used for the first order on the writing module one.Term WR R2 represents the writing of secondary shown the write order to the storer on second module.Therefore, on command line, the controller 220 memory module 250 in the memory module in groove 0 230 and the groove 1 sends and has the write order that two differences write.1104, therefore module register 232 makes the write order on the memory module 230 postpone a clock period through module register the time owing to be timed.1106, module register 252 is with 0 write order sends the ATC signal of the memory module 250 that is used for groove 1 simultaneously from storage register 232 to groove, and module register 232 does not send ATC pulse or signal to memory module 230.

1108, active termination deducts in two clock period in the CAS stand-by period memory module in the groove 1 250 is connected.For the CAS stand-by period that is set to three, the clock period that the memory storage on the memory module 250 of active termination in groove 1 receives after the ATC signal connects.1110, on the DQ line, for 0 grade, the input of the data of module 230 the CAS stand-by period subtract one in beginning, wherein burst-length four is driven by DQS.

1112, show on system command bus 260, producing to the write order of the storer on second module for writing of secondary by controller 220.1114, the module register 252 of memory module 250 is the memory storage regeneration write order on the memory module 250 in the groove 1.

1116, the module register 232 of memory module 230 is that the memory storage on the memory module 230 in the groove 0 produces ATC pulse or signal.1118, owing to the CAS stand-by period is three, so the active termination of the memory module in the groove 0 230 is receiving and write order simultaneously ATC signal afterwards the clock period connection of storage register 252 for the regeneration of the memory storage on the memory module 250 in the groove 1.1120, on the DQ line, subtract for one time in the CAS stand-by period for 2 grades, the input of the data of module 250, wherein burst-length four is driven by DQS.

Active termination on the memory module 250 in the groove 1 burst-length 4 divided by 2 add a half clock cycle the time separated, trip time of about three half clock cycles after connecting is provided.As can see from Figure 11, the active termination on the memory module 250 in the groove 1 writes the data in the memory storage on the memory module in the groove 0 230 fully and brackets.Equally, the active termination on the memory module 230 in the groove 0 writes the data in the memory storage on the memory module in the groove 1 250 fully and brackets.There is a period of time in situation for shown in Figure 11, and wherein active termination on the memory module 230 in the groove 2 and the active termination on the memory module 250 in the groove 1 are all connected.This does not cause any problem because on that time data bus without any data.Effective active termination of system 200 is shown in 1122, and its explanation active termination goes up two approaching write commands sequence for the time and kept effectively.

Because switching on and off on the memory storage in using the different memory module of public DQ bus of active termination takes place, therefore the memory storage on two memory modules need carry out work with identical burst-length for the identical CAS stand-by period.In addition, command line need be shared by two memory modules, because in the supposition command operation is that the generation and the follow-up of active termination of carrying out the ATC signal on the memory module switch on and off under the condition of in related time frame another storer being carried out.

Figure 12 represents according to theory of the present invention, has the sequential chart 1200 of read operation in the storer of CAS stand-by period three and burst-length four at an embodiment of the method for the active termination control that is used for comprising the control of expansion active termination.In order to discuss, sequential chart 1200 can be applicable to the system 200 of Fig. 2.1202, the read command on the system command bus 260 is detected by module register 232,252.RD RO represents the reading of zero level shown the read command of the storer that is used for the first order on the read module one.Term RD R2 represents the reading of secondary shown the read command to the storer on second module.1204, therefore module register 232 makes the read command on the memory module 230 postpone a clock period through register the time owing to be timed.1206, the module register 252 on the memory module 250 sends the ATC signal, and it postpones a clock period than the read command that module register 232 sends for the storer on the memory module 230.The coordination of this timing promotes by the module register 232,252 that all receives common clock signal and all spy upon the public system bus.Module register 232 does not send ATC pulse or signal to memory module 230, will carry out read operation on the memory module in the groove 0 230 to this.

1208, the time that active termination deducts two clock period in the CAS stand-by period connects the memory module in the groove 1 250.For the CAS stand-by period that is set to three, when receiving after the ATC signal clock period, connect by the memory storage of active termination on memory module 250.The storer also burst-length after connecting active termination is added definite trip time in the half clock cycle divided by two.For burst-length four, storer be set to trip time active termination connect after three half clock cycles.1210, on the DQ line, subtract for one time in the CAS stand-by period for 0 grade, the output of the data of module 230, wherein burst-length four is driven by DQS.

But before connecting active termination for the memory storage on the memory module in the groove 1 250, controller 220 sends another read command 1212.1214, the memory storage of clock period on memory module 230 that the module register 232 of the memory module 230 in the groove 0 detects on system command bus 260 after 1212 read commands sends read command.A clock period after module register 232 sends 1214 read commands, 1216, the storer on the memory module 250 in 252 pairs of grooves 1 of the module register on the memory module 250 produces another ATC signal.The storer that receives this 2nd ATC signal on the memory module 250 is determined new active termination turn-on time and new trip time according to the arrival of the 2nd ATC signal.From Figure 12,1218, two the clock period place beginning of new turn-on time after first turn-on time, this is before plan trip time of determining from an ATC signal that is received.Storer will be according to the turn-on time of the 2nd ATC signal replacement active termination that is received, and three half clock cycles place that are set to the new turn-on time of determining trip time.Like this, active termination remains between two read operations of the storer on the memory module 230 in the groove 0.

1220, on the DQ line, be read out for the second reading order of the storer of the memory module in the groove 0 230 for 0 grade, the data of module 230 output response.These data are read out after the data read about first read command immediately.Can see that in Figure 12 reading fully fully of the data of the memory module 230 after two read commands from groove 0 brackets the active termination of the on-state in the memory storage on the memory module 250 in the groove 1.

1222, before the read operation of the storer on the memory module 230 in groove 230 was finished, controller 220 sent the read command of the storer on the memory module 250 in the groove 1.1224, clock period module register 252 detects read command on system command bus 260 after, the memory storage on memory module 250 sends read command.A clock period after storage register 252 sends read command, memory module 232 is that the memory storage on the memory module 230 in the groove 0 produces the ATC signal.After deducting the one-period of two clock period,, connect in the memory storage on the memory module 230 of active termination in groove 0 then 1228 as the CAS stand-by period.1230, on the DQ line, subtract for one time in the CAS stand-by period for 2 grades, the output of the data of module 250, wherein burst-length four is driven by DQS.1232, effective active termination of system on the memory module 230 read and memory module 250 on read all and bracket.The on-state of the active termination of the on-state of the active termination on the memory storage of memory module 230 on the memory storage of short-term and memory module 250 overlaps.In this coincidence period, there are not data on the system data bus.

For all read and write orders, turn-on time is identical with trip time.For CAS stand-by period three and burst-length four, turn-on time is for receiving clock period after the ATC signal, and trip time is then for connecting three half clock cycles after the active termination.If monitor the additional order that reads or writes, make to be arranged in to be determined turn-on time from the previous order disconnection active termination new active termination before that reads or writes, then revise trip time.Certainly, relatively connect and all memories to change of burst-length reprogramming that can be different from for three CAS stand-by period and be different from four trip time by employing.But, as previously described, because the read and write operation is that the memory storage on the memory module is carried out, and active termination is that the memory storage on another storer is carried out, thus the timing of all storeies to require for all storeies that have identical CAS stand-by period and burst-length and receive common clock and be coupled to common bus be identical.

Conclusion

At by the active termination of register on the module, by way of example rather than the mode that limits above structure and method have been described.A kind of method and apparatus is provided, is used for the active termination control of storer, provide the active termination control signal to carry out to storer by module register.The read and write order of module register monitors system command bus.Response detects and reads or writes order, and module register produces the active termination control signal to storer.Storer is connected active termination according to the information in the one or more mode registers that are programmed into storer.In one embodiment, the CAS stand-by period is used for determining turn-on time, and burst-length is used for determining the trip time of active termination after connecting.

As the result of this method, in system, provide the port of termination or the quantity of pin to be reduced.In various embodiments, the pin that is used for active termination control does not need to be located at system controller, mainboard or memory module.

Though this paper has illustrated and described specific embodiment, those skilled in the art can understand, and is suitable for realizing that any scheme of same use can replace described specific embodiment.The application is intended to contain any modification of the present invention or change.Should be appreciated that above description is an illustrative rather than restrictive.By reading above description, those skilled in the art can know combination and other embodiment of above embodiment.Scope of the present invention comprises other any application of adopting said structure and method for making.Scope of the present invention should be determined jointly with reference to the complete equivalent scope that claims and claim contain.

Claims

1. A method for providing proactive termination control comprising:

monitoring the system command bus in a first module register on the first memory module; and

In response to detecting a predetermined command on the system command bus, sending an active termination control signal from the first module register to the first storage device on the first memory module, wherein sending the active termination control signal from the first module register is the same as sending the active termination control signal from the second module register. The second module register on the two memory modules sends the predetermined command to the second storage device on the second memory module at the same time or occurs one clock cycle after the second module register sends the predetermined command to the second storage device.

2. The method of claim 1, wherein an active termination control signal is issued in response to detecting a write command or a read command on the system command bus.

3. The method of claim 2, wherein detecting in the first module register a predetermined command on the system command bus comprises monitoring in the first module register whether a chip select signal or an inverted chip select is received Signal.

4. The method of claim 2, wherein detecting in the first module register the predetermined command monitored on the system command bus comprises monitoring whether two ports of the first module register receive a chip select signal .

5. The method of claim 1, wherein after a write command is detected on the system command bus, sending an active termination control signal is simultaneously with sending the write command from the second module register to the second memory device occur.

6. The method as claimed in claim 5, wherein sending a write command from the second module register to the second memory device is performed in the second memory device one clock cycle after the write command is detected on the system command bus. occurs on the module.

7. The method of claim 1, wherein after a read command is detected on the system command bus, issuing an active termination control signal after sending the read command from the second module register to the second memory device Delayed by one clock cycle.

8. The method of claim 1, wherein issuing the active termination control signal is delayed by one or more clock cycles after the predetermined command is monitored on the system command bus.

9. A module register, comprising:

connection lines for coupling to control lines of memory on the memory module;

a plurality of input command ports coupled to a system command bus to monitor the system command bus;

one or more chip select ports;

The clock port that receives the system clock signal;

a decoding circuit coupled to the plurality of input command ports, the one or more chip select ports, and the clock port, the decoding circuit having a function for receiving commands detected at the plurality of input command ports, receiving One or more chip-select signals monitored at the one or more chip-select ports and logic circuitry receiving the system clock signal from the clock port, the logic circuitry configured to respond to received commands, received issuing an active termination control signal from one or more chip select signals and the system clock signal, the active termination control signal being delayed by one or more clock cycles of the system clock signal; and

coupled to an unsolicited termination control port of the decode circuit for outputting the unsolicited termination control signal, wherein the module register is operable with storage configured on a memory module in response to the Decoding circuitry detects a predetermined command and issues the active termination control signal to the storage device on the memory module, such that the module register is configured to be coupled to the system command bus from the system clock signal according to the system clock signal The active termination control signal is issued at the same time as the predetermined command is issued by another module register of another module register coupled to the system command bus, or one clock cycle after the predetermined command is issued from another module register coupled to the system command bus. .

10. The modular register of claim 9, wherein the decoding circuitry includes logic circuitry arranged to decode write commands and read commands.

11. The module register of claim 10, wherein the decode circuit includes a device configured to cause the output of the active termination control signal to A logic circuit that delays one clock cycle after the command's expected time.

12. The module register of claim 11, wherein the estimated time to issue a read command is one clock cycle after the read command from the system command bus is issued.

13. The module register of claim 10, wherein the decode circuit includes a device configured to issue the active command at the same time as the expected time to issue the write command if the write command from the system command bus is decoded. Logic circuit for terminating control signals.

14. The module register of claim 13, wherein the estimated time to issue a write command is one clock cycle after the write command from the system command bus is issued.

15. The modular register of claim 9, wherein the modular register is placed in an integrated circuit.

16. The module register according to claim 15, wherein the integrated circuit includes a logic circuit disposed in the decoding circuit for decoding write commands and read commands.

17. The module register according to claim 15, wherein the integrated circuit includes a device arranged in the decoding circuit for causing an output of an active termination control signal associated with a read command to be output at an output associated with a write command. A logic circuit that delays one clock cycle after the active termination of the control signal.

18. A memory module comprising:

one or more storage devices; and

a module register coupled to the one or more storage devices, the one or more storage devices being external to the module register, the module register comprising:

a connection line coupled to a control line to the one or more memory devices;

a plurality of input command ports coupled to a system command bus to monitor commands on the system command bus to other module registers;

one or more chip select ports;

The clock port that receives the system clock signal;

coupled to an active termination control port of the decode circuit, the active termination control port coupled to the control lines to the one or more memory devices to provide The one or more storage devices issue the active termination control signal, wherein the module register is configured to issue the predetermined command from one of the other module registers at the same time as the system clock signal. The active termination control signal is issued or the active termination control signal is issued one clock cycle after the predetermined command is issued from one of the other module registers.

19. The memory module of claim 18, wherein the decoding circuitry includes logic circuitry configured to decode write commands and read commands.

20. The memory module of claim 19, wherein the decode circuit includes a device configured to cause the output of the active termination control signal to A logic circuit that delays one clock cycle after the command's expected time.

21. The memory module of claim 19, wherein the decode circuit includes a device configured to issue the active command at the same time as the expected time to issue the write command if the write command from the system command bus is decoded. Logic circuit for terminating control signals.

22. A system with active termination control, the system comprising:

controller;

system command bus;

two or more memory modules coupled to the controller, each memory module including a module register and one or more storage devices external to the module register such that the module registers on the memory modules operatively drive control signals to the same One or more storage devices on a memory module, each module register includes:

connection lines coupled to control lines of the one or more memory devices on the same memory module on which the module registers are mounted;

a plurality of input command ports coupled to the system command bus to monitor commands on the system command bus to other module registers;

one or more chip select ports;

The clock port that receives the system clock signal;

coupled to an unsolicited termination control port of the decode circuit, the unsolicited termination control port coupled to the control lines to the one or more memory devices on the same memory module in response to detecting on the system command bus a predetermined command to issue said active termination control signal to said one or more memory devices on the same memory module, wherein said module register is configured to switch from one of said other module registers according to said system clock signal The active termination control signal is issued at the same time as the predetermined command is issued or issued one clock cycle after the predetermined command is issued from one of the other module registers.

23. The system of claim 22, wherein the decoding circuitry includes logic circuitry configured to decode write commands and read commands.

24. The system of claim 23, wherein the decode circuit includes an output configured to cause the output of the active termination control signal to be issued on a module if a read command from the system command bus is decoded A logic circuit that delays one clock cycle after a read command.

25. The system of claim 23, wherein the decode circuit includes a device configured to issue the active termination concurrently with an on-module write command if a write command from the system command bus is decoded. Logic circuits for control signals.

26. The system of claim 22, wherein the system comprises:

means for determining a set of bits to be sent to and loaded into one or more storage devices on said two or more memory modules;

means for arranging said bits in a predetermined format; and

means for outputting the set of bits, wherein the set of bits includes at least one bit for selecting a single-slot or dual-slot system.

27. The system of claim 26, wherein the at least one bit for selecting a single-slot or dual-slot system is configured to select a single-slot system while programming the memory device to ignore a received unsolicited termination State of the control signal.

28. The system of claim 26, wherein the set of bits includes one or more bits for selecting a plurality of termination values.

29. The system of claim 28, wherein the one or more bits for selecting a plurality of stop values select either a 75 ohm stop value or a 150 ohm stop value.

30. The system of claim 26, wherein the set of bits includes one or more bits for enabling or disabling aggressive termination control.

31. The system of claim 22, comprising means for storing a data structure having fields containing data representative of a single-slot or dual-slot memory system.

32. The system of claim 31, wherein the data representing a single-slot or dual-slot memory system is represented by one bit.

33. The system of claim 31, wherein the data structure includes a field containing data representing a plurality of termination values for one or more of the storage devices.

34. The system of claim 33, wherein the field includes one or more bits for selecting a 75 ohm termination value or a 150 ohm termination value.

35. The system of claim 31 , wherein the data structure includes a field having one or more bits containing an active termination control indicating enabling or disabling of one or more of the storage devices The data.