CN100530952C - An amplifier gain control circuit of wireless transceiver - Google Patents

Abstract

The invention discloses an amplifier gain control circuit of a wireless transceiver, its main structure includes at least one amplifier, an analog-to-digital converter, a digital-to-analog converter and a bias circuit; the analog-to-digital converter is used to receive an analog control Voltage to generate a digital control signal, and control the gain of the amplifier according to the digital control signal; the digital-to-analog converter receives the digital control signal and generates an analog signal; and the bias circuit is used to receive the analog signal and the analog control voltage, and use the analog The method fine-tunes and corrects the amplifier gain to correct the minimum bit error generated by the digital control method, thereby avoiding the operation in the non-linear region when the amplifier gain is adjusted.

Description

The amplifier gain control circuit of wireless transceiver

Technical field

The invention relates to a kind of amplifier gain control circuit of wireless transceiver, adjust amplifier gain, and cooperate the analog form fine setting to revise amplifier gain, operate in the inelastic region in the time of will avoiding amplifier gain to adjust with digital form.

Background technology

See also Fig. 1, be the block schematic diagram of the amplifier gain control circuit of prior art wireless transceiver.As shown in the figure, amplifier gain control circuit 10 includes a bias circuit 11 and casacade multi-amplifier 13/14/15.Wherein first order amplifier 13 is in order to receive an input signal, for example: a radio frequency or analog signal, and respectively input signal is amplified with first order amplifier 13, n-1 level amplifier 14 and n level amplifier 15.Bias circuit 11 connects amplifiers 13/14/15 at different levels respectively, and control the gain of amplifiers 13/14/15 at different levels, for example bias circuit 11 will receive an analog control voltage (VAGC), and produce a plurality of bias voltage signals according to analog control voltage (VAGC), go to control the gain of amplifiers 13/14/15 at different levels again with each bias voltage signal, by this input signal is amplified.

Bias circuit 11 mainly is a gain amplifier of controlling amplifiers 13/14/15 at different levels with simulated mode in the structure of prior art.Yet, when amplifier 13/14/15 utilization analog form is adjusted gain significantly, the intraware of amplifier 13/14/15 will be made, for example: transistor, enter the operating area of inelastic region easily, the requirement that causes the gain amplifier of output signal not reach the linearity, and then wireless transceiver 10 can't operate in preferable operating state.

Summary of the invention

Main purpose of the present invention, be to provide a kind of amplifier gain control circuit of wireless transceiver, mainly gain with the digital form control amplifier, and cooperate the analog form fine setting to revise amplifier gain, revise the minimum bit error that digital form control is produced by this, operate in the inelastic region when avoiding amplifier gain to adjust.

Secondary objective of the present invention is to provide a kind of amplifier gain control circuit of wireless transceiver, can convert an analog control voltage to a digital controlled signal by the setting of analog-digital converter, and with the gain of digital controlled signal control amplifier.

The present invention a purpose, be to provide a kind of amplifier gain control circuit of wireless transceiver, setting by digital analog converter can convert digital controlled signal to one analog signal, and bias circuit can be revised amplifier gain according to analog control voltage that is received and analog signal fine setting, to revise the minimum bit error that digital control approach was produced.

For reaching above-mentioned purpose, the invention provides a kind of amplifier gain control circuit of wireless transceiver, its primary structure includes: at least one amplifier; One analog-digital converter connects amplifier, and in order to receive an analog control voltage, converts analog control voltage to a digital controlled signal, and with the gain of digital controlled signal control amplifier; One digital analog converter connects analog-digital converter, and in order to the reception digital controlled signal, and digital controlled signal is converted to an analog signal; And a bias circuit, connect digital analog converter and amplifier, and receive analog control voltage and analog signal, and with the gain of analog form control amplifier.

Compared with prior art, the amplifier gain control circuit of wireless transceiver provided by the invention is adjusted amplifier gain with digital form, and cooperates the analog form fine setting to revise amplifier gain, operates in the inelastic region in the time of will avoiding amplifier gain to adjust.

Description of drawings

Fig. 1: be the block schematic diagram of the amplifier gain control circuit of prior art wireless transceiver;

Fig. 2: be the block schematic diagram of amplifier gain control circuit one preferred embodiment of wireless transceiver of the present invention;

Fig. 3: be the curve synoptic diagram of analog-digital converter of the present invention;

Fig. 4: be the circuit diagram of the present invention's numeral amplifying unit one preferred embodiment;

Fig. 5: the circuit diagram that is first switch element;

Fig. 6: be the circuit diagram of bias circuit one preferred embodiment of the present invention;

Fig. 7: the circuit diagram of simulating amplifying unit one preferred embodiment for the present invention.

Wherein, Reference numeral is:

10 amplifier gain control circuits, 11 bias circuits

13 first order amplifiers, 14 n-1 level amplifiers

15 n level amplifiers, 100 amplifier gain control circuits

20 analog-digital converters, 30 amplifiers

40 numerals are amplified single 41 current sources

42 first differential units, 421 switch elements

43 second differential units, 431 first load elements

45 the 3rd differential units, 451 second load elements

47 first control units, 471 first switch elements

473 transistors, 475 resistance

479 first resistance, 49 second control units

491 second switch unit, 499 second resistance

50 digital analog converters, 60 bias circuits

61 current sources, 62 first nodes

63 differential units, 64 Section Points

651 first current mirrors, 653 second current mirrors

67 first load units, 69 second load units

70 simulation amplifying units, 71 current sources

73 first differential units, 75 second differential units

751 first load elements 77 the 3rd differential unit

771 second load elements

Embodiment

At first, see also Fig. 2, be the block schematic diagram of amplifier gain control circuit one preferred embodiment of wireless transceiver of the present invention.As shown in the figure, amplifier gain control circuit 100 mainly includes at least one amplifier 30, an analog-digital converter (ADC) 20, a digital analog converter (DAC) 50 and a bias circuit 60.

Analog-digital converter 20 connects amplifier 30, and receives an analog control voltage VAGC, and analog-digital converter 20 can convert analog control voltage VAGC to a digital controlled signal D1, and digital controlled signal D1 can be in order to the gain of digitally-controlled amplifier 30.Digital analog converter 50 connects analog-digital converter 20, and in order to receive the digital controlled signal D1 that analog-digital converter 20 is produced, digital analog converter 50 can be converted into digital controlled signal D1 one analog signal A1.Bias circuit 60 connects digital analog converter 50 and amplifier 30, and in order to receive analog signal A1 and the analog control voltage VAGC that digital analog converter 50 is produced, bias circuit 60 can be finely tuned the gain of revising amplifier 30 according to the difference between analog signal A1 and analog control voltage VAGC by this.

Again, amplifier 30 of the present invention includes a digital amplifying unit 40 and a simulation amplifying unit 70.Numeral amplifying unit 40 connects analog-digital converter 20, and to receive digital controlled signal D1, then digital controlled signal D1 is with the gain amplifier of control figure amplifying unit 40.And simulation amplifying unit 70 connects digital amplifying unit 40 and bias circuit 60, and bias circuit 60 will be revised the gain amplifier of simulation amplifying unit 70 with the analog bias fine setting.

In the above embodiment of the present invention, mainly be the gain that comes the digital amplifying unit 40 of control amplifier 30 with digital controlled signal D1, therefore can avoid when significantly adjusting amplifier 30 gains, causing amplifier 30 to operate in the inelastic region.And last bias circuit 60 carries out the fine gains of analog circuit unit 70 in the mode of analog bias, to revise the minimum bit error that digital control approach was produced, can adjust amplifier 30 gains accurately by this, to avoid commonly using the problem that structure is met with.

In embodiments of the present invention, analog-digital converter 20 is to be example with ten accurate position (level) resolution, and the voltage range of analog control voltage VAGC is set at 1V to 2V, and then the per unit section is set at 0.1V, as shown in Figure 3, certainly when practical application above-mentioned numerical value all can change.

Analog-digital converter 20 of the present invention can be made up of a plurality of comparator, and the per unit section has a corresponding comparator.When analog control voltage VAGC input analog-digital converter 20, the action that each comparator in the analog-digital converter 20 will compare analog control voltage VAGC respectively is by this to obtain digital controlled signal D1.For example: analog control voltage VAGC is 1.63V, then the comparator of the constituent parts section below the 1.6V will obtain 1 result, and the comparator of the constituent parts section more than the 1.7V will obtain 0 result, analog-digital converter 20 can obtain the digital controlled signal D1 of ten accurate positions (1111110000), and the gain that can further directly remove the digital amplifying unit 40 of control amplifier 30 with this digital controlled signal D1 of ten accurate, perhaps in another embodiment of the present invention, digital controlled signal D1 also can be via the decoding of a decoder (decoder), and the gain of control figure amplifying unit 40.

See also Fig. 4 and Fig. 5, be respectively the circuit diagram of the present invention's numeral amplifying unit one preferred embodiment and the circuit diagram of first switch element.As shown in the figure, digital amplifying unit 40 includes a current source 41, one first differential unit 42, one second differential unit 43, one the 3rd differential unit 45, one first control unit 47 and one second control unit 49.Wherein first differential unit 42 connects current source 41, second differential unit 43 and the 3rd differential unit 45 respectively, and in order to receiving an input signal (+/-), and this input signal (+/-) is a differential input signal (+/-).

Second differential unit 43 includes one first load elements, 431, the second differential units 43 and connects first control unit 47 and one first reference voltage Vref 1 respectively, and exports one first output signal (-); The 3rd differential unit 45 includes one second load elements 451, the 3rd differential unit 45 connects second control unit 49 and first reference voltage Vref 1 respectively, and export one second output signal (+), wherein first output signal (-) and second output signal (+) can be a differential output signal (+/-).

First control unit 47 is in order to provide one first control voltage X ₁, and with this first control voltage of second differential unit, 43 receptions X ₁ Second control unit 49 is then in order to provide one second control voltage X ₂, and with this second control voltage of the 3rd differential unit 45 receptions X ₂Wherein, the first control voltage X ₁Reach the second control voltage X ₂Size mainly be decision by digital controlled signal D1, and the first control voltage X ₁Reach the second control voltage X ₂Be input into second differential unit 43 and the 3rd differential unit 45 simultaneously,, produce this differential output signal (+/-) by this, and reach the purpose that gains with digital form control amplifier 30 to control second differential unit 43 and the 3rd differential unit 45 simultaneously.

First control unit 47 includes the connection of one first switch element 471 and one first resistance 479, and first switch element 471 is in order to receiving digital controlled signal D1, and changes the first control voltage X of 479 loads of first resistance according to digital controlled signal D1 ₁ Second control unit 49 then includes the connection of a second switch unit 491 and one second resistance 499, and second switch unit 491 also can receive digital controlled signal D1, and changes the second control voltage X of 499 loads of second resistance according to digital controlled signal D1 ₂

The circuit diagram of first switch element 471, as shown in Figure 5, first switch element 471 includes a plurality of transistors 473 and a plurality of resistance 475, wherein each resistance 475 is one another in series, and each resistance 475 is in parallel with corresponding transistor 473 again, and with transistor 473 reception digital controlled signal D1, for example: 2 ⁿ... 2 ¹2 ⁰

When first switch element 471 receives digital controlled signal D1, the startup that every signal of this digital controlled signal D1 will be controlled each transistor 473 whether, for example: the position 2 of digital controlled signal D1 ⁰If 1, then receive position 2 ⁰Transistor 373 will be activated, otherwise the position 2 ⁰If 0, then receive position 2 ⁰Transistor 373 will be closed.As mentioned above, each transistor 473 of first switch element 471 will carry out the switch start according to digital controlled signal D1, and change the resistance value of first switch element 471, make the electric current that flows through first resistance 479 also can change thereupon, and adjust the first control voltage X by this ₁Can adjust the first control voltage X by digital controlled signal D1 by above-mentioned mode ₁Size, and with the first control voltage X ₁The gain of control figure amplifying unit 40.

The structure of second switch unit 491 is similar to first switch element 471, and both also can select the transistor 473 and the resistance 475 of similar number, and certainly when practical application, both also can select to include the transistor 473 and the resistance 475 of different numbers.

Again, first load elements 431 of the present invention and/or second load elements 451 also can be adjusted for the voltage of load, as variable resistor, variation by load voltage on first load elements 431 and second load elements 451, can make the output signal (-) of winning produce relative change simultaneously, and further adjust the gain of digital amplifying unit 40 with second output signal (+).

In another embodiment of the present invention, first differential unit 42 of numeral amplifying unit 40 still includes at least one switch element 421, the structure of switch element 421 is similar to first switch element 471 shown in Figure 5, and can change the voltage of load by opening or closing of transistor 473.In addition, the transistor 473 of the switch element 421 in the present embodiment and resistance 475 quantity can be identical with first switch element 471, and according to the load on the digital controlled signal D1 control switch unit 421, and reach the purpose of adjusting digital amplifying unit 40 gains.Yet in another embodiment of the present invention, also can make that the transistor 473 of switch element 421 and resistance 475 quantity are different with first switch element 471, the gain of same tunable integers word amplifying unit 40.

See also Fig. 6, be the circuit diagram of bias circuit one preferred embodiment of the present invention.As shown in the figure, bias circuit 60 includes a current source 61, a differential unit 63, one first current mirror 651 and one second current mirror 653.Wherein current source 61 connects differential unit 63, and differential unit 63 is connected with first current mirror 651 and second current mirror 653 respectively.

Differential unit 63 is the electric current I s, one second reference voltage Vref 2 and the analog control voltage VAGC that are provided of received current source 61 respectively, and the electric current I a and the Ib of differential unit 63 outputs will change along with the size of analog control voltage VAGC.First current mirror 651 receives the electric current I a that differential units 63 are produced, and mapping electric current I a and produce one first electric current I ₁653 of second current mirrors receive the current Ib that differential unit 63 is produced, and mapping current Ib and produce one second electric current I ₂And first current mirror 651 connects one first load unit 67 and digital analog converter 50 via a first node 62,653 of second current mirrors connect one second load unit 69 and digital analog converters 50 via a Section Point 64, and first load unit 67 and second load unit 69 will produce the first load current I respectively ₁₁And the second load current I ₂₁

As mentioned above, first electric current I ₁And second electric current I ₂The control of big I by analog control voltage VAGC change size, one first voltage V that is produced on first node 62 and the Section Point 64 like this ₁And one second voltage V ₂Therefore, also can follow certainly and increase or downgrade.

As analog control voltage VAGC during greater than reference voltage VreF2, the first voltage V ₁Will be greater than the second voltage V ₂, first node 62 will have an electric current I ₁₂Flow to digital analog converter 50, and the first load current I ₁₁To change, and make the first voltage V on the first node 62 ₁Therefore down downgrade, will receive an electric current I from digital analog converter 50 with time Section Point 64 ₂₂, and the second load current I ₂₁To change, and make the second voltage V on the Section Point 64 ₂Therefore up increase, downgrade and increase the first voltage V by this ₁And the second voltage V ₂, so that the first voltage V ₁Be equal to the second voltage V ₂

Otherwise if analog control voltage VAGC is during less than reference voltage Vref 2, then first node 62 will receive an electric current I from digital analog converter 50 ₁₂, and Section Point 64 will have an electric current I ₂₂Flow to digital analog converter 50.And, the electric current I that digital analog converter 50 flowed out or flowed into ₁₂And electric current I ₂₂Be to be the identical reverse current of size.

So on first node 62, first current mirror, 651 formed first electric current I ₁Will equal electric current I ₁₂With the first load current I ₁₁Sum total; And on Section Point 64, second current mirror, 653 formed second electric current I ₂Will equal electric current I ₂₂With the second load current I ₂₁Sum total.In other words, the first load current I ₁₁It will be first electric current I ₁With electric current I ₁₂Difference; And the second load current I ₂₁It then can be second electric current I ₂With electric current I ₂₂Difference.

So when analog control voltage VAGC is integer, for example 1.1,1.2,1.3....1.9,2.0 the time, analog control voltage VAGC and digital analog converter (DAC) are if the result that 50 aanalogvoltages of changing out subtract each other zero, for example: when VAGC=1.6V, analog-digital converter (ADC) 20 is output as (1111110000), and also be to be 1.6V via the aanalogvoltage that digital analog converter (DAC) 50 goes back to, this moment, both voltages were all consistent, and do not need with 30 gains of analog form correction amplifier.

Otherwise, the result that the aanalogvoltage that analog control voltage VAGC and digital analog converter (DAC) 50 changed out subtracts each other has a voltage difference, for example: when VAGC=1.61～1.69V, analog-digital converter (ADC) 20 is output as (1111110000), so, the aanalogvoltage that goes back to via digital analog converter (DAC) 50 is 1.6V, therefore the aanalogvoltage changed out of analog control voltage VAGC and digital analog converter (DAC) 50 its both subtracts each other result's voltage difference, to make V1 be adjusted into the same with V2 voltage, then analog control voltage VAGC adjusts the Ia of bias circuit 60 again, the Ib size of current, just can change V1, V2 voltage and further control amplifier 30 gains, therefore between 1.6～1.7V, the result that the aanalogvoltage that analog control voltage VAGC and digital analog converter (DAC) 50 changed out its both subtracts each other, to have 0.1V voltage difference scope, can simulate the scope of amplifying by this voltage difference control amplifier 30 by this.

In embodiments of the present invention, bias circuit 60 is connected with digital analog converter 50, and the electric current I that flows into or flow out by digital analog converter 50 ₁₁/ I ₁₂, increase or downgrade the first voltage V ₁And the second voltage V ₂, and the first voltage V ₁And the second voltage V ₂To equal the difference between analog control voltage VAGC and analog signal A1, this difference be by analog-digital converter 20 when carrying out digital translation, because minimum value position (LSB) error that factor caused.

In addition,, make the described bias circuit 60 of Fig. 6 be connected, yet digital analog converter 50 can be same when practical application, and flow into by this or outflow I with two digital analog converters 50 in embodiments of the present invention in order to increase the convenience of explanation ₁₂/ I ₂₂To bias circuit 60.

Therefore, the analog signal A1 (I that flows into or flow out when digital analog converter 50 ₁₂/ I ₂₂) when being provided in the first node 62 of bias circuit 60 and Section Point 64, analog signal A1 (I ₁₂/ I ₂₂) will with first electric current I ₁And second electric current I ₂Carry out an action of subtracting each other, and make load current I ₁₁, I ₂₁Change.

Certainly, in another embodiment of the present invention, the analog signal A1 that digital analog converter 50 is provided also may be selected to be aanalogvoltage, and by a plus-minus circuit, for example: operational amplifier, and be connected with Section Point 64 with first node 62, the mode that so gets final product working voltage control is finely tuned the first voltage V ₁With the second voltage V ₂

See also Fig. 7, simulate the circuit diagram of amplifying unit one preferred embodiment for the present invention.As shown in the figure, simulation amplifying unit 70 includes a current source 71, one first differential unit 73, one second differential unit 75 and one the 3rd differential unit 77.Wherein this first differential unit 73 connects current source 71, second differential unit 75 and the 3rd differential unit 77, and in order to receive an input signal (+/-), and this input signal (+/-) can be the output signal that produced of digital amplifying unit 40 (+/-), in addition, simulation amplifying unit 70 is connected with the first node 62 (as shown in Figure 6) and the Section Point 64 (as shown in Figure 6) of bias circuit 60 respectively.。

Second differential unit 75 includes one first load elements 751, and second differential unit 75 connects the first node 62 and the Section Point 64 of bias circuit 60 respectively, receives the first voltage V respectively ₁And the second voltage V ₂, and according to the first voltage V ₁And the first voltage V ₂And produce corresponding first output signal (-).

The 3rd differential unit 77 includes one second load elements 771, and the 3rd differential unit 77 connects the first node 62 and the Section Point 64 of bias circuit 60 respectively, receives the first voltage V respectively ₁And the second voltage V ₂, and according to the first voltage V ₁And the first voltage V ₂And produce corresponding second output signal (+), and this first output signal (-) and second output signal (+) can be a differential output signal (+/-).

Therefore, the present invention simulate amplifying unit 70 can be according to the first voltage V ₁And the second voltage V ₂Revise the minimum bit error (LSB) that is caused with digital form control, make amplifier 30 can obtain a gain amplifier accurately by this.

Again, first load elements 751 of the present invention and second load elements 771 also can be adjusted for the voltage of load, as variable resistor, variation by load voltage on first load elements 751 and second load elements 771, can make the output signal (-) of winning produce relative change, and further adjust 70 gains of simulation amplifying unit with second output signal (+).

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims (16)

1. a kind of amplifier gain control circuit of wireless transceiver, is characterized in that, comprises: at least one amplifier; An analog-to-digital converter connected to the amplifier and used to receive an analog control voltage, convert the analog control voltage into a digital control signal, and use the digital control signal to control the gain of the amplifier; a digital-to-analog converter connected to the analog-to-digital converter for receiving the digital control signal and converting the digital control signal into an analog signal; and A bias circuit is connected with the digital-to-analog converter and the amplifier, and receives the analog control voltage and the analog signal, and controls the gain of the amplifier in an analog manner. 2. the amplifier gain control circuit of wireless transceiver according to claim 1, is characterized in that, this amplifier comprises: a digital amplification unit connected to the analog-to-digital converter to receive the digital control signal; and An analog amplifying unit is connected with the bias circuit and the digital amplifying unit. 3. the amplifier gain control circuit of wireless transceiver according to claim 2, is characterized in that, this digital amplifying unit comprises: a current source; a first differential unit connected to the current source and receiving an input signal; A second differential unit, including a first load element, connected to the first differential unit, for receiving a first control voltage and a first reference voltage, and generating a first output signal; and A third differential unit includes a second load element connected to the first differential unit for receiving a second control voltage and the first reference voltage to generate a second output signal. 4. the amplifier gain control circuit of wireless transceiver according to claim 3, is characterized in that, this digital amplifying unit also comprises: a first control unit connected to the second differential unit to provide the first control voltage; and A second control unit is connected to the third differential unit to provide the second control voltage. 5. The amplifier gain control circuit of a wireless transceiver according to claim 4, wherein the first control unit includes a first switch unit and a first resistor, and the second control unit includes a second switch unit and a second resistor. 6. The amplifier gain control circuit of the wireless transceiver according to claim 5, wherein the first switch unit includes a plurality of transistors and a plurality of resistors, and each resistor is connected in series with each other and connected in parallel with the corresponding transistor respectively . 7. The amplifier gain control circuit of a wireless transceiver as claimed in claim 6, wherein the transistor is used for receiving the digital control signal. 8. The amplifier gain control circuit of the wireless transceiver according to claim 5, wherein the second switch unit includes a plurality of transistors and a plurality of resistors, and each resistor is connected in series with each other and connected in parallel with the corresponding transistor respectively . 9. The amplifier gain control circuit of a wireless transceiver as claimed in claim 8, wherein the transistor is used to receive the digital control signal. 10. The amplifier gain control circuit of a wireless transceiver according to claim 3, wherein the first differential unit includes at least one switch unit. 11. The amplifier gain control circuit of a wireless transceiver according to claim 10, wherein the switch unit comprises a plurality of transistors and a plurality of resistors, and each resistor is connected in series with each other and connected in parallel with a corresponding transistor. 12. The amplifier gain control circuit of a wireless transceiver according to claim 11, wherein the transistor is used to receive the digital control signal. 13. The amplifier gain control circuit of the wireless transceiver according to claim 2, wherein the bias circuit comprises: a differential unit, connected to a current source, and used to receive the analog control voltage and a second reference voltage; a first current mirror connected to the differential unit, and a first load unit and the digital-to-analog converter are connected with a first node of the first current mirror; and A second current mirror is connected to the differential unit, and a second node of the second current mirror is connected to a second load unit and the digital-to-analog converter. 14. The amplifier gain control circuit of a wireless transceiver according to claim 13, wherein the digital-to-analog converter comprises at least one current mirror unit. 15. The amplifier gain control circuit of the wireless transceiver according to claim 13, wherein the analog amplifying unit is respectively connected to the first node and the second node of the bias circuit. 16. The amplifier gain control circuit of the wireless transceiver according to claim 15, wherein the analog amplifying unit comprises: a current source; a first differential unit connected to the current source and used to receive an input signal; A second differential unit, including a first load element, connected to the first differential unit, the first node and the second node of the bias circuit; and A third differential unit includes a second load element connected to the first differential unit, the first node and the second node of the bias circuit.

Images