CN100520711C - Memory interface, memory arrangement and method of controlling memory access - Google Patents

Abstract

Disclosed is a kind of memory interface (1), is used for controlling to be divided into a plurality of memory areas (SROM0, ..., SROM5.5, EROM0, ..., EROM7.5, UROM0, ..., UROM3.5 ) program and/or data memory (MEM) access. The memory interface (1) includes: an address calculation device (2), which performs a logical operation on a logical storage address (iadr[0-i]) by using an offset value (OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2), and converts the logical storage address (iadr[0-i]) translates to a physical storage address (phys_adr[0-j]), where the offset value is assigned to a given memory area (SROM0, ..., SROM5.5, EROM0, ..., EROM7.5, UROM0, ..., UROM3.5), and are stored in the volatile offset memory (3). At least one offset value (OFFSET_BOOT) is read from a preset address in the program and/or data memory (MEM).

Description

Memory interface, memory setting and method for controlling memory access

technical field

The invention relates to a memory interface for controlling access to a program and/or data memory divided into a plurality of memory areas, said memory interface comprising address calculation means for Shift values to perform logical operations on logical storage addresses, converting logical storage addresses to physical storage addresses.

The invention also relates to a memory arrangement with a memory interface according to the invention. Finally, the invention also relates to a method of controlling access to a program and/or data memory divided into a plurality of memory areas, wherein the memory interface performs a logical memory The logical operation of the address converts the logical storage address into a physical storage address.

Background technique

Program and data memories having logically and physically distinct areas are well known in the art. Thus, as shown in the left-hand part of Fig. 1, there is a logical division of the program memory MEM in a microcontroller-based integrated circuit (IC), for example developed by the applicant, for a motor vehicle immobilizer realization. Said logical division of the program memory MEM comprises: a system area SROM0, . . . , SROM 5.5, with memory blocks each of 256 bytes; , EROM 7.5 have each a memory block of 256 bytes, and the second user area UROM 0, ..., UROM 3.5 have each a memory block of 256 bytes. As an option, there may also be a test area (not shown). Individual storage locations in the system area and user area are accessed through the logical address iadr[0-12]. Bit iadr[0] to bit iadr[7] are used to access individual storage locations within a given storage block. The memory location is addressed, and bits iadr[8] to iadr[12] are used to select the memory block. In addition, there is a control signal en_sysrom for distinguishing between logical system memory areas SROM 0, ..., SROM 5.5 and logical user memory areas EROM 0, ..., EROM 7.5 and UROM 0, ..., UROM 3.5. When the control signal en_sysrom is 1, the system memory area SROM 0, ..., SROM 5.5 is accessed; when the control signal en_sysrom is 0, the user memory area EROM0, ..., EROM 7.5 and UROM 0, . .. and UROM 3.5 for access. In the illustrated embodiment, the function of the control signal en_sysrom is in principle equivalent to the fourteenth address bit. As can be seen, only that part of the address space that can be accessed by logical addressing is used. Unused memory blocks in the system memory areas SROM 0, ..., SROM 5.5 and in the user memory areas EROM 0, ..., EROM 7.5 and UROM 0, ..., UROM 3.5 are marked with X in Figure 1. In addition, the logical memory areas SROM 0, ..., SROM5.5, EROM 0, ..., EROM 7.5 and UROM 0, ..., UROM 3.5 can be divided in different physical memories, as shown in Figure 1 , which shows two memory modules MEM 1 and MEM 2 in schematic form. The logical system memory areas SROM 0, ..., SROM 5.5 and the second user areas UROM 0, ..., UROM 3.5 are accommodated in the memory module MEM1, while only the first user memory areas EROM 0, ..., EROM 7.5 Located in memory module MEM2. It can be seen that the first memory module MEM1 is completely occupied by the system memory area SROM 0, ..., SROM 5.5 and the second user memory area UROM 0, ..., UROM 3.5, while the second memory module MEM2 is occupied by the first user memory area The memory areas EROM 0, ..., EROM 7.5 are fully occupied and there are no unused physical memory areas. The individual memory modules MEM1 and MEM2 can be chosen from different types of memory, and memory module MEM1 can be in the form of a write-only ROM, while memory module MEM2 can be in the form of a rewritable EEPROM or flash memory.

Due to the logical addressing of the system memory areas SROM 0, ..., SROM 5.5 and the user memory areas EROM 0, ..., EROM 7.5 and UROM 0, ..., UROM 3.5, memory interfaces are required for the The logical addresses iadr[0-12] are mapped to the correct physical addresses for the individual memory modules MEM1, MEM2. In the embodiment shown in FIG. 1, the relationship between the logical and physical addresses in the system memory areas SROM 0, ..., SROM 5.5 and the first user memory areas EROM0, ..., EROM 7.5 is direct. However, for the second user memory areas UROM 0, ..., UROM 3.5, calculation units are required for subtracting the offset from the logical address iadr[0-12] to determine the physical address. In addition, the logical address iadr[0-12] must be assigned to the correct physical memory module MEM1.

A disadvantage that has been found so far is that a separate memory interface has to be designed for each product with a different memory configuration. Therefore, the circuit design must accommodate any changes in the size and/or type of memory. Subsequent changes to the memory area allocation are not possible. In ROM-masking products, only the program can be changed, not the physical size of the memory. Likewise, it is almost impossible to equalize the size of the memory regions. Thus, it may happen that there is memory left unused in one memory area but is required in some other area.

Contents of the invention

It is an object of the present invention to provide a memory interface of the kind specified in the first paragraph above, a memory arrangement of the kind specified in the second paragraph above, and a control memory storage device of the kind specified in the third paragraph above. approach, wherein the disadvantages set forth above are avoided.

To achieve the above object, a memory interface of the kind detailed in the opening paragraph is specified, additionally comprising offset control means for writing offset values to the volatile offset memory, wherein the offset control means It is configured to read at least one offset value from a preset address in the program and/or data memory.

In order to achieve the above objects, a memory arrangement including a memory interface according to the invention is also specified, as well as a program and/or data memory which is divided into a plurality of memory areas and has a stored offset value Preset storage location.

Finally, the method detailed at the beginning is specified, wherein, before address conversion, at least one offset value is read from a preset address in the program and/or data memory, and the offset value is stored in the easy in the volatile offset memory.

What is achieved by the features according to the invention is that it is no longer necessary to change the memory interface itself if a different memory configuration is required for a new product. Only the memory configuration needs to be reprogrammed. This speeds up the design process when creating new products. Therefore, for ROM variants, only the memory needs to be replaced and the configuration reprogrammed by non-volatile writing of new offset values to preset memory locations in program and/or data memory of. No additional design change steps are required. Allocation of memory areas can be changed simply by changing the ROM mask. Therefore, for ROM mask products, the division of memory areas can even be simply reset by new ROM codes at no additional cost. This is especially advantageous when ROM is the only memory used, since no additional memory is required to store the memory configuration. In addition, the hardware-based nature of the sequence of writing offset values to the volatile offset memory by the offset control means provides the advantage that while implementing new system programs (needing more memory space or different memory partitioning), for example At this time, the memory partition can still be changed by software means, but the user is prevented from unauthorized access to the memory.

Advantageously, the offset control device is configured to read the offset value from a preset address in the program and/or data memory when the memory interface is initialized, and write the offset value into the volatile offset Memory; the memory interface is configured to grant access to the program and/or data memory only thereafter. Advantageously, the memory structure can only be used by the program or running program code after the correct offset value has been written into the offset memory. Therefore, prohibited memory accesses can be excluded.

Advantageously also, the address calculation means are configured to receive at least one control signal selecting a memory region and to take this control signal into account when converting a logical memory address into a physical memory address. This offers the advantage that logical memory areas can be configured in a very flexible manner and that logical memory areas can be accessed selectively. For example, separate control lines can be assigned to each logical memory region (system region, user region), and a logical memory region can be selected by selectively applying a signal to one of these control lines while preventing other logic Access to the memory area.

It is also advantageous that the offset control device is configured to write the offset value into the volatile offset memory at runtime of the memory interface, since this makes it possible to reconfigure the memory interface at runtime.

Finally, it is also advantageous that the offset control means comprise an offset control input and an offset configuration input and are configured to read in an offset value from one of the offset configuration inputs depending on the signal at the offset control input, and write it to volatile offset memory. In this way, the memory interface can be reconfigured in a preset manner at runtime. For this purpose, a program-operable offset control input causes the offset control device to read in an offset value via an offset configuration input by programming a non-volatile memory in which the offset value is stored. Access to provide the offset value. Non-volatile memory may include hardwired circuits, mask-programmable locations, and the like.

These and other aspects of the invention are apparent from and will be described with reference to the embodiments described hereinafter, without however limiting the invention.

Description of drawings

In the picture:

Figure 1 shows an example of a memory arrangement with three logical memory regions divided between two physical memory modules.

Figure 2 is a schematic block circuit diagram of a memory arrangement and memory interface according to the present invention.

Detailed ways

FIG. 2 is a block circuit diagram of an embodiment of a memory arrangement and a memory interface 1 according to the invention, by which the logical and physical partitioning of the memory shown in FIG. 1 described above is realized. The memory arrangement comprises a program and/or data memory MEM comprising the two memory modules MEM1 and MEM2 of FIG. form of rewritten EEPROM or flash memory. Individual memory locations in the memory modules MEM1 and MEM2 can be accessed via the physical address bus 9 . Their data (shown as “data”) can be read out via the data bus 11 , and also read in in the case of the rewritable memory module MEM2 . It should be mentioned that for the purposes of the present invention it does not matter whether the logical or physical division of the memory MEM is organized into blocks, or whether the addressing is linear. In the case of a block-organized memory MEM, the size of the memory block is likewise unimportant. As explained in the description of FIG. 1, the program and/or data memory MEM comprises logical system memory areas SROM 0, . . . , SROM 5.5 and two logical User memory areas UROM0, ..., UROM 3.5 and EROM 0, ..., EROM 7.5. The memory interface 1 according to the present invention is used for correct conversion of logical storage address iadr[0-i] to physical storage address phys_adr[0-j].

The memory interface 1 includes address calculation means 2 in the form of hardware. The address calculation means 2 comprises an input of a logical address bus 10 having, in the embodiment shown, 13 address lines consistent with the memory configuration shown in FIG. 1 . Address calculation device 2 also has the input of control line 12, thus is to select logical system memory area SROM 0, ..., SROM 5.5 or logical user memory area UROM 0, ..., UROM 3.5 and EROM 0, ..., Input of the control signal en_sysrom of EROM 7.5. In the embodiment shown, the function of the control line 12 is equivalent to that of the additional address lines, since if the control signal en_sysrom is at a logic 1 level, the system memory regions SROM 0, ..., SROM 5.5 For access, if the control signal en_sysrom is at a logic 0 level, the user memory areas UROM 0, ..., UROM 3.5 and EROM 0, ..., EROM 7.5 are accessed. Individual memory locations are addressed via logical memory addresses iadr[0-i].

However, it should be mentioned that according to the invention there may also be multiple control lines provided (not shown in the figure). In this case, each of these control lines can be used to communicate with a logical memory area SROM 0, ..., SROM 5.5, UROM 0, ..., UROM 3.5, and EROM 0, ..., EROM 7.5 communicates, or a combination of signals on these control lines is used to communicate with logical memory areas SROM 0, ..., SROM 5.5, UROM 0, ..., UROM3.5, and EROM 0, ..., Combination of EROM 7.5 for communication.

Via the logical address bus 10 and the control line 12 , the logical storage addresses iadr[0-i] of the system storage locations and the user storage locations are fed into the address calculation means 2 . In addition, the selection information is transmitted to the address calculation device 2, and the selection information is related to whether the system memory area SROM0, ..., SROM 5.5, or the user memory area UROM 0, ..., UROM 3.5 or EROM0, ..., one of EROM 7.5 is related. In the address calculation means 2, these logical storage addresses iadr[0-i] and selection information are converted into physical storage addresses phys_adr[0-j] of the physical memory modules MEME1 and MEM2. In addition, the address calculation means 2 generates chip selection signals CS1 and CS2, through which individual memory modules MEM1 and MEM2 can be selectively accessed.

The address calculation means 2 converts the logical storage addresses iadr[0-i] received via the logical address bus 10 into physical storage addresses phys_adr[0-j] assigned to the storage locations in the memory modules MEM1 and MEM2. In doing so, the address calculation means performs a logical operation for the logical memory address iadr[0-I] using the preset values OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2. In a preferred simple embodiment, the logical operations include addition and subtraction of the offsets OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 and the logical memory address iadr[0-i]. However, the present invention is not limited to this form of logical operation. By way of example only, when converting to physical storage address phys_adr[0-j], other forms of logical operations will be mentioned, namely the correspondence of multiple offsets OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 with logical storage address iadr[0-i] Addition, and addition or subtraction of the sum of offsets to the logical storage address iadr[0-i], or additional storage address permutation, or additional product of storage block size.

The address output of the address calculation device 2 is connected to the physical address bus 9, and the determined physical storage address phys_adr[0-j] is written into via the physical address bus 9. Instead of one physical address bus 9 and multiple chip select signals CS1, CS2, there may be multiple physical address buses 9 or possible combinations of these.

While in the prior art, the offset value used for logical operation is fixed and stored in the non-volatile memory of the memory interface 1, the memory interface 1 according to the present invention includes a volatile offset memory 3, for example, the The volatile offset memory 3 can take the form of flip-flops or latches and the offset values OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 can be written therein and subsequently read from the offset memory 3 by means of the address calculation means 2 Out, used for logical operation with storage address iadr[0-i]. In this case, the writing of the offset values OFFSET_BOOT, OFFSET_RT1 , OFFSET_RT2 into the offset memory 3 is performed by the offset control means 4 implemented in the form of hardware in the memory interface 1 .

According to the invention, it is proposed that during the initialization of the memory interface 1, the offset control means 4 select from preset memory locations in the program and/or data memory MEM (from the memory module MEM1 in this example, as indicated by arrow 5 ) reads the offset value OFFSET_BOOT and writes the offset value OFFSET_BOOT into the volatile offset memory 3, thus causing the memory interface 1 to boot with the correct offset value OFFSET_BOOT. It should be mentioned that it is useful to write an offset value OFFSET_BOOT into a memory module MEM1 segmented into a plurality of memory areas, wherein preferably a specific offset configuration for said memory module MEM1 is stored in the memory module MEM1. In addition, it is proposed to disable the address calculation means 2 by means of the offset control means 4 until the writing of the offset values OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 to the volatile offset memory 3 has been completed, and only then to authorize access to the program and/or Access to the data memory MEM is symbolically indicated by the enable signal en_ad. By initialization of the memory interface 1 performed by the hardware means, the correct segmentation of the program and/or data memory MEM is set before any code from said memory can be executed.

Due to this provision according to the invention, no modification of the memory interface 1 itself is required if a modified program and/or data memory configuration is to be used. Instead, the configuration must be reprogrammed in an easy manner by writing the modified offset value OFFSET_BOOT into the new program and/or data memory MEM to be used. This is the process that speeds up the design process when creating a new product. Therefore, the allocation of memory areas can be changed simply by changing the ROM mask. Thus, in the case of a ROM-mask, the memory areas SROM 0, ..., SROM 5.5, EROM0, ..., EROM 7.5, UROM 0, ..., the division of UROM 3.5.

In another very flexible embodiment of the memory interface 1 according to the invention, the offset control means 4 are configured to write the offset values OFFSET_RT1, OFFSET_RT2 to the volatile offset memory 3 at runtime of the memory interface 1 , thus enabling memory segmentation to be changed by software means. For this purpose, the offset control device 4 has an offset control input 6 and two offset configuration inputs 7 , 8 . Depending on the software control signal at the offset control input 6, the offset control device 4 reads in the offset value OFFSET_RT1 (via the offset configuration input 7) or OFFSET_RT2 (via the offset configuration input 8) and writes these offset values to into volatile offset memory 3. In this way, memory segmentation can be changed at runtime. The offset configuration inputs 7, 8 obtain the offset values OFFSET_RT1, OFFSET_RT2 by accessing a non-volatile memory (not shown) in which the offset values OFFSET_RT1, OFFSET_RT2 are stored, the non-volatile memory comprising hardwired circuits, mask-programmable cells, etc.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The term "comprising" and the like does not exclude the presence of elements or steps other than those listed in any claim or the description generally. Singular reference signs of an element do not exclude plural reference signs of such elements and vice versa. In a device claim enumerating several means, several of these means can be embodied by one and the same item of hardware or software. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims (8)

1. a memory interface (1) is used to control to the program that is divided into a plurality of memory areas and/or the access of data-carrier store (MEM), and described memory interface comprises:

-address calculating device (2), be used for by utilizing off-set value to carry out logical operation at logical storage address (iadr0-i), logical storage address (iadr0-i) is converted to physical storage address (phys_adr0-j), wherein, described off-set value is stored in the volatibility offset memories (3), and is assigned to given memory areas; And

-skew control device (4) is used for writing off-set value to volatibility offset memories (3), and described skew control device (4) configuration is used for reading at least one off-set value from the default address of program and/or data-carrier store (MEM),

Wherein, described skew control device configuration is used for when the initialization of described memory interface (1), read in off-set value in the default address from program and/or data-carrier store (MEM), and described off-set value is write described volatibility offset memories (3), and described memory interface (1) configuration only is used for after the reading in and write of described off-set value allowance to the access of program and/or data-carrier store (MEM).

2. memory interface according to claim 1 (1), wherein, described address calculating device (2) configuration is used to receive at least one control signal (en_sysrom) that memory areas is selected, and considers described control signal when logical storage address (iadr0-i) is converted to physical storage address (phys_adr0-j).

3. memory interface according to claim 1 (1), wherein, described skew control device (4) configuration was used in the working time of memory interface (1), and off-set value is write in the volatibility offset memories (3).

4. memory interface according to claim 3 (1), wherein, described skew control device (4) comprises skew control input (6) and offset configuration input (7,8), and configuration is used for according to importing the signal that (6) are located in skew control, from one of offset configuration input (7,8), read in off-set value, and described off-set value is write in the volatibility offset memories (3).

5. memory devices, comprise according to each described memory interface (1) of claim 1 to 4 and program and/or data-carrier store (MEM), described program and/or data-carrier store are divided into a plurality of memory areas, and have the default memory location of having stored off-set value.

6. a control is to the method for the access of the program that is divided into a plurality of memory areas and/or data-carrier store (MEM), and memory interface (1) is carried out following steps:

Read at least one off-set value in-the default address from program and/or data-carrier store (MEM);

-described at least one off-set value is stored in the volatibility offset memories (3); And

-carry out logical operation by utilizing off-set value at logical storage address (iadr0-i), logical storage address (iadr0-i) is converted to physical storage address (phys_adr0-j), wherein, described off-set value is assigned to given memory areas, and be stored in the volatibility offset memories (3), wherein

When the initialization of memory interface (1) reading in and storing of described off-set value taking place, and only permits the access to program and/or data-carrier store (MEM) after the reading in and store of described off-set value.

7. at least one control signal (en_sysrom) in selection memory district is estimated and considered to be used for to method according to claim 6 wherein, when logical storage address (iadr0-i) is converted to physical storage address (phys_adr0-j).

8. method according to claim 6 wherein, writes volatibility offset memories (3) in the working time of memory interface (1) with off-set value.

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