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CN100502005C - 半导体器件的阱区 - Google Patents

半导体器件的阱区 Download PDF

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CN100502005C
CN100502005C CNB2003801080465A CN200380108046A CN100502005C CN 100502005 C CN100502005 C CN 100502005C CN B2003801080465 A CNB2003801080465 A CN B2003801080465A CN 200380108046 A CN200380108046 A CN 200380108046A CN 100502005 C CN100502005 C CN 100502005C
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CN1732571A (zh
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詹姆斯·B·伯尔
迈克·飞尔汗
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    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
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    • H10D89/213—Design considerations for internal polarisation in field-effect devices
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Abstract

本发明提供对角深阱区以用于在表面阱区里发送体偏置电压给金属氧化物半导体场效应晶体管(MOSFET)。

Description

半导体器件的阱区
技术领域
本发明关于一种金属氧化物半导体场效应晶体管(MOSFET)，尤其关于发送体偏置电压到MOSFET的领域。本发明部分揭露用于在表面阱区发送体偏置电压给MOSFET的对角深阱区。
背景技术
具有形成于半导体基板上的MOSFET的半导体器件的物理布局图的产生是一项挑战性的任务。在创造该物理布局图中消耗了大量的时间与资源。然而，如果新物理布局图使用现有物理布局图的实质部分，资源的消耗可最小化，例如，如果根据新物理设计的需要利用与改良具有没有体偏置的MOSFET的现有物理布局图，具有体偏置的MOSFET的新物理布局图可以较少的费用来实现。不幸的是，改良现有物理布局图的工艺典型地要求形成一额外的体偏置电压发送层于半导体器件的表面上，既然现有物理布局图使用绝大部分(如果不是全部)可利用的表面面积，这会产生严重的问题。
发明内容
本发明提供对角深阱区以用于在表面阱区里发送体偏置电压给金属氧化物半导体场效应晶体管(MOSFET)。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而所附图式仅提供参考与说明用，并非用来对本发明加以限制。
图1为本发明一实施例的形成在N阱上的pFET的俯视图，其绘示pFET具有施加于其本体B端子的体偏置电压Vnw；
图2绘示本发明一实施例相对定位一N阱与一对角深N阱区于一半导体器件表面之下；
图3A为本发明一实施例的多个N阱与一对角深N阱(DDNW)区的俯视图；
图3B是本发明一实施例的图3A沿箭头399的侧视图；
图4是本发明一实施例的多个N阱与形成网状构造的多个对角深N阱(DDNW)区的俯视图；
图5绘示本发明一实施例具有多个N阱与多个对角深N阱(DDNW)区形成网状构造的物理布局图。
具体实施方式
将对本发明的较佳实施例详细使用标号，其例子如下附附图所示，虽然本发明通过这些实施例进行描述，但是，可以理解的是，这些实施例不是用于限制本发明于这些实施例，相反，本发明可涵盖使用了本发明的构思且落入后附权利要求界定的本发明范围内的选择性的、变更的、与等同的实施例。而且，本发明下述详细描述中，很多特定细节的描述是为了彻底理解本发明，然而，本领域普通技术人员可意识到本发明没有这些特定的细节也可实施。
尽管本发明的下面描述将会集中在发送体偏置电压给pFET(或P型MOSFET)，其在使用P型基板与N阱工艺时经由一N型掺杂的传导次表面区设置在表面N阱上，本发明一样可应用于发送体偏置电压给nFET(或N型MOSFET)，其在使用N型基板与P阱工艺时经由一P型掺杂的传导次表面区设置在表面P阱上。
图1为本发明一实施例在使用P型基板与N阱工艺时设置在N阱10里的pFET 50(或P型MOSFET)的俯视图，该pFET 50具有施加于其本体B端子的体偏置电压Vnw。如图1所示，该pFET 50具有栅极G、漏极D(P型掺杂)、源极S(P型掺杂)及本体B端子。特别是，该本体B端子与N阱10耦合。该N阱具有N型掺杂。掺杂有N型掺杂剂的半导体器件区具有一种传导性，而掺杂有P型掺杂剂的半导体器件区具有另一种传导性。典型的是，在不同的半导体器件区使用不同的掺杂剂浓度。
该pFET 50体偏置以影响其性能。在没有体偏置时，源极S与本体B端子耦合在一起，而具有体偏置时，源极S与本体B端子没耦合在一起。如果具有电力调节pFET 50的门槛电压水平，体偏置能控制pFET 50的源极S与本体B端子之间的势差。
在体偏置的情况下，本体B端子接收体偏置电压Vnw。如上所述，本体B端子与N阱10连接，这样，体偏置电压Vnw施加到N阱10上。
改良现有的物理布局图，胜于产生全新的半导体器件物理布局图以支持具有体偏置电压Vnw的pFET 50，特别是，可通过使用一对角深N阱区来发送体偏置电压Vnw到N阱10而来改良现有的物理布局图，该对角深N阱可作为在N阱下面的传导次表面阱层，这可避免需要在没有很多自由表面积供额外发送的半导体器件表面上设置另一表面发送层。
特别是，与表面金属层成对比，该体偏置电压Vnw经由一个或多个对角深N阱区(其为传导次表面阱层)发送到N阱。这种方式的优点是，典型的在半导体器件的浓密充满的表面积上没有空间供额外的金属发送层的时候，由于穿过阱的发送信号通常被阱的低录放幅频响应与潜在高电阻所阻碍的事实，在半导体器件表面下的面积经常未充分使用。在本发明，胜于传输信号，对角深N阱区用于保持与配送体偏置电压Vnw。
图2绘示本发明一实施例相对定位一N阱10(也称为表面N阱)与一对角深N阱区20于一半导体器件表面70的下面。该N阱10形成于半导体器件表面70的下面且具有N型掺杂，该对角深N阱区20形成于N阱10的下面，这样，对角深N阱区20与N阱10共享一次表面传导边界25，其允许对角深N阱区20具有类似于一传导次表面发送层的功能以发送体偏置电压Vnw到N阱，即，对角深N阱区20沿次表面传导边界25接触N阱。而且，对角深N阱区20埋在半导体器件表面70的下面。该对角深N阱区20具有N型掺杂。可以理解的是，如果使用N型基板与P阱工艺，将利用P型掺杂的对角深阱具有象一传导次表面发送层的功能以发送体偏置电压到表面P阱。
该次表面传导边界25的规格与尺寸决定了N阱10与对角深N阱区20的传导路径的电阻，当次表面传导边界25的尺寸增加，N阱10与对角深N阱区20的次表面传导路径的电阻降低以形成一低电阻传导路径。
如图3A所示，其为本发明一实施例的多个N阱(如N阱1与N阱2)与一对角深N阱(DDNW)区310的俯视图。胜于为一连续平面层，该DDNW区310为一图案化层。如图3A所示，该对角深N阱区310为一条状，且位于半导体器件的N阱1与N阱2下方。该对角深N阱区310、N阱1与N阱2具有N型掺杂。而且，该对角深N阱区310的方位相对于该N阱1与N阱2在其对角线上或倾斜的。在一实施例中，该对角深N阱区310与N阱(如N阱1或N阱2)形成一个大约45度角。
可以理解的是，该对角深N阱区310可具有其它配置，且多个对角深N阱区可图案化成不同的排列。例如，另外的对角深N阱区可定位与该对角深N阱区310平行且在间隔远离该对角深N阱区310的位置上。通过转动对角深N阱区310的方位大约90度，也可形成该对角深N阱区310的转动版，而且该对角深N阱区310与其转动版可排列成X图案(或十字形图案)于N阱1与N阱2之下。
该对角深N阱区310发送体偏置电压Vnw到N阱1与N阱2，因此该pFET 370可被体偏置。这样，用于该体偏置电压Vnw的端子可形成于有自由表面积的地方，例如在N阱1、N阱2或对角深N阱区310之上。另外，通过防止形成nFET 380于其上的P型区或P阱区385的隔离，对角深N阱区310使nFET(N型MOSFET)380能以任何方式被体偏置。这样，该对角深N阱区310允许在P阱区385与形成于对角深N阱区310之下的次表面层之间形成传导路径。而且，该对角深N阱区310的位置与尺寸基于该N阱与P型区或P阱的分布状态，目标是提供低电阻传导路径。然而，该对角深N阱区310的规格与尺寸应避免将P型区或P阱与形成于对角深N阱区310之下的次表面层隔离。
图3B是本发明一实施例的图3A沿箭头399的侧视图，如图3B所示，在N阱1与该对角深N阱区310之间形成第一次表面传导边界396，而且，于N阱2与该对角深N阱区310之间形成第二次表面传导边界397。该体偏置电压Vnw经由该第一与第二表面传导边界396、397发送到N阱1与N阱2。
图4是本发明一实施例的多个N阱(如N阱1与N阱2)与形成网状构造的多个对角深N阱(DDNW)区的俯视图。于此，对角深N阱区410A、410B与对角深N阱区412A、412B、412C直交，因此，对角深N阱区410A、410B、412A、412B、412C形成次表面网状构造以发送体偏置电压Vnw到N阱1与N阱2，这样，该pFET 470可被体偏置。
相对于N阱1与N阱2的方位，网状构造490处于对角线上，在一实施例中，该网状构造490相对于N阱(如N阱1与N阱2)转动大约45度。每一对角深N阱区412A、412B、412C、410A、410B呈条状，具有N型掺杂，且位于半导体器件的N阱1与N阱2之下。可以理解的是，网状构造490也可具有其它配置，例如，相邻对角深N阱区之间的间隙440A、440B可在尺寸上进行变化，而且对角深N阱区与间隙面积430的比例可以变化。
另外，通过防止形成nFET 480于其上的P型区或P阱区485的隔离，网状构造490使nFET(N型MOSFET)480能以任何方式被体偏置。在对角深N阱区之间的区495防止P阱区485的隔离，使P阱区485与形成于对角深N阱区412A、412B、412C、410A、410B之下的次表面层之间能形成一传导路径。在一实施例中，该网状构造的面积可在对角深N阱区与间隙面积430之间被等分。
如上所述，用于该体偏置电压Vnw的端子可形成于有自由空间的地方，例如在N阱1、N阱2或对角深N阱区412A、412B、412C、410A、410B之上。而且，该网状构造490的位置与尺寸基于该N阱与P型区或P阱的分布状态，目标是提供低电阻传导路径。
然而，该网状构造490的尺寸应避免将P型区或P阱485与形成于对角深N阱区之下的次表面层隔离。而且间隙面积430的尺寸设置可提供在P型区或P阱485与形成于对角深N阱区之下的次表面层之间的低电阻传导路径，间隙面积430越大，传导路径的电阻越小。另外，径向扩散与径向损耗能进一步减小间隙面积430，潜在地掐掉该在P型区或P阱485与形成于对角深N阱区之下的次表面层之间的传导路径。作为对这种情况的解决方案，在相邻对角深N阱区之间的间隙440A、440B做得足够宽以避免掐掉该在P型区或P阱485与形成于对角深N阱区之下的次表面层之间的传导路径。然而，随着对角深N阱区的数量与尺寸的提升，由于在N阱区与对角深N阱区之间有更大与更多次表面传导边界，发送体偏置电压Vnw的传导路径的电阻降低。因此，在每种设计情形，在间隙面积430与对角深N阱区之间存在一种平衡。
图5绘示本发明一实施例具有多个N阱与形成网状构造的多个对角深N阱(DDNW)区510的物理布局图。如上所述，该多个对角深N阱(DDNW)区510形成次表面网状构造，其可发送体偏置电压Vnw到N阱570，且没有将P型区或P阱580与形成于对角深N阱区510之下的次表面层隔离。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。

Claims (29)

1.一种半导体器件，其具有一表面，其特征在于，包括：
一第一传导性的第一阱区，其设置在该表面之下；
一第一传导性的第二阱区，其设置在该表面之下；及
数个第一传导性的传导次表面区，其分别设置在该第一与第二阱区之下，其中该数个传导次表面区排列成次表面网状构造，且其中该次表面网状构造相对于第一与第二阱区对角定位以使在第一阱区与次表面网状结构之间形成数个第一传导边界及在第二阱区与次表面网状结构之间形成数个第二传导边界，以在第一与第二阱区之间形成数个次表面传导路径。
2.如权利要求1所述的半导体器件，其特征在于，每一传导次表面区具有N型掺杂。
3.如权利要求2所述的半导体器件，其特征在于，该第一与第二阱区具有N型掺杂。
4.如权利要求3所述的半导体器件，其特征在于，该第一阱区包括一P型金属氧化物半导体场效应晶体管，其中该第二阱区包括一P型金属氧化物半导体场效应晶体管。
5.如权利要求1所述的半导体器件，其特征在于，每一传导次表面区具有P型掺杂。
6.如权利要求5所述的半导体器件，其特征在于，该第一与第二阱区具有P型掺杂。
7.如权利要求6所述的半导体器件，其特征在于，该第一阱区包括一N型金属氧化物半导体场效应晶体管，其中该第二阱区包括一N型金属氧化物半导体场效应晶体管。
8.如权利要求1所述的半导体器件，其特征在于，每一传导次表面区呈条形。
9.如权利要求1所述的半导体器件，其特征在于，该次表面网状构造发送体偏置电压给第一与第二阱区。
10.如权利要求1所述的半导体器件，其特征在于，该次表面网状构造相对于第一阱区转动45度。
11.如权利要求1所述的半导体器件，其特征在于，该次表面网状构造相对于第二阱区转动45度。
12.如权利要求1所述的半导体器件，其特征在于，该次表面网状构造的面积包括所述第一传导性的所述传导次表面区的面积和在相邻平行的所述第一传导性的传导次表面区之间的间隙的面积，并且所述第一传导性的所述传导次表面区的面积与所述间隙的面积彼此相等。
13.如权利要求1所述的半导体器件，其特征在于，进一步包括一第二传导性的第二次表面层，其设置在该次表面网状构造之下，其中相邻平行的第一传导性的传导次表面区之间的间隙设置足够宽以避免掐掉在该半导体器件的所述表面与该第二次表面层之间的传导路径。
14.一种半导体器件，其具有一表面，其特征在于，包括：
一第一传导性的第一阱区，其设置在该表面之下；
一第一传导性的第二阱区，其设置在该表面之下；及
一第一传导性的传导次表面区，其设置在该第一与第二阱区之下，其中该传导次表面区相对于第一与第二阱区对角定位以使在第一阱区与传导次表面区之间形成一第一传导边界及在第二阱区与传导次表面区之间形成一第二传导边界，以在第一与第二阱区之间形成一次表面传导路径。
15.如权利要求14所述的半导体器件，其特征在于，该传导次表面区具有N型掺杂，该第一与第二阱区具有N型掺杂，该器件进一步包括一第一传导性的第二传导次表面区，其设置在第一与第二阱区之下，其中第二传导次表面区与该传导次表面区平行。
16.如权利要求14所述的半导体器件，其特征在于，还包括：
一第二传导性区，其设置在该表面之下，其中：
所述第一传导性的传导次表面区设置在该第一与第二阱区之下，并且还设置该第二传导性区之下，其中相对于第一与第二阱区对角定位的该传导次表面区还相对于该第二传导性区对角定位以使在第一阱区与传导次表面区之间形成的第一传导边界及在第二阱区与传导次表面区之间形成的第二传导边界在第一与第二阱区之间形成一次表面传导路径，且没有隔离该第二传导性区。
17.如权利要求14或16所述的半导体器件，其特征在于，该传导次表面区具有N型掺杂。
18.如权利要求17所述的半导体器件，其特征在于，该第一与第二阱区具有N型掺杂。
19.如权利要求18所述的半导体器件，其特征在于，该第一阱区包括一P型金属氧化物半导体场效应晶体管，其中该第二阱区包括一P型金属氧化物半导体场效应晶体管。
20.如权利要求16所述的半导体器件，其特征在于，
该传导次表面区具有N型掺杂，
该第一阱区具有N型掺杂，
该第二阱区具有N型掺杂，
该第一阱区包括一P型金属氧化物半导体场效应晶体管，
该第二阱区包括一P型金属氧化物半导体场效应晶体管，
该第二传导性区具有P型掺杂，且
该第二传导性区包括一N型金属氧化物半导体场效应晶体管。
21.如权利要求14或16所述的半导体器件，其特征在于，该传导次表面区具有P型掺杂。
22，如权利要求21所述的半导体器件，其特征在于，该第一与第二阱区具有P型掺杂。
23.如权利要求22所述的半导体器件，其特征在于，该第一阱区包括一N型金属氧化物半导体场效应晶体管，其中该第二阱区包括一N型金属氧化物半导体场效应晶体管。
24.如权利要求16所述的半导体器件，其特征在于，
该传导次表面区具有P型掺杂，
该第一阱区具有P型掺杂，
该第二阱区具有P型掺杂，
该第一阱区包括一N型金属氧化物半导体场效应晶体管，
该第二阱区包括一N型金属氧化物半导体场效应晶体管，
该第二传导性区具有N型掺杂，且
该第二传导性区包括一P型金属氧化物半导体场效应晶体管。
25.如权利要求14或16所述的半导体器件，其特征在于，该传导次表面区呈条形。
26.如权利要求14或16所述的半导体器件，其特征在于，该传导次表面区发送体偏置电压给第一与第二阱区。
27.如权利要求14或16所述的半导体器件，其特征在于，该传导次表面区与第一阱区形成一45度角。
28.如权利要求14或16所述的半导体器件，其特征在于，该传导次表面区与第二阱区形成一45度角。
29.如权利要求16所述的半导体器件，其特征在于，该传导次表面区与第二传导性区形成一45度角。
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AU2003300399A1 (en) 2004-07-29
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US20040124475A1 (en) 2004-07-01
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US7863688B2 (en) 2011-01-04
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US6936898B2 (en) 2005-08-30
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US8415730B2 (en) 2013-04-09
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