CN100506686C - Method for manufacturing piezoresistance type micro-cantilever beam sensor on SOI silicon sheet - Google Patents

Abstract

The invention discloses a method for manufacturing a piezoresistive micro-cantilever beam sensor on an SOI silicon wafer, which belongs to the scope of micro-processing technology and micro-detection devices. It is characterized in that: the sensor is prepared by SOI (silicon on insulator) silicon wafer, that is, a single crystal silicon piezoresistive sensitive device is prepared in the upper silicon of the SOI silicon wafer, and the lateral dry etching process of silicon is used to release it from the front The micro-cantilever makes it suspended in the air. The invention adopts SOI silicon wafers and uses an isotropic dry etching process to release the micro-cantilever beam structure from the front, the manufacturing process is simple and easy, and the yield is high; the piezoresistive sensitive device of single crystal silicon material is prepared from the upper silicon layer of SOI silicon wafers , The piezoresistive coefficient is large, which can significantly improve the sensitivity of the sensor.

Description

Method for fabricating piezoresistive micro-cantilever sensor on SOI silicon wafer

technical field

The invention belongs to the scope of micro-processing technology and micro-detection devices, in particular to a method for manufacturing piezoresistive micro-cantilever beam sensors on SOI silicon wafers using micro-processing technology.

Background technique

In recent years, micro-mechanical sensors based on micro-cantilever structures have become a research hotspot of widespread concern. This type of sensor has the advantages of miniaturization, low cost, high sensitivity and mass production, and has broad application prospects in the fields of physical, chemical and biological sensing. The basic working principle of this type of sensor is to convert parameters such as mass, electric field, magnetic field, temperature and stress into the bending or resonance frequency of the micro-cantilever beam, so as to realize the combination of microscopic surface morphology, magnetic field, acceleration, chemical molecules, Detection of biomolecular binding and other signals.

The method of measuring the bending and resonance frequency of the microcantilever is called the readout method. Commonly used readout methods are optical and electrical methods. Optical readout has high sensitivity, but the system is complex, difficult to operate and difficult to integrate, while electrical methods such as piezoresistive, capacitive, and piezoelectric readout have relatively low sensitivity, but have the advantages of simple operation and easy integration. Among the electrical readout methods, the piezoresistive readout method is most widely used because of its ease of implementation.

The basic principle of piezoresistive readout is: the piezoresistive sensitive device is fabricated on the micro-cantilever beam. When the micro-cantilever beam bends under the action of external physical quantities, the electrical characteristics of the piezoresistive sensitive device will change due to the piezoresistive effect of silicon. Corresponding changes will occur, such as the resistance value of the piezoresistor will change, and the source-drain current of the MOSFET will change; by measuring the resistance value or the change of the source-drain current, the measurement of the bending amount of the micro-cantilever beam can be realized, so as to realize the Sensing effect of external physical quantity. In order to improve the sensitivity of the piezoresistive readout method, the key is to increase the piezoresistive coefficient of the piezoresistive material.

The release of the microcantilever structure, that is, the formation of the suspended structure, is a critical step in the fabrication process. The existing release process is relatively complicated, and it is necessary to protect the front side of the silicon wafer and release the structure from the back side, resulting in poor release effect and low yield.

Contents of the invention

The object of the present invention is to provide a kind of method that adopts micromachining technology to manufacture piezoresistive micro-cantilever beam sensor on SOI silicon chip, it is characterized in that, comprises the following steps by manufacturing sequence:

1) Use SOI silicon chip as the substrate material for the sensor, the SOI silicon chip is composed of the lower silicon substrate, the original oxide layer and the upper silicon;

2) Perform photolithography on the SOI silicon wafer, form a varistor as a sensitive device in the upper silicon of the SOI silicon wafer by ion implantation, and connect the varistor to the SOI silicon wafer by using a reverse bias P-N junction. The upper silicon insulation of the silicon wafer; or make MOSFET (metal-oxide-semiconductor field-effect transistor) in the upper silicon of the SOI silicon wafer by using an integrated circuit manufacturing process as a sensitive device;

3) Deposit silicon dioxide as an insulating layer, sputter metal on the surface of the silicon wafer, form the metal wiring of the sensitive device through photolithography and etching, and deposit silicon oxide as a passivation layer;

4) Perform photolithography on the silicon wafer, and sequentially etch the surface to form a micro-cantilever pattern, exposing the surface of the lower silicon substrate of the SOI silicon wafer;

5) Using an isotropic reactive ion etching process to laterally etch the underlying silicon substrate exposing the SOI silicon wafer in step 4), releasing the microstructure from the front of the silicon wafer to make it suspended, that is, forming the micro-cantilever beam.

The upper silicon is 100, 111 or 110 crystal orientation;

Said MOSFET is N type, P type, silicon gate or aluminum gate type.

The present invention has the following advantages due to the adoption of the above technical scheme:

1. In the existing method of piezoresistive micro-cantilever beam sensors made of ordinary silicon wafers, the piezoresistor is a polysilicon material, and its piezoresistive coefficient is relatively low. The invention adopts an integrated circuit manufacturing process, and the piezoresistor or MOSFET prepared in the upper silicon layer of the SOI silicon wafer is a monocrystalline silicon material, and its piezoresistive coefficient is far greater than that of polycrystalline silicon material, which can significantly improve the sensitivity of the sensor.

2. The isotropic reactive ion etching process is used to release the micro-cantilever beam from the front of the silicon wafer. The process is simple and easy, and the yield is high, which effectively avoids the front protection during the release process from the back of the silicon wafer by the commonly used KOH wet etching process. And the problem of microcantilever and substrate adhesion.

Description of drawings

Figure 1 (a)-(g) is a schematic diagram of the process flow of the embodiment of the present invention using piezoresistors as sensitive devices.

FIG. 2 is a schematic structural diagram of a micro-cantilever beam sensor using a silicon gate MOSFET as a sensitive device according to the present invention.

Detailed ways

The invention provides a piezoresistive micro-cantilever beam sensor method manufactured on SOI silicon wafers by adopting micro-machining technology, which is simple and feasible, and has high yield rate. The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments, but is not limited to the embodiments.

Fig. 1 shows that the present invention adopts piezoresistor as the schematic diagram of the embodiment of the microcantilever beam sensor of sensitive device, comprises the following steps according to the manufacturing sequence:

1) adopt SOI silicon chip as the substrate material of preparing described micro-cantilever beam sensor, SOI silicon chip is made of lower layer silicon substrate 11, original oxide layer 12 and upper layer silicon 13 (as shown in Figure 1a), wherein upper layer silicon 13 Can be 100, 111 or 110 crystal orientation;

2) Perform photolithography on the SOI silicon wafer to form a varistor pattern; use ion implantation technology to implant impurity ions opposite to the doping type of the upper silicon 13 into the upper silicon 13 of the SOI silicon wafer to form a sensitive The varistor 2 of the device (as shown in Figure 1b) uses a reverse-biased P-N junction to insulate the varistor 2 from the upper silicon 13 of the SOI silicon wafer; that is, if the doping type of the upper silicon 13 is N-type, inject P-type Impurities; if the doping type of the upper silicon 13 is P-type, inject N-type impurities;

3) Forming silicon oxide on the surface of the SOI silicon wafer by using a plasma-enhanced chemical vapor deposition process as an electrical insulating layer 3 between the metal wiring and the upper layer of silicon 13 (as shown in Figure 1c); then photolithography , etch on the surface of the electrical insulating layer 3 of the silicon wafer to form a metal connection contact hole, and then form aluminum metal on the surface of the electrical insulating layer 3 of the silicon wafer by a sputtering process, and form the aluminum metal connection 4 through photolithography and etching (as shown in FIG. 1d); adopt plasma enhanced chemical vapor deposition to form a silicon oxide passivation layer 5 (as shown in Figure 1e) on the surface of the silicon wafer electrical insulation layer 3 and the metal aluminum wiring 4;

4) Carry out photolithography to the silicon chip to form the micro-cantilever pattern; sequentially etch the silicon oxide passivation layer 5, the silicon oxide electrical insulating layer 3, the upper layer silicon 13 of the SO1 silicon chip and the original oxide layer of the SOI silicon chip 12. Form a micro-cantilever pattern to be released, exposing the surface of the lower silicon substrate 11 of the SOI silicon wafer (as shown in Figure 1f);

5) Using an isotropic reactive ion etching process such as sulfur hexafluoride (SF ₆ ) or xenon difluoride (XeF ₂ ), etc., laterally etch the lower silicon substrate 11 exposing the SOI silicon wafer in step 4), from The microstructure is released on the front side of the silicon wafer, that is, the micro-cantilever beam 0 is formed (as shown in FIG. 1g ).

Fig. 2 shows that the present invention adopts silicon gate MOSFET to make the embodiment structural representation of the microcantilever sensor of sensitive device, and its process flow comprises the following steps according to the manufacturing sequence:

1) SOI silicon wafers are used as the substrate material for preparing the micro-cantilever sensor. The SOI silicon wafers are composed of a lower silicon substrate 11, an original oxide layer 12 and an upper silicon 13, wherein the upper silicon 13 can be 100, 111 or 110 crystal orientation;

2) adopt plasma-enhanced chemical vapor deposition process to form silicon oxide on the surface of the SOI silicon wafer, and form an electrical insulating layer 3 between the metal connection line to be made and the upper silicon 13 through photolithography and etching; Thermal oxidation to form the gate oxide layer 21 of the MOSFET; use a low-pressure chemical vapor deposition process to form polysilicon on the surface of the silicon wafer, and form the silicon gate 22 of the MOSFET through photolithography and etching; perform photolithography on the silicon wafer to form MOSFET source and drain Pole region pattern, and implant the impurity ions opposite to the doping type of the upper silicon 13 into the upper silicon 13 of the SOI silicon wafer by an ion implantation process to form MOSFET source and drain electrodes 23; that is, if the upper silicon 13 doping type is N-type, then inject P-type impurities; if the doping type of the upper layer silicon 13 is P-type, then inject N-type impurities;

3) Metal aluminum is formed on the electrical insulating layer 3 of the silicon wafer and the surface of the MOSFET device by a sputtering process, and the metal aluminum connection 4 is formed by photolithography and etching; then, plasma-enhanced chemical vapor deposition is used on the electrical insulating layer of the silicon wafer A silicon oxide passivation layer 5 is formed on the surface of the metal aluminum connection 4;

4) Carry out photolithography to the silicon chip to form the micro-cantilever pattern; sequentially etch the silicon oxide passivation layer 5, the silicon oxide electrical insulating layer 3, the upper layer silicon 13 of the SOI silicon chip and the original oxide layer of the SOI silicon chip 12. Form the micro-cantilever pattern to be released, exposing the surface of the lower silicon substrate 11 of the SOI silicon wafer;

5) Using an isotropic reactive ion etching process such as sulfur hexafluoride (SF ₆ ) or xenon difluoride (XeF ₂ ), etc., to perform lateral etching on the lower silicon substrate 11 exposing the SOI silicon wafer in step 4), from The microstructure is released on the front side of the silicon wafer, that is, the micro-cantilever O (as shown in FIG. 2 ) is formed.

When the piezoresistive micro-cantilever manufactured through the process flow of the above embodiment is applied to actual detection, due to the piezoresistive effect, the bending of the micro-cantilever will cause changes in the piezoresistive value or the source-drain current of the MOSFET sensitive device. This change can realize the measurement of the bending amount of the micro-cantilever beam, thereby realizing the sensing function of the external physical quantity.

Claims (5)

1. A method for manufacturing piezoresistive micro-cantilever sensor on SOI silicon chip, is characterized in that, comprises the following steps by manufacturing sequence: 1) Use SOI silicon chip as the substrate material for the sensor, the SOI silicon chip is composed of the lower silicon substrate, the original oxide layer and the upper silicon; 2) Perform photolithography on the SOI silicon wafer, form a varistor as a sensitive device in the upper silicon of the SOI silicon wafer by ion implantation, and connect the varistor to the SOI silicon wafer by using a reverse bias P-N junction. The upper layer silicon insulation of the silicon wafer; or make MOSFET as a sensitive device in the upper silicon layer of the SOI silicon wafer by using an integrated circuit manufacturing process; 3) Deposit silicon dioxide as an insulating layer, and photolithographically etch a metal wiring contact hole, sputter metal on the surface of the silicon wafer insulating layer, form the metal wiring of the sensitive device through photolithography and etching, and depositing silicon oxide as a passivation layer; 4) Perform photolithography on the silicon wafer, and sequentially etch the surface to form a micro-cantilever pattern, exposing the surface of the lower silicon substrate of the SOI silicon wafer; 5) Using an isotropic reactive ion etching process to laterally etch the underlying silicon substrate exposing the SOI silicon wafer in step 4), releasing the microstructure from the front of the silicon wafer to make it suspended, that is, forming the micro-cantilever beam. 2 . The method for manufacturing a piezoresistive micro-cantilever sensor on an SOI silicon wafer according to claim 1 , wherein the upper layer of silicon has a crystal orientation of 100, 111 or 110. 3. The method for manufacturing a piezoresistive micro-cantilever sensor on an SOI silicon wafer according to claim 1, wherein the MOSFET is N-type, P-type, silicon gate or aluminum gate type. 4. according to the method for manufacturing piezoresistive micro-cantilever sensor on SOI silicon chip according to claim 1, it is characterized in that, adopt piezoresistor to make the technological process step of the micro-cantilever sensor of sensitive device: 1) adopt SOI silicon chip as the substrate material of preparing described micro-cantilever beam sensor, SOI silicon chip is made of lower layer silicon substrate (11), original oxide layer (12) and upper layer silicon (13), wherein upper layer silicon (13) ) is 100, 111 or 110 crystal orientation; 2) performing photolithography on the SOI silicon wafer to form a varistor pattern; using an ion implantation process to implant impurity ions opposite to the doping type of the upper silicon (13) into the upper silicon (13) of the SOI silicon wafer , forming a varistor (2) as a sensitive device, using a reverse bias P-N junction to insulate the varistor (2) from the upper silicon (13) of the SOI silicon wafer; that is, if the doping type of the upper silicon (13) is N-type , then implant P-type impurities; if the doping type of the upper silicon (13) is P-type, then inject N-type impurities; 3) adopt plasma-enhanced chemical vapor deposition process to form silicon oxide on the surface of the SOI silicon wafer, as the electrical insulation layer (3) between the metal wiring to be made and the upper silicon (13); then photolithography, on the silicon The surface of the electrical insulating layer (3) is etched to form a metal connection contact hole, and then metal aluminum is formed on the surface of the electrical insulating layer (3) of the silicon wafer by a sputtering process, and the metal aluminum connection (4) is formed by photolithography and etching ; Forming a silicon oxide passivation layer (5) on the surface of the silicon wafer electrical insulation layer (3) and the metal aluminum wiring (4) by plasma enhanced chemical vapor deposition; 4) Carry out photolithography to the silicon wafer to form the micro-cantilever pattern; sequentially etch the silicon oxide passivation layer (5), the silicon oxide electrical insulating layer (3), the upper silicon (13) of the SOI silicon wafer and the SOI silicon The original oxide layer (12) of the sheet forms a micro-cantilever pattern to be released, exposing the lower silicon substrate (11) surface of the SOI silicon sheet; 5) Using an isotropic reactive ion etching process of sulfur hexafluoride or xenon difluoride, laterally etch the lower silicon substrate (11) that exposed the SOI silicon wafer in step 4), releasing the microstructure from the front side of the silicon wafer , that is, the micro-cantilever beam (0) is formed. 5. according to the method for manufacturing piezoresistive micro-cantilever sensor on SOI silicon chip according to claim 1, it is characterized in that, adopt silicon gate MOSFET to make the process flow step of the micro-cantilever sensor of sensitive device: 1) adopt SOI silicon chip as the substrate material of preparing described micro-cantilever beam sensor, SOI silicon chip is made of lower layer silicon substrate (11), original oxide layer (12) and upper layer silicon (13), wherein upper layer silicon (13) ) is 100, 111 or 110 crystal orientation; 2) Forming silicon oxide on the surface of the SOI silicon wafer by using a plasma-enhanced chemical vapor deposition process, and forming an electrical insulating layer (3) between the metal wiring to be produced and the upper layer of silicon (13) through photolithography and etching; Thermally oxidizing the silicon wafer to form a gate oxide layer (21) of the MOSFET; using a low-pressure chemical vapor deposition process to form polysilicon on the surface of the silicon wafer, and forming a silicon gate (22) of the MOSFET through photolithography and etching; Photolithography, forming MOSFET source and drain electrode region patterns, and using an ion implantation process to implant impurity ions opposite to the doping type of the upper silicon (13) into the upper silicon (13) of the SOI silicon wafer to form MOSFET source and drain electrodes. Pole (23); that is, if the doping type of the upper silicon (13) is N-type, inject P-type impurities; if the upper-layer silicon (13) doping type is P-type, inject N-type impurities; 3) Metal aluminum is formed on the electrical insulating layer (3) of the silicon wafer and the surface of the MOSFET device by a sputtering process, and the metal aluminum connection (4) is formed by photolithography and etching; and then plasma-enhanced chemical vapor deposition is used on the silicon A silicon oxide passivation layer (5) is formed on the surface of the electrical insulating layer (3) and the metal aluminum wiring (4); 4) Carry out photolithography to the silicon wafer to form the micro-cantilever pattern; sequentially etch the silicon oxide passivation layer (5), the silicon oxide electrical insulating layer (3), the upper silicon (13) of the SOI silicon wafer and the SOI silicon The original oxide layer (12) of the sheet forms a micro-cantilever pattern to be released, exposing the lower silicon substrate (11) surface of the SOI silicon sheet; 5) Using an isotropic reactive ion etching process of sulfur hexafluoride or xenon difluoride, laterally etch the lower silicon substrate (11) that exposed the SOI silicon wafer in step 4), releasing the microstructure from the front side of the silicon wafer , that is, the micro-cantilever beam (0) is formed.

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