CN100499132C - High density semiconductor memory cell and memory array - Google Patents

Abstract

A programmable memory cell consisting of transistors located at the intersections of column bit lines and row word lines is disclosed. The transistor has a gate formed by a column bit line and a source connected to a row word line. The memory cell is programmed by applying a voltage potential between the column bit line and the row word line to create a programmed p+ region, forming a pn diode in the substrate below the transistor gate. Also, the word lines are formed from the buried diffused N+ layer, while the column bit lines are formed from the counter-doped polysilicon layer.

Description

High Density Semiconductor Memory Cells and Memory Arrays

related application

This application is a continuation-in-part of co-pending U.S. Patent Application Serial No. 10/765,802, filed January 26, 2004, entitled "HIGH DENSITY SEMICONDUCTOR MEMORY CELLAND MEMORY ARRAY USING A SINGLE TRANSISTOR AND HAVING VARIABLEGATE OXIDE BREAKDOWN" , and that application is co-pending U.S. Patent Application Serial No. 10/677,613, filed October 1, 2003, entitled "HIGH DENSITY SEMICONDUCTOR MEMORY CELL AND MEMORY ARRAY USINGA SINGLE TRANSISTOR HAVING A BURIED N+CONNECTION" Continuation-in-Part of co-pending U.S. Patent Application Serial No. 10/448,505, filed May 30, 2003, entitled "HIGH DENSITY SEMICONDUCTORMEMORY CELL AND MEMORY ARRAY USING A SINGLE TRANSISTOR" and 2002 Continuation-in-Part of co-pending U.S. Patent Application Serial No. 10/133,704, filed April 26, entitled "HIGH DENSITY SEMICONDUCTOR MEMORY CELLAND MEMORY ARRAY USING A SINGLE TRANSISTOR," requires the above under 35 USC §120 Priority for all applications.

technical field

The present invention relates to a non-volatile programmable semiconductor memory, and more particularly to a one-transistor memory cell programmed by breaking down the transistor gate oxide, and a memory array incorporating such a cell.

Background technique

Non-volatile memory retains stored data when power is removed, which is highly desirable in many different types of electronic devices. One commonly available type of non-volatile memory is programmable read-only memory ("PROM"), which utilizes word-line/bit-line cross-point elements such as fuses, antifuses, and floating-gate avalanche Charge-trapping devices injected into metal-oxide-semiconductor ("FAMOS") transistors store logic information.

An example of a PROM cell that utilizes breakdown of a silicon dioxide layer in a capacitor to store digital data is disclosed in US Patent No. 6,215,140 to Reisinger et al. The basic PROM disclosed by Reisinger et al. uses a series of combinations of oxide capacitors and junction diodes as crosspoint elements (the term "crosspoint" refers to the intersection of bitlines and wordlines). An intact capacitor represents a logic value of 0, while an electrical breakdown capacitor represents a logic value of 1. The thickness of the silica layer is adjusted to obtain the desired performance specification. The breakdown charge of silicon dioxide is about 10 C/cm ² (coulombs/cm ² ). If a voltage of 10 volts is applied to a capacitive dielectric with a thickness of 10 nm (obtaining a field strength of 10 mV/cm), a current of about 1 mA/cm ² will flow. At 10 volts, this results in a significant amount of time to program the memory cell. However, in order to reduce the high power loss that occurs during electrical breakdown, it is more advantageous to design the dielectric of the capacitor thinner. For example, a memory cell structure with a capacitive dielectric thickness of 3 to 4 nm can operate at about 1.5V. At this voltage, the capacitive dielectric still does not break down, so 1.5V is sufficient to read data from the memory cell. Data is stored at eg 5V, in which case a cell strand in a memory cell structure can be programmed in about 1 millisecond. In this case, an energy loss of approximately 50 watts (10 coulombs x 5 V) occurs per cm ² of capacitor dielectric. If the required power consumption is about 0.5W, it takes about 100 seconds to program a 1 gigabit memory. If the tolerable power consumption is higher, then programming can be completed correspondingly faster.

Certain types of nonvolatile memory can be programmed and erased repeatedly. These include Erasable Programmable Read Only Semiconductor Memory commonly known as EPROM, and Electrically Erasable Programmable Read Only Semiconductor Memory generally known as EBPROM. EPROM memory is erased with ultraviolet light and programmed with various voltages; EEPROM memory is erased and programmed with various voltages applied. Both EPROM and EBPROM have suitable structures, commonly referred to as floating gates, that charge and discharge according to the data to be stored thereon. The charge on the floating gate establishes the threshold voltage of the device, V _T , which is sensed when the memory is read to determine the data stored therein. In general, efforts are made to minimize gate oxide stress in these types of memory cells.

Devices, commonly referred to as Metal-Nitride-Oxide-Silicon ("MNOS") devices, have a channel in silicon between source and drain electrodes, and consist of a silicon dioxide layer, a silicon nitride layer, and The aluminum layer is covered by the gate structure. The MNOS device can be switched between two threshold voltage states VTH _(high) and _VTH(low) by applying an appropriate voltage pulse to the gate, which causes electrons to flow through the oxide-nitride gate (VTH _{(high) )} ), or driven out from the oxide-oxide gate (V _TH(low) ). Furthermore, efforts are made to minimize gate oxide stress in these types of memory cells.

Junction breakdown memory cells that utilize charge stored on the gate of a gated diode to store logic 0 and 1 values are disclosed in US Patent to Hoffman et al. (US Patent No. 4,037,243). Charge is stored on the gate by utilizing the capacitance formed between the p-type electrode and the gate electrode of the gated diode. Charge storage is enhanced by utilizing composite dielectrics in capacitors formed from silicon dioxide and silicon nitride layers instead of silicon dioxide. The erase voltage applied across the electrodes of the gated diode fills the oxide-nitride interface surface with a negative charge that remains after the erase operation is complete. This negative interface charge allows the gated diode to operate in the induced junction mode even after the erase voltage is removed. Thereafter when the gated diode is read out, it shows a field induced junction breakdown of the channel and a saturation current flows. The field-induced junction breakdown voltage is lower than the metallurgical junction breakdown voltage. However, applying a write voltage to the electrodes of the gated diode fills the silicon dioxide/silicon nitride interface with a positive charge that remains after the write operation is complete. Thereafter, when reading the gated diode, it will not be broken down because there is no channel. Only a weak current flows. Different current flows are sensed and represent different logic states.

Improvements in the various processes used to fabricate various types of non-volatile memory tend to lag behind improvements in widely used processes, such as advanced CMOS logic processes. For example, in order to make various special regions and structures required for high-voltage generation circuits, triple wells, floating gates, ONO layers, and special source and drain junctions commonly seen in the above-mentioned devices, device processes such as flash EEPROM devices tend to Uses 30% more masking steps than standard advanced CMOS logic processes. As a result, the process for flash devices tends to be one or two generations behind standard advanced CMOS logic processes and is around 30% more expensive per die. As another example, the antifuse process must be suitable for making various antifuse structures and high-voltage circuits, so it also tends to be one or two generations behind the standard advanced CMOS logic process.

In general, the preparation of silicon dioxide used in metal-oxide-silicon (MOS) devices such as capacitors and transistors requires special care. Great care is required to ensure that the silicon dioxide layer is not stressed during fabrication and subsequently during normal operation of the integrated circuit so that the desired device characteristics are obtained and stable over time. One example of the level of care during fabrication is disclosed in Kuroda, US Patent No. 5,241,200, which discloses the use of diffusion layers and bypasses to discharge charge accumulated in word lines during the wafer fabrication process. Avoidance of such charge accumulation ensures that a large electric field is not applied to the gate insulating film, thereby preventing changes in transistor characteristics and degradation and breakdown of the gate insulating film when a word line is used as its gate wiring.

An example of the degree of care taken in circuit design to avoid stressing the silicon dioxide layers of transistors during normal circuit operation is disclosed in US Patent No. 6,249,472 to Tamura et al. Tamura et al. disclose an antifuse circuit having an antifuse in series with a p-channel MOS transistor in one embodiment, and in series with an n-channel MOS transistor in another embodiment. While fabricating antifuses does not require the additional film fabrication processes typically required to fabricate antifuse circuits, Tamura et al. pose additional problems. When the antifuse shorts out, the transistors connected in series are exposed to high voltages high enough to break down the transistor's silicon dioxide layer. Tamura et al. disclose adding another transistor to the circuit to avoid exposing the first transistor to a breakdown potential.

The above material generally shows that various prior art memory technologies still suffer from disadvantages.

Description of drawings

FIG. 1 is a schematic circuit diagram of a portion of a memory array according to the present invention.

FIG. 2 is a partial layout diagram of a part of the memory array shown in FIG. 1 .

FIG. 3 is a cross-sectional view of an integrated circuit structure corresponding to a portion of the memory array of FIG. 2 .

FIG. 4 is a voltmeter illustrating the operation of the memory cell of FIGS. 1-3.

Figure 5 is a cross-sectional view of a memory cell that has been programmed.

Figure 6 is a schematic circuit diagram of a memory cell that has been programmed.

Fig. 7 is a sectional view of an experimental device.

Figure 8 is a graph showing the effect of constant voltage stress on ultra-thin gate oxide.

FIG. 9 is a graph showing various stages of current-voltage characteristics of an ultra-thin gate oxide as degradation progresses.

Figure 10 is a graph showing breakdown time versus gate voltage for a 63% distribution on a semi-logarithmic scale, measured on n-channel field effect transistors (inversion) for various oxide thicknesses.

Figure 11 is a graph showing the current-voltage characteristics of an n-type device measured after detection of a sequential breakdown event.

Figure 12 is a partial layout diagram of a portion of a memory array formed in accordance with an alternative embodiment of the present invention.

Figure 13 is a cross-sectional view of the integrated circuit structure taken along line A-A' corresponding to the portion of the memory array of Figure 12 .

Fig. 14 is a cross-sectional view of the integrated circuit structure taken along line B-B' corresponding to a portion of the memory array of Fig. 12 .

Figure 15 is a voltmeter showing the operation of the memory cell of Figures 12-14.

Figure 16 is a cross-sectional view of one embodiment of a memory cell formed in accordance with the present invention.

FIG. 17 is a schematic circuit diagram of the memory cell of FIG. 16 .

FIG. 18 is a voltmeter showing the operation of the memory cell of FIG. 16. FIG.

FIG. 19 is a top view layout showing the extent of nitrogen implantation in one method of forming the memory cell of FIG. 16. FIG.

20-23 illustrate cross-sectional views of one method for forming the memory cell of FIG. 16 .

24-25 illustrate cross-sectional views of alternative methods for forming the memory cell of FIG. 16 .

26-27 show cross-sectional views of alternative methods for forming memory cells of the present invention.

Figure 28 shows a top view and a cross-sectional view of an alternative embodiment of the invention.

FIG. 28A is an alternative embodiment of FIG. 28 that minimizes the pitch of the polysilicon bitlines.

FIG. 29 shows a worksheet for the embodiment of FIG. 28 .

Figure 30 shows a top view and a cross-sectional view of another alternative embodiment of the present invention.

Figure 31 shows a top view and a cross-sectional view of another alternative embodiment of the present invention with N-type polysilicon doping.

FIG. 32 shows a worksheet for the embodiment of FIG. 31 .

FIG. 33 is a schematic diagram of the memory array of FIG. 28 .

Detailed ways

厚或更薄的高质量栅氧化物，其通常可由当今可用的先进CMOS逻辑工艺得到。这种氧化物通常通过淀积、通过自硅有源区的氧化物生长或通过它们的一些组合形成。其它适合的电介质包括氧化物-氮化物-氧化物复合物、化合物氧化物等。Semiconductor memory cells with data storage elements built around a gate oxide are used to store information by establishing the leakage current level of the memory cell by stressing the ultra-thin dielectric until breakdown (soft or hard). A memory cell is read by sensing the current drawn by the cell. Suitable ultra-thin dielectrics are about 10-50 for use in transistors

Thick or thinner high quality gate oxides are generally available from advanced CMOS logic processes available today. This oxide is typically formed by deposition, by oxide growth from the silicon active region, or by some combination thereof. Other suitable dielectrics include oxide-nitride-oxide composites, compound oxides, and the like.

In the following description, numerous specific details are provided in order to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other words, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects of the invention.

Reference to "one embodiment" or "an embodiment" throughout the specification means that a specific component, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, particular components, structures or features may be combined in any suitable manner in one or more embodiments.

The present invention relates to other types of gate oxide breakdown based non-volatile memory designs developed by the present inventors and assigned to the same assignee as the present invention. U.S. Patent Application Serial No. 09/955,641, filed September 18, 2001, titled "SEMICONDUCTOR MEMORY CELL AND MEMORY ARRAYUSING A BREAKDOWN PHENOMENA IN AN ULTRA-THIN DIELECTRIC," filed December 17, 2001 U.S. Patent Application Serial No. 10/024,327, filed October 17, 2001, for "SEMICONDUCTOR MEMORY CELL AND MEMORY ARRAY USING ABREAKDOWN PHENOMENA IN AN ULTRA-THIN DIELECTRIC," entitled "SMARTCARD HAVING NON-VOLATILE MEMORY FORMED FROM LOGIC PROCESS," U.S. Patent Application Serial No. 09/982,034, and U.S. Patent Application Serial No. 09/982,314, filed October 17, 2001, entitled "REPROGRAMMABLE NON-VOLATILE OXIDE MEMORY FORMED FROM LOGIC PROCESS" Examples are provided, each of which is incorporated herein by reference. However, in each of the memory cells described above, the cell size is relatively large. The present invention provides much smaller cell sizes, whereby higher densities can be achieved.

Figure 1 shows an example of a memory array 100 formed in accordance with the present invention. Memory array 100 is a 3 row by 4 column array, however it is understood that the array may be of any size. Memory array 100 includes twelve memory cells 102 each including a MOS transistor 104 . For example, memory cell 102 at the intersection of first row _R1 and first column _C1 includes a MOS transistor 104 whose gate is connected to column line _C1 (also referred to herein as a "bit line" or "column bit line"). ”), whose source is connected to row line _R1 (also referred to herein as “word line” or “row word line”), and whose drain is left floating and connected to the drain of adjacent memory cell 102. Alternatively, as will be seen below, where shallow trench isolation (STI) is used to isolate two memory cells, the drains of adjacent devices need not be connected since no current flows through the drains.

As will be seen below, during the programming step, a relatively large voltage is applied to the gates of the transistors 102 of the selected column (via the bit line _Cx , where x = 1-M, and M is the total number of columns) to breakdown of the gate oxide of transistor 12 . In one embodiment, the other memory cells 102 shown in FIG. 1 are also formed from the same transistors 102 at the intersections of column bitlines _Cx and row wordlines _Ry , where y=1-N, and N is the total number of columns.

The use of transistor 102 as a data storage element in memory array 100 of FIG. 1 is advantageous because the transistor can be fabricated using many conventional CMOS processes with only one polysilicon deposition step without adding any masking steps thereto. In contrast, "floating gate" flash memory requires at least two layers of polysilicon. Moreover, with the development of current technology, the size of transistors can be made very small. For example, the current 0.18 micron, 0.13 micron and smaller line width process will greatly increase the density of flash memory.

Although only a 4x3 memory array 100 is shown, in practice such memory arrays contain memory cells on the order of a gigabit or more when fabricated, for example, using an advanced 0.13 μm CMOS logic process. With the further improvement of the CMOS logic process, larger memories will be realized. Memory array 100 is actually organized into bytes and pages and redundant rows (not shown), which can be done in any desired manner. Many suitable memory organizations are known in the art.

0.18μm工艺为0.13μm工艺为0.09μm工艺为

)厚的热生长栅氧化硅。FIG. 2 shows a partial layout 200 of a portion of memory array 100, and FIG. 3 shows a cross-section of an illustrative MOS integrated circuit 300 showing its corresponding memory cells 102 formed from transistors 104 according to the layout of FIG. main structural aspects. The layout diagram in Figure 2 is suitable for advanced CMOS logic processes. The term MOS is generally understood to apply to any gate material, including doped polysilicon and other good conductors and various types of gate dielectrics, not limited to silicon dioxide, and the term is used as such herein. For example, the dielectric may be any type of dielectric, such as an oxide or nitride, that undergoes hard or soft breakdown after a voltage is applied for a period of time. In one embodiment, approximately 50 Angstroms (0.25 μm process is

The 0.18μm process is The 0.13μm process is The 0.09μm process is

) thick thermally grown gate silicon oxide.

Preferably, the memory array 100 is laid out in a grid, wherein column lines such as C ₁ , C ₂ , C ₃ and C ₄ are connected with row lines such as R ₁ , R ₂ , R ₃ and R ₄ and the diffused source regions of transistor 104 Orthogonal to the drain region. Transistor 104 at the intersection of row line _R1 and column line _C1 is formed in p-well active region 302 in the following manner.

The ultra-thin gate oxide layer 304 is formed by deposition or thermal oxidation. A polysilicon layer is then deposited and doped, which is patterned using a gate mask containing patterns for the column bitlines C ₁ , C ₂ , C ₃ and C ₄ , which also serves as the gate 310 of transistor 104 . Alternatively, the column bit lines may be separate structures connected to the gates 310 of the transistors through column bit line segments. The various source and drain regions are formed by conventional process steps (implantation, spacing and n+ source/drain implantation), forming n+ source region 306 and n+ drain region 308 . Importantly, it should be noted that the polysilicon gate 310 for transistor 104 should not overlap the n+ source/drain regions. Therefore, lightly doped drain structures are not used. As described below, by not having the polysilicon gate 310 overlap or be close to the n+ source/drain region, the polysilicon gate will not be directly shorted to the n+ source/drain region during programming.

Also, a contact (also referred to as a row word line segment) to the n+ source/drain region 306 is formed to connect to the row line _Ry . Row lines _Ry are formed by metal deposition to be etched later. Also, an interlayer dielectric (not shown) is deposited over the polysilicon layer. Accordingly, contact vias connecting the metal row line R _y to the n+ source region 306 are formed within the interlayer dielectric.

The operation of memory array 100 is now explained with reference to the illustrative voltages shown in FIG. 4 . It will be appreciated that voltages are illustrative and that different voltages may be used in different applications or when using different process technologies. During programming, individual memory cells in memory array 100 are exposed to one of four possible programming voltage combinations, shown on rows 401, 403, 405, and 407 of FIG. The read voltages are shown on rows 409 , 411 , 413 and 415 . Assume that memory cell 102 is selected for programming and that memory cell 102 is located at the intersection of R ₁ and C ₁ . A selected memory cell 102 is said to be at a selected row and selected column ("SR/SC"). As shown in row 401, the voltage on the selected wordline _R1 (denoted as _Vwordline or "voltage on wordline") is 0 volts, and the voltage on bitline _C1 (denoted as _Vbitline or "Voltage on bit line") is the programming voltage (Vpp), in this case 8 volts. Thus, the voltage across the gate of transistor 104 (bit line C ₁ ) and the source of transistor 104 (word line R ₁ ) is 8 volts. The gate oxide 304 of transistor 104 is designed to break down at this potential difference, which programs the memory cell. During programming, the voltage potential breaks down the gate oxide and causes leakage current to flow through the gate oxide into the underlying substrate, mostly collected by the N+ source/drain connected to ground. Furthermore, as a result, a programmed n+ region 501 is formed in the p-well 302 between the n+ source region 306 and the n+ drain region 308 of the transistor 104 (see FIG. 5 ).

It will be appreciated that the precise magnitude of the applied voltage depends on the thickness of the gate oxide and other factors. Thus, for example, for a 0.13 micron CMOS process, the gate oxide is typically thinner, thereby requiring a lower voltage difference between the selected word line and the selected bit line. In one embodiment, bit line C ₁ and unselected word lines have a voltage of 4.5 volts, and unselected bit line R ₁ has a voltage between 0 and 1.2 volts when using a 0.13 micron CMOS process.

Consider the effect on memory cells 102 located at the intersection of a selected row and an unselected column ("SR/ _UC "), eg R 1 and C ₂ , when R ₁ and C ₁ are selected rows and columns. As shown on row 405, the voltage on word line _R1 is 0 volts and the voltage on unselected bit line _C2 is 0 or floating. This results in a relatively low potential difference across the gate oxide 304 of transistor 104 , which is insufficient to break down the gate oxide of transistor 104 at the crossover point. Under these conditions, memory cell 102 is not programmed.

Consider the effect on memory cells 102 located at the intersection of a selected column and _an unselected row ("UR/SC"), eg, _R2 and _C1 , when R1 and C1 are the selected row and _column . As shown on row 403, the voltage on unselected word line _R2 is floating or _Vpp and the voltage on bit line _C1 is _Vpp (8 volts in this example). This results in a relatively low potential difference across the gate oxide 304 of the transistor 104 . Under these conditions, memory cell 102 is not programmed.

Consider the effect on memory cells 102 located at the intersection of an unselected column and an unselected row ("UR/UC") when _R1 and C1 _are the selected row and column, e.g., _R2 and _C2 . As shown on row 407, the voltage on the unselected word line _R2 is floating or _Vpp , and the voltage on the unselected bit line _C2 is 0 volts or floating. This results in a negative potential difference across the gate 304 and N+ source/drain of transistor 104 . Since the N+ source/drain is positive and the gate is negative, higher voltages on the source/drain will not pass under the gate, and as a result memory cell 102 does not program under these conditions. Also, the voltage on unselected word lines will be biased to an intermediate voltage, such as 2V to 6V, to prevent cells from being programmed. However, programmed cells will result in leakage current from the selected bit line to the unselected word line. If the unselected bit line is floating, leakage current will charge it, which causes the voltage in the bit line to rise. By biasing the unselected word lines _Rx to _Vpp we can prevent this leakage and thus reduce the charging time of the selected bit lines by the programmed cells.

After memory cell 102 is programmed by breaking down gate oxide 304, the physical properties of cell 102 are changed. Turning to FIG. 5, transistor 104 of memory cell 102 has been programmed. During programming, a programmed n+ region 501 is formed under the gate of transistor 104 . The programmed n+ region 501 is formed as current flows (during the programming process) through the gate oxide 304 and builds up in the substrate (p-well 302).

Although difficult to see in FIG. 3 , as mentioned above, the polysilicon gate 310 of transistor 104 should not vertically overlap n+ source/drain regions 306 and 308 . In practice, lateral separation between the gate 310 and the n+ source region 306 and n+ drain region 308 should be sufficient to prevent short circuits during programming, for example by using CMOS LDD spacers. This lateral separation is denoted as lateral distance D, as shown in FIG. 3 . In one embodiment, the lateral distance D is between 0.02 microns and 0.08 microns, as specified by an LDD dielectric spacer in a CMOS logic device. By not having the polysilicon gate overlap or be close to the n+ source/drain region, the polysilicon gate will not be directly shorted to the n+ source/drain region during programming. Instead, programmed n+ regions 501 are formed. Furthermore, additional methods may be employed to avoid shorting between gate 310 and n+ regions 306 and 308 . As just one example, the gate oxide near n+ regions 306 and 308 can be made thicker by poly gate sidewall oxidation after gate poly etch. It should be understood that other methods are also suitable.

The programmed memory cell in FIG. 5 can be seen in schematic form in FIG. 6 . As a result of programming the memory cell, two gated diodes 601 and 603 are formed. Gating diodes 601 and 603 prevent current flow from word line _Ry to bit line _Cx . However, since a positive gate bias can induce n+ inversion, current is allowed to flow from bit line _Cx to word line _Ry during a read operation, which can create a connection to the N+ source/drain region.

The memory array 100 is read in the following manner. A read select voltage V _RD (eg, 1.8 volts) is applied to the selected column bit line ("SC") and a read select voltage of 0 volts is applied to the selected row word line ("SR"). Note that these voltages are for a typical 0.18 micron CMOS process. Typically lower voltages will be used for smaller more advanced CMOS processes. For example, for a 0.13 micron CMOS process, the read select voltage on the selected column bit line may be approximately 1.2 volts.

Assume that _R1 and _C1 are the selected row and column ("SC/SR") and the memory cells at the intersections are programmed. As shown on row 409, 1.8 volts (the read select voltage) is applied to the gate of transistor 104 via bit line _C1 and 0 volts is applied to the source via word line _R1 . This causes current to flow from bit line C ₁ , through the gate oxide of transistor 104 , and out through word line R ₁ which is grounded to zero. By detecting the current on the bit line, it can be determined whether the memory cell 102 is programmed. If memory cell 102 is not programmed, no current will flow, which indicates that the memory cell is not programmed.

Consider the effect on memory cells 102 located at the intersection of a selected column and an unselected row ("UR/SC") when _R1 and _C1 are the selected row and column for a read operation, e.g., _R2 and _C1 . As shown on line 411 , 1.8 volts is applied to the selected bit line C ₁ and the source is left floating or V _RD via the unselected word line R ₂ . There is no voltage potential across the transistor and no current flows, which indicates that the memory cell is not programmed. By biasing the unselected word line _R2 to V _RD , the time to charge the selected bit line through the programmed cell can be reduced. This is because if the unselected word lines are floating, it will take some time for the selected bit to be charged by the programmed cell.

Consider the effect on memory cells 102 located at the intersection of an unselected column and a selected row ("SR/UC") when _R1 and _C1 are the selected row and column for a read operation, e.g., _R1 and _C2 . As shown on line 413, 0 volts is applied to the unselected bit line _C2 and 0 volts is applied to the source via the selected word line _R1 . There is no voltage potential across the transistor and no current flows, which indicates that the memory cell is not programmed.

Consider the effect on memory cells 102 located at the intersection of an unselected column and an unselected row ("UR/UC") when R and C _are the selected row and column for a read operation, e.g. _, R ₂ and C ₂ . As shown on line 415, 0 volts is applied to the unselected bit line _C2 , and the source remains floating or _VRD via the unselected word line _R2 . Even for previously programmed cells, the programmed cell acts like a reverse biased diode, so there is no current flow from the unselected word line (1.8V) to the unselected bit line (0V), which indicates that the memory cell Not programmed.

Therefore, as seen above, during a read cycle, no current is drawn by memory cells located at intersections with unselected rows or unselected columns. Note that unselected word lines can remain floating. This embodiment will tend to reduce leakage current through the wordlines, as well as allow the use of smaller wordline drivers, thereby saving integrated circuit space.

Furthermore, in an alternative embodiment, in case unselected word lines or from selected word lines are charged to V _pp via previously programmed cells, or via word line drivers, in order to increase the n+ source/drain To improve junction breakdown voltage and reduce junction leakage, high-energy, low-dose n+ ion implantation can be used. The implant can be a standard n+ ESD protection implant or other current implant steps from a conventional CMOS process, thus remaining within a standard CMOS logic process. However, in other embodiments, special injection steps can be added to optimize the injection.

Alternative embodiments of the present invention are indicated in Figures 12-14. A table of operating conditions for such an alternative embodiment is shown in FIG. 15 . In the alternative embodiment of FIG. 12, the row word lines _R1 and _R2 are formed by metal deposition as shown in the embodiment in FIG. Instead, row wordlines _R1 and _R2 , and generally all row wordlines _Ry , are formed from a buried n+ layer formed in the substrate. Thus, the buried n+ layer replaces the aforementioned metal word lines. As such, no metal contact connecting the row wordline _RY to the N+ source region 306 is required. In general, this allows for higher density integration of storage arrays.

For clarity, it should be noted that the buried N+ layer forming the row word lines _R1 and _R2 of FIG. 12 is shown, while the N+ source region 306 and n+ drain region 308 are not shown in the top view of FIG. 12 .

FIG. 13 is a cross-sectional view of the silicon substrate taken along line AA' of FIG. 12 . A buried N+ layer 1301 is formed just below the N+ source region 306 and the N+ drain region 308 . In effect, the N+ source region 306 is in electrical contact with the buried N+ layer 1301 . Thus, the buried n+ layer 1301 replaces the metal row line R _y of FIG. 2 . In addition, the n+ drain region 308 is also in contact with the buried N+ layer 1301 .

Fig. 14 shows a cross-sectional view of the substrate taken along line B-B' of Fig. 12 . In this embodiment, shallow trench isolation ("STI") 1401 is used to separate and isolate the memory cells. An n+ layer 1301 is shown buried below the surface of the substrate, but still separated by shallow trench isolations 1401 .

Forming the buried n+ layer 1301 will require additional masking and implantation steps. In one embodiment, arsenic can be used as a dopant instead of phosphorus in order to limit the thickness of the diffusion layer in deep submicron processes. Buried n+ layer 1301 may be formed using high energy ion implantation before or after the thin gate oxide layer and/or polysilicon deposition is formed. Alternatively, the buried n+ layer 1301 can be deposited using epitaxial deposition techniques. Moreover, in order to be compatible with the CMOS logic process, the lightly doped P-type implant is the same as the logic NMOS threshold voltage V _t implant.

The buried n+ layer 1301 can reduce the size of the memory array by 50% or more compared to the embodiment shown in FIG. many.

Finally, Figure 15 shows a table of operating conditions for the embodiment of Figures 12-14. The programming voltage _Vpp is about 8-9 volts for a gate oxide thickness of 32 angstroms, or 5-6 volts for a gate oxide thickness of 20 angstroms. Typically, V _DD is the input/output voltage and is on the order of approximately 3.3 volts or 2.5 volts. The supply voltage for V _CC is typically 1.8 volts for the 0.18-micron process and 1.2 volts for the 0.13-micron process. As you can see, there can be a range of voltages used in order to form program and read functions. Also note that at rows 405 and 407 (for unselected columns), the voltage on the column bit line V _{bit line} is less than 0.5 volts. If the unselected column bit lines are greater than 0.5 volts (in other words _Vt ), previously programmed cells along the shared column bit line will have a large leakage current through the programmed cells. This leakage current can be reduced or eliminated by limiting the Vbit _line below _Vt .

Various studies of oxide breakdown in environments other than the memory cell 102 shown in array 100 indicate suitable voltage levels for breakdown of ultra-thin gate oxides and for establishing controllable breakdown. Breakdown occurs in the gate oxide when the ultrathin gate oxide is subjected to voltage-induced stress. Although the exact mechanism leading to the intrinsic breakdown of the gate oxide is unknown, the breakdown process is a gradual process through a soft breakdown ("SBD") phase to a hard breakdown ("HBD") phase. One cause of breakdown is believed to be oxide defect sites. These defect sites can act on the cell to cause breakdown, or can trap charge and thus cause localized high electric fields and currents, as well as positive feedback conditions leading to thermal runaway. Improved manufacturing processes that cause fewer oxide defects have reduced the occurrence of this type of breakdown. Another cause of breakdown is believed to be electron and hole trapping at various locations, which causes thermal runaway even in defect-free oxides.

Rasras et al. performed carrier separation experiments, which showed that under positive gate bias, the impact ionization of electrons in the substrate is the main source of substrate hole current. Mahmoud Rasras, Ingrid De Wolf, Guido Groeseneken, Robin Degraeve, Hermane. Maes, Substrate Hole Current Origin after Oxide Breakdown, IEDM00-537, 2000. Constant pressure stress experiments were carried out on ultra-thin oxides in a scheme involving channel inversion, showing that both SBDs and HBDs can be used to store data, and the required time can be obtained by controlling the time that the gate oxide storage element is subjected to stress. SBD and HBD degrees. Fig. 7 shows a schematic sectional view showing the experimental setup. The effect of constant voltage stress on an ultra-thin gate oxide is shown in the graph of Figure 8, where the x-axis is time in seconds and the y-axis is current in logarithmic amperes. Figure 8 shows the measured gate and substrate hole currents before and after soft breakdown and hard breakdown under constant voltage stress. For a time of approximately 12.5 seconds, the total current was essentially constant and was mainly electron current as measured by _Ig . The leakage is believed to arise from Fowordlineer-Nordhein ("FN") tunneling and stress-induced leakage current ("SILC"). At approximately 12.5 seconds, a large jump in the measured substrate hole current is observed, which is a sign of the onset of soft breakdown ("SBD"). From about 12.5 seconds to about 19 seconds, the total current remains essentially constant at this new level, although there is some fluctuation in the substrate current. At about 19 seconds, large jumps in both electron current and substrate hole current indicate the onset of hard breakdown ("HBD"). Figure 8 shows that by controlling the time the gate oxide storage element is subjected to stress, the extent to which a desired SBD or HBD can be achieved.

Sune et al. investigated post-SBD conduction in ultrathin silicon dioxide films. Jordi Sune, Enrique Miranda, Post Soft Breakdown conduction in SiO2 GateOxide, IEDM 00-533, 2000. The various stages in the current-voltage ("I-V") characteristics of an ultra-thin gate oxide as it degrades are shown in Figure 9, where the x-axis is voltage in volts and the y-axis is logarithmic in amperes current. Figure 9 shows that a wide range of voltages can be used to program gate oxide storage elements, and that either SBD or HBD can be used to store information in gate oxide storage elements. Also included are several post-breakdown I-V characteristics showing the evolution from SBD to HBD. The amount of leakage current generated at SBD and HBD and in intermediate cases between these two extremes is roughly linear with voltage magnitude in the range of about 2.5 volts to 6 volts.

Wu et al. studied the voltage dependence of voltage acceleration in ultrathin oxides. E.Y. Wu et al., Voltage-Dependent Voltage-Acceleration of Oxide Breakdown for Ultra-Thin Oxides, IEDM 00-541, 2000. Figure 10 is a graph of breakdown time versus gate voltage at the 63% distribution in semi-logarithmic scales for n-channel FETs (inverted) with measured oxide thickness varying from 2.3nm to 5.0nm. The distribution is generally uniform and linear, and indicates that the process is controllable.

Miranda et al. measured the IV characteristics of nMOSFET devices with 3nm oxide thickness and 6.4× ^{10-5 cm2} area after detection of successive breakdown events. Miranda et al., "Analytic Modeling of Leakage Current Through Multiple Breakdown Paths in SiO ₂ Films", IEEE 39 ^th Annual International Reliability Physics Symposium, Orlando, FL, 2001, pp 367-379. Figure 11 shows these results for the linear region, where "N" is the number of conducting channels. These results are very linear, indicating that the pathway is essentially resistive.

In the embodiments described above, typically n-type lightly doped drain (NLDD) implants are blocked to avoid overlapping gate and source/drain N+ diffusions (see FIG. 3 and spacing D). This creates a reverse diode between the wordline N+S/D diffusion and the bitline polysilicon gate in the programmed cell. This results in an unselected word line (biased at Vdd or higher in the case of a floating word line charged by a bit line selected at Vpp through a programmed cell) to an unselected bit line (0 volts biased or floating) reduces leakage current between.

In the structures shown in Figures 1-6 and 12-15, the gate oxide breakdown point is near the gate edge near the word line N+ diffusion (see Figure 5). The punch-through voltage from the N+ diffusion of the word line to the breakdown point of the oxide is relatively low, so the reverse diode is not effective in preventing leakage current from the unselected word line to the unselected bit line. This is undesirable for several reasons.

Therefore, according to the present invention, the gate oxide close to the floating N+ diffusion region is made more susceptible to breakdown than the gate oxide close to the word line N+ diffusion region. While this can be achieved in a number of ways, two separate approaches are described: (1) Make the gate oxide near the floating N+ diffusion region thinner than the gate oxide near the wordline N+ diffusion region (shown below for Various methods implemented in two specific embodiments); or (2) Implantation damages the gate oxide near the floating N+ diffusion region, so that the gate oxide is more likely to break down. It can be understood that the present invention is mainly focused on having a lower breakdown voltage in the floating N+ diffusion region, and any fabrication or structure developed or developed for this purpose is within the scope of the present invention.

In one embodiment, as shown in FIG. 16 , in order to move the gate oxide break point away from the gate edge at the word line N+ diffusion region, the gate oxide on the side of the floating N+ source (diffusion) region can be made thinner ( Alternative 1). The floating N+ diffusion region connects two adjacent cells on the same word line. Optionally, the gate oxide can be made thinner on the gate side near the N+ region of the word line (Option 2). Note that the present invention can be easily extended to PMOS devices, where the PMOS devices are formed inside the N-well.

Memory cells using this different gate oxide MOS device have the following advantages:

1. Programming cells by oxide breakdown usually preferably occurs on the floating source side of the gate.

2. This provides a robust reverse diode between the programmed cell's drain (word line contact) and the polysilicon gate (bit line).

3. The reverse diode shoot-through voltage is thus greatly improved compared to a uniform gate oxide cell, where gate oxide breakdown would occur near the drain side (causing a low reverse diode shoot-through voltage).

4. The programming voltage will be reduced (down to 3.5-5V) because the source side gate oxide thickness is much thinner than standard gate oxide, which typically requires 6 to 6.5V to program.

Figure 17 illustrates equivalent circuit diagrams of different oxide 1T memory cells. Figure 18 shows cell operating bias voltages for one embodiment. There are several techniques that can be used to form the different gate oxides described above, two of which are described below.

Alternative 1: Use a nitrogen (N2) implant (or other implant species that can reduce the silicon oxidation rate) on one side of the gate to create a different gate oxide thickness. However, the different gate oxides produced by this method are not self-aligned.

As shown in Figures 19 and 20, after the P-well and channel Vt implants, a photomask is used to perform a selective nitrogen implant in the silicon region where the thinner gate oxide will grow.

(对于0.13μm类的工艺)。同时，在氮注入的硅区中将生长10至15

较薄的栅氧化物。Turning next to Figure 21, the post-implantation photomask is removed, a gate oxide pre-clean step is performed, and a general gate oxidation is performed to grow 20 on the non-nitrogen implanted regions

(for 0.13μm-like processes). Simultaneously, 10 to 15

thinner gate oxide.

Turning to FIG. 22, after the gate polysilicon deposition and polysilicon gate etch, NLDD implants and N+S/D implants follow. Finally, NMOS memory cells are formed with different gate oxide thicknesses on the source and drain as shown.

Finally, turning to FIG. 23, after contact connections to the word line diffusion (WordLine) and the polysilicon bit line (BitLine), memory cells with different gate oxide NMOS devices are formed.

In an alternative method (alternative 2), an isotropic etch is used on the drain side followed by oxidation. The different gate oxides produced by the method described above are self-aligned. Specifically, as shown in FIG. 24, after the gate polysilicon is etched, use a photoresist to cover the source side, and perform isotropic etching (usually wet etching) to gate the drain (word line) side. An undercut occurs on the oxide.

Next, as shown in Figure 25, the photoresist is removed and an oxidation step is performed to fill the undercut gate, thus making a thicker gate oxide on the drain (word line) side. This is followed by conventional NLDD implant, spacer deposition, spacer etch and S/D implant.

The above two approaches describe varying the thickness of the gate oxide on a positional basis relative to the transistor source and drain. This is done so that the gate oxide closer to the floating N+ diffusion has a lower breakdown voltage. Another way to achieve the same task is to damage the gate oxide closer to the floating N+ diffusion region by eg heavy ion implantation.

Specifically, another method is to implant heavy ions such as As+ to selectively damage the gate oxide so that the breakdown voltage of the oxide is lower than that of general gate oxides. This is also a self-alignment process. For example, as shown in FIG. 26, after gate poly etch, photoresist is used to cover the drain side. Then, an angled (15-60 degree, 2-way or 4-way spin implant) As+ implant is performed on the floating source side. As shown in Figure 27, the next step is to remove the photoresist and perform the usual LDD implant, spacer deposition, spacer etch and S/D implant.

As with the above-described embodiments, the buried N+ layer embodiments of FIGS. 12-15 require special (and often complex) implantation processes. To remove the contact to the word line, an implant is used to create a buried N+ layer connection below the surface channel. The variable gate oxide breakdown embodiments of Figures 16-27 require additional and special process steps to make variable G _Ox .

In yet another alternative embodiment shown in Figure 28, a surface N+ diffusion is used instead of a deeply buried N+ layer. Note that the term diffused is used herein to refer to encompassing doped regions formed by implantation or diffusion processes. This embodiment can be fabricated using a standard CMOS process flow with one additional masking and implantation step. After oxide breakdown, a PN junction diode can then be formed.

As shown in Figure 28, the transistors are now similar to PMOS transistors in terms of surface N+ word lines instead of traditional N wells. Note, however, that the N+ word line 2801 is isolated by shallow trench isolation. Surface level N+ word lines 2801 are formed at the surface of the substrate (by diffusion or implantation). For example, As+ (or any other n-type dopant) diffusion can be performed prior to gate oxidation. Optionally, As+ can be implanted before or after gate oxidation, or even after polysilicon gate deposition, to form N+ word line 2801, if implantation is used.

After forming the N+ word line 2801 in the substrate and completing the gate oxidation process, a polysilicon layer is formed on the gate oxide. The polysilicon layer is then conventionally etched to form bit lines 2803 . Additional (ie unnecessary) P+S/D regions 2805 are then also formed, such as for example by using a self-aligned implant step. As part of this implant, the polysilicon layer that forms the gate of the transistor is implanted and becomes P+ type polysilicon. This implementation is compatible with standard CMOS logic processes and saves additional masking and implantation steps. However, this implementation also causes unnecessary incidental P+ source/drain doping.

It should be noted that the N+ word line 2801 should be deeper than the P+S/D region 2805 to ensure good conductivity of the N+ word line 2801 . However, to prevent low punch-through leakage through shallow trench isolation (STI) between adjacent bit lines, the N+ word line cannot be too deep.

In order to minimize the effect of the attached P+ source/drain doping from hindering the buried N+ connection, the spacing between adjacent polysilicon lines can be made as small as possible. By so doping, the lightly doped drain (LDD) spacers will be brought close to each other, effectively minimizing or even eliminating P+ source/drain implants. An example of this is shown in Figure 28A. However, as shown in FIG. 33, the N+ word line contacts the memory array periodically, such as every 64 columns.

The operation of the memory array is shown in the table of FIG. 29 . The programming voltage (Vpp) is the voltage necessary between the bit line and the word line to be sufficient to punch through or electrically break down the gate oxide. Since the programming voltage is the difference between the voltage on the word line (Vwp) and the voltage on the bit line (Vbp), various combinations of voltages can be distributed between the bit line and the word line.

(0.18μm工艺)，Vpp＝|Vwp-Vbp|＝7～10V，或对于G_Ox＝20

(0.13μm工艺)为5～7V。在一个实施例中，Vwp＝0～Vpp且Vwp可以便利地设置为Vdd。Vbp可以在-Vpp～+Vpp的范围内。Vrd是读取电压，其在Vcc至Vdd之间。对于0.18μm工艺，Vcc＝1.8V，且对于0.13μm工艺为1.2V。Vdd为I/O电压(3.3V或2.5V)。In one embodiment, for G _Ox =32

(0.18μm process), Vpp=|Vwp-Vbp|=7～10V, or for G _Ox =20

(0.13μm process) is 5-7V. In one embodiment, Vwp=0˜Vpp and Vwp can be conveniently set to Vdd. Vbp may be in the range of -Vpp˜+Vpp. Vrd is the read voltage, which is between Vcc to Vdd. Vcc = 1.8V for 0.18um process and 1.2V for 0.13um process. Vdd is the I/O voltage (3.3V or 2.5V).

An alternative embodiment is shown in FIG. 30 . In this embodiment, no source and drain regions are formed. This embodiment is likely to be implemented in the case of CMOS processes with selective doping for P+ polysilicon or N+ polysilicon, such as implant doping during deposition, or after polysilicon deposition and doping, before polysilicon etch. In this case, the concern about P+S/D doping hindering N+ wordlines is no longer an issue. This will result in the device structure shown in Figure 30. Thus, in this embodiment, the structure is simply to intersect the polysilicon bitlines over the buried wordlines. The principle of operation is roughly the same as that shown in FIG. 29 .

The above ideas can be easily extended to the N+ polysilicon/gate oxide/P+ word line embodiment. In such an embodiment, only the type of doping is reversed, with an array formed in the N-well. Specifically, as shown in FIG. 31 , an N well 3101 is first formed in the substrate. Then, a p-type dopant such as boron is introduced into the N-well to form a P+ word line 3103 . The p-type doping can be performed before or after gate oxidation, or even after polysilicon deposition.

After the P+ word line 3103 is formed in the substrate and the gate oxidation process is completed, a polysilicon layer is formed over the gate oxide. The polysilicon layer is then conventionally etched to form bit lines 3105 . Next, N+S/D regions 3107 are formed, such as for example by using a self-aligned implant step. As part of this implant, the polysilicon layer that forms the gate of the transistor is also implanted and becomes N+ type polysilicon.

It should be noted that the P+ word line 3101 should be deeper than the N+ S/D region 3107 to ensure good conductivity of the P+ word line 3103 . However, to prevent low punch-through leakage through shallow trench isolation (STI) between adjacent bit lines, the P+ word line cannot be too deep.

Also, in this embodiment, there is no need to form source and drain regions. This embodiment is likely to be implemented in the case of a CMOS process with selective doping for N+ polysilicon, such as implant doping during polysilicon deposition, or after polysilicon deposition, before polysilicon etch. In this case, the concern about N+S/D doping hindering P+ wordlines is no longer an issue.

(0.18μm工艺)，Vpp＝|Vbp-Vwp|＝7～10V，或对于

(0.13μm)为5～7V。Vbp可以在-Vpp～+Vpp的范围内，且Vwp可以是在0～Vpp的范围内，或便利地设置为Vdd。Vrd是读取电压，其在Vcc至Vdd之间。Vdd为3.3V或2.5V的I/O电压。对于0.18μm工艺，Vcc＝1.8V，且对于0.13μm工艺为1.2V。The memory array operation is shown in the table of FIG. 32 . The program voltage Vpp can be divided between bit lines and word lines. for

(0.18μm process), Vpp=|Vbp-Vwp|=7～10V, or for

(0.13μm) is 5~7V. Vbp can be in the range of -Vpp~+Vpp, and Vwp can be in the range of 0~Vpp, or conveniently set to Vdd. Vrd is the read voltage, which is between Vcc to Vdd. Vdd is the I/O voltage of 3.3V or 2.5V. Vcc = 1.8V for 0.18um process and 1.2V for 0.13um process.

The embodiment shown in Figures 28-32 provides advantageous properties. For example:

(1) Using a standard CMOS process with only one additional buried N+ or P+ mask and implant, a gate oxide antifuse memory cell array consisting of cells of size 4F^2 (where F is the minimum feature size) can be constructed .

(2) The unit is constructed with a structure of P+ polysilicon/Gox/N+ word line/P well or N+ polysilicon/Gox/P+ word line/N well/P substrate. Buried diffused word lines can be isolated by standard STI or other isolation methods.

(3) Bit lines and word lines are constructed by counter-doped polysilicon lines and buried diffusion lines.

(4) The cell array can be selectively programmed by applying Vpp across the cell gate oxide in both polarities. After programmed Gox breakdown, a P-N junction diode is formed between the polysilicon and the buried diffusion line.

(5) By applying a positive voltage to the P terminal of the PN junction diode, the programmed cells can be selectively read, so that the diode is forward biased to form a sensing current.

(6) The programming voltage Vpp can be distributed between the bit line and the word line, so that the programming voltage on the bit line or the word line can be reduced.

的量级，或对于0.13μm约为20

的量级。这种超薄栅氧化物两端的电压在编程时可能暂时地比Vcc高很多，对于以0.25μm工艺制造的集成电路其通常为2.5伏，对于以0.13μm工艺制造的集成电路为1.2伏。这种超薄氧化物在没有晶体管性能的显著退化时通常可以耐受高达4或5伏。Note that the transistors used in the memory cells described here are, in most cases, low voltage logic transistors typically having, for example, ultra-thin gate oxide thicknesses of the order of 50 μm for a 0.25 μm process.

on the order of , or about 20 for 0.13 μm

magnitude. The voltage across this ultra-thin gate oxide may temporarily be much higher than Vcc during programming, typically 2.5 volts for integrated circuits fabricated on a 0.25 μm process and 1.2 volts for an integrated circuit fabricated on a 0.13 μm process. This ultra-thin oxide can typically withstand up to 4 or 5 volts without significant degradation in transistor performance.

The description of the invention and its application set forth herein is illustrative and not intended to limit the scope of the invention. Variations and modifications of the embodiments disclosed herein may be made, and practical substitutions and equivalents for the various elements of the embodiments are known to those of ordinary skill in the art. For example, the various voltages presented in the various examples are illustrative only, since there is some disagreement among people as to the exact voltage to choose within a voltage range, and in any case the voltage is related to device characteristics. The terms row word line and column bit line are used to describe the types of lines commonly used in memories, but some memories may call them otherwise. Furthermore, the various doping types can be inverted so that the n-channel transistors described above can be replaced by p-channel transistors. In this case, the p-channel transistor will be formed in a large n-well, and a buried p+ layer can be used. These and other variations and modifications of the embodiments disclosed herein can be made without departing from the scope and spirit of the invention.

Claims (7)

1. a programmable memory cell is formed in the p N-type semiconductor N substrate, and is used for having the memory array of row bit line and row word line, and this memory cell comprises:

Transistor has the semiconductor region that the 2nd p+ of grid that p+ mixes, the gate dielectric between above this grid and the described substrate and contiguous this grid mixes; And

The semiconductor region that wherein transistorized the 2nd p+ mixes one of is connected in the described capable word line, and wherein said capable word line forms by the n type district at the near surface of described Semiconductor substrate.

2. memory cell as claimed in claim 1, wherein said grid is by forming one of in the described row bit line.

3. memory cell as claimed in claim 1, wherein when described memory cell has been programmed, described memory cell further is included in the doped region that is programmed that forms in the described substrate in the channel region.

4. a programmable memory cell is formed in the n type trap, and is used in the memory array with row bit line and row word line, and this memory cell comprises:

Transistor has the semiconductor region that the 2nd n+ of grid that n+ mixes, the gate dielectric between above this grid and the substrate and contiguous this grid mixes; And

The semiconductor region that wherein transistorized the 2nd n+ mixes one of is connected in the described capable word line, and wherein said capable word line forms by the p type district at the near surface of described n type trap.

5. memory cell as claimed in claim 4, wherein said grid is by forming one of in the described row bit line.

6. memory cell as claimed in claim 4, wherein when described memory cell has been programmed, described memory cell further is included in the doped region that is programmed that forms in the described substrate in the channel region.

7. memory cell as claimed in claim 4, wherein said n type trap is replaced by n type substrate.

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