CN100495322C - Device and method for processing abnormal multi-layer nesting of preprocessing microinstructions - Google Patents
Device and method for processing abnormal multi-layer nesting of preprocessing microinstructions Download PDFInfo
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Abstract
本发明涉及复杂指令集计算机内部异常处理技术，尤其涉及对预处理微指令发生异常多层嵌套进行处理的设备及方法，所述方法包括：微指令在执行过程中发生异常，译码部件缓存异常信息，并对缓存的异常信息进行译码产生微指令地址；B、译码部件按产生的微指令地址索引微指令存储器获取异常预处理微指令，并将获取的异常预处理微指令发送给后端部件，后端部件在执行接收的异常预处理微指令时如果再次发生异常，则执行步骤C；如果不发生异常，则执行步骤D；C、后端部件刷空计算机的指令流水线，译码部件缓存再次发生的异常信息，并对再次发生的异常信息进行译码产生微指令地址，转而执行步骤B；D、后端部件跳转并执行异常处理程序。
The present invention relates to complex instruction set computer internal abnormality processing technology, in particular to a device and method for processing abnormal multi-layer nesting of pre-processing micro-instructions. Abnormal information, and decode the abnormal information of the cache to generate the microinstruction address; B, the decoding part indexes the microinstruction memory according to the generated microinstruction address to obtain the abnormal preprocessing microinstruction, and sends the acquired abnormal preprocessing microinstruction to Back-end components, if an exception occurs again when the back-end components execute the received exception preprocessing microinstructions, then execute step C; if no exception occurs, then execute step D; The code component caches the reoccurring exception information, and decodes the reoccurring exception information to generate a microinstruction address, and then executes step B; D, the back-end component jumps and executes the exception handling program.
Description
Technical field
The present invention relates to complex instruction set computer (CISC) internal abnormality treatment technology, relate in particular to and a kind of the Apparatus and method for that unusual multilayer nest is handled is taken place the pre-service micro-order.
Background technology
(Complex Instruction Set Computer CISC) is meant based on microprogram, has the computing machine of complex instruction set based on the computing machine of sophisticated vocabulary.In the CISC system, article one, complicated order generally need be translated into many micro-orders, many micro-orders that are translated are stored in the ROM (read-only memory) (ROM) of CPU, and what the instruction pipelining in the processor was handled is these micro-orders, rather than the complicated order of the operating system visible before the translation.
Micro-order can be operated more register resources than complicated order usually.For example, sophisticated vocabulary generally can be operated 8 visible general-purpose registers, and microinstruction set can be operated the visible general-purpose register more than 32 or 64.With 32 visible general-purpose registers is example, 8 general-purpose registers that can be used as sophisticated vocabulary wherein, and 24 remaining code translators that then keep to give microinstruction set are as temporary register or as other purposes.
Instruction pipelining in the processor often takes place unusual when handling many micro-orders being translated into by a complicated order.After taking place unusually, the treatment mechanism that exists in the prior art at first changes one section pre-service micro-order over to, carrying out this section pre-service micro-order can the save register scene, and from internal memory, obtain the destination address of redirect or by carrying out the destination address that micro-order dynamically generates redirect, jump to the exception handler of operating system visible then according to destination address, the execute exception handling procedure can be realized unusual reparation.The destination address of above-mentioned redirect leaves in a certain fixed area of Installed System Memory usually.
Problem of above-mentioned treatment mechanism existence promptly may take place again unusually when the pre-service micro-order is carried out in the back unusual the generation, and then form the unusual multilayer nest of pre-service micro-order.At this moment, the unusual multilayer nest that processor should in time take place the pre-service micro-order is handled, and when these are unusually correctly repaired in assurance, is unlikely to cause the chaotic of instruction flow again even enters unusual endless loop.
But, also do not exist at present the technology that unusual multilayer nest is handled is taken place the pre-service micro-order, how the pre-service micro-order being taken place that unusual multilayer nest handles is to be badly in need of the major issue that solves at present.
Summary of the invention
(1) technical matters that will solve
At the deficiency that above-mentioned prior art exists, a fundamental purpose of the present invention is to provide a kind of the equipment that unusual multilayer nest is handled is taken place the pre-service micro-order, and what make generation is able to orderly and correct reparation unusually.
Another fundamental purpose of the present invention is to provide a kind of the method that unusual multilayer nest is handled is taken place the pre-service micro-order, and what make generation is able to orderly and correct reparation unusually.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of the equipment that unusual multilayer nest is handled is taken place the pre-service micro-order, this equipment comprises:
Instruction fetching component be used for taking out instruction from the command high speed buffer internal memory, and the instruction that will take out sends to decoding unit;
Decoding unit is used for the abnormal information of buffer memory is deciphered, and the microinstruction address index microinstruction storage that produces by decoding obtains unusual pre-service micro-order, and the unusual pre-service micro-order that will obtain sends to emission element and instruction resequencing buffer;
Emission element, the off-the-shelf instruction of unusual pre-service micro-order data that is used for receiving sends to execution unit;
Execution unit is used to carry out the instruction that is received from emission element, and the result that will carry out writes back to the instruction resequencing buffer;
The instruction resequencing buffer is used for preserving the status information of every instruction of computer instruction streamline, and guarantees the precise abnormal of instruction, when the instruction generation is unusual abnormal information is exported to instruction fetching component, decoding unit, emission element and execution unit;
Described instruction resequencing buffer is exported to instruction fetching component with abnormal information when the instruction generation is unusual, decoding unit, emission element and execution unit, it is invalid that instruction fetching component is changed to its instruction address register and instruction output bus after receiving this abnormal information, it is invalid that decoding unit is changed to its order register, and this abnormal information is buffered in the unusual impact damper, and to the buffering abnormal information decipher the generation microinstruction address, decoding unit obtains unusual pre-service micro-order by the microinstruction address index microinstruction storage that produces, and the unusual pre-service micro-order that will obtain is given back-end component, this back-end component comprises emission element, execution unit and instruction resequencing buffer, if it is unusual that back-end component takes place when the unusual pre-service micro-order that carry out to receive once more, then back-end component is brushed the instruction pipelining of empty computing machine, the abnormal information that the decoding unit buffer memory takes place once more, and carry out above-mentioned exception handling procedure, until no abnormal generation; Back-end component redirect and execute exception handling procedure, by the time sequencing of unusual generation by the back to first one by one to repairing unusually.
Described decoding unit comprises:
Unusual impact damper is used for the abnormal information that buffer memory is received from the instruction resequencing buffer, and according to the selection signal that is received from the microcode address maker abnormal information of buffer memory is sent to the microcode address maker;
Order register is used to deposit the current opcode byte that is executing instruction;
The microcode address maker is used for from unusual impact damper and order register selection information, and the information of selecting to obtain is deciphered the generation microinstruction address, obtains micro-order by the microinstruction address index microinstruction storage that produces;
Microinstruction storage is used to store micro-order, and according to the selection signal that is received from the micro-order selector switch micro-order that microcode address maker index obtains is sent to the micro-order selector switch;
The simple instruction code translator is used for the information of order register buffer memory is deciphered, and will decipher the micro-order that produces according to the selection signal that is received from the micro-order selector switch and send to the micro-order selector switch;
The micro-order selector switch is used for selecting micro-order from microinstruction storage and simple instruction code translator, and the micro-order of selecting to obtain is sent to the micro-order maker;
The micro-order maker is used for the micro-order that is received from the micro-order selector switch is deciphered, and the micro-order after the decoding is outputed on the decoding bus.
Described microcode address maker and micro-order selector switch are No. two selector switchs, and microcode address maker priority processing selects the information obtained, micro-order selector switch priority processing to select the micro-order of obtaining from unusual impact damper from microinstruction storage.
Described emission element further comprises rename logic, is used to eliminate writing between the register and is correlated with relevant with read-write.
The quantity of described execution unit is at least one.
A kind of the method that unusual multilayer nest is handled is taken place the pre-service micro-order, this method comprises:
A, instruction resequencing buffer are preserved the status information of every instruction in the computer instruction streamline, and guarantee the precise abnormal of instruction, take place abnormal information to be exported to instruction fetching component, decoding unit, emission element and execution unit when unusual in instruction; It is invalid that decoding unit is changed to its order register after receiving this abnormal information, and this abnormal information is buffered in the unusual impact damper, and the abnormal information of buffering is deciphered the generation microinstruction address;
B, decoding unit obtain unusual pre-service micro-order by the microinstruction address index microinstruction storage that produces, and the unusual pre-service micro-order that will obtain sends to back-end component, this back-end component comprises emission element, execution unit and instruction resequencing buffer, if it is unusual that back-end component takes place when the unusual pre-service micro-order that carry out to receive once more, then execution in step C; If do not take place unusually, then execution in step D;
C, back-end component are brushed the instruction pipelining of empty computing machine, the abnormal information that the decoding unit buffer memory takes place once more, and the abnormal information that takes place once more deciphered the generation microinstruction address, then execution in step B;
D, back-end component redirect and execute exception handling procedure, by the time sequencing of unusual generation by the back to first one by one to repairing unusually.
Described step B comprises:
B1, decoding unit obtain unusual pre-service micro-order by the microinstruction address index microinstruction storage that produces, and the unusual pre-service micro-order that will obtain sends to emission element and instruction resequencing buffer;
B2, emission element send to execution unit with the unusual pre-service micro-order of DSR, and execution unit will send to the instruction resequencing buffer to the result that unusual pre-service micro-order is carried out;
B3, instruction resequencing buffer are checked the queue heads instruction that Roq_head points to, the article one of instructing resequencing buffer to utilize Roq_head to point to buffering is not herein submitted instruction to, if it is unusual that the unusual pre-service micro-order that Roq_head points to takes place, then execution in step C; If the unusual pre-service micro-order that Roq_head points to does not take place unusually, then execution in step D.
It is to send by the sequence of addresses of micro-order that the unusual pre-service micro-order that decoding unit described in the step B1 will obtain sends to emission element.
The unusual pre-service micro-order that decoding unit described in the step B1 will obtain further comprises when sending to emission element: the unusual pre-service micro-order that decoding unit will obtain leaves in the instruction resequencing buffer by the sequence of addresses of micro-order.
The instruction pipelining of the empty computing machine of described brush is meant what ream weight ordering impact damper passed through to realize to decoding unit, emission element and execution unit output abnormality information; The abnormal information that described decoding unit buffer memory takes place once more is that the abnormal information that will take place once more is buffered in the unusual buffer zone.
Described abnormal information can have error code information, and described decoding unit further is cached to error code information in the unusual buffer zone.
Described step D comprises: the instruction resequencing buffer jumps to exception handler, re-executes time profound exception handler after the exception handler of bottommost layer time executes, and carries out the exception handler of top layer time at last.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilizes the present invention, when unusual multilayer nest takes place in the pre-service micro-order, by brushing the instruction pipelining of empty computing machine, redirect and execute exception handling procedure, after executing, the inferior exception handler of bottommost layer re-executes time profound exception handler, carry out the exception handler of top layer time at last, realized the processing that unusual multilayer nest carries out is taken place the pre-service micro-order, what make generation is able to orderly and correct reparation unusually.
2, utilize the present invention, owing to realized the processing that unusual multilayer nest carries out is taken place the pre-service micro-order, what make generation is able to orderly and correct reparation unusually, so can further guarantee the correct recovery of dependence between the register, and then make processor continue execution command from breakpoint, guaranteed carrying out smoothly of instruction execution.
3, utilize the present invention, a plurality of unusual for what when carrying out many micro-orders, trigger, equally can be by the instruction pipelining of the empty computing machine of brush, redirect and execute exception handling procedure, that triggers during to many micro-orders a plurality ofly repairs unusually one by one, and then realize that to a plurality ofly handling unusually that many micro-orders trigger what make generation is able to orderly and correct reparation unusually.
Description of drawings
Fig. 1 is for according to the structured flowchart that the pre-service micro-order is taken place the equipment that unusual multilayer nest handles provided by the invention;
Fig. 2 is for according to the structured flowchart that the pre-service micro-order is taken place decoding unit in the equipment that unusual multilayer nest handles provided by the invention;
The synoptic diagram that unusual multilayer nest carries out treatment facility middle finger ream weight ordering impact damper for taking place according to provided by the invention to the pre-service micro-order in Fig. 3;
The realization flow figure that unusual multilayer nest is handled overall technological scheme takes place for the present invention to the pre-service micro-order in Fig. 4;
Three layers of nested synoptic diagram of handling for taking place to the pre-service micro-order in Fig. 5;
Fig. 6 is for setting up the synoptic diagram that relies on and cancel dependence for register in the rename module;
Fig. 7 is according in the embodiment of the invention method flow diagram that unusual multilayer nest is handled being taken place the pre-service micro-order.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is for according to the structured flowchart that the pre-service micro-order is taken place the equipment that unusual multilayer nest handles provided by the invention.Provided by the invention the equipment that unusual multilayer nest handles is taken place the pre-service micro-order is a central processing unit (CPU), and this CPU comprises instruction fetching component 101, decoding unit 102, emission element 103, execution unit 104 and instruction resequencing buffer (ROQ) 105.
Wherein, instruction fetching component 101 comprises order register, command high speed buffer internal memory (cache), and the instruction bypass impact damper, branch predictors etc. are specifically formed structure and can different the work be adjusted accordingly with the complexity of the system of realization.Instruction fetching component 101 is used for taking out instruction from command cache, and the instruction that will take out sends to decoding unit 102.
Decoding unit 102 is used for after the instruction that receives instruction fetching component 101 transmissions, abnormal information to buffer memory is deciphered, the microinstruction address index microinstruction storage that produces by decoding obtains unusual pre-service micro-order, and the unusual pre-service micro-order that will obtain sends to emission element 103.The structure of decoding unit 102 will describe in further detail in Fig. 2, just repeat no more here.
The off-the-shelf instruction of unusual pre-service micro-order data that emission element 103 is used for receiving sends to execution unit 104.Emission element 103 can further include rename logic, is used to eliminate writing between the register and is correlated with relevant with read-write.
Execution unit 104 is used to carry out the instruction that is received from emission element 103, and the result that will carry out writes back to ROQ 105.Generally speaking, because CPU need carry out various instruction simultaneously, and each execution unit can only be carried out one type instruction at synchronization, so the quantity of execution unit generally is at least one.
ROQ 105 is used for preserving the status information of every instruction of computer instruction streamline, and guarantees the precise abnormal of instruction, output abnormality information when the instruction generation is unusual.Whether the status information of every instruction comprises mainly whether instruction is finished, instructs and submit to etc. in the computer instruction streamline, also has for branch instruction that branch writes back, branch triggers etc.
Based on Fig. 1 is described the structured flowchart that unusual multilayer nest carries out treatment facility is taken place in the pre-service micro-order; Fig. 2 shows the structured flowchart of decoding unit 102 among Fig. 1, and this decoding unit comprises unusual impact damper (Ex_buffer) 201, order register (Ir) 202, microcode address maker (Rom_pcgenerator) 203, microinstruction storage (uROM) 204, simple instruction code translator (Simpledecoder) 205, micro-order selector switch (Micro code selecter) 206 and micro-order maker (Uopgenerator) 207.
Wherein, Ex_buffer 201 is used for the abnormal information that buffer memory is received from ROQ 105, and according to the selection signal that is received from Rom_pc generator 203 abnormal information of buffer memory is sent to Rom_pc generator 203.
Based on Fig. 1 and the described structured flowchart of Fig. 2, it is as follows that the present invention to the pre-service micro-order flow process that unusual multilayer nest handles takes place: if execution unit 104 notes abnormalities in the process of implementation, then abnormal information is sent to ROQ 105 by result bus (result bus), ROQ 105 sends to decoding unit 102 by exception bus (exception bus) with abnormal information, decoding unit 102 is received and Ir 202 is put after this abnormal information invalidly, and this abnormal information is buffered among the Ex_buffer201.Clapping Rom_pc generator 203 at next selects the abnormal information of buffer memory among the Ex_buffer 201 to decipher, generate microinstruction address urom_pc, and obtain micro-order by the urom_pc index uROM204 that generates, the micro-order of obtaining sends to Uopgenerator 207 by Micro code selecter 206, and 207 pairs of micro-orders of Uop generator are further deciphered and outputed on the decode bus.If take place nestedly unusually, abnormal information can be buffered to again among the Ex_buffer 201, and abnormality processing has begun so again.What take place in the time of just can handling the unusual pre-service of complicated order according to this decoder architecture design is nested unusually.
Based on Fig. 1 is described the structured flowchart that unusual multilayer nest carries out treatment facility is taken place the pre-service micro-order, Fig. 3 shows the synoptic diagram of ROQ 105 among Fig. 1.Micro-order among the ROQ 105 is to deposit by the sequence of addresses of micro-order, and Roq_head points to the instruction of ROQ 105 queue heads, and Roq_tail points to the next item down of rear of queue.It is precise abnormal that ROQ 105 can be used for guaranteeing instructing, when a micro-order among the ROQ 105 take place unusual after, ROQ 105 issues instruction fetching component 101 with abnormal information, decoding unit 102, emission element 103 and execution unit 104 etc.
Based on Fig. 1, Fig. 2 with Fig. 3 is described that the structured flowchart that unusual multilayer nest carries out treatment facility is taken place the pre-service micro-order, Fig. 4 shows the present invention the realization flow figure that unusual multilayer nest is handled overall technological scheme is taken place the pre-service micro-order, and this method may further comprise the steps:
Step 401: micro-order takes place unusually in the process of implementation, decoding unit buffer memory abnormal information, and the abnormal information of buffer memory deciphered the generation microinstruction address;
Step 402: decoding unit obtains unusual pre-service micro-order by the microinstruction address index microinstruction storage that produces, and the unusual pre-service micro-order that will obtain sends to back-end component (this back-end component comprises emission element, execution unit and ROQ), if it is unusual that back-end component takes place when the unusual pre-service micro-order that carry out to receive once more, then execution in step 403; If do not take place unusually, then execution in step 404;
Step 403: the ROQ in the back-end component brushes the instruction pipelining of empty computing machine, the abnormal information that the decoding unit buffer memory takes place once more, and the abnormal information that takes place once more deciphered the generation microinstruction address, then execution in step 402;
Step 404: ROQ redirect in the back-end component and execute exception handling procedure, by the time sequencing of unusual generation by the back to first one by one to repairing unusually.
Above-mentioned steps 402 comprises:
Step 4021: decoding unit obtains unusual pre-service micro-order by the microinstruction address index microinstruction storage that produces, and the unusual pre-service micro-order that will obtain sends to emission element;
In this step, to send to emission element be that sequence of addresses by micro-order sends to the unusual pre-service micro-order that will obtain of decoding unit;
Further, decoding unit leaves the unusual pre-service micro-order the obtained sequence of addresses by micro-order among the ROQ in when the unusual pre-service micro-order that will obtain sends to emission element.
Step 4022: emission element sends to execution unit with the unusual pre-service micro-order of DSR, and unusual pre-service micro-order needs to carry out 1 in execution unit claps or clap more, and execution unit will send to ROQ to the result that unusual pre-service micro-order is carried out.
Step 4023:ROQ claps the unusual pre-service micro-order of checking that Roq_head points to per 1, can check preceding 4,2 or 1 instruction, and unusual if the unusual pre-service micro-order that Roq_head points to takes place, then execution in step 403; If the unusual pre-service micro-order that Roq_head points to writes back, and do not take place unusually, then execution in step 404.
In the above-mentioned steps 403, the ROQ in the described back-end component brushes the instruction pipelining of empty computing machine, is that ROQ passes through to realize to instruction fetching component, decoding unit, emission element and execution unit output abnormality information;
The abnormal information that described decoding unit buffer memory takes place once more is that the abnormal information that will take place once more is buffered in the unusual buffer zone, if abnormal information has error code information, then decoding unit further also is cached to error code information in the unusual buffer zone.
Above-mentioned steps 404 comprises: the ROQ in the back-end component jumps to exception handler, after executing, the inferior exception handler of bottommost layer re-executes time profound exception handler, carry out the exception handler of top layer time at last, so just formed a depth-first traversal, behind unusual processed the finishing of bottommost layer, the sort processor structure can trigger the unusual of time profound level, and behind all unusually all processed finishing, complicated order just can obtain carrying out.
Based on Fig. 4 is described the realization flow figure that unusual multilayer nest is handled overall technological scheme is taken place the pre-service micro-order, Fig. 5 shows three layers of nested synoptic diagram of handling is taken place the pre-service micro-order.
As can be seen from Figure 5, processor jumps to exception handler for the first time to the 3rd layer handle unusually, this 3rd layer be to produce unusually by the unusual pre-service micro-order of the second layer.After the 3rd layer unusual reparation was finished, processor turned back to breakpoint and re-executes this instruction, and the result triggers unusually once more, and this moment is because the 3rd layer unusually be repaired, triggering be the unusual of the second layer.Processor jumps to exception handler for the second time to the handling unusually of the second layer, and after the unusual reparation of the second layer was finished, processor can turn back to breakpoint and carry out the unusual instruction of this generation once more, and the result causes triggering for the third time unusually.This moment is because all being repaired unusually of the 3rd layer and the second layer, so only can trigger the unusual of ground floor.Processor jumps to exception handler for the third time to the handling unusually of ground floor, and after the unusual reparation of ground floor was finished, processor can turn back to breakpoint and carry out the unusual instruction of this generation once more, and instruction just can be smoothly by having carried out.
For the register dependence that cancellation after exception-triggered has been set up, need specify the micro-order numbering for each register relies on.Fig. 6 shows in the rename module and sets up the synoptic diagram that relies on and cancel dependence for register.As shown in Figure 6, when running into micro-order 1, logic register 1 is mapped to physical register 3; When running into micro-order 6, logic register 2 is mapped to physical register 1; When running into micro-order 8, logic register 3 is mapped to physical register 5; Because micro-order 3,4,5 and 7 does not have corresponding destination register, so micro-order 3,4,5 and 7 is not set up corresponding relation with register, micro-order 3,4 is carried out and is not write back for 5 and 7; When running into micro-order 9, logic register 1 is mapped to physical register 7, and this moment, logic register 1 shone upon two physical registers 3 and 7, and their difference is that corresponding micro-order numbering is different, promptly is respectively 2 and 9.
In Fig. 6, if a micro-order has taken place unusually, then rename module is received this abnormal information, will compare according to the unusual micro-order of dependence of having set up and generation, and will be positioned at the dependence cancellation that the micro-order foundation afterwards of unusual micro-order takes place.For example, if micro-order 8 has taken place unusually, the dependence that micro-order 9 was set up after then rename module will be cancelled is promptly cancelled the dependence of logic register 1 to physical register 7, and other dependence keeps.
Provided by the invention the method that unusual multilayer nest is handled to be taken place in the pre-service micro-order in order more clearly illustrating, to be elaborated below in conjunction with specific embodiment.
In the present embodiment, be example with the processor of x86, a lot of complicated orders is arranged in the processor of x86 series, common as the instruction of string copy, soft interruptions int n instruction, indirect jump instruction etc., these instruct pairing micro-order to be stored in a rom.Decoding unit is obtained complicated order from storer after, can remove index rom, take out micro-order and send to rename logic and emission element respectively according to the operation code field of this instruction and other the domain of dependence.
The visible general-purpose register of X86 has 8, is respectively eax, ebx, ecx, edx, esp, ebp, esi and edi, corresponds to 8 common registers of micro-order.In addition, microinstruction set also has been assigned with 24 temporary registers, and these 24 temporary registers are used for cushioning the operation result of each execution unit, comprise adding unit, multiplying unit, division parts, memory access parts etc.Because it is relevant to produce data to these 32 registers when micro-order is carried out, this being correlated with carried out rename by the rename logic of rear end, thereby eliminated the false appearance pass.Micro-order after the rename is put in the resequencing buffer according to the order of sequence.Micro-order in the resequencing buffer has three state, dummy status, and mapping status writes back state.When a certain the state in the resequencing buffer be sky, represent that this can deposit a micro-order, just be not used at present.Mapping status represents that current list item deposited a micro-order, and this micro-order is to come from the rename components, which transmits, and this instruction just carries out or just medium to be launched in scoring plug at execution unit, does not also have operation result to produce.Write back the current instruction of state representation and be finished, and execution result write in the register file, just waited for that processor does last affirmation at execution unit.
Based on Fig. 4 is described the realization flow figure that unusual multilayer nest is handled overall technological scheme is taken place in the pre-service micro-order, Fig. 7 shows according in the embodiment of the invention method flow diagram that unusual multilayer nest is handled being taken place the pre-service micro-order, may further comprise the steps:
Step 701: resequencing buffer sends to the rename parts with the micro-order that has write back of queue heads in order, and the rename parts are revised the status information of respective objects register according to the micro-order that is received from resequencing buffer;
In this step, if the micro-order of queue heads has been attached abnormal information, then to send to the information of rename parts invalid for resequencing buffer, and resequencing buffer will send to decoding unit to the micro-order of having attached abnormal information once more.
Step 702: decoding unit from receive unusual obtain unusual vector, and the unusual vector coding that will obtain is a special instruction, the instruction address at the unusual place that record takes place.
Step 703: decoding unit obtains corresponding micro-order according to special instruction index from rom that coding produces, ROQ carries out the micro-order of obtaining and obtains the exception handler address, carry out pop down again, preserve pretreatment operation such as crucial scene, change formal exception handler over to according to the exception handler address that obtains then; If taken place again unusually unusual multilayer nest to take place promptly in pop down and the crucial on-the-spot process of preservation, then execution in step 705; If unusual multilayer nest does not take place, then execution in step 704.
Step 704: the ROQ execute exception handling procedure in the back-end component to repairing unusually of taking place, and re-executes this instruction, process ends after exception handler is complete.
Step 705: the new unusual vector that the decoding unit buffering obtains, with the new unusual vector coding that obtains is a special instruction, and according to the special instruction that comes by new unusual vector coding again from rom index obtain corresponding micro-order, the micro-order of obtaining by execution obtains the exception handler address for the second time;
In this step, in the time of decoding unit buffering obtains new unusual vector, Re-Order Buffer is cleared, and other various functional parts have also all been done removing work.
Step 706: decoding unit carries out pop down, preserves pretreatment operation such as crucial scene, if taken place again unusually unusual multilayer nest to take place promptly in pop down and the crucial on-the-spot process of preservation, then execution in step 708; If unusual multilayer nest does not take place, then execution in step 707.
Step 707: decoding unit changes formal exception handler over to according to the exception handler address that obtains for the second time, to repairing unusually of taking place, and re-executes this instruction, process ends after exception handler is complete.
Step 708: decoding unit continues execution in step 705 and 706, until unusual multilayer nest no longer takes place, changes formal exception handler over to, to repairing unusually of taking place, and re-executes this instruction after exception handler is complete.
In the present embodiment, processor is to handle with following order execute exception: can re-execute the exception handler of inferior profound level after the exception handler of bottommost layer time executes, carry out the exception handler of top layer time at last.
In illustrated embodiment step 701 of the present invention, the micro-order that resequencing buffer will attach abnormal information sends to decoding unit.In actual applications, the micro-order that to attach abnormal information at resequencing buffer sends to decoding unit simultaneously, can further the micro-order of having attached abnormal information be sent to the rename parts, the rename parts can be analyzed the abnormal information that receives, and then all dependences of once setting up of instruction back, cancellation abnormal information place.The technical scheme of being lifted in such technical scheme and the embodiment of the invention is consistent on thinking, should be included within protection scope of the present invention.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1, a kind of the equipment that unusual multilayer nest is handled is taken place in the pre-service micro-order, it is characterized in that this equipment comprises:
Instruction fetching component be used for taking out instruction from the command high speed buffer internal memory, and the instruction that will take out sends to decoding unit;
Decoding unit is used for the abnormal information of buffer memory is deciphered, and the microinstruction address index microinstruction storage that produces by decoding obtains unusual pre-service micro-order, and the unusual pre-service micro-order that will obtain sends to emission element and instruction resequencing buffer;
Emission element, the off-the-shelf instruction of unusual pre-service micro-order data that is used for receiving sends to execution unit;
Execution unit is used to carry out the instruction that is received from emission element, and the result that will carry out writes back to the instruction resequencing buffer;
The instruction resequencing buffer is used for preserving the status information of every instruction of computer instruction streamline, and guarantees the precise abnormal of instruction, when the instruction generation is unusual abnormal information is exported to instruction fetching component, decoding unit, emission element and execution unit;
Described instruction resequencing buffer is exported to instruction fetching component with abnormal information when the instruction generation is unusual, decoding unit, emission element and execution unit, it is invalid that decoding unit is changed to its order register after receiving this abnormal information, and this abnormal information is buffered in the unusual impact damper, and to the buffering abnormal information decipher the generation microinstruction address, decoding unit obtains unusual pre-service micro-order by the microinstruction address index microinstruction storage that produces, and the unusual pre-service micro-order that will obtain is given back-end component, this back-end component comprises emission element, execution unit and instruction resequencing buffer, if it is unusual that back-end component takes place when the unusual pre-service micro-order that carry out to receive once more, then back-end component is brushed the instruction pipelining of empty computing machine, the abnormal information that the decoding unit buffer memory takes place once more, and carry out above-mentioned exception handling procedure, until no abnormal generation; Back-end component redirect and execute exception handling procedure, by the time sequencing of unusual generation by the back to first one by one to repairing unusually.
2, equipment according to claim 1 is characterized in that, described decoding unit comprises:
Unusual impact damper is used for the abnormal information that buffer memory is received from the instruction resequencing buffer, and according to the selection signal that is received from the microcode address maker abnormal information of buffer memory is sent to the microcode address maker;
Order register is used to deposit the current opcode byte that is executing instruction;
The microcode address maker is used for from unusual impact damper and order register selection information, and the information of selecting to obtain is deciphered the generation microinstruction address, obtains micro-order by the microinstruction address index microinstruction storage that produces;
Microinstruction storage is used to store micro-order, and according to the selection signal that is received from the micro-order selector switch micro-order that microcode address maker index obtains is sent to the micro-order selector switch;
The simple instruction code translator is used for the information of order register buffer memory is deciphered, and will decipher the micro-order that produces according to the selection signal that is received from the micro-order selector switch and send to the micro-order selector switch;
The micro-order selector switch is used for selecting micro-order from microinstruction storage and simple instruction code translator, and the micro-order of selecting to obtain is sent to the micro-order maker;
The micro-order maker is used for the micro-order that is received from the micro-order selector switch is deciphered, and the micro-order after the decoding is outputed on the decoding bus.
3, equipment according to claim 2; it is characterized in that; described microcode address maker and micro-order selector switch are No. two selector switchs; microcode address maker priority processing selects the information obtained, micro-order selector switch priority processing to select the micro-order of obtaining from unusual impact damper from microinstruction storage.
4, equipment according to claim 1 is characterized in that, described emission element further comprises rename logic, is used to eliminate writing between the register and is correlated with relevant with read-write.
5, equipment according to claim 1 is characterized in that, the quantity of described execution unit is at least one.
6, a kind of the method that unusual multilayer nest is handled is taken place in the pre-service micro-order, it is characterized in that this method comprises:
A, instruction resequencing buffer are preserved the status information of every instruction in the computer instruction streamline, and guarantee the precise abnormal of instruction, take place abnormal information to be exported to instruction fetching component, decoding unit, emission element and execution unit when unusual in instruction; It is invalid that decoding unit is changed to its order register after receiving this abnormal information, and this abnormal information is buffered in the unusual impact damper, and the abnormal information of buffering is deciphered the generation microinstruction address;
B, decoding unit obtain unusual pre-service micro-order by the microinstruction address index microinstruction storage that produces, and the unusual pre-service micro-order that will obtain sends to back-end component, this back-end component comprises emission element, execution unit and instruction resequencing buffer, if it is unusual that back-end component takes place when the unusual pre-service micro-order that carry out to receive once more, then execution in step C; If do not take place unusually, then execution in step D;
C, back-end component are brushed the instruction pipelining of empty computing machine, the abnormal information that the decoding unit buffer memory takes place once more, and the abnormal information that takes place once more deciphered the generation microinstruction address, then execution in step B;
D, back-end component redirect and execute exception handling procedure, by the time sequencing of unusual generation by the back to first one by one to repairing unusually.
7, method according to claim 6 is characterized in that, described step B comprises:
B1, decoding unit obtain unusual pre-service micro-order by the microinstruction address index microinstruction storage that produces, and the unusual pre-service micro-order that will obtain sends to emission element and instruction resequencing buffer;
B2, emission element send to execution unit with the unusual pre-service micro-order of DSR, and execution unit will send to the instruction resequencing buffer to the result that unusual pre-service micro-order is carried out;
B3, instruction resequencing buffer are checked the queue heads instruction that Roq_head points to, the article one of instructing resequencing buffer to utilize Roq_head to point to buffering is not herein submitted instruction to, if it is unusual that the unusual pre-service micro-order that Roq_head points to takes place, then execution in step C; If the unusual pre-service micro-order that Roq_head points to does not take place unusually, then execution in step D.
8, method according to claim 7 is characterized in that, it is to send by the sequence of addresses of micro-order that the unusual pre-service micro-order that decoding unit described in the step B1 will obtain sends to emission element.
9, method according to claim 7 is characterized in that, the unusual pre-service micro-order that decoding unit described in the step B1 will obtain further comprises when sending to emission element:
The unusual pre-service micro-order that decoding unit will obtain leaves in the instruction resequencing buffer by the sequence of addresses of micro-order.
10, method according to claim 6 is characterized in that,
The instruction pipelining of the empty computing machine of described brush is meant what ream weight ordering impact damper passed through to realize to decoding unit, emission element and execution unit output abnormality information;
The abnormal information that described decoding unit buffer memory takes place once more is that the abnormal information that will take place once more is buffered in the unusual buffer zone.
11, method according to claim 10 is characterized in that, described abnormal information can have error code information, and described decoding unit further is cached to error code information in the unusual buffer zone.
12, method according to claim 6 is characterized in that, described step D comprises:
The instruction resequencing buffer jumps to exception handler, re-executes time profound exception handler after the exception handler of bottommost layer time executes, and carries out the exception handler of top layer time at last.
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| US9747105B2 (en) | 2009-12-17 | 2017-08-29 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
| CN101834801B (en) * | 2010-05-20 | 2012-11-21 | 哈尔滨工业大学 | Data caching and sequencing on-line processing method based on cache pool |
| CN103226499B (en) * | 2013-04-22 | 2016-02-24 | 华为技术有限公司 | A kind of method of the abnormal data recovered in internal storage and device |
| CN103986660B (en) * | 2014-05-30 | 2018-01-23 | 华为技术有限公司 | The device of loading micro code and the method for loading micro code |
| CN104156241B (en) * | 2014-07-31 | 2019-08-13 | 中国船舶重工集团公司第七0九研究所 | The initiated configuration method and system of processor microprogram |
| CN104268029A (en) * | 2014-09-23 | 2015-01-07 | 天津国芯科技有限公司 | Nesting exception processing circuit and method for embedded PowerPC (performance optimization with enhanced RISC (reduced instruction set computer)-performance computing) processor |
| CN112579170B (en) * | 2020-12-10 | 2022-11-08 | 海光信息技术股份有限公司 | A processor and method for reducing virtual address calculation |
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| US20020092002A1 (en) * | 1999-02-17 | 2002-07-11 | Babaian Boris A. | Method and apparatus for preserving precise exceptions in binary translated code |
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| US6216222B1 (en) * | 1998-05-14 | 2001-04-10 | Arm Limited | Handling exceptions in a pipelined data processing apparatus |
| US20020092002A1 (en) * | 1999-02-17 | 2002-07-11 | Babaian Boris A. | Method and apparatus for preserving precise exceptions in binary translated code |
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