CN1004853B - Junction field effect transistor resistance type differential amplifier - Google Patents

Abstract

Here the JFET transistor difference amplifier acts as the input stage for the meter operational amplifier, which presents high input impedance and low leakage current. This goal is achieved by biasing the JFET transistor to make it work in the resistance region of the drain current-gate-source voltage characteristic curve instead of the saturation region.

Description

Junction field effect transistor resistor type differential amplifier

The present invention relates to the technology of differential amplifiers, and in particular to junction field effect transistor amplifiers operating in resistive regions.

The differential amplifier will be described herein as an input stage of an ammeter, but the present invention may be applied to other aspects such as an amplifier exhibiting high input impedance when measuring voltage and an amplifier exhibiting low input bias current or bleed current when measuring current.

Differential amplifiers are often used to measure voltage and current and are often used in the input stage of an electricity meter. It is well known in the art that electricity meters are commonly used primarily for measuring dc voltages and currents, but also include extended measurements of many parameters, such as resistance or charge. For voltage measurements, the meter is distinguished by a high input resistance, which is typically between 10 ¹³ and 10 ¹⁵ ohms. This is important for measuring the voltage of a power supply with high series resistance with a conventional Digital Voltmeter (DVM) under conditions that may cause overload. For example, when measuring electrochemical electromotive force or PH, the electricity meter has a high input resistance.

When the meter is used to measure current, it should exhibit very low input bias current (bleed current) because the current resolution capability of the microampere of the meter can be in the range of fA (10 ^-15 a) or aA (10 ^-18 a). The main purpose of the ammeter micro amp range is to measure very high resistance by means of an applied voltage across a resistor in series with the micro amp meter, with a resistance value of 10 ¹² to 10 ¹⁶ ohms.

In order to provide an input stage of an ammeter with high input impedance and low bleed current, the commonly used input stage consists of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The mosfet is used as an input stage of a differential amplifier, and sometimes a differential amplifier is used as an operational amplifier or OP-AMP. An example of using a MOSFET OP-AMP input stage in an electricity meter is already in us patent 3,654,468 to iran king. An ammeter having such an input stage has exhibited the desired high input impedance and low bleed (or input bias) current. The high input impedance achieved by MOSFET transistors is largely dependent on the insulating properties of the thin silicon dioxide layer or gate insulating layer. Such a circuit, while exhibiting the desired low input bias current characteristics, also has poor overload characteristics unless an appropriate protection circuit is provided. For example, an input voltage transient of 30 volts or higher may cause breakdown or destruction of the gate insulation layer. In addition, such MOSFET transistors often require fine compensation, temperature compensation, common mode rejection, noise, and bias current selection, and the effects of these compensation and selection may be intermittent, inefficiency, and lot dependent.

It is known in the past to use JFET transistors as input stages for power meters instead of MOSFET transistors. Such JFET transistors are connected in differential amplifiers, which exhibit improved voltage characteristics compared to MOSFET transistors, but input bias current flows high, for example up to 10 times. While the MOSFET input exhibits a low bias current, which is on the order of less than 5fA (5 x 10 ^-15 a). On the other hand, JFET input stages are known to exhibit very good voltage characteristics while having an input bias current of up to 60fA. It is important that the input bias current of the meter must be less than the input current being measured. For the known JFET transistors, the input bias current as large severely limits the possibilities of using the JFET input stage in an ammeter.

It is therefore a basic object of the present invention to provide a JFET input stage for use in an electric meter which presents a high input impedance and has a low bleed current comparable to the MOSFET input stage described above, without the need to use complex protection circuits as required for MOSFET input stages.

It is a further object of the present invention to provide an input stage for a JFET differential amplifier having voltage characteristics approaching those of prior art JFET source output circuits and input bias current characteristics approaching those of prior art MOSFET input stages.

It is a further object of the present invention to provide an input stage using JFET transistors that are biased to operate to reduce gate channel leakage and operate primarily in the manner of voltage controlled resistors rather than current sources as in prior art JFET power followers. Thus, high immunity is provided to prevent damage caused by overload and electrostatic discharge, as well as low voltage noise and low bias drift, while optimizing the input bias current.

In accordance with the present invention, the above and other objects include the use of a pair of JFET transistors as input stages for a differential amplifier, and the provision of a biasing circuit for maintaining a drain-to-source voltage (V _DS) below the V _GS-V_GSOFF voltage, so as to reduce V _DG and V _GS, thereby further reducing gate channel leakage. Thus, the differentially connected JFET transistors operate in the resistive region rather than the saturation region of the drain-to-source voltage characteristic. The JFET transistor operates as a voltage controlled resistor rather than as a gate-to-source voltage (V _GS) resistive current source.

The above and other objects and advantages of the present invention will become more apparent from the following description of the preferred embodiments thereof, taken in conjunction with the accompanying drawings. The accompanying drawings are incorporated in and constitute a part of this specification, in which:

FIG. 1 is a block diagram illustration of an electricity meter that may be employed with the present invention:

FIG. 2 is a more detailed block diagram of an ammeter op-amp for use in the ammeter of FIG. 1;

FIG. 3 is a schematic diagram of an ammeter op amp as a voltage measurement circuit;

FIG. 4 is a schematic diagram of an ammeter op amp as a current measurement circuit;

FIG. 5 is a schematic illustration of a prior art MOSFET input stage;

FIG. 6 is a schematic illustration of a prior art JFET source output input stage;

Fig. 7 is a schematic illustration of a JFET resistance amplifier according to the invention;

FIG. 8 is a graphical representation of leakage current in microamps (μA) versus drain-source voltage in volts (V), useful in describing the invention herein;

FIG. 9 is a schematic diagram of the equivalent circuit of FIG. 7, useful in describing the present invention;

fig. 10 is a schematic circuit diagram of an ammeter op-amp using a JFET input stage in accordance with the present invention.

Referring to the drawings, the showings are for the purpose of illustrating preferred embodiments only and not for the purpose of limiting the same. Fig. 1 illustrates a block diagram of the components used in an electricity meter to which the present invention is applied. It includes an ammeter OP AMP or OP-AMP10 for receiving an input signal from the test circuit and giving an output in the form of either current (for ampere-timing) or voltage (for volt-timing). Appropriate feedback elements and switching circuitry 12 are used to determine whether the meter is to be used as an ammeter or voltmeter. The output voltage of the operational amplifier 10 is applied to an analog-to-digital converter 14, which output voltage is converted to digital form and transmitted through a programmed microprocessor 16 to an appropriate display 18. In addition, a keyboard or the like may be used to determine the manner in which the meter is operating, such as a voltmeter or ammeter, by the microprocessor selecting the operating state of the feedback element and switching circuit 12.

The ammeter operational amplifier 10, as shown in fig. 2, includes an input stage 20, a gain stage 22, and an output stage 24. The input stage is here a critical point, which employs a high input impedance, low leakage current JFET differential amplifier. The output stage of the amplifier is coupled to a gain stage 22, for example an integrated circuit operational amplifier may be used to obtain high gain, low noise, low compensation drift and suitable frequency response characteristics. The output stage 24 provides the necessary voltage and current compliance to achieve the various test functions of the meter. It is the input stage that determines the quality of the meter in a large scale measurement, and the following discussion will be directed to this.

Consider first the simplified diagram of fig. 3, which shows the ammeter operational amplifier 10 connected as a voltage measurement circuit, with an input voltage V _h applied between ground and the positive or non-inverting input of the operational amplifier. As long as the gain is very high, e.g. in the order of magnitude of 100,000, the output voltage V _OUT is proportional to the differential between the inputs.

The current measurement scheme for an ammeter op amp is shown in fig. 4, where input power I _in is applied to the inverting input of the op amp. The output of the operational amplifier is connected to the inverting input through a feedback resistor R _F. It should be noted that the non-inverting input of the operational amplifier is connected to ground. As shown in fig. 4, the output voltage V _suT is a representative value of the measured current, and its error depends on the magnitude of the input bias current I _BIAS. Thus, the input bias current should be added to the input current I _in in the ammeter circuit. Therefore, the bias current I _BIAS should be much smaller than any measured current. For this reason, the input stage of the meter greatly affects the quality of operation, since any errors will be transmitted through the gain stage and the output stage.

Turning now to fig. 5, a prior art MOSFET input stage for use in an ammeter op amp is shown. This is representative of the circuitry described above for use in patent number 3,654,468 to iran, as an example. The circuit includes a pair of differentially connected MOSFET transistors 30 and 32. The pair of MOSFET transistors are of a general type and may be of either P-channel or N-channel type. In either case, the drains are connected together to form a drain bias voltage V _DD. The sources of which are connected to a point through resistors 34, 36 and then to a source voltage V _SS. The gate is an input terminal and the source is a differential output terminal. Since MOSFET differential amplifiers are sensitive to overload conditions, input protection circuitry 40 is provided as is discussed above in the U.S. patent No. 3,654,468 to israel. The MOSFET differential amplifier shown in fig. 5 provides the desired low input bias current and high input impedance to the input stage of the ammeter operational amplifier. However, this circuit requires an input protection circuit 40, which is a well-designed actual circuit. The protection circuit affects the voltage and time response.

In operation, the MOSFET differential amplifier operates in the saturation region of a known current-voltage characteristic, as will be discussed below. In this case, the drain-to-source voltage V _DS is maintained at a level so that it is greater than V _GS-V_GSOFF, where V _GSOFF is the value of the gate-to-source voltage when the leakage current established by the manufacturer is substantially zero, which is typically 1 to 10 nanoamperes (nA).

Referring to fig. 6, a JFET source output differential amplifier as an input stage of an ammeter op amp of the prior art is shown. It may be an N-type channel or a P-type channel, the polarity of which is not shown in fig. 6, which illustrates that both types may be used. The circuit includes a pair of JFET transistors 50 and 52 having their drains connected together and commonly connected to a drain bias voltage V _DD. The gates thereof serve to receive differential inputs and a current limiting resistor 54 is provided on the gate circuit of transistor 50 to limit gate-to-source current during overload. The source of which is connected through load resistors 56 and 58 to a node connected to source voltage V _SS. As shown, a differential output is available from the sources.

The JFET differential amplifier functions as a source-to-gate output because the drain-to-source voltage V _GS is greater than V _GS-V_GSA. The JFET transistor acts as a current source proportional to the gate-source voltage V _GS. Thus when the input gate voltage changes, the leakage current is unbalanced, which is amplified by the source resistors 56 and 58 and produces a differential output. The JFET differential amplifier has many improvements in voltage characteristics over the MOSFET amplifier of fig. 5. JFET amplifiers improve immunity to damage caused by overload or electrostatic discharge and reduce noise, improving stability against temperature and time variation compensation. But has the disadvantage that the input bias current characteristic of JFET is much higher in value than that of MOSFET, for example its input bias current is 10 times higher in value.

Having discussed prior art implementations of the meter input stage of fig. 5 and 6, a view will now be made of JFET resistive differential amplifiers constructed in accordance with the present invention and shown in fig. 7. Fig. 8 shows a characteristic curve of leakage current versus drain-source voltage, and fig. 9 shows an equivalent circuit of a JFET resistance differential amplifier.

The JFET resistance differential amplifier is similar in structure to the JFET source output amplifier, with the main difference being that the drain-to-source voltage V _DS is less than the voltage V _GS-V_GSOFF. The circuit includes a pair of JFET transistors 60 and 62 having their drains connected together to be commonly connected to a drain bias voltage V _DD. A current limiting resistor 64 is connected to the gate of transistor 60 and applies a differential input to the gate. The source is connected to a midpoint leading to voltage V _SS through load resistors 66 and 68.

Although the circuits of fig. 6 and 7 are similar in structure, it should be emphasized that the drain-to-source voltage V _DS is less than V _GS-V_GSOFF in fig. 7. Thus, the JFET transistor in fig. 7 is not proportional to V _GS as in fig. 6, but is a bridge voltage controlled resistor as in the equivalent circuit of fig. 9. Lowering the drain-source voltage V _DS below V _GS-V_GSOFF results in reduced gate channel leakage as V _DG and V _GS change.

Turning now to fig. 8, a JFET transistor operating curve of leakage current I _D versus drain-source voltage V _DS is shown for various gate-to-source voltages V _S. There are two distinct operating regions, a resistive region and a saturation region, separated by a dashed line 70 as shown in fig. 8. In this example, resistive region 72 is to the left of the dashed line and saturation region 74 is to the right of dashed line 70. The characteristic curves include 76, 78, 80, and 82, representing a gate-source voltage V _GS of 0 volts, -0.1V, -0.2, and-0.5V, respectively. The dashed line 70 may be defined as:

V_DS＝V_GS-V_GSOFF

As long as the drain-source voltage V _DS is greater than V _GS-V_GSOFF, the transistor operates as a current source, the value of which depends on V _GS. This is the normal operating region of the JFET transistor as shown in fig. 6.

Each point at which the curves 76-82 intersect the dashed line is considered to be the pinch-off voltage V _P for the gate-source voltage at the corresponding voltage level. When V _GS＝V_GSOFF, the leakage current I ₀ is substantially within the nominal approximately zero (1.0 to 10 nanoampere nA). The leakage current I _D is shown as curve 84, with V _GSOFF at a level of-1.27V.

When the circuit of fig. 7 is plus drain-to-source voltage V _DS and its value is less than V _GS-V_GSOFF, the JFET transistor operates in region 72 of the fig. 8 characteristic and acts as a resistor whose resistance depends on the gate-to-source voltage V _GS. In the equivalent circuit, where the gate-source voltage in fig. 7-10 is much less than the absolute value of V _GSOFF, the JFET channel resistance is seen as variable resistors R _DS1 and R _DS2 representing JFET resistors 60 and 62, respectively, operating within the characteristic resistance region 72. Resistor R _DS is equal to I _D divided by V _GS. If the input signal V _GS changes, a change in the channel resistance R _DS will be caused. For this reason, the bridge arms have to be matched. Thus, the resistors 66 and 68 match each other and act as fixed arms of the bridge, each resistor having a resistance 20 times the JFET channel resistance. That is, the JFET can be placed with a very low gate-to-channel voltage, and the bridge supply should be bootstrap for the gate of the JFET. When the circuit is used as an input stage of an operational amplifier with feedback, the two gates of the non-inverting and inverting inputs will in fact maintain the same voltage. The bridge remains biased at the same operating point almost all the time except for the amount of change that must be made to the op amp output to increase the gate voltage, which is typically a few hundred microvolts or less. From the above equations can be derived to calculate the gains of V _DS and JFET, equations (1) and (2) are as follows:

Where R _S = channel series resistance, K depends on the particular device used (K value about 1.5) and

Equations (1) and (2) are important to the practice of the present invention to ensure that the gate channel junction is reverse biased under all operating conditions and to determine the gain of the circuit. The number of stages of the gain determining circuit is determined due to the total error of the second stage error shadow circuit. Knowing that the increase in leakage current and the decrease in gain will vary from bias point to bias point, the correct leakage versus voltage scheme can be determined for the circuit application.

The circuit implementation of the ammeter op-amp is based on the block diagram in fig. 2, but is shown in fig. 10 with respect to the combined features shown in fig. 7, and includes an input stage 20', a gain line 22' and an output stage 24 'along with feedback and switching element 12'. The input stage 20' is constructed in accordance with fig. 7 and therefore uses like reference numerals to identify like devices. Thus, the JFET resistor amplifier includes a pair of JFET transistors 60 and 62 having their drains connected together and commonly connected to a drain bias voltage V _DD. The source is connected to a source bias voltage V _SS through matched load resistors 66 and 68. An input protection resistor 64 connects the input to the gate of transistor 60. Two bias voltages are derived from dc voltage sources V _1A and V _1G, each 5 volt bootstrap power supply. The source bias voltage V _SS is derived from the negative terminal of the dc supply V _1G and the drain bias voltage V _DD is derived from the junction of the resistors 85 and 86 across the voltage supply V _1A. In this arrangement, the resistors are selected to separate the voltage V ₁ so that the value of V _DD is 0.4 volts. The differential output of the JFET differential amplifier is taken from its source and applied to an operational amplifier 87 connected as in fig. 10, while its output is applied as a control reference to the base of NPN transistor 88 and the base of PNP transistor 89. When the output of the operational amplifier 87 is positive, the transistor 88 is turned on. When the output of the operational amplifier 87 is negative, the transistor 89 is turned on. To allow voltage measurements up to 200 volts, the output stage uses 220 volts dc sources V _2A and V _2B.

The feedback and switching network 12' includes a feedback resistor 90 that is placed in the circuit only to measure current when the switch 92 is closed, as shown. Also in this condition, the two-pole one-volt switch is in the position shown so that the gate of JFET62 is grounded when measuring current.

In the example of fig. 10, the source or load resistors 66 and 68 are a set of matched resistors each having a resistance of 200K ohms and establish a bias current near the zero drift operating point at a value of I _D = 25 microamps. The drain bias voltage V _DD is established at 0.4 volts, which ensures that the source voltage V _S1 and the source voltage V _S2 are greater than 100 millivolts, so that the forward bias of the junction is prevented despite any device changes. The choice of drain voltage V _DD also provides a minimum gain of 0.24, which determines a maximum drift of 28.4 microvolts per degree celsius and a maximum noise of 9.8 microvolts peak-to-peak in the range from 0.1 to 10HZ, and provides a 3.8 to 14-fold reduction in leakage compared to the JFET source output, as shown in fig. 6. Furthermore, the circuit of FIG. 10 brings the input bias current to 5X 10 ^-15 A at 23 ℃.

Having described the invention with reference to the preferred method, it is needless to say that various modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (5)

1. JFET differential amplifier, including: The first and second JFET transistors, whose drains are connected together, a first and a second resistor, which are respectively connected to the source of the transistor and connected to form a junction, An input circuit connected to the gate of the transistor and an output circuit connected to the source of the transistor. means for applying a DC bias voltage Vss to the node in order to bias the source through the resistor, A device for providing a DC drain bias voltage _VDD to the commonly connected drains, characterized in that: The bias voltage supply device provides a voltage of a selected value so that the JFET transistor operates in the resistance region of the drain current ID _- drain-source voltage _VDS characteristic curve, thereby acting as a voltage-controlled resistor whose resistance varies with the gate-source voltage _VOS . 2. A JFET differential amplifier as claimed in claim 1 further characterized in that said bias voltage supply means provides a bias voltage of a value selected so as to operate each JFET transistor in a state where its drain-source voltage V _DS is less than V _DS - V _DSOFF voltage, wherein V _OSOFF is the gate-to-source voltage when said JFET transistor is rated to have substantially no leakage current. 3. A JFET differential amplifier as claimed in claim 2, further characterized in that said first and second resistors have equal resistance values. 4. A JFET differential amplifier as claimed in claim 3, further characterized in that the resistance of said first and second resistors is larger than the channel resistance of said first and second transistors, respectively. 5. A JFET differential amplifier as claimed in claim 4 further characterized in that the resistance value of each of said first and second resistors is twenty times the channel resistance value of each of said first and second transistors.

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