CN100484042C - Method and apparatus for message payload transparent transmission logic verification - Google Patents

Abstract

The invention discloses a method and device for verifying message payload transparent transmission logic. The method mainly includes: generating each payload value of a message input at the input terminal of a logic device according to a predetermined algorithm; and verifying the logic device sequentially according to the predetermined algorithm The output terminal outputs each payload value of the message, and if each payload value of the output message complies with the predetermined algorithm, it is confirmed that the verification is passed; otherwise, it is confirmed that the logical device has a logic error. The device mainly includes a logic verification message generating unit and a logic verification unit. Since the present invention only needs to process the data with a predetermined algorithm at the input end of the logic device, and only needs to verify whether each payload value of the output message conforms to the predetermined algorithm at the output end, it can determine whether the logic of the logic device is correct, which can improve the verification speed and correct the error rate. The test is accurate.

Description

Method and device for verifying message payload transparent transmission logic

technical field

The invention relates to the technical field of communication testing, in particular to a method and device for verifying message payload transparent transmission logic applied in large-scale logic chips.

Background technique

In the prior art, a message refers to an information unit transmitted from a sender to a receiver. The composition of the message mainly includes the following parts: message header + payload + message tail, for example, the Ethernet message format is as follows:

Destination address (6 bytes) Source address (6 bytes) type (2 bytes) Data (46~1500 bytes) CRC (4 bytes)

Wherein, the destination address, source address and type field are the header of the message, the data field is the payload, the length of the payload is variable, and the CRC is the tail of the message.

The logic chip is a chip designed to realize specific logic functions. For example, many large-scale logic chips are used in switching services to realize switching logic functions. Many existing large-scale logic chips directly forward the payload part of the transmitted message, that is, the logic chip transparently transmits the message payload without processing. This feature can be used to check whether the large-scale logic chip is working normally.

The prior art mainly adopts two methods to realize the verification of message payload transparent transmission logic: a direct comparison method and a CRC32 check method (cyclic redundancy check method).

Using the direct payload comparison method, it is necessary to first store the payload content of the message input from the input terminal of the logic chip, and then directly compare the payload content of the message output by the logic chip with the payload content of the stored input message byte by byte for verification , after comparison, if the two are consistent, the verification is passed, otherwise, the logic chip is faulty.

This message payload transparent transmission logic verification method has the following disadvantages:

The direct comparison method needs to store the message payload content of the input logic chip. When verifying at the output terminal of the logic device, the saved input message payload content is first read, and then compared with the output message payload content byte by byte. In comparison, operations such as reading the saved message payload content from the storage device and comparing input and output messages byte by byte are time-consuming, thus affecting the verification speed. For example, when used in a simulation system, the simulation speed will be greatly reduced.

Further, the CRC32 check method can be used to carry out logical verification of message payload transparent transmission, which mainly adopts the following steps to realize logical verification:

First, construct the input message at the input end of the logic device, where the message payload consists of two parts: the last four bytes of the payload (CRC32 part), all the message payload bytes except the last four bytes of the payload (data part);

The content of the CRC32 part is the check code calculated by the CRC32 calculation of the data part. Specifically, the CRC check code can be obtained by dividing the binary value of the data stream by a constant, the quotient is discarded, and the remainder is used as the CRC check code Append to the end of the data stream to generate a new data stream for sending;

Similarly, at the receiving end, the new data stream is removed by the same constant, and it is checked whether the remainder is a constant (usually 0). If the remainder is a constant, it is considered that the transmission is correct, otherwise it is considered that an error has occurred in the transmission.

Using the CRC32 check method to perform logical verification of message payload transparent transmission has the following disadvantages:

Since the CRC32 verification method requires the input and output terminals of the logic device to perform CRC32 algorithm processing bit by bit, due to the complexity of the CRC32 algorithm processing, the implementation workload is relatively large. Section) data errors can be completely detected, but for data errors larger than 32 bits (4 bytes) in data transmission, it cannot be completely detected.

Contents of the invention

The technical problem solved by the present invention is to provide a verification method and device for message payload transparent transmission logic with accurate verification and fast verification speed. Using the method and device, the message payload transparent transmission of large-scale logic chips Pass logic verification will be faster and more accurate.

In order to solve the above problems, the verification method of message payload transparent transmission logic of the present invention comprises the following steps:

A. Generate each payload value of the input message at the input terminal of the logic device according to a predetermined algorithm;

B. sequentially judge whether the adjacent payload values in the output message of the logic device output conform to the predetermined algorithm, if each payload value of the output message conforms to the predetermined algorithm, then confirm that the verification is passed, Otherwise, it is confirmed that the logic device has a logic error.

Wherein, the input message in step A is a message of a stream, and the last payload value of the previous message and the first payload value of the immediately following message of the stream also conform to the predetermined algorithm.

Wherein, the verification described in step B specifically includes steps:

B1. Read a payload value;

B2. Continue to read the next payload value;

B3. Judging whether the previous payload value and the next payload value conform to the predetermined algorithm, if they conform to the predetermined algorithm, then go to B4, otherwise, go to B5;

B4, judge whether each payload value of the output message has all been verified, if all verified, then confirm that the verification is passed, otherwise, keep the last payload value, and then return to B2;

B5. Confirm that the logical device has a logic error, and exit the verification.

Wherein, each payload value of the input message in the step A is generated according to byte, word or double word.

Wherein, the predetermined algorithm is an incremental algorithm.

Correspondingly, the verification device of the message payload transparent transmission logic of the present invention includes:

The logic verification message generation unit is connected to the input terminal of the logic device, and is used to generate each payload value of the input message at the input terminal of the logic device according to a predetermined algorithm;

The logic verification unit is connected to the output terminal of the logic device, and is used to sequentially judge whether the adjacent payload values in the output message of the output terminal of the logic device conform to the predetermined algorithm, if each payload value of the output message If it conforms to the predetermined algorithm, it is confirmed that the verification is passed; otherwise, it is confirmed that the logical device has a logic error.

Wherein, the input message is a message of a flow, and the last payload value of the previous message of the flow and the first payload value of the immediately following message of the flow also conform to the predetermined algorithm.

Wherein, the logic verification unit includes:

The reading module is used to sequentially read each payload value of the output message;

The first judging module is used to judge whether a payload value read by the reading module and the next payload value read by the reading module conforms to the predetermined algorithm, and if it conforms to the predetermined algorithm, the judgment is true, Otherwise, the judgment is false, and the logical device logic error is confirmed;

The second judging module, if the judgment of the first judging module is true, then further judge whether each payload value of the output message has been verified completely, if all verified, then confirm that the verification is passed, otherwise, keep the latter payload value, the reading module continues to read the next payload value and hand it over to the first judging module to continue judging.

Wherein, the logic verification message generation unit generates each payload value of the input message according to byte, word or double word.

Wherein, the predetermined algorithm is an incremental algorithm.

Compared with the prior art, the present invention has the following advantages:

On the one hand, compared with the direct comparison method, the present invention does not need to save the input message at the input terminal of the logic device, does not need to read the operation of the input message, and does not need verbatim between the input message and the output message payload content. The operation of section comparison can improve the verification speed. If it is applied to logic verification simulation and test, the test speed will be much faster than the direct comparison method;

On the other hand, compared with the CRC32 algorithm, the present invention only needs to perform predetermined algorithm processing on the data at the input end of the logic device, and only needs to verify whether each payload value of the output message conforms to the predetermined algorithm at the output end to determine whether the logic device logic is Correct, because the CRC32 algorithm needs to avoid the cumbersome processing operations of data processing at the input and output terminals of the logic device, the verification speed can be improved;

Further, the present invention detects the payload of the output message according to the predetermined algorithm and can fully guarantee that the verification is correct, therefore, avoiding the situation that the CRC32 algorithm is theoretically only in the process of logical device data forwarding and is less than 32 bits (4 bytes) in error In order to ensure the detection of wrong shortcomings.

Description of drawings

Fig. 1 is a schematic diagram of the composition of the verification device of the message payload transparent transmission logic of the present invention;

Fig. 2 is a schematic diagram of the composition of the logic verification unit shown in Fig. 1;

Fig. 3 is a flow chart of a specific embodiment of the method for verifying message payload transparent transmission logic of the present invention.

Detailed ways

Referring to Fig. 1, Fig. 1 is a schematic diagram of the composition of the verification device of the message payload transparent transmission logic of the present invention, and the verification device mainly includes: a logic verification message generating unit 11 and a logic verification unit 12, which are respectively described as follows:

Logic verification message generation unit 11, which is mainly used to generate each payload value of the input message at the input terminal of the logic device according to a predetermined algorithm, which can be by byte, or by word or double word as a unit to generate the input message Text payload, the predetermined algorithm can adopt incremental algorithm, etc.;

Logic verification unit 12, which is mainly used to verify each payload value of the output message of the logic device output according to the predetermined algorithm, if each payload value of the output message conforms to the predetermined algorithm, then confirm that the verification is passed, Otherwise, it is confirmed that the logic device has a logic error.

Optimized, when the logic verification message generation unit 11 generates the message payload, if the input message is a message of a flow, each payload value of the message of the flow is generated according to the predetermined algorithm, in addition, the flow of the message The payload value between adjacent messages is also generated according to the predetermined algorithm, that is, it is necessary to ensure that the payload value of the same message conforms to the predetermined algorithm, and the last payload value of the previous message of the same flow and the tight The first payload value of the following message also complies with the predetermined algorithm.

The logic verification unit 12 is described below, with reference to Fig. 2, the logic verification unit 12 mainly includes: a reading module 121, a first judging module 122 and a second judging module 123, specifically as follows:

The reading module 121 is mainly used to sequentially read each payload value of the output message;

The first judging module 122 is mainly used to judge whether a payload value read by the reading module 121 and the next payload value that the reading module 121 continues to read subsequently conform to a predetermined algorithm, and if it conforms to a predetermined algorithm, then The judgment is true, otherwise the judgment is false, and the logical device logic error is confirmed;

The second judging module 123, if the judgment of the first judging module 122 is true, then further judge whether each payload value of the output message has been verified, if all verified, then confirm that the verification is passed, otherwise, keep the latter For the payload value, the reading module 121 continues to read the next payload value and hand it over to the first judging module 122 to continue judging.

A relatively simple example is given below to illustrate the verification method of the message payload transparent transmission logic of the present invention.

Assuming that the input message at the input terminal of the logic device is pkt1, and the message output at the output terminal of the logic device after logic processing is pkt2, at first, each payload value of the input message pkt1 is generated according to a predetermined algorithm, and the generated same message is The payload value conforms to the predetermined algorithm. As an example, the predetermined algorithm can use an incremental algorithm: next_data=data+1, and the respective payload values of the input message generated according to the algorithm are as follows:

pkt1: 0, 1, 2. . . 14

Further, at the output terminal of the logic device, verify each payload value of the output message according to the predetermined algorithm, that is, verify whether the payload value of the message pkt1 output after logical processing conforms to the predetermined algorithm, if it meets the stated Predetermined algorithm, if the message payload has not been processed by the logic chip, it can be determined that the message payload transparent transmission logic of the logic chip is correct, that is, the output message payload is the same as the input message payload, and each of the output message pkt2 The payload values are as follows:

pkt2: 0, 1, 2, 3. . . 14

If the payload value of the output message changes, for example, the payload value 2 of the output message pkt2 is changed to 3, as shown below:

pkt2: 0, 1, 3, 3. . . 14

Since the previous payload value is 3 and the latter payload value is also 3, it does not conform to the predetermined algorithm (3=2+1). Therefore, it can be determined that the logic chip is faulty, and the chip message payload transparent transmission logic is faulty.

Continuing to explain the method of the present invention, the invention is equally applicable to the message text of the same stream, and the stream refers to a plurality of messages with some identical characteristics; as for the previous Ethernet message, the message with the same DMAC value can be As a stream, when the method of the present invention is applied, each payload value of the same message of the stream conforms to the predetermined algorithm, the last payload value of the previous message of the same stream and the following The first payload value of a message also complies with the predetermined algorithm.

Referring to Fig. 3, a typical embodiment is used for illustration, the predetermined algorithm still adopts the incremental algorithm: next_data=data+1:

Assuming that the five messages of the same flow input by the input terminal of the logical device are pkt1-pkt5, in step 31, the payloads of the five input messages are generated according to the incremental algorithm, and the payload values of the payloads of each message are respectively

pkt1: 0, 1, 2. . . 14

pkt2: 15, 16, 17, 18. . . 89

pkt3: 90, 91, 92, 93. . . 123

pkt4: 124, 125, 126. . . 174

pkt5: 175, 176, 177. . . 247

The payload value of each of the above messages conforms to the incremental algorithm, such as 16=15+1, 17=16+1; the payload value between the packets of the same flow also conforms to the incremental algorithm, such as 15=14+1 , 90=89+1. In this way, after processing by the logic device, in step 32, when the message is output at the output terminal of the logic device, each payload value of the output message is verified according to the incremental algorithm, and the verification mainly includes the following processes:

In step s321, read a payload value;

Then in step s322, continue to read the next payload value;

Further, in step s323, it is judged whether the previous payload value and the latter payload value conform to the predetermined algorithm, if they conform to the predetermined algorithm, then enter step s324, otherwise, enter step s325, confirm that the logic device has a logic error, and exit the verification;

Wherein step s324, judge whether each payload value of the output message has all been verified, if all verified, then enter step s326, confirm that the verification is passed, otherwise, in step s327, only keep the last payload value, then return to step s322.

For example:

1) Assuming that the payload value 17 of pkt2 is changed to other values such as 45 after logical processing, since it does not meet 45=16+1, it can be judged that the payload value 45 is incorrect and the logical device is wrong;

2) Assuming that the payload value 16 of pkt2 is discarded, since it does not meet 17=15+1, it can be judged that the payload value 17 is incorrect and the logic device is wrong;

3) Assuming that the entire message of pkt2 is discarded, since it does not conform to 90=14+1, it can be judged that the payload value 90 is incorrect and the logical device is wrong.

It can be seen that the present invention can conveniently and accurately judge whether the logic device processes the payload of the message correctly, and at the same time does not need to compare the payload content of the message at the output end with the payload content of the message at the input terminal byte by byte.

The predetermined algorithm in the above embodiment is described by using the incremental algorithm as an example. In fact, other algorithms can also be used in the present invention, such as the decreasing algorithm or the random function rand() algorithm. repeat.

In addition, the above-mentioned generation of the input message payload according to the predetermined algorithm may be in units of bytes, words, or double words, and verification is also performed in units of said units during corresponding verification.

The verification method of the message payload transparent transmission logic of the present invention mainly generates each payload value of the input message at the input end of the logic device through a predetermined algorithm, and then uses the predetermined algorithm to verify the payload of the output message at the output end of the logic device. If each payload value of the message complies with the predetermined algorithm, it is confirmed that the verification is passed; otherwise, it is determined that the logic of transparent transmission of the message payload is wrong. Since there is no need to compare the payload content of the input message with the payload content of the output message byte by byte, and there is no cumbersome processing of the CRC32 algorithm, it can ensure that the speed of logic verification simulation and testing is better than that of the existing technology .

The above only describes the present invention with preferred embodiments, and does not therefore limit the scope of rights of the present invention. Therefore, without departing from the idea of the present invention, all equivalent changes made by using the description and accompanying drawings of the present invention are all It is equally included in the scope of the claims of the present invention.

Claims (10)

1, a kind of verification method of message payload transparent transmission logic, it is characterized in that, described method comprises the steps: A. Generate each payload value of the input message at the input terminal of the logic device according to a predetermined algorithm; B. sequentially judge whether the adjacent payload values in the output message of the logic device output conform to the predetermined algorithm, if each payload value of the output message conforms to the predetermined algorithm, then confirm that the verification is passed, Otherwise, it is confirmed that the logic device has a logic error. 2. The verification method of message payload transparent transmission logic according to claim 1, wherein the input message in step A is a message of a flow, and the last payload of the previous message of the flow value and the first payload value of the immediately following message also conform to the predetermined algorithm. 3. The verification method of message payload transparent transmission logic according to claim 1 or 2, wherein the verification described in step B specifically includes the following steps: B1. Read a payload value; B2. Continue to read the next payload value; B3. Judging whether the previous payload value and the next payload value conform to the predetermined algorithm, if they conform to the predetermined algorithm, then go to B4, otherwise, go to B5; B4, judge whether each payload value of the output message has all been verified, if all verified, then confirm that the verification is passed, otherwise, keep the last payload value, and then return to B2; B5. Confirm that the logical device has a logic error, and exit the verification. 4. The method for verifying message payload transparent transmission logic according to claim 3, characterized in that, in the step A, each payload value of the input message is generated according to byte, word or double word. 5. The method for verifying message payload transparent transmission logic according to claim 3, wherein the predetermined algorithm is an incremental algorithm. 6. A verification device for message payload transparent transmission logic, characterized in that it comprises: The logic verification message generation unit is connected to the input terminal of the logic device, and is used to generate each payload value of the input message at the input terminal of the logic device according to a predetermined algorithm; The logic verification unit is connected to the output terminal of the logic device, and is used to sequentially judge whether the adjacent payload values in the output message of the output terminal of the logic device conform to the predetermined algorithm, if each payload value of the output message If it conforms to the predetermined algorithm, it is confirmed that the verification is passed; otherwise, it is confirmed that the logical device has a logic error. 7. The device for verifying message payload transparent transmission logic according to claim 6, wherein the input message is a message of a flow, and the last payload value of the previous message of the flow is the same as The first payload value of the immediately following message also complies with the predetermined algorithm. 8. The device for verifying message payload transparent transmission logic according to claim 6 or 7, wherein the logic verification unit includes: The reading module is used to sequentially read each payload value of the output message; The first judging module is used to judge whether a payload value read by the reading module and the next payload value read by the reading module conforms to the predetermined algorithm, and if it conforms to the predetermined algorithm, the judgment is true, Otherwise, the judgment is false, and the logical device logic error is confirmed; The second judging module, if the judgment of the first judging module is true, then further judge whether each payload value of the output message has been verified completely, if all verified, then confirm that the verification is passed, otherwise, keep the latter payload value, the reading module continues to read the next payload value and hand it over to the first judging module to continue judging. 9. The verification device of message payload transparent transmission logic according to claim 8, characterized in that, the logic verification message generation unit generates each payload value of the input message according to byte, word or double word. 10. The device for verifying message payload transparent transmission logic according to claim 8, wherein the predetermined algorithm is an incremental algorithm.

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