CN100458757C - Inter core communication method and apparatus for multi-core processor in embedded real-time operating system - Google Patents

Abstract

The invention discloses an inter-core communicating method of multi-core processor in embedded real time operation system. It includes following steps: distributing memory as multi-core information sharing pool; writing information the source core would send into the pool; sending the information to target core; target core sending the information storing in pool to target mission. The invention also discloses an inter-core communicating device. It improves the inter-core communicating efficiency and realizes the unification of inner core communication and inter-core communication.

Description

Inter-core communication method and device of multi-core processor in embedded real-time operating system

technical field

The invention relates to an embedded real-time operating system and a multi-core processor, in particular to an inter-core communication method and device for a multi-core processor in an embedded real-time operating system.

Background technique

With the rapid development of network and computer technology, the performance requirements of CPU (Central Process Unit, central processing unit) are getting higher and higher. In the past, the improvement of CPU performance was mainly realized by increasing the main frequency, and the increase of the main frequency required a substantial increase in the number of transistors, and the ensuing heat dissipation problem became increasingly prominent. In addition to increasing the main frequency, another way to improve CPU performance is the multi-core processor.

A multi-core processor integrates more than two computing units on one processor, and each computing unit becomes a core, so that one CPU can provide performance close to that of multiple CPUs. Each core in the multi-core processor runs its own task, and often needs to transmit data information (commonly referred to as message delivery) between tasks on multiple cores. In the prior art, passing data between multiple cores pipes for communication.

Figure 1 shows the structure of a multi-core processor with two cores, core M 110 and core N 120. Core M 110 and core N 120 have their own dedicated memory areas 130 and 140 respectively, and there is a shared memory area between the two cores 170. Each core is assigned a data pipeline for sending data to other cores in the shared memory area 170. Since the data pipeline is unidirectional, there is a core M to core N data pipeline 180 allocated by the core M 110 in the shared memory area 170. and core N allocated core N to core M data pipeline 190 . Each core stores a static routing table in a dedicated memory area that points to data pipes to other cores. Core M 110 and core N120 have their own virtual interrupt modules 150 and 160 respectively, any one of the cores can trigger a virtual interrupt of the core by operating the virtual interrupt module of the target core, and the interrupt notifies the target core that there is new data in the data channel arrival.

When a source task on the core M 110 sends a message to a destination task on the core N 120, the core M 110 queries the routing table in the dedicated memory area 130, finds the core M to core N data pipeline 180, and will transfer the data of the message Information is copied from the dedicated memory area 130 to the core M to core N data pipeline 180; at the same time, the core M 110 uses the internal virtual interrupt to shake hands with the core N 120 through the virtual interrupt module 160 of the core N 120, and transfers the target task identification and message identification . The core N 120 responds to the virtual interrupt, copies the data information of the message from the core M to the core N data pipeline 180 into the dedicated memory area 140 according to the target task identification, packs it into a message and delivers it to the target task.

In the prior art, the inter-core communication of multi-core processors has the following problems:

The length of a message transmitted between cores is limited: since the data pipeline is fixedly allocated in the shared memory area and always occupies the shared memory area, it is usually impossible for the data pipeline to allocate a large amount of memory; The possibility of writing conflicts requires the design of the data pipeline to have a certain depth, that is, it can accommodate multiple messages, so that the length of each message is limited, and the general inter-core communication can only transmit messages with a small amount of data;

Low efficiency of inter-core communication: From the above message sending process, it can be seen that to complete an inter-core communication, all data of the message needs to be copied twice, which greatly reduces the efficiency of inter-core communication;

The communication methods of intra-core tasks and inter-core tasks are different: ERTOS (Embedded Real Time Operating System, embedded real-time operating system) provides a message queue mechanism for inter-task communication within a core; Language is a virtual I/O (input and output) device, which uses the communication mechanism provided by the driver, which makes the development of application programs extremely inconvenient.

Contents of the invention

The present invention aims to solve the problems of low inter-core communication efficiency of the existing multi-core processor, limited message length for one communication transfer, and inconsistency of intra-core communication and inter-core communication.

The inter-core communication method of the multi-core processor in the embedded real-time operating system of the present invention comprises the following steps:

a) allocate memory in the shared memory area as a multi-core shared message pool;

b) The source core allocates a multi-core message memory block in the multi-core shared message pool for writing the message

c) The source core writes the message to be sent into the multi-core shared message pool;

d) The source core sends the address of the message in the multi-core shared message pool and the target task identifier to the target core through the data pipeline;

e) The destination core transmits the message stored at the address in the multi-core shared message pool to the destination task;

f) After the destination task receives the message, the destination core releases the multi-core message memory block occupied by the message from the shared message pool.

In addition, the shared memory area of the multi-core processor is provided with a data pipeline for inter-core communication.

Preferably, the multi-core message memory block includes a header information area and a data area, wherein the header information area is used to store header information, and the header information includes the size of the multi-core message memory block and the task identifier to which it belongs , the data area is used to store the data of the message;

The message memory block of the single-core message pool of the embedded real-time operating system has the same format as the header information of the multi-core message memory block.

Preferably, step e) specifically further includes: the destination core puts the address of the message in the multi-core shared message pool into the message queue of the destination task.

Preferably, between said step a) and step b), it specifically further includes:

The source core indicates the target core ID and the target task ID of the message;

Judging whether the target core identification is identical to the source core identification, if identical, the message is sent to the purpose task by the message sending function in the single core provided by the embedded real-time operating system, and the step b) is not performed, c), d), e); if different, perform steps b), c), d), e).

Preferably, said step a) includes before: uniformly numbering all tasks running on the multi-core processor and recording the identification of the core running the task;

Between said step a) and step b), it also specifically includes:

The source core indicates the destination task number of the message;

Judging whether the purpose task is running on the source core, if so, the message is sent to the purpose task by the message sending function in the single core provided by the embedded real-time operating system, and the steps b) and c are not performed ), d), e); if not, perform steps b), c), d), e).

Preferably, when the source core of the message is different from the target core, before the step b) includes: the source core locks the spin lock of the multi-core shared message pool;

The steps between step b) and step c) include: the source core releases the spin lock of the multi-core shared message pool.

Preferably, when the source core of the message is different from the target core, after the step e) and before the step f), include: the target core locks the spin lock of the multi-core shared message pool;

After the step f), it includes: the target core releases the spin lock of the multi-core shared message pool.

Preferably, the step d) is specifically:

The source core copies the address and the target task identifier of the message in the multi-core shared message pool to the data pipeline;

The source core triggers the virtual interrupt of the destination core;

The destination core responds to the virtual interrupt, and copies the address and destination task identifier of the message in the multi-core shared message pool from the data pipeline.

The present invention also provides an inter-core communication device of a multi-core processor in an embedded real-time operating system, including a core, an inter-core communication control module, a virtual interrupt module, an inter-core message module, and a shared memory area, where:

The inter-core message module writes the message to be sent into the multi-core shared message pool according to the sending instruction of the core, and returns the address of the sent message in the multi-core shared message pool to the core; The address of the message in the multi-core shared message pool, read the received message and pass it to the core;

The multi-core shared message pool is used to store messages for inter-core communication;

The inter-core communication control module is used to copy the address and destination task identifier of the message to be sent in the multi-core shared message pool to the data channel according to the sending instruction of the core, and send messages sent by other cores to the core in the multi-core The address and the target task identifier in the shared message pool are copied from the data channel to the core;

The data channel is used to transfer the address and the target task identifier of the message in the multi-core shared message pool between the cores;

The virtual interrupt module triggers virtual interrupts of other cores according to the sending instruction of the core, and accepts the triggering of other cores to generate a virtual interrupt to notify the core to receive messages sent by other cores;

The device also includes an identification module, an intra-kernel communication module and a single-core message pool, wherein:

The identifying module is used to identify that the destination core of the message is the sending instruction of the core, and transfer the sending instruction that the destination core is the core to the in-core communication module;

The in-core communication module allocates and releases a message memory block in the single-core message pool according to the sending instruction of the core, and performs communication between tasks in the core through the message memory block;

The single-core message pool uses message memory blocks to store messages communicated between tasks within the core.

Preferably, the inter-core message module includes a message memory module and a spin lock module, wherein:

The message memory module allocates a multi-core message memory block in the multi-core shared message pool for the message to be sent according to the sending instruction of the core, writes the sending message in the allocated multi-core message memory block, and returns the sending message to the core The address in the multi-core shared message pool; or according to the address of the message to be received delivered by the core in the multi-core shared message pool, read the received message and pass it to the core, and release the multi-core message memory block that receives the message;

The spin lock module locks the spin lock of the multi-core shared message pool before the message memory module allocates and releases the multi-core message memory block, and releases the spin lock after allocating and releasing the multi-core message memory block.

Preferably, both the multi-core message memory block and the message memory block include a header information area and a data area, wherein the header information includes the size of the multi-core message memory block or the message memory block, and the identifier of the task to which it belongs. The data area is used to store the data of the message;

The multi-core message memory block has the same header information format as the message memory block.

The present invention establishes a multi-core shared message pool in the shared memory area to store the messages transmitted between the cores, and uses a data pipeline to transmit the message to the address in the message pool in the multi-core, thereby realizing the message queue communication mechanism between the cores, thereby avoiding two The copy process of the message data improves the efficiency of inter-core communication, and the length of each message transmission is no longer limited by the capacity of the data pipeline;

Furthermore, since both the single-core task communication and the inter-core task communication in the present invention adopt the message queue mechanism, and a single message sending and receiving interface is provided for the core, the unification of the internal communication and the inter-core communication is realized, and the application program Development provides convenience.

Description of drawings

Figure 1 shows a schematic structural view of a multi-core processor with two cores;

Fig. 2 shows the flowchart of the inter-core communication method of the present invention;

FIG. 3 is a structural diagram of the inter-core communication device of the present invention.

Detailed ways

ERTOS provides a message queue mechanism for single-core intra-kernel task communication. ERTOS controls a piece of memory in the dedicated memory area of the core, which is dedicated to message data storage for intra-kernel communication. This piece of memory is called a single-core message pool. Before sending a message, a task allocates a message memory block of a specified size from the single-core message pool through ERTOS. A message memory block is divided into a header information area and a data area. The header information area records the relevant information of the message memory block, such as the size, the ID (identification) of the task it belongs to, etc., and the task stores the message data in the data area. .

The message queue is created by the tasks running on the core. The message queue is essentially a linked list. Each item in the linked list represents a message. The actual content varies with ERTOS. The necessary content points to the represented message. The link pointer of the message, or the address of the message in the single-core message pool.

When a task sends a message, it writes the message data into the data area of the allocated message memory block. After that, call the message sending function provided by ERTOS to send the message to the message queue bound to the destination task. The specific implementation of this process is as follows: ERTOS modifies the link pointer of the message queue of the target task to point to the message memory block; modifies the link information recorded in the header information of the message memory block and inserts the message memory block into the message queue linked list of the target task middle.

It can be seen that no data copying occurs during this process. It should be pointed out that the implementation mechanism of the ERTOS message queue must be consistent with the implementation mechanism of the message pool, because the two need to have a unified understanding of the header information format of the message memory block.

The single-core message pool of ERTOS is a single-core exclusive message pool, which only provides the allocation and recycling function of message memory blocks for one core. Mutually exclusive access to a single-core message pool only needs to be performed between multiple tasks on one core, and is implemented by mechanisms such as semaphores and mutexes provided by ERTOS. A single-core message pool cannot serve message communication between multiple cores.

The idea of the present invention is to realize a message pool shared by multiple cores, and realize inter-core message communication in combination with a message queue of tasks in the core. The flow of the inter-core communication method in the present invention is shown in FIG. 2 , wherein the core running on the task sending the message is the source core, and the core running on the target task receiving the message is the target core.

In step S010, memory is allocated in the shared memory area as a multi-core shared message pool. The multi-core shared message pool is used to store message data and header information for inter-core communication. It can be created during system initialization or before the source core sends messages.

In step S020, a data pipeline from the source core to the target core is established in the shared memory area. The method for establishing the data pipeline is the same as that in the prior art, and will not be repeated here.

In the present invention, the source core still needs to transfer the address and the target task ID of the message in the multi-core shared message pool to the target core through the data pipeline, that is to say, the address and the target task ID still need to be copied twice. However, since these contents are only a few bytes of data, it will hardly affect the efficiency of inter-core communication.

In step S030, determine whether the source core performs inter-core communication, if yes, execute step S050; if not, execute step S040, send a message through the single-core message sending function provided by ERTOS, and perform inter-core task communication.

Since the inter-core communication of the present invention can be realized in the form of a message queue, the condition of unifying the inter-core communication and the inter-core communication interface is met. That is to say, when sending a message, it is not necessary to distinguish that both intra-core communication and inter-core communication use the same parameters, and determine whether to use the same parameters for intra-core communication or inter-core communication based on these parameters.

There are many ways to implement this step, the following are two optional ways:

When the source core sends a message, regardless of intra-core communication or inter-core communication, the parameters include the destination core ID and the destination task ID of the message; in this way, as long as it is judged whether the destination core ID is the same as the source core ID, it can be known Is it intra-core communication or inter-core communication;

Uniformly number all tasks running on the multi-core processor, and record the ID of the core running the task; when the source core sends a message, it includes the target task number of the message in the parameter; find out the core running the target task ID, check whether it is the same as the source core ID to know whether it is intra-core communication or inter-core communication.

In step S050, the source core locks the spin lock of the multi-core shared message pool.

In a multi-core system with a shared memory area, since each core can request critical resources in the shared memory area at any time, that is, a memory block shared by multiple cores, the shared memory area should provide a mutual exclusion mechanism. To avoid resource usage into chaos. The shared memory area implements mutual exclusion access as follows:

Before using a critical resource in the shared memory area, each core needs to apply for memory space allocation in the critical resource. After the application is successful, the core obtains the address of the requested memory space. The core can only access this section of memory space through this address. If other cores want to operate on this section of memory space, they must first obtain this address. Therefore, the applying core can use this section of memory space alone, or it can The control of the space is handed over to other cores.

The shared memory area provides a spin lock for each critical resource to control the allocation and release process of the critical resource. Any core can try to lock a spin lock. If the spin lock has been locked by other cores and has not been unlocked, the operation of applying for a lock will cause the core performing this operation to fall into a busy state until The core that holds the spinlock performs an unlock operation on it. A check critical resource applies for memory space allocation, and locks the spin lock to ensure that there will be no other operations on the critical resource memory space at the same time, so as to ensure the exclusive right to use the allocated memory space.

In the present invention, a spin lock is also used to realize mutually exclusive access to a multi-core shared message pool between cores.

In step S060, the source core allocates a multi-core message memory block in the multi-core shared message pool for writing the message. In the present invention, the multi-core message memory block also includes a header information area and a data area, wherein the header information also includes information such as the size of the multi-core message memory block, the task ID to which it belongs, and the data area is used to store the data of the transmitted message.

In order to realize the unification of intra-core communication and inter-core communication, the multi-core message memory block should have the same structure as the message memory block in the single-core message pool, especially the format of the same header information.

In step S070, the source core releases the spin lock of the multi-core shared message pool.

In step S080, the source core writes the message to be sent into the multi-core shared message pool, that is, writes into the multi-core message memory block allocated in the multi-core shared message pool.

In step S090, the source core sends the address of the message in the multi-core shared message pool and the target task ID to the target core through the data pipeline.

The method of sending data through the data pipeline in this step is the same as that in the prior art, specifically:

The source core copies the address of the message in the multi-core shared message pool and the target task identifier to the data pipeline from the source core to the target core;

The source core triggers the virtual interrupt of the destination core;

The destination core responds to the virtual interrupt, and copies the address of the message in the multi-core shared message pool and the destination task identifier from the data pipeline from the source core to the destination core.

In step S100, the destination core transmits the message stored at the address in the multi-core shared message pool to the destination task.

When the multi-core message memory block has the same structure as the single-core message memory block, the destination task can use the same method as the intra-core communication to receive the message. In this case, the destination core writes the link information of the address included in the message in the multi-core shared message pool into the message queue of the destination task, and the destination task can receive the message sent by the source core.

In step S110, the target core locks the spin lock of the multi-core shared message pool.

In step S120, the destination core releases the multi-core message memory block.

In step S130, the target core releases the spin lock of the multi-core shared message pool.

After the destination task receives the message, execute steps S110 to S130 to release the multi-core message memory block occupied by the communicated message.

The present invention also provides a device for realizing inter-core communication in ERTOS, the structure of which is shown in FIG. 3 . It should be noted that the shared memory area 350 , the data channel 351 in the shared memory area 350 and the multi-core shared message pool 352 are shared by all cores in the multi-core processor, while other modules in the figure are only used by one core. The data channel 351 is used to transfer the address and the target task identifier of the message in the multi-core shared message pool between cores, and the multi-core shared message pool 352 is used to store messages communicated between cores.

When a core 310 sends a message to another core, an instruction is sent to an output. The message memory module 341 in the inter-core message module 340 allocates a multi-core message memory block in the multi-core shared message pool 352 for the message to be sent according to the sending instruction, writes the message to be sent therein, and sends the message in the multi-core shared message pool 352 The address of is returned to the core 310;

The core 310 outputs a sending instruction to the inter-core communication control module 320 , and simultaneously notifies the inter-core communication control module 320 of the address and the target task identifier of the message to be sent in the multi-core shared message pool 352 . The inter-core communication control module 320 copies the address and the target task identifier into the data channel 351;

The core 310 outputs a sending instruction to the virtual interrupt module 330, and the virtual interrupt module 330 triggers a virtual interrupt of the target core; so far, the message sending is completed.

When another core sends a message to the core 310, the virtual interrupt module 330 accepts the trigger of the source core to generate a virtual interrupt, and notifies the core 310 that the message sent by other cores arrives;

The core 310 notifies the inter-core communication control module 320 to receive the data, and the inter-core communication control module 320 copies the address and the destination task identifier in the multi-core shared message pool 352 of the message sent to the core 310 by the source core to the core 310;

Kernel 310 instructs inter-core message module 340 to read the data, and simultaneously notifies the inter-core message module 340 of the address of the message to be received in the multi-core shared message pool 352, and the message memory module 341 in the inter-core message module 340 reads the data from the multi-core shared message pool 352 The specified address reads the received message and passes it to the core 310, and releases the multi-core message memory block of the received message after the message is used; so far, the message reception is completed.

The spin lock module 342 in the inter-core message module 340 is used for controlling the mutually exclusive access to critical resources in the multi-core shared message pool 352, and locks the self-locking of the multi-core shared message pool 352 before the message memory module 341 allocates and releases the multi-core message memory block. spinlock, and release the spinlock after allocating and freeing the multicore message memory block.

In order to make inter-core communication and intra-core communication have a unified interface for the core 310 , an identification module 360 can be added between the core 310 and the inter-core message module 340 , the inter-core communication control module 320 and the virtual interrupt module 330 connected thereto.

Since the core 310 is triggered by the virtual interrupt module 320 when receiving the message from the inter-core communication, the identification module 360 can only identify the sending instruction of the core 310 as the destination core of the message when the core 310 sends data, and send The destination core is the send instruction of the core 310 itself, which is passed to the in-core communication module 370 .

The in-core communication module 370 allocates and releases a message memory block in the single-core message pool 380 according to the sending instruction, and performs communication between tasks in the core through the message memory block. The single-core message pool 380 uses message memory blocks to store messages communicated between tasks within the core.

When the multi-core shared message pool 352 and the single-core message pool 380 implement the same mechanism for their respective multi-core message memory blocks and message memory blocks, the core 310 can use the same message queue to receive messages for inter-core communication and intra-core communication. This requires that the multi-core message memory block is the same as the message memory block, including the header information area and the data area, where the header information includes the size of the memory block and the task identifier to which it belongs, and the data area is used to store the data of the message; at the same time, the multi-core message memory The block must also have the same header information format as the message memory block.

It can be seen that the inter-core communication in the present invention only needs to copy the data of a few bytes, and does not need to copy the data of the message twice. Such a communication mechanism improves the efficiency of the inter-core communication and can meet the needs of more applications; the present invention It also unifies the interface of message queue communication between cores and the interface of multi-task communication within a single core, which is convenient for users to use. However, the function of the multi-core shared message pool provided by the present invention can better meet the needs of users.

The process of transferring data between cores through the data channel is related to the motherboard hardware used by ERTOS in the specific implementation. In order to enable ERTOS to run on a variety of mainboards without modification, the solution in the prior art is to add a layer of BSP (Board Support Package) to the mainboard hardware and ERTOS to provide correct interfaces for ERTOS and shield The underlying hardware is different. Specific to the realization of the inter-core data channel, there are two interfaces with the BSP, one is the interface provided by the BSP to the data sender, and the other is the interface provided by the data receiver to the BSP.

The present invention proposes to carry out the definition of standardization to above-mentioned two interfaces, like this, when hardware environment changes, or BSP realizes the internal mechanism of fixed-length data communication between cores to change, or realizes inter-core fixed-length data communication by other modules As long as the standardized definitions of these two interfaces are complied with, the method or device of the present invention can still work correctly without modification. This maximizes portability.

The present invention only needs to know the target core and the target task ID when realizing inter-core communication, so it is not only applicable to ERTOS with static tasks, but also applicable to ERTOS with the function of dynamically creating tasks.

The embodiments of the present invention described above are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (11)

1. the communication method between cores of polycaryon processor in the embedded real-time operating system, the shared drive district of described polycaryon processor is provided with the data pipe that is used for internuclear communication, it is characterized in that, may further comprise the steps:

A) storage allocation is shared message pool as multinuclear in the shared drive district;

B) source nuclear is shared at multinuclear and is distributed multinuclear message memory block in the message pool, is used for writing the message that will send;

C) source is examined the message that will send and is write the shared message pool of multinuclear;

D) source nuclear sends to purpose nuclear with address, the purpose task identification of described message in the shared message pool of multinuclear by data pipe;

E) purpose is examined the described message that address described in the shared message pool of multinuclear is deposited and is sent the purpose task to;

F) after the purpose task receives message, purpose nuclear shared multinuclear message memory block of release message from share message pool.

2. according to the described communication method between cores of claim 1, it is characterized in that: described multinuclear message memory block comprises header information zone and data area, wherein said header information zone is used for depositing header information, described header information comprises the size of described multinuclear message memory block, affiliated task identification, and described data area is used for depositing the data of described message;

The message memory block of the monokaryon message pool of described embedded real-time operating system has identical form with the header information of described multinuclear message memory block.

3. according to the described communication method between cores of claim 2, it is characterized in that step e) specifically also comprises: purpose nuclear is put into the address of described message in the shared message pool of multinuclear the message queue of purpose task.

4. according to the described communication method between cores of claim 3, it is characterized in that, specifically also comprise between described step a) and the step b): source nuclear indicates the purpose nuclear sign and the purpose task identification of described message;

Judge whether described purpose nuclear sign identical with source nuclear sign, if identical, then message transmission function sends to the purpose task with message in the monokaryon that provides by described embedded real-time operating system, and does not carry out described step b), c), d), e); If different, then carry out described step b), c), d), e).

5. according to the described communication method between cores of claim 3, it is characterized in that, comprise before the described step a): the sign of all tasks of moving on the polycaryon processor being carried out the nuclear of unified numbering and this task of record operation;

Also specifically comprise between described step a) and the step b):

Source nuclear indicates the purpose mission number of described message;

Judge the whether operation on the nuclear of source of described purpose task, if then message sends function message is sent to the purpose task in the monokaryon that provides by described embedded real-time operating system, and does not carry out described step b), c), d), e); If not, then carry out described step b), c), d), e).

6. according to any described communication method between cores of claim 2 to 5, it is characterized in that: nuclear is examined not simultaneously with purpose when the source of described message, comprises before the described step b): source nuclear locking multinuclear is shared the spin lock of message pool;

Comprise between described step b) and the step c): source nuclear is removed the spin lock that multinuclear is shared message pool.

7. according to the described communication method between cores of claim 6, it is characterized in that nuclear is examined not simultaneously with purpose when the source of described message, comprises after the described step e) with before the step f): the spin lock of the shared message pool of purpose nuclear locking multinuclear;

Comprise after the described step f): purpose nuclear is removed the spin lock that multinuclear is shared message pool.

8. according to the described communication method between cores of claim 7, it is characterized in that described step d) is specially:

Address and purpose task identification that source nuclear is shared described message in the message pool at multinuclear are copied to described data pipe;

Source nuclear triggers the void interruption of purpose nuclear;

The empty interruption of purpose nuclear response copies out address and the purpose task identification of described message in the shared message pool of multinuclear from described data pipe.

9. the internuclear communicator of polycaryon processor in the embedded real-time operating system, it is characterized in that, comprise nuclear, internuclear communication control module, empty interrupt module, inter-core message module and comprise data channel and the shared drive district of the shared message pool of multinuclear, wherein:

Described inter-core message module instructs the message that will send to write the shared message pool of multinuclear according to the transmission of described nuclear, returns to described nuclear and sends the address of message in the shared message pool of multinuclear; And, read reception message and pass to described nuclear according to the address of the message that will receive in the shared message pool of multinuclear of described nuclear transmission;

Described multinuclear is shared the message that message pool is used for storing internuclear communication;

Described internuclear communication control module is used for copying in the data channel according to address and purpose task identification that the message that the transmission of described nuclear instruction will send is shared in the message pool at multinuclear, and other are authorized address and the purpose task identification shared in the message pool at multinuclear toward the message of described nuclear copies from data channel to described nuclear;

Described data channel is used at address and the purpose task identification of internuclear pass-along message in the shared message pool of multinuclear;

Described empty interrupt module interrupts according to the void of other nuclears of transmission instruction triggers of described nuclear, and the described stone grafting of the empty interrupt notification of triggering for generating of accepting other nuclears is received other and authorized the message of sending;

Described device also comprises communication module and monokaryon message pool in identification module, the nuclear, wherein:

It is the transmission instruction of described nuclear that described identification module is used for the purpose nuclear of identification message, and is that the transmission instruction of described nuclear passes to communication module in the described nuclear with purpose nuclear;

Communication module is distributed and the release message memory block in described monokaryon message pool according to the transmission instruction of described nuclear in the described nuclear, the communication in examining by the message memory block between task;

Described monokaryon message pool is stored the message of intertask communication in the nuclear with the message memory block.

10. according to the described internuclear communicator of claim 9, it is characterized in that described inter-core message module comprises message memory modules and spin lock module, wherein:

Described message memory modules is shared at multinuclear for the message that will send according to the transmission instruction of described nuclear and is distributed multinuclear message memory block in the message pool, in the multinuclear message memory block that distributes, write transmission message, return to described nuclear and send the address of message in the shared message pool of multinuclear; Perhaps, read reception message and pass to described nuclear, and discharge the multinuclear message memory block that receives message according to the address of the message that will receive in the shared message pool of multinuclear of described nuclear transmission;

Described spin lock module described multinuclear of locking before described message memory modules distributes and discharges multinuclear message memory block is shared the spin lock of message pool, and removes described spin lock in distribution with after discharging multinuclear message memory block.

11. according to the described internuclear communicator of claim 10, it is characterized in that, described multinuclear message memory block and message memory block all comprise header information zone and data area, wherein said header information comprises the size of described multinuclear message memory block or described message memory block, affiliated task identification, and described data area is used for depositing the data of described message;

Described multinuclear message memory block has identical header information form with described message memory block.

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