CN100440437C - Manufacturing method of thin film transistor, electro-optical device and electronic instrument - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 241
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 94
- 239000010408 film Substances 0.000 claims abstract description 435
- 239000004065 semiconductor Substances 0.000 claims abstract description 324
- 238000000034 method Methods 0.000 claims abstract description 199
- 239000004020 conductor Substances 0.000 claims abstract description 107
- 239000000463 material Substances 0.000 claims abstract description 70
- 230000002093 peripheral effect Effects 0.000 claims abstract description 70
- 230000008569 process Effects 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000000151 deposition Methods 0.000 claims abstract description 37
- 238000001035 drying Methods 0.000 claims abstract description 37
- 239000007788 liquid Substances 0.000 claims description 74
- 239000012535 impurity Substances 0.000 claims description 23
- 230000008021 deposition Effects 0.000 claims description 19
- 238000005507 spraying Methods 0.000 claims description 8
- 238000001556 precipitation Methods 0.000 claims description 7
- 238000002309 gasification Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 238000005530 etching Methods 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 229910052814 silicon oxide Inorganic materials 0.000 description 21
- 238000000059 patterning Methods 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000004544 sputter deposition Methods 0.000 description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 11
- 239000002904 solvent Substances 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 238000002425 crystallisation Methods 0.000 description 8
- 230000008025 crystallization Effects 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 239000000370 acceptor Substances 0.000 description 7
- 239000003929 acidic solution Substances 0.000 description 7
- 239000010410 layer Substances 0.000 description 7
- 238000004528 spin coating Methods 0.000 description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- BGHCVCJVXZWKCC-UHFFFAOYSA-N tetradecane Chemical compound CCCCCCCCCCCCCC BGHCVCJVXZWKCC-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000009736 wetting Methods 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 239000002270 dispersing agent Substances 0.000 description 4
- 239000010419 fine particle Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000013545 self-assembled monolayer Substances 0.000 description 4
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 3
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- -1 but in this case Substances 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000011344 liquid material Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- XBYRMPXUBGMOJC-UHFFFAOYSA-N 1,2-dihydropyrazol-3-one Chemical class OC=1C=CNN=1 XBYRMPXUBGMOJC-UHFFFAOYSA-N 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 2
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 2
- MWPLVEDNUUSJAV-UHFFFAOYSA-N anthracene Chemical compound C1=CC=CC2=CC3=CC=CC=C3C=C21 MWPLVEDNUUSJAV-UHFFFAOYSA-N 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 125000000524 functional group Chemical group 0.000 description 2
- 238000007429 general method Methods 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 239000011859 microparticle Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920001690 polydopamine Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 210000000352 storage cell Anatomy 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000008096 xylene Substances 0.000 description 2
- 229920000265 Polyparaphenylene Polymers 0.000 description 1
- XBDYBAVJXHJMNQ-UHFFFAOYSA-N Tetrahydroanthracene Natural products C1=CC=C2C=C(CCCC3)C3=CC2=C1 XBDYBAVJXHJMNQ-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000002612 dispersion medium Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012789 electroconductive film Substances 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- QSQIGGCOCHABAP-UHFFFAOYSA-N hexacene Chemical compound C1=CC=CC2=CC3=CC4=CC5=CC6=CC=CC=C6C=C5C=C4C=C3C=C21 QSQIGGCOCHABAP-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- AUHZEENZYGFFBQ-UHFFFAOYSA-N mesitylene Substances CC1=CC(C)=CC(C)=C1 AUHZEENZYGFFBQ-UHFFFAOYSA-N 0.000 description 1
- 125000001827 mesitylenyl group Chemical group [H]C1=C(C(*)=C(C([H])=C1C([H])([H])[H])C([H])([H])[H])C([H])([H])[H] 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- SLIUAWYAILUBJU-UHFFFAOYSA-N pentacene Chemical compound C1=CC=CC2=CC3=CC4=CC5=CC=CC=C5C=C4C=C3C=C21 SLIUAWYAILUBJU-UHFFFAOYSA-N 0.000 description 1
- CVLHDNLPWKYNNR-UHFFFAOYSA-N pentasilolane Chemical compound [SiH2]1[SiH2][SiH2][SiH2][SiH2]1 CVLHDNLPWKYNNR-UHFFFAOYSA-N 0.000 description 1
- DOBUHXUCKMAKSP-UHFFFAOYSA-N pentasilolanylsilane Chemical compound [SiH3][SiH]1[SiH2][SiH2][SiH2][SiH2]1 DOBUHXUCKMAKSP-UHFFFAOYSA-N 0.000 description 1
- 239000003495 polar organic solvent Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229940042055 systemic antimycotics triazole derivative Drugs 0.000 description 1
- IFLREYGFSNHWGE-UHFFFAOYSA-N tetracene Chemical compound C1=CC=CC2=CC3=CC4=CC=CC=C4C=C3C=C21 IFLREYGFSNHWGE-UHFFFAOYSA-N 0.000 description 1
- 125000005259 triarylamine group Chemical group 0.000 description 1
- 150000001651 triphenylamine derivatives Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
本发明的目的是提供一种通过简易且廉价的工序以亚微数量级的精度形成薄膜晶体管用的栅电极和半导体膜的技术。本发明提供的薄膜晶体管的制造方法,包括半导体膜薄膜的形成方法和/或栅电极的形成方法,其中半导体膜薄膜的形成方法包括:在基板上配置包含半导体材料的液滴(14)的工序;使液滴干燥,通过在该液滴的至少周边部析出半导体材料来形成半导体膜(16)的工序,而栅电极的形成方法包括:配置含导电性材料的液滴的工序;使液滴干燥,通过在该液滴的至少周边部析出导电性材料来形成栅电极的工序。
An object of the present invention is to provide a technique for forming a gate electrode and a semiconductor film for a thin film transistor with submicron accuracy through a simple and inexpensive process. The method for manufacturing a thin film transistor provided by the present invention includes a method for forming a semiconductor film and/or a method for forming a gate electrode, wherein the method for forming a semiconductor film includes: a step of disposing a droplet (14) containing a semiconductor material on a substrate make the droplet dry, and form a semiconductor film (16) by depositing a semiconductor material at least at the peripheral portion of the droplet, and the method for forming the gate electrode includes: a step of disposing a droplet containing a conductive material; making the droplet drying, and depositing a conductive material on at least the periphery of the droplet to form a gate electrode.
Description
发明领域field of invention
本发明涉及半导体膜的制造方法和使用该半导体膜的薄膜晶体管的制造方法。The present invention relates to a method of manufacturing a semiconductor film and a method of manufacturing a thin film transistor using the semiconductor film.
背景技术 Background technique
以往,作为薄膜晶体管制造工序的半导体膜的形成方法,广泛采用使用半导体材料形成具有大于需要的面积的薄膜,通过对其图案化去除不要的部分来成型的方法。此外,栅电极也多是形成钽、铝等的导电性薄膜,对其图案化来制作。Conventionally, as a method of forming a semiconductor film in a thin film transistor manufacturing process, a method of forming a thin film having a larger than necessary area using a semiconductor material and patterning the thin film to remove unnecessary portions has been widely used. In addition, the gate electrode is often produced by forming a conductive thin film of tantalum, aluminum, or the like, and patterning it.
作为图案化方法的一个例子,举出光刻法。光刻法是在形成得很宽的薄膜上,使用光掩模形成希望的抗蚀剂图案,通过蚀刻处理未被抗蚀剂图案覆盖的部分将该薄膜成型为目的形状的方法。近年来,由于半导体元件的高集成化,小于1微米的所谓亚微米数量级的成型技术变得必要了,采用蚀刻时形成更微细的掩模图案或使用波长短的X射线和电子射线曝光的分辨率高的方法。As an example of the patterning method, photolithography is mentioned. Photolithography is a method in which a desired resist pattern is formed using a photomask on a wide thin film, and the portion not covered by the resist pattern is etched to form the thin film into a desired shape. In recent years, due to the high integration of semiconductor elements, the so-called sub-micron order forming technology smaller than 1 micron has become necessary, and the formation of finer mask patterns during etching or the resolution of X-rays and electron beam exposures with shorter wavelengths have become necessary. high rate method.
此外,微细形状的薄膜也可通过喷墨法形成。例如,提出将包含有机半导体材料等的半导体材料的溶液由喷墨式喷出装置喷出到基板上来形成半导体膜的方法。在由喷墨法喷出的情况下,由于基板表面的湿润性,喷出的液滴由于湿润而扩展,有时难以正确地描绘微细图案。因此,提出在基板表面上预先形成贮格围堰(bank)来控制液滴的配置,从而根据希望的图案配置喷出的液滴的方法(例如参照专利文献1或专利文献2)。In addition, a thin film of a fine shape can also be formed by an inkjet method. For example, a method has been proposed in which a solution containing a semiconductor material such as an organic semiconductor material is discharged onto a substrate from an inkjet type discharge device to form a semiconductor film. In the case of ejection by the inkjet method, due to the wettability of the substrate surface, the ejected droplets spread due to wetting, and it may be difficult to accurately draw a fine pattern. Therefore, a method has been proposed in which a cell bank is formed in advance on the surface of a substrate to control the arrangement of droplets so that the discharged droplets are arranged in a desired pattern (for example, refer to
【专利文献1】特开昭59-75205号公报[Patent Document 1] JP-A-59-75205
【专利文献2】特开2000-353594号公报[Patent Document 2] JP-A-2000-353594
但是,在光刻法中,微细图案的形成和用于使用X射线和电子射线的曝光的装置很昂贵,吞吐量也低。此外,喷墨法中,液滴直径在数微米以上,因此难以成型亚微米数量级的薄膜。使用贮格围堰的方法中,为形成贮格围堰,必须使用上述光刻法和喷墨法,因此产生成本和效率问题。However, in photolithography, apparatuses for formation of fine patterns and exposure using X-rays and electron beams are expensive, and the throughput is low. In addition, in the inkjet method, the droplet diameter is more than several microns, so it is difficult to form a thin film on the order of submicron. In the method using the storage cell dam, in order to form the storage cell dam, it is necessary to use the photolithography method and the ink-jet method described above, thus causing problems of cost and efficiency.
发明内容 Contents of the invention
因此,本发明的第一课题是提供一种可通过简易且廉价的工序,以亚微数量级的精度形成薄膜晶体管用的半导体膜的薄膜晶体管的制造方法。Therefore, a first object of the present invention is to provide a method of manufacturing a thin film transistor capable of forming a semiconductor film for the thin film transistor with submicron precision through simple and inexpensive steps.
此外,本发明的第二课题是提供一种可通过简易且廉价的工序,以亚微数量级的精度形成薄膜晶体管用的栅电极的薄膜晶体管的制造方法。In addition, a second object of the present invention is to provide a method of manufacturing a thin film transistor capable of forming a gate electrode for a thin film transistor with submicron order of accuracy through simple and inexpensive steps.
进而,本发明的第三课题是提供一种可通过简易且廉价的工序,以亚微数量级的精度形成多个与多个薄膜晶体管对应的栅电极的薄膜晶体管的制造方法。Furthermore, a third object of the present invention is to provide a method of manufacturing a thin film transistor capable of forming a plurality of gate electrodes corresponding to a plurality of thin film transistors with submicron precision through simple and inexpensive steps.
为解决上述第一课题,本发明的薄膜晶体管的制造方法的第一方式是一种薄膜晶体管的制造方法,该薄膜晶体管具备半导体膜、在半导体膜上设置的沟道区域、夹持沟道区域设置的源区域和漏区域、经栅绝缘膜与沟道区域相对置的栅电极,其中包括:在基板上配置包含半导体材料的液滴的工序;使液滴干燥来产生闭环现象,在该液滴的至少周边部析出半导体材料的工序;在该液滴的中央部析出上述半导体材料的情况下,通过去除中央部的上述半导体材料来形成半导体膜的工序。In order to solve the above-mentioned first problem, a first aspect of the method for manufacturing a thin film transistor of the present invention is a method for manufacturing a thin film transistor including a semiconductor film, a channel region provided on the semiconductor film, and a channel region sandwiching the semiconductor film. The source region and the drain region, and the gate electrode opposite to the channel region through the gate insulating film include: the process of disposing liquid droplets containing semiconductor materials on the substrate; drying the liquid droplets to generate a closed-loop phenomenon. A step of depositing a semiconductor material in at least the peripheral portion of the droplet; and a step of forming a semiconductor film by removing the semiconductor material in the center portion of the droplet when the semiconductor material is deposited in the center portion of the droplet.
一般地,在基板上配置的液滴在周边部(边缘)干燥进行得快。因此,液滴包含溶质或分散物质(下面统称溶质等)的情况下,在该液滴的干燥过程中,液滴周边部中溶质等的浓度首先达到饱和,开始析出。另一方面,液滴内部产生从液滴中央部向周边部的液体流动,以补充液滴周边部由蒸发而失去的液滴,液滴中央部的溶质等随着该流动运行到周边部,随着液滴的干燥在周边部开始析出。这样,将液滴中包含的溶质等,沿着基板上配置的液滴形状的外周环状析出的现象称为“闭环”(pinning)。In general, the liquid droplets arranged on the substrate dry quickly at the peripheral portion (edge). Therefore, when a droplet contains a solute or a dispersed substance (hereinafter collectively referred to as a solute, etc.), during the drying process of the droplet, the concentration of the solute or the like in the periphery of the droplet first becomes saturated, and precipitation begins. On the other hand, a liquid flow from the central part of the droplet to the peripheral part is generated inside the droplet to replenish the droplet lost by evaporation at the peripheral part of the droplet, and the solute in the central part of the droplet travels to the peripheral part along with the flow, As the droplet dries, precipitation starts at the periphery. In this way, the phenomenon that the solute contained in the droplet is deposited in a ring shape along the outer periphery of the droplet shape arranged on the substrate is called "pinning".
本发明的薄膜晶体管的制造方法的第一方式,其特征在于,在基板上配置包含半导体材料的液滴,通过使该液滴干燥,由闭环现象将半导体材料析出到液滴周边部。根据闭环现象,可以简单工序形成亚微米数量级的微细半导体膜。此外,半导体膜的形状,可通过干燥速度的调整、配置液滴的基板表面的湿润性调整来控制,可形成环状,或形成在中央部也形成薄膜的圆形或椭圆形。任何情况下,通过引起闭环,可防止干燥途中周边部退缩、薄膜变小或飞出。此外,液滴中央部也形成薄膜的情况下,如后所述,通过去除其一部分可加工成微细形状。A first aspect of the method for manufacturing a thin film transistor according to the present invention is characterized in that a droplet containing a semiconductor material is placed on a substrate, and the droplet is dried to deposit the semiconductor material around the droplet by a closed-loop phenomenon. Due to the closed loop phenomenon, a fine semiconductor film on the order of submicron can be formed in a simple process. In addition, the shape of the semiconductor film can be controlled by adjusting the drying rate and the wettability of the substrate surface on which the droplets are placed, and can be formed into a ring shape, or a circular or elliptical shape in which a thin film is also formed in the center. In any case, by causing a closed loop, shrinkage of the peripheral part during drying, shrinkage of the film, or flying out can be prevented. Also, when a thin film is formed at the center of the droplet, it can be processed into a fine shape by removing a part of it as described later.
此外,本说明书中使用的术语“薄膜晶体管”,只要包括在半导体膜上设置的沟道区域、与沟道区域对应的源区域和漏区域、经栅绝缘膜与沟道区域对置的栅电极,则不限定其构成,可以是在绝缘基板上按半导体膜、栅绝缘膜、栅电极的顺序依次层叠的所谓顶置栅极型,也可以是在绝缘基板上按栅电极、栅绝缘膜、半导体膜的顺序依次层叠的所谓底置栅极型。In addition, the term "thin film transistor" used in this specification only includes a channel region provided on a semiconductor film, a source region and a drain region corresponding to the channel region, and a gate electrode opposed to the channel region through a gate insulating film. , its structure is not limited, and it may be a so-called overhead gate type in which a semiconductor film, a gate insulating film, and a gate electrode are sequentially stacked on an insulating substrate, or it may be a gate electrode, a gate insulating film, and a gate electrode on an insulating substrate. The so-called bottom gate type in which semiconductor films are stacked sequentially.
本发明的薄膜晶体管的制造方法的第一方式中,优选是在配置液滴的工序中,配置2个以上的液滴,使半导体膜材料在这些液滴融合时得到的液滴形状的周边部析出。In the first aspect of the manufacturing method of the thin film transistor of the present invention, it is preferable that in the step of arranging the droplets, two or more droplets are arranged, and the peripheral portion of the droplet shape obtained when these droplets are fused in the semiconductor film material is preferably formed. Precipitate.
如果2个以上的液滴非常接近或部分重叠地配置,则由于各液滴的湿润扩展而融合2个以上的液滴。由此,可将液滴形状作种种改变,从而得到的半导体薄膜的形状自由度也提高。例如,通过直线状并置并融合多个液滴,可得到线状的液滴。如果由线状的液滴引起闭环,则其周边部析出半导体材料时,可得到亚微米数量级的宽度的直线状的半导体膜。此外,除将全部液滴融合形成1个大液滴之外,还可通过反复融合2个以上的液滴并在其周边部析出半导体膜而得到直线状的半导体膜。If two or more liquid droplets are arranged very close to each other or partially overlapped, the two or more liquid droplets will fuse due to the wet spread of each liquid droplet. As a result, the droplet shape can be changed in various ways, and the degree of freedom in the shape of the obtained semiconductor thin film is also increased. For example, linear droplets can be obtained by juxtaposing and fusing a plurality of droplets in a straight line. When the ring is closed by the linear droplet and a semiconductor material is precipitated at the peripheral portion thereof, a linear semiconductor film having a width on the order of submicrons can be obtained. In addition, instead of fusing all the droplets to form one large droplet, a linear semiconductor film can be obtained by repeatedly fusing two or more droplets and depositing a semiconductor film on the periphery thereof.
此外,本发明的薄膜晶体管的制造方法的第一方式中,优选是还包括在配置液滴的工序之后提高液滴中液滴周边部的半导体膜材料的浓度的工序。Furthermore, in the first aspect of the thin film transistor manufacturing method of the present invention, it is preferable to further include a step of increasing the concentration of the semiconductor film material in the peripheral portion of the droplet after the step of arranging the droplet.
作为提高液滴中液滴周边部的半导体膜材料的浓度的工序,可举出例如在配置液滴的基板上加上温度梯度来与液滴内产生对流的工序、在配置于基板上的液滴上重叠喷出溶剂(或分散溶剂)的工序等。通过这种工序,半导体材料集中在液滴周边部,促进周边部的析出。如上所述,即便没有本工序,通过液滴中央部和周边部的溶质等的浓度差产生从液滴中央部向周边部的液体流动,但通过由本工序产生积极地将半导体材料运送到液滴周边部的流动,可更有效地防止液滴中央部残留半导体材料。As a step of increasing the concentration of the semiconductor film material in the peripheral portion of the droplet, for example, a step of adding a temperature gradient to the substrate on which the droplet is arranged to generate convection with the inside of the droplet; The process of dropping and overlapping spraying solvent (or dispersing solvent), etc. Through such a process, the semiconductor material concentrates on the peripheral portion of the droplet, and the deposition at the peripheral portion is promoted. As described above, even without this step, the liquid flow from the center of the droplet to the periphery occurs due to the concentration difference between the center of the droplet and the peripheral portion of the solute, but by this step, the semiconductor material is actively transported to the droplet. The flow at the periphery can more effectively prevent the semiconductor material from remaining in the center of the droplet.
本发明的薄膜晶体管的制造方法的第一方式,优选是还包括在形成半导体膜的工序之后,去除半导体膜的一部分以分割半导体膜的工序,和形成栅电极以分别对应分割的半导体膜的工序。The first aspect of the method for manufacturing a thin film transistor according to the present invention preferably further includes a step of removing a part of the semiconductor film to divide the semiconductor film after the step of forming the semiconductor film, and a step of forming gate electrodes corresponding to the divided semiconductor films. .
作为去除半导体膜的工序,可举出例如附加有机溶剂来溶出半导体材料并去除每个溶剂的方法、蚀刻法等。去除工序中,不需要亚微米数量级的精度,因此可用蚀刻法比较廉价地进行。通过这样分割半导体膜、形成栅电极以对应各半导体膜,可高密度高效率地形成多个微细薄膜晶体管。此外,液滴干燥时,除液滴周边部外,在例如液滴中央部也析出半导体材料的情况下,通过用同样方法去除中央部的半导体膜,可仅得到周边部的微细的半导体膜。As the step of removing the semiconductor film, for example, a method of adding an organic solvent to elute the semiconductor material and remove each solvent, an etching method, and the like are mentioned. In the removal process, precision on the order of submicrons is not required, so it can be performed relatively inexpensively by etching. By dividing the semiconductor film in this way and forming gate electrodes corresponding to the respective semiconductor films, a plurality of fine thin film transistors can be formed with high density and high efficiency. In addition, when the droplet is dried, if the semiconductor material is also deposited in the center of the droplet in addition to the periphery of the droplet, by removing the semiconductor film in the center in the same way, only the fine semiconductor film in the periphery can be obtained.
此外,本发明的薄膜晶体管的制造方法的第一方式,优选是包含在配置液滴的工序之前进行平坦化基板表面的工序。Furthermore, the first aspect of the thin film transistor manufacturing method of the present invention preferably includes a step of planarizing the surface of the substrate before the step of arranging the liquid droplets.
平坦化的工序,例如通过化学机械研磨(CMP)、蚀刻法等进行。此外,旋涂法中形成SOG(玻璃上旋转)膜的方法,从成本看对于得到平坦面也是很好的方法。如果基板表面平坦,液滴均匀地湿润扩展,因此可高精度地进行半导体膜的图案化。The planarization process is performed, for example, by chemical mechanical polishing (CMP), etching, and the like. In addition, the method of forming a SOG (Spin On Glass) film in the spin coating method is also an excellent method for obtaining a flat surface in terms of cost. If the surface of the substrate is flat, the droplet wets and spreads uniformly, so the semiconductor film can be patterned with high precision.
本发明的薄膜晶体管的制造方法的第一方式中,优选是将热或光能照射到通过闭环得到的半导体膜。作为热或光能照射,可举出例如快速热处理(Rapid Thermal Process)(RTP)的处理、激光照射。由此,可提高半导体膜的结晶性。In the first aspect of the manufacturing method of the thin film transistor of the present invention, it is preferable to irradiate heat or light energy to the semiconductor film obtained by loop closure. Examples of heat or light energy irradiation include rapid thermal processing (Rapid Thermal Process) (RTP) treatment and laser irradiation. Thereby, the crystallinity of the semiconductor film can be improved.
此外,本发明的薄膜晶体管的制造方法的第一方式中,还可包括在形成半导体膜的工序之后通过将杂质注入半导体膜而形成源区域和漏区域的工序。通过该工序可将上述半导体膜用于薄膜晶体管。In addition, the first aspect of the thin film transistor manufacturing method of the present invention may further include a step of forming a source region and a drain region by implanting impurities into the semiconductor film after the step of forming the semiconductor film. Through this step, the semiconductor film described above can be used for a thin film transistor.
此外,为解决上述第二课题,本发明的薄膜晶体管的制造方法的第二方式是一种薄膜晶体管的制造方法,该薄膜晶体管具备在半导体膜上设置的沟道区域、对应沟道区域的源区域和漏区域、经栅绝缘膜与沟道区域相对置的栅电极,其中包括:液滴配置工序,通过控制栅绝缘膜表面的湿润性,配置液滴以使得包含导电性材料的液滴的周边部与沟道区域相对置;和析出工序,使液滴干燥来产生闭环现象,使导电性材料在该液滴的至少周边部析出,并在该液滴的中央部析出上述半导体材料的情况下,通过去除中央部的上述半导体材料来形成栅电极。In addition, in order to solve the above-mentioned second problem, a second aspect of the method of manufacturing a thin film transistor of the present invention is a method of manufacturing a thin film transistor including a channel region provided on a semiconductor film, and a source corresponding to the channel region. region, drain region, and the gate electrode opposite to the channel region through the gate insulating film, which includes: a droplet disposition process, by controlling the wettability of the surface of the gate insulating film, disposing the droplets so that the droplet containing the conductive material The peripheral part is opposite to the channel region; and the precipitation step is to dry the liquid droplet to generate a closed-loop phenomenon, to deposit the conductive material at least in the peripheral part of the liquid droplet, and to deposit the above-mentioned semiconductor material in the central part of the liquid droplet Next, the gate electrode is formed by removing the above-mentioned semiconductor material in the central portion.
即,本发明的薄膜晶体管的制造方法的第二方式,其特征在于,通过利用上述的“闭环”现象配置液滴,使得包含导电性材料的液滴周边部与沟道区域对置,将析出的导电性膜用作栅电极。根据闭环现象,可用简单工序形成亚微米数量级的微细导电性膜。That is, the second aspect of the manufacturing method of the thin film transistor of the present invention is characterized in that by utilizing the above-mentioned "closed loop" phenomenon, the liquid droplets are arranged so that the periphery of the liquid droplets containing the conductive material faces the channel region, and the deposited The conductive film was used as the gate electrode. Due to the closed-loop phenomenon, a fine conductive film on the order of submicron can be formed with a simple process.
本发明的薄膜晶体管的制造方法的第二方式中,优选是在液滴配置工序中,通过控制上述栅绝缘膜的表面的湿润性,配置成上述液滴的周边部与上述沟道区域相对置。In the second aspect of the method for manufacturing a thin film transistor according to the present invention, it is preferable that in the droplet arrangement step, by controlling the wettability of the surface of the gate insulating film, the peripheral portion of the droplet is arranged to face the channel region. .
作为通过控制湿润性配置成上述液滴的周边部与上述沟道区域相对置的方法,可举出例如除与沟道区域对置的位置外,形成对导电性材料具有低的亲和性的表面修饰膜(例如自组织化单分子膜(SAMs:Self-Assembled Monlayer),在该表面修饰膜形成后配置包含导电性材料的液滴的方法。根据该方法,导电性材料避开形成亲和性低的表面修饰膜的区域,容易在与沟道区域对置的位置上析出。As a method of arranging so that the peripheral portion of the droplet faces the channel region by controlling the wettability, for example, forming a layer having a low affinity for a conductive material except at a position facing the channel region Surface-modified membranes (such as self-assembled monomolecular membranes (SAMs: Self-Assembled Monlayer), a method of disposing droplets containing conductive materials after the surface-modified membranes are formed. According to this method, conductive materials avoid forming affinity The low-resistance surface-modifying film region tends to deposit at the position facing the channel region.
本发明的薄膜晶体管的制造方法的第二方式中,优选是在析出工序中,包含去除在液滴的中央部析出的导电性材料的工序。In the second aspect of the manufacturing method of the thin film transistor of the present invention, it is preferable that the deposition step includes a step of removing the conductive material deposited in the center of the droplet.
作为去除析出的导电性材料的方法,可举出例如附加有机溶剂、酸性溶液来溶出导电性材料并去除每个溶剂的方法、蚀刻法等。去除工序中,不需要亚微米数量级的精度,因此可用蚀刻法比较廉价地进行。通过去除中央部的导电性薄膜,可仅得到周边部的微细的导电性薄膜。As a method of removing the deposited conductive material, for example, a method of adding an organic solvent or an acidic solution to elute the conductive material and remove each solvent, an etching method, and the like are mentioned. In the removal process, precision on the order of submicrons is not required, so it can be performed relatively inexpensively by etching. By removing the conductive thin film in the central part, only the fine conductive thin film in the peripheral part can be obtained.
本发明的薄膜晶体管的制造方法的第二方式中,优选是将多个沟道区域设置在1个薄膜晶体管的半导体膜上的情况下,在液滴配置工序中配置1个或多个液滴使得液滴的周边部与该多个沟道区域相对置,在析出工序中形成分别对置于该多个沟道区域的多个栅电极。In the second aspect of the manufacturing method of the thin film transistor of the present invention, when a plurality of channel regions are provided on the semiconductor film of one thin film transistor, one or more droplets are arranged in the droplet arrangement step. The peripheral portion of the droplet is made to face the plurality of channel regions, and a plurality of gate electrodes respectively facing the plurality of channel regions are formed in the deposition step.
如在一个薄膜晶体管的半导体膜上设有多个沟道的高集成化的结构的情况下,根据苯发明的制造方法,也可以简易地形成栅电极。液滴的配置的控制,也可以通过如上述的润湿性的控制进行,并也可以调节干燥来进行控制。通过调整干燥,在液滴中央部上也析出导电性材料,也能够形成圆形或椭圆形状的导电性薄膜,而形成所述薄膜后,去除中央部的薄膜而可以形成栅电极。For example, in the case of a highly integrated structure in which a plurality of channels are provided on the semiconductor film of one thin film transistor, the gate electrode can be easily formed according to the manufacturing method of the benzene invention. The arrangement of the droplets can also be controlled by controlling the wettability as described above, and can also be controlled by adjusting the drying. By adjusting the drying, the conductive material is also deposited in the center of the droplet, and a circular or elliptical conductive thin film can also be formed. After forming the thin film, the thin film in the center can be removed to form a gate electrode.
本发明的薄膜晶体管的制造方法的第二方式中,优选是析出工序包括去除在上述液滴周边部析出导电性材料的一部分的去除工序,该去除工序中断开导电性材料以形成分别对置于上述多个沟道区域的多个栅电极。In the second aspect of the manufacturing method of the thin film transistor of the present invention, it is preferable that the deposition step includes a removal step of removing a part of the conductive material deposited at the peripheral portion of the droplet, and in the removal step, the conductive material is disconnected so as to form opposing layers. A plurality of gate electrodes in the plurality of channel regions.
例如,通过去除断开以环状形成的导电性材料的一部分,形成圆弧形状的多个栅电极。通过这种结构可以简单工序形成多个栅电极,可更高密度地形成栅长度短的高性能的薄膜晶体管。For example, a plurality of arc-shaped gate electrodes are formed by removing a portion of the conductive material formed in a ring-shaped break. With such a structure, a plurality of gate electrodes can be formed in a simple process, and a high-performance thin film transistor with a short gate length can be formed at a higher density.
此外,本发明的薄膜晶体管的制造方法的第二方式中,优选是在液滴配置工序中,配置2个以上的液滴,在析出工序中,使导电性材料在上述2个以上的液滴融合时得到的液滴形状的至少周边部析出。In addition, in the second aspect of the manufacturing method of the thin film transistor of the present invention, it is preferable that in the droplet arrangement step, two or more droplets are arranged, and in the deposition step, the conductive material is placed on the above two or more droplets. At least the peripheral portion of the droplet shape obtained during fusion is precipitated.
如上所述,通过融合2个以上的液滴,将液滴形状作种种改变,从而得到的导电性薄膜的形状自由度也提高。例如,通过直线状并置并融合多个液滴,可得到线状的液滴。如果由线状的液滴引起闭环,则其周边部析出导电性材料时,可得到亚微米数量级的宽度的直线状的栅电极图案。此外,除将全部液滴融合形成1个大液滴之外,还可以通过反复融合2个以上的液滴并在其周边部析出导电性薄膜得到直线状的导电性薄膜。As described above, by fusing two or more liquid droplets, the shape of the liquid droplets can be changed in various ways, and the degree of freedom in the shape of the obtained conductive thin film is also increased. For example, linear droplets can be obtained by juxtaposing and fusing a plurality of droplets in a straight line. When the loop is closed by the linear droplet and a conductive material is precipitated at its peripheral portion, a linear gate electrode pattern with a submicron order of width can be obtained. In addition, in addition to fusing all the droplets to form one large droplet, a linear conductive thin film can also be obtained by repeatedly fusing two or more droplets and depositing a conductive thin film on the periphery thereof.
此外,本发明的薄膜晶体管的制造方法的第二方式中,优选是还包括在液滴配置工序之后提高液滴中液滴周边部的导电性材料的浓度的工序。In addition, in the second aspect of the manufacturing method of the thin film transistor of the present invention, it is preferable to further include a step of increasing the concentration of the conductive material in the peripheral portion of the droplet after the droplet arrangement step.
作为提高液滴中液滴周边部的导电性材料的浓度的工序,可举出例如在配置液滴的基板上加上温度梯度来与液滴内产生对流的工序、在配置于基板上的液滴上重叠喷出溶剂(或分散溶剂)的工序等。通过这种工序,导电性材料集中在液滴周边部,促进周边部的析出。如上所述,即便没有本工序,通过液滴中央部和周边部的溶质等的浓度差产生从液滴中央部向周边部的液体流动,但通过由本工序产生积极地将导电性材料运送到液滴周边部的流动,可更有效地防止液滴中央部残留导电性材料。As a step of increasing the concentration of the conductive material in the peripheral portion of the droplet, for example, a step of adding a temperature gradient to the substrate on which the droplet is arranged to generate convection with the inside of the droplet; The process of dropping and overlapping spraying solvent (or dispersing solvent), etc. Through such a process, the conductive material gathers at the peripheral portion of the droplet, and the deposition at the peripheral portion is promoted. As described above, even without this step, the liquid flow from the center of the droplet to the periphery occurs due to the concentration difference between the center of the droplet and the periphery of the solute, but the conductive material is actively transported to the liquid by this step. The flow at the periphery of the droplet can more effectively prevent the conductive material from remaining in the center of the droplet.
此外,本发明还提供具备含2个沟道区域的1个半导体膜、对应上述沟道区域的源区域和漏区域、经栅绝缘膜对置上述2个沟道区域的栅电极,形成上述栅电极的导电膜为1个环状导电膜的薄膜晶体管。In addition, the present invention also provides a semiconductor film including two channel regions, a source region and a drain region corresponding to the above-mentioned channel regions, and a gate electrode facing the above-mentioned two channel regions through a gate insulating film, forming the above-mentioned gate electrode. The conductive film of the electrode is a thin film transistor having a ring-shaped conductive film.
这种薄膜晶体管在例如顶置栅型的情况下,可通过在栅绝缘膜上配置以2个沟道区域的距离为直径大小的包含导电性材料的液滴,借助将其干燥并引起闭环现象来制造。该薄膜晶体管栅长度为亚微米数量级,极短的栅电极隔开微小间隔高密度形成,因此可高集成化。In the case of such a thin-film transistor, for example, in the case of an overhead gate type, liquid droplets containing a conductive material whose diameter is the distance between two channel regions can be placed on the gate insulating film to dry it and cause a closed-loop phenomenon. to manufacture. The gate length of the thin film transistor is on the order of submicron, and the extremely short gate electrodes are formed at high density with tiny intervals, so it can be highly integrated.
此外,具备上述2个沟道区域的薄膜晶体管的情况下,也可以形成夹持2个沟道区域的1组源区域和漏区域,也可以对应2个沟道区域的每一个形成2个薄膜晶体管。作为前者的应用,形成3个以上的对应1组源区域和漏区域的栅电极的所谓多栅型薄膜晶体管也包含于本发明中。供给的电流增多了栅电极增加的部分,性能也提高这些。此外,电流量相等的情况下,每1个栅电极的电流变少,电流损失和发热可被抑制,是优选的。此外,后者情况下,即,对应2个沟道区域的每一个形成2个薄膜晶体管的情况下,2个薄膜晶体管中一个对应N沟道型MOS晶体管,而另一个可为对应P沟道型MOS晶体管的互补型MOS晶体管。In addition, in the case of a thin film transistor having the above-mentioned two channel regions, a set of source region and drain region sandwiching the two channel regions may be formed, or two thin film transistors may be formed corresponding to each of the two channel regions. transistor. As an application of the former, a so-called multi-gate thin film transistor in which three or more gate electrodes are formed corresponding to one set of source regions and drain regions is also included in the present invention. As the current supplied increases, the portion of the gate electrode increases, and the performance is also improved. In addition, when the amount of current is equal, the current per one gate electrode is reduced, and current loss and heat generation can be suppressed, which is preferable. In addition, in the latter case, that is, in the case where two thin film transistors are formed corresponding to each of the two channel regions, one of the two thin film transistors corresponds to an N-channel MOS transistor, and the other may correspond to a P-channel MOS transistor. Complementary MOS transistors of type MOS transistors.
此外,为解决上述第三课题,本发明的薄膜晶体管的制造方法的第三方式是一种制造2个以上的薄膜晶体管的方法,该薄膜晶体管具备含沟道区域的半导体膜、夹持上述沟道区域相对置的源区域和漏区域、经栅绝缘膜与上述沟道区域相对置的栅电极,其特征在于,具备:配置工序,通过控制栅绝缘膜表面的湿润性,配置包含导电材料的液滴,以使该液滴周边部的至少一部分与1个以上的上述沟道区域相对置;析出工序,通过仅在上述液滴的周边部析出上述导电材料来形成上述栅电极,其中将形成的上述栅电极的每一个与至少一个其他的栅电极相连接。In addition, in order to solve the above-mentioned third problem, a third aspect of the method of manufacturing a thin film transistor of the present invention is a method of manufacturing two or more thin film transistors including a semiconductor film including a channel region, and sandwiching the channel region. The source region and the drain region facing the channel region, and the gate electrode facing the above-mentioned channel region through the gate insulating film are characterized in that they include: arranging process, by controlling the wettability of the surface of the gate insulating film, arranging the conductive material a liquid droplet, so that at least a part of the peripheral portion of the liquid droplet faces one or more of the channel regions; a deposition step, forming the gate electrode by depositing the conductive material only at the peripheral portion of the liquid droplet, wherein the Each of the aforementioned gate electrodes is connected to at least one other gate electrode.
即,本发明的薄膜晶体管的制造方法的第三方式中,通过利用上述“闭环现象”,滴下包含导电材料的液滴并形成导电性薄膜,将其用作栅电极,从而可廉价且容易得到亚微米数量级的宽度的环状栅电极,此外,可容易形成对应多个薄膜晶体管的多个栅电极。That is, in the third aspect of the manufacturing method of the thin film transistor of the present invention, by using the above-mentioned "closed-loop phenomenon", droplets containing a conductive material are dropped to form a conductive thin film, and this is used as a gate electrode, so that it can be cheaply and easily obtained. A ring-shaped gate electrode with a width on the order of submicron can be easily formed, and a plurality of gate electrodes corresponding to a plurality of thin film transistors can be easily formed.
此外,导电性薄膜可环状析出,通过控制包含导电材料的液滴的干燥速度、导电材料的粒径、接触角、浓度,或通过在配置一次的液滴上重叠配置其他液滴等方法可析出环状以外的形状,而采用哪个形状或控制方法是设计上的事情。In addition, the conductive thin film can be precipitated in a ring shape. By controlling the drying speed of the droplet containing the conductive material, the particle size, contact angle, and concentration of the conductive material, or by overlapping and arranging other droplets on the once-arranged droplet, etc. Shapes other than rings are precipitated, and which shape or control method to adopt is a matter of design.
本发明的薄膜晶体管的制造方法的第三方式,其特征在于,在制造的薄膜晶体管中,形成的各栅电极与至少一个其他栅电极电连接。这种构成在配置的液滴仅为1个的情况下,也可将液滴配置成该液滴的周边部与多个沟道区域对置。A third aspect of the method for manufacturing a thin film transistor according to the present invention is characterized in that, in the manufactured thin film transistor, each gate electrode formed is electrically connected to at least one other gate electrode. In such a configuration, even when only one droplet is arranged, the droplet can be arranged such that the peripheral portion of the droplet faces a plurality of channel regions.
配置的液滴为2个以上的情况下,通过各液滴的周边部的至少一部分与1个以上的上述沟道区域对置,并且各液滴的周边部的至少一部分与至少其他液滴的周边部重叠,各栅电极电连接至少1个以上的其他栅电极。When there are two or more droplets arranged, at least a part of the peripheral portion of each droplet is opposed to one or more of the above-mentioned channel regions, and at least a part of the peripheral portion of each droplet is in contact with at least one of other droplets. The peripheral portions overlap each other, and each gate electrode is electrically connected to at least one other gate electrode.
通过这种构成,可得到并列连接了多个薄膜晶体管的多沟道型晶体管,可用1个栅信号驱动多个晶体管。With such a configuration, a multi-channel transistor in which a plurality of thin film transistors are connected in parallel can be obtained, and a plurality of transistors can be driven by a single gate signal.
此外,为解决上述第三课题,本发明提供一种薄膜晶体管的制造方法,其是制造2个以上的薄膜晶体管的方法,该薄膜晶体管具备含沟道区域的半导体膜、夹持上述沟道区域相对置的源区域和漏区域、经栅绝缘膜与上述沟道区域相对置的栅电极,其特征在于,包括:配置工序,通过控制栅绝缘膜表面的湿润性,配置包含导电材料的液滴,以使各液滴周边部的至少一部分与1个以上的上述沟道区域相对置;析出工序,通过仅在上述液滴的周边部析出上述导电材料来形成上述栅电极;分离工序,将分别对置上述沟道区域的各栅电极形成为与和其他沟道区域对置的栅电极分离开的岛状。In addition, in order to solve the above-mentioned third problem, the present invention provides a method of manufacturing a thin film transistor, which is a method of manufacturing two or more thin film transistors, the thin film transistor includes a semiconductor film including a channel region, and sandwiches the channel region. The opposite source region and drain region, and the gate electrode opposite to the above-mentioned channel region through the gate insulating film are characterized in that it includes: an arrangement process, by controlling the wettability of the surface of the gate insulating film, a droplet containing a conductive material is arranged so that at least a part of the periphery of each droplet is opposed to one or more of the channel regions; the deposition step is to form the gate electrode by depositing the conductive material only at the periphery of the droplet; the separation step is to separate Each gate electrode facing the channel region is formed in an island shape separated from the gate electrode facing the other channel region.
该方法中,通过分离由闭环现象形成的导电性薄膜并形成栅电极,能够容易形成与多个薄膜晶体管的每一个对应的多个栅电极,同时可高密度地得到微细栅电极。In this method, a plurality of gate electrodes corresponding to each of a plurality of thin film transistors can be easily formed by separating a conductive thin film formed by a closed-loop phenomenon to form a gate electrode, and at the same time, fine gate electrodes can be obtained at high density.
优选是上述分离工序通过例如去除析出的栅电极的一部分而进行。导电性薄膜的去除,可以通过例如供给碱性溶剂并溶出薄膜,按每个溶剂去除导电材料的方法、蚀刻法进行。Preferably, the separation step is performed by, for example, removing a part of the precipitated gate electrode. The removal of the conductive thin film can be performed by, for example, a method of supplying an alkaline solvent to elute the thin film, and removing the conductive material for each solvent, or an etching method.
此外,本发明的薄膜晶体管制造方法中,优选是制造的薄膜晶体管各自具有一个栅电极,对于各个栅电极形成有一组源区域和漏区域。通过这种结构,可高密度形成多连接的晶体管。此外,与相邻的其他薄膜晶体管共有源区域和/或漏区域的构成也包含于本发明中。In addition, in the thin film transistor manufacturing method of the present invention, it is preferable that the manufactured thin film transistors each have one gate electrode, and a set of source regions and drain regions are formed for each gate electrode. With this structure, multi-connected transistors can be formed at high density. In addition, a structure in which a source region and/or a drain region is shared with other adjacent thin film transistors is also included in the present invention.
此外,优选是在上述液滴配置工序中配置下一液滴,使之重叠在先配置的液滴周边部所析出的导电材料的一部分上,再分散导电材料的一部分。通过采用这种构成,可根据析出的导电性薄膜的形状具有自由度。In addition, it is preferable to arrange the next droplet in the above-mentioned droplet arrangement step so as to overlap a part of the conductive material deposited on the periphery of the previously arranged droplet, and then disperse a part of the conductive material. By adopting such a configuration, it is possible to have a degree of freedom according to the shape of the deposited conductive thin film.
此外,优选是液滴配置工序中配置2个以上的液滴,析出工序中使导电性材料在2个以上的液滴融合时得到的液滴形状的至少周边部析出。由此,可得到更大的环状导电性薄膜、直线状的导电性薄膜等。In addition, it is preferable that two or more droplets are arranged in the droplet arrangement step, and the conductive material is deposited on at least the peripheral portion of the droplet shape obtained when two or more droplets are fused in the deposition step. Thereby, a larger annular conductive thin film, a linear conductive thin film, and the like can be obtained.
本发明的薄膜晶体管的制造方法中,优选是将制造的各薄膜晶体管的半导体膜形成为与其他薄膜晶体管的半导体膜分离的岛状。In the manufacturing method of the thin film transistor of the present invention, it is preferable that the semiconductor film of each thin film transistor to be manufactured is formed in an island shape separated from the semiconductor film of other thin film transistors.
此外,本发明的薄膜晶体管的制造方法,优选是在液滴配置工序之前包括在各个沟道区域上形成表面平坦的栅绝缘膜的工序。如果绝缘膜表面平坦,则配置液滴时均匀地湿润扩展,从而容易控制液滴形状。In addition, the method of manufacturing a thin film transistor according to the present invention preferably includes a step of forming a gate insulating film with a flat surface on each channel region before the droplet arrangement step. If the surface of the insulating film is flat, the liquid droplets will be uniformly wetted and spread at the time of disposing, and the shape of the liquid droplets can be easily controlled.
另外,本发明的薄膜晶体管制造方法的第二和第三方式,优选是在上述液滴配置工序之前,包括在上述各个沟道区域上形成表面平坦的栅绝缘膜的工序,并在上述液滴喷出工序中,该栅绝缘膜上配置液滴。In addition, the second and third aspects of the thin film transistor manufacturing method of the present invention preferably include the step of forming a gate insulating film with a flat surface on each of the above-mentioned channel regions before the above-mentioned droplet disposing step, In the discharge step, droplets are placed on the gate insulating film.
平坦的栅绝缘膜例如为涂布型绝缘膜。例如,在形成半导体图案的基板上,以旋涂法形成SOG膜时,形成在有半导体图案的区域薄、在没有半导体图案的区域厚的绝缘膜,可以得到表面平坦的绝缘膜。SOG膜可以为1层,替代上述CMP等可将SOG膜用作平坦化机构。另一方面,在半导体膜上通过溅射法形成绝缘膜时,半导体膜上层叠的部分与没有半导体膜的区域上形成的部分在绝缘膜中产生阶差,但该情况下,可通过化学机械研磨(CMP)和蚀刻等形成。The flat gate insulating film is, for example, a coating type insulating film. For example, when an SOG film is formed by spin coating on a substrate on which a semiconductor pattern is formed, an insulating film that is thin in a region with a semiconductor pattern and thick in a region without a semiconductor pattern can be formed to obtain an insulating film with a flat surface. The SOG film may be one layer, and the SOG film may be used as a planarization mechanism instead of the above-mentioned CMP or the like. On the other hand, when an insulating film is formed on a semiconductor film by sputtering, there is a step difference in the insulating film between the layered portion of the semiconductor film and the portion formed on the region without the semiconductor film, but in this case, chemical mechanical Formed by grinding (CMP) and etching etc.
如果栅绝缘膜的表面平坦,则栅绝缘膜上配置液滴时均匀地湿润扩展,因此容易将液滴配置为希望的形状,可以高精度地进行栅电极的图案化。If the surface of the gate insulating film is flat, the droplets will spread evenly when placed on the gate insulating film, so that the droplets can be easily arranged in a desired shape, and the gate electrode can be patterned with high precision.
此外,本发明还包含具备由上述本发明的薄膜晶体管制造方法制造的薄膜晶体管的电光学装置、具备该薄膜晶体管的电子仪器。In addition, the present invention also includes an electro-optical device including a thin film transistor manufactured by the thin film transistor manufacturing method of the present invention described above, and an electronic device including the thin film transistor.
这里,电光学装置一般是具备本发明的薄膜晶体管的通过电作用而发光或具备改变来自外部的光的状态的电光元件的装置,包含自发光装置和控制来自外部的光的通过的装置。例如,作为电光元件,有液晶元件、具有分散了电泳粒子的分散介质的电泳元件、EL(电致发光)元件、具备使通过电场施加产生的电子正对发光板来发光的电子放射元件的有源矩阵型显示装置等。Here, the electro-optical device is generally a device including the thin film transistor of the present invention that emits light by electricity or has an electro-optical element that changes the state of light from the outside, and includes self-emitting devices and devices that control the passage of light from the outside. For example, as an electro-optical element, there are liquid crystal elements, electrophoretic elements having a dispersion medium in which electrophoretic particles are dispersed, EL (electroluminescent) elements, and electron emitting elements that emit light from electrons generated by application of an electric field to a light-emitting plate. source matrix type display device, etc.
此外,所谓电子仪器一般是具备本发明的薄膜晶体管的实现一定功能的仪器,例如具备电光学装置、存储器。其构成不特别限定,但可包含例如IC卡、移动电话机、录像机、个人计算机、头戴式显示器、背投或正投型投影仪,此外还有带显示功能的传真装置、数字照相机的取景器、便携型电视、DSP装置、PDA、电子记事本、电光揭示板、宣传广告用显示器等。In addition, the so-called electronic equipment generally refers to an equipment equipped with the thin film transistor of the present invention that realizes a certain function, such as an electro-optical device and a memory. Its composition is not particularly limited, but may include, for example, IC cards, mobile phones, video recorders, personal computers, head-mounted displays, rear or front projection projectors, facsimile devices with display functions, and viewfinders for digital cameras. Devices, portable TVs, DSP devices, PDAs, electronic notebooks, electro-optical display boards, displays for advertising, etc.
此外,本发明还提供一种使用在基板上形成的半导体膜形成半导体元件的半导体装置的制造方法,包括:在基板上配置含半导体材料的液滴的工序;和使液滴干燥来产生闭环现象,在该液滴的至少周边部析出半导体材料的工序;通过在该液滴的中央部析出上述半导体材料的情况下,去除中央部的上述半导体材料来形成半导体膜的工序。该制造方法中可用简单工序高密度形成微细半导体膜。In addition, the present invention also provides a method of manufacturing a semiconductor device using a semiconductor film formed on a substrate to form a semiconductor element, comprising: a step of disposing liquid droplets containing a semiconductor material on the substrate; and drying the liquid droplets to generate a closed-loop phenomenon , a step of depositing a semiconductor material in at least the peripheral portion of the droplet; and a step of forming a semiconductor film by removing the semiconductor material in the center portion of the droplet when depositing the semiconductor material in the center portion of the droplet. In this manufacturing method, a fine semiconductor film can be formed at high density with a simple process.
附图说明 Description of drawings
图1是第一实施方式的半导体膜装置的说明图。FIG. 1 is an explanatory diagram of a semiconductor film device according to a first embodiment.
图2是第一实施方式的半导体膜装置的说明图。FIG. 2 is an explanatory diagram of a semiconductor film device according to the first embodiment.
图3是喷墨式喷出装置的立体图。Fig. 3 is a perspective view of an inkjet type discharge device.
图4是喷墨头的侧面截面图。Fig. 4 is a side sectional view of an inkjet head.
图5是第二实施方式的半导体膜装置的说明图。5 is an explanatory diagram of a semiconductor film device according to a second embodiment.
图6是第二实施方式的半导体膜装置的说明图。6 is an explanatory diagram of a semiconductor film device according to a second embodiment.
图7是第三实施方式的半导体膜装置的说明图。7 is an explanatory diagram of a semiconductor film device according to a third embodiment.
图8是第三实施方式的半导体膜装置的说明图。8 is an explanatory diagram of a semiconductor film device according to a third embodiment.
图9是第四实施方式的半导体膜装置的说明图。9 is an explanatory diagram of a semiconductor film device according to a fourth embodiment.
图10是第四实施方式的半导体膜装置的说明图。10 is an explanatory diagram of a semiconductor film device according to a fourth embodiment.
图11是第四实施方式的半导体膜装置的说明图。11 is an explanatory diagram of a semiconductor film device according to a fourth embodiment.
图12是第五实施方式的半导体膜装置的说明图。12 is an explanatory diagram of a semiconductor film device according to a fifth embodiment.
图13是第五实施方式的半导体膜装置的说明图。13 is an explanatory diagram of a semiconductor film device according to a fifth embodiment.
图14是第六实施方式的半导体膜装置的说明图。14 is an explanatory diagram of a semiconductor film device according to a sixth embodiment.
图15是第六实施方式的半导体膜装置的说明图。15 is an explanatory diagram of a semiconductor film device according to a sixth embodiment.
图16是第七实施方式的半导体膜装置的说明图。16 is an explanatory diagram of a semiconductor film device according to a seventh embodiment.
图17是第七实施方式的半导体膜装置的说明图。17 is an explanatory diagram of a semiconductor film device according to a seventh embodiment.
图18是第八实施方式的半导体膜装置的说明图。18 is an explanatory diagram of a semiconductor film device according to an eighth embodiment.
图19是第八实施方式的半导体膜装置的说明图。19 is an explanatory diagram of a semiconductor film device according to an eighth embodiment.
图20是第九实施方式的半导体膜装置的制造方法的说明图。20 is an explanatory diagram of a method of manufacturing a semiconductor film device according to a ninth embodiment.
图21是第九实施方式的半导体膜装置的制造方法的说明图。21 is an explanatory diagram of a method of manufacturing a semiconductor film device according to a ninth embodiment.
图22是第九实施方式的半导体膜装置的制造方法的说明图。22 is an explanatory diagram of a method of manufacturing a semiconductor film device according to a ninth embodiment.
图23是第十实施方式的半导体膜装置的说明图。23 is an explanatory diagram of a semiconductor film device according to a tenth embodiment.
图24是第十一实施方式的半导体膜装置的说明图。24 is an explanatory diagram of a semiconductor film device according to an eleventh embodiment.
图25是第十一实施方式的半导体膜装置的说明图。25 is an explanatory diagram of a semiconductor film device according to an eleventh embodiment.
图26是表示第十一实施方式的半导体膜装置的等效电路的图。26 is a diagram showing an equivalent circuit of a semiconductor film device according to an eleventh embodiment.
图27是用以说明第十一实施方式的栅电极的形成方法的图。FIG. 27 is a diagram for explaining a method of forming a gate electrode according to the eleventh embodiment.
图28是第十二实施方式的半导体膜装置的说明图。28 is an explanatory diagram of a semiconductor film device according to a twelfth embodiment.
图29是表示第十二实施方式的半导体膜装置的等效电路的图。29 is a diagram showing an equivalent circuit of a semiconductor film device according to a twelfth embodiment.
图30是第十三实施方式的半导体膜装置的说明图。30 is an explanatory diagram of a semiconductor film device according to a thirteenth embodiment.
图31是用以说明第十三实施方式的栅电极的形成方法的图。FIG. 31 is a diagram for explaining a method of forming a gate electrode according to a thirteenth embodiment.
图32是第十四实施方式的半导体膜装置的说明图。32 is an explanatory diagram of a semiconductor film device according to a fourteenth embodiment.
图33是用以说明第十四实施方式的栅电极的形成方法的图。FIG. 33 is a diagram for explaining a method of forming a gate electrode according to a fourteenth embodiment.
图34是表示电光学装置的连接状态的一个例子的图。FIG. 34 is a diagram showing an example of a connection state of an electro-optical device.
图35是采用电光学装置构成的各种电子仪器的说明图。Fig. 35 is an explanatory diagram of various electronic devices constructed using electro-optical devices.
图36是采用电光学装置而构成的各种电子仪器的说明图。图中:Fig. 36 is an explanatory diagram of various electronic devices constructed using electro-optical devices. In the picture:
10、50-基板,12、52、72-绝缘膜,14、54-液滴,16、56、74、88-半导体膜,18、58、76-栅绝缘膜,20、62-栅电极,22、78-源/漏区域,25、80-源/漏电极,30-喷墨式喷出装置,31-喷墨式喷头,100-电光学装置10, 50-substrate, 12, 52, 72-insulating film, 14, 54-droplet, 16, 56, 74, 88-semiconductor film, 18, 58, 76-gate insulating film, 20, 62-gate electrode, 22, 78-source/drain area, 25, 80-source/drain electrode, 30-inkjet ejection device, 31-inkjet nozzle, 100-electro-optical device
具体实施方式 Detailed ways
下面参照附图说明本发明的实施方式。Embodiments of the present invention will be described below with reference to the drawings.
<第一实施方式><First Embodiment>
图1和图2是表示本发明的薄膜晶体管的制造方法的第一方式的半导体膜制造方法的说明图。本实施方式中,其特征在于,在绝缘基板上配置含半导体材料的液滴并使其干燥,利用闭环现象形成半导体膜。1 and 2 are explanatory views showing a semiconductor film manufacturing method according to a first embodiment of the thin film transistor manufacturing method of the present invention. The present embodiment is characterized in that droplets containing a semiconductor material are placed on an insulating substrate and dried to form a semiconductor film using a closed-loop phenomenon.
(绝缘膜形成工序)(Insulating film forming process)
图1(A)是形成绝缘膜12的基板的平面图。沿该图2A-2A线的截面图在图2(A)表示。如图2(A)所示,绝缘膜12形成在玻璃等绝缘材料构成的基板10上。本实施方式中,形成氧化硅膜作为绝缘膜12。氧化硅膜可通过例如等离子体化学气相沉积(PECVD法)、减压化学气相沉积法(LPCVD法)、溅射法等物理气相体积法等成膜。此外也可以通过涂布法形成SOG膜。成膜后,表面并不十分平坦的情况下,使用氟酸的湿蚀刻、或使用CMP法平坦化表面。通过旋涂法成膜的SOG膜具有平坦化效果,因此上述平坦化工序不需要。由此,绝缘膜12的表面凹凸变没有,液滴均匀湿润扩展,从而容易配置希望形状的液滴。FIG. 1(A) is a plan view of a substrate on which an insulating
(液滴配置工序)(droplet disposition process)
接着如图1(B)所示,在绝缘膜12上配置含半导体材料的液滴14。沿该图2B-2B线的截面图在图2(B)表示。Next, as shown in FIG. 1(B),
作为半导体材料,可使用例如有机半导体材料。有机半导体材料可溶解于甲苯、二甲苯、三甲苯等非极性有机溶剂,可作为液滴配置在绝缘膜12上。作为有机半导体材料,可举出萘、蒽、并四苯、并五苯、并六苯等低分子化合物,或以及羟基二唑衍生物(PBD)、羟基二唑二聚物(OXD-8)、铍-苯并喹啉络合物(Bebq)、三苯胺衍生物(MTDATA)和三芳基胺衍生物、三唑衍生物、聚苯撑、聚烷基芴、聚烷基噻吩、(P3HT)、聚乙烯芘、聚乙烯萘、F8T2(poly(9,9-dioctylfluorene-co-bithiophene))等的高分子化合物,但不限定于此。有机半导体可在室温加工,不需要大规模制造装置,可廉价制造。此外,作为包含半导体膜材料的液滴,可使用将从环戊硅烷和硅烷基环戊硅烷构成的组中选择的至少一种硅化合物溶于二甲苯等的有机溶剂中得到的液体,根据这些材料,可形成无机半导体膜。As the semiconductor material, for example, an organic semiconductor material can be used. The organic semiconductor material can be dissolved in non-polar organic solvents such as toluene, xylene, and mesitylene, and can be disposed on the insulating
作为在绝缘膜12上配置液滴14的方法,可举出使用微滴管(micropipette)、微喷洒、喷墨等的方法,但可进行特别正确的图案化的喷墨方法是最好的。喷墨法使用后述的喷墨式喷出装置进行。Methods of disposing the
(半导体材料析出工序)(Semiconductor material precipitation process)
如图1(B)和图2(B)所示,在绝缘膜12上配置的液滴14在周边部15比在中央部干燥速度快,周边部15上半导体材料先达到饱和浓度,开始析出。成为液滴的周边部通过析出的半导体材料钉住的状态,引起抑制随着其之后的干燥的液滴收缩(外径收缩)的“闭环现象”。由于周边部15的干燥速度快,产生从液滴中央部向周边部15的液体流动,半导体膜上材料被运到周边部15的结果,形成追随液滴外形的环状半导体膜16。As shown in Figure 1(B) and Figure 2(B), the
图1(C)中表示出液滴完全干燥、半导体膜上材料沿着液滴周边部形状析出、形成半导体膜16的状态。沿着该图的2C-2C线的截面图在图2(C )中表示。半导体膜16形成宽度1微米以下的环状。FIG. 1(C) shows a state where the droplet is completely dried, the material on the semiconductor film is deposited along the shape of the periphery of the droplet, and the
液滴14干燥时,可以控制成提高液滴中的液滴周边部的半导体材科浓度。例如,调节基板的温度,或通过在暂时干燥的半导体膜上再次喷出液滴来控制液滴的气化状态或粘度,在液滴中产生对流,可有效地将半导体材料移动到周边部15。这样一来,半导体材料集中在液滴周边部,可更有效地防止在半导体膜16的中央部17残留半导体材料,可析出宽度细的环状半导体膜,从而不需要图案化就可直接用于半导体元件的形成。When the
得到的半导体膜16上通过照射热或光能可以提高结晶性。例如,可举出快速热处理(RTP)的热处理,或作为光能可举出X射线、紫外线、可见光线、红外线(热线)、激光、毫米波、微波、电子射线、放射线(α线、β线、γ线)等,尤其优选是可高输出照射的激光。作为激光,可举出各种气体激光、固体激光(半导体激光)等,但激元激光、Nd-YAG激光、Ar激光、CO2激光、He-Ne激光等适宜。其中具有半导体膜表面吸收照射能量的350nm以下波长的激元激光特别适合。The crystallinity of the obtained
(元件形成工序)(Element forming process)
接着以薄膜晶体管为例说明使用上述制造方法制造的半导体膜形成半导体元件的工序。Next, a process of forming a semiconductor element using the semiconductor film manufactured by the above-mentioned manufacturing method will be described by taking a thin film transistor as an example.
图1(D)和图2(D)中表示形成栅绝缘膜18和栅电极20的状态。图2(D)是沿着图1(D)的2D-2D线的截面图。FIG. 1(D) and FIG. 2(D) show the state where the
如图2(D)所示,在半导体膜16上形成栅绝缘膜18和栅电极20。栅绝缘膜18为例如氧化硅膜,氧化硅膜可通过例如电子回旋加速器共振PECVD法(ECR-PECVD法)等成膜法、和SOG膜形成。栅电极20可通过在由溅射法等的成膜法形成钽、铝等的导电体薄膜后通过进行图案化来形成。As shown in FIG. 2(D), a
图1(D)中,为表示半导体膜16和栅电极20的位置关系,省略了栅绝缘膜18。栅电极20配置成横过环状的半导体膜16。In FIG. 1(D), the
接着以栅电极20为掩模注入成为施主和受主的杂质元素,进行所谓的自匹配离子注入,在半导体膜16上形成源/漏区域22和沟道区域23。例如,作为杂质元素注入磷(P),之后,将XeCl激元激光调整为400mJ/cm2的能量密度进行照射来活化杂质元素,从而形成N型源/漏区域。此外,替代激光照射,可进行250℃~400℃左右的热处理进行杂质元素的活化。Next, impurity elements serving as donors and acceptors are implanted using the
接着如图1(E)和2(E)所示,表示出层间绝缘膜和源/漏电极的形成工序。图2(E)是沿着图1(E)的2E-2E线的截面图。而如2(E)所示,形成由氧化硅膜构成的层间绝缘膜24以覆盖栅绝缘膜18和栅电极20。氧化硅膜通过例如PECVD法、SOG法等成膜法形成500nm左右。接着贯通栅绝缘膜18和层间绝缘膜24形成跨源/漏区域22的接触孔,在这些接触孔内通过溅射法等成膜法埋入铝、钨等的导电体后图案化,从而形成源/漏电极25。这样形成薄膜晶体管。Next, as shown in FIGS. 1(E) and 2(E), the steps of forming an interlayer insulating film and source/drain electrodes are shown. FIG. 2(E) is a cross-sectional view along line 2E-2E of FIG. 1(E). And, as shown in 2(E), an
图1(E)中,为明确源/漏区域22、栅电极20、源/漏电极25等的位置关系,省略了栅绝缘膜和层间绝缘膜。环状形成的半导体膜中未层叠栅电极的部分为源/漏区域22,层叠了栅电极的部分为沟道区域,形成薄膜晶体管。源/漏电极形成在源/漏区域的中央。In FIG. 1(E), in order to clarify the positional relationship of the source/
这样,本实施方式中,用包含半导体材料的液体的配置和其干燥这样的简单工序可形成规定形状的半导体膜,不用图案化半导体膜就可连续进行绝缘膜形成工序。Thus, in the present embodiment, a semiconductor film of a predetermined shape can be formed by simple steps of disposing a liquid containing a semiconductor material and drying it, and the insulating film forming process can be continuously performed without patterning the semiconductor film.
(液滴喷出装置)(droplet ejection device)
上述各液滴通过从喷墨式喷出装置喷出液体形成。因此,使用图3说明喷墨式喷出装置。图3是喷墨式喷出装置30的立体图。喷墨式喷出装置30主要由底座32、第一移动部件34、第二移动部件36、作为重量测定部件的电子天平(未图示)、头31、封盖单元33以及清除单元35构成。包含第一移动部件34、第二移动部件36的喷墨式喷出装置30的动作由控制装置控制。图3中,X方向是底座32的左右方向,Y方向是前后方向,Z方向是上下方向。Each of the droplets described above is formed by ejecting a liquid from an inkjet type ejection device. Therefore, an inkjet type discharge device will be described using FIG. 3 . FIG. 3 is a perspective view of an
第一移动部件34,使2个导轨38与Y轴方向一致地直接设置在底座32的上面。该第一移动部件34具有可沿着2个导轨38移动的滑块39。作为该滑块39的驱动部件,可采用例如线性电动机。由此,滑块39可沿着Y轴方向移动,可定位在任意位置。The first moving member 34 is provided directly on the upper surface of the base 32 so that the two
滑块39上面固定电动机37,电动机37的转子上固定台(table)46。该台46保持基板10并定位。即,通过使未图示的吸附保持部件动作,通过台46的孔46A吸附基板10,可将基板10保持在台46上。此外,电动机37例如为直接驱动电动机。通过对该电动机37通电台46与转子一起旋转向θz方向,台46上设置头31扔掉液体,或尝试喷出(预备喷出)的预备喷出区域。The motor 37 is fixed on the
另一方面,底座32后方立设2个支柱36A,该支柱36A上端部架设有柱子36B。并且柱子36B的整个面上设置有第二移动部件36。该第二移动部件36具有沿着X轴方向配置的2个导轨84A,具有可沿着导轨84A移动的滑块82。作为该滑块82驱动部件,可采用例如线性电动机。由此,滑块82可沿着X轴方向移动,可定位在任意位置。On the other hand, two
滑块82上设置有头31。头31连接作为摇动定位部件的电动机84,85,86,87。电动机84可使头31在Z轴方向移动,而且可定位在任意位置。电动机85可使头31在围绕Y轴的β方向摇动,而且可定位在任意位置。电动机86可使头31在围绕X轴的γ方向摇动,而且可定位在任意位置。电动机87可使头31在围绕Z轴的α方向摇动,而且可定位在任意位置。The slider 82 is provided with the
如上所述,基板10可在Y方向上移动并定位,可在θz方向上摇动并定位。头31可在X、Z方向上移动并定位,可在α、β、γ方向上摇动并定位。因此,本实施方式的喷墨式喷出装置30可正确控制头31的喷墨面31P和台上的基板10的相对位置和姿势。As described above, the
(喷墨头)(inkjet head)
这里,参照图4说明头31的结构。图4是喷墨头的侧面截面图。头31通过液滴喷出方式将液体L从喷嘴41喷出。作为液滴喷出方式,可适用利用作为压电体元件的压电元件喷出液体的压电方式、通过加热液体产生的泡(气泡)喷出液体的方式等公知的种种技术。其中压电方式不对液体加热,因此具有不对材料组成等产生影响的优点。图4的头31采用压电方式。Here, the configuration of the
头31的头主体40上形成有贮液器(reservoir)45和从贮液器45分支的多个墨水室43。贮液器45成为用以向各墨水室43供给液体L的流路。此外,头主体40下端面安装有构成喷墨面的喷嘴板。该喷嘴板上对应于各墨水室43打开喷出液体L的多个喷嘴41。并且,从各墨水室43朝向对应的喷嘴41形成有墨水流路。另一方面,头主体40上端面安装有振动板44。振动板44形成着各墨水室43的壁面。该振动板44外侧对应于各墨水室43设置有压电元件42。压电元件42用一对电极(未示出)夹持水晶等压电材料。该一对电极连接于驱动电路49。A
并且,从驱动电路49向压电元件42施加电压时,压电元件42膨胀变形或收缩变形。压电元件42收缩变形时,墨水室43的压力降低,从贮液器45向墨水室43流入液体L。此外压电元件42的压力降低,从贮液器45向墨水室43流入液体L。压电元件42膨胀变形时,墨水室43的压力增加,从喷嘴41喷出液体L。此外,通过施加电压的频率改变可控制压电元件42的变形速度。即,通过控制对压电元件42的施加电压控制液体L的喷出条件。Further, when a voltage is applied from the driving
另一方面,图3所示的喷墨式喷出装置备有封盖单元33以及清除单元35。封盖单元33用于防止头31的喷墨面31P干燥,在喷墨式喷出装置30待机时盖住喷墨面31P。清除单元35是用于去除头31的喷嘴上的堆积物,从而吸入喷嘴内部的部件。清除单元35为去除头31上的喷墨面31P的污染物而对喷墨面31P进行擦拭。On the other hand, the inkjet discharge device shown in FIG. 3 includes a
<第二实施方式><Second Embodiment>
图5和图6表示本发明的第二方式的半导体膜的制造方法。本实施方式中,也以薄膜晶体管为例说明。本实施方式中,其特征在于除半导体膜外,栅电极也通过配置并干燥包含传导性材料的液体形成。5 and 6 show a method of manufacturing a semiconductor film according to a second embodiment of the present invention. In this embodiment mode, a thin film transistor is also used as an example for description. The present embodiment is characterized in that the gate electrode is also formed by disposing and drying a liquid containing a conductive material in addition to the semiconductor film.
(半导体膜形成工序)(Semiconductor film formation process)
首先,如图5(A)和(B)所示,在绝缘膜52上配置包含半导体材料的液滴54,使其干燥而得到半导体膜56。两图中的6A-6A线和6B-6B线的截面图,在图6(A)和(B)中表示。绝缘膜52层叠在玻璃基板等的基板50上。绝缘膜形成工序、液滴配置工序、半导体材料析出工序,通过与第一实施方式相同的方法进行,省略说明。First, as shown in FIGS. 5(A) and (B),
(栅电极形成工序)(Gate electrode formation process)
接着使用图5(C)(D)和图6(B’)~(D),说明形成用于使用由上述制造方法制造的半导体膜的半导体元件的栅电极的工序。图5的6C-6C线和6D-6D线的截面图分别是图6(C)和(D )。图5中为表示半导体膜和栅电极的位置关系,省略了栅绝缘膜58。Next, a process of forming a gate electrode for a semiconductor element using the semiconductor film produced by the above-mentioned production method will be described with reference to FIGS. 5(C)(D) and 6(B') to (D). The sectional views of the 6C-6C line and the 6D-6D line of Fig. 5 are Fig. 6 (C) and (D ) respectively. In FIG. 5 , the
首先,使用图6(B’)表示在半导体膜56上形成栅绝缘膜58的工序。栅绝缘膜58可以是例如氧化硅膜,氧化硅膜可通过例如电子回旋加速器共振PECVD法(ECR-PECVD法)等成膜法形成。如图6(B)所示,由这种方法形成的栅绝缘膜58上,在半导体膜56上层叠的区域与其他区域中产生阶差。栅绝缘膜58上有凹凸时,平坦化表面。作为平坦化方法,使用例如CMP法或回蚀刻法。这样,包含导电性材料的液滴,在栅绝缘膜58上更均匀地湿润扩展,容易控制液滴形状。此外,栅绝缘膜中使用SOG膜时,SOG膜自动吸收半导体膜56的阶差,可以得到平坦的栅绝缘膜表面。First, the step of forming the
接着如图5(C)和6(C)所示,在栅绝缘膜58上配置含栅电极材料的液滴60。作为栅电极材料优选是导电性微粒子,例如Ag、Au、Cu等直径数nm左右的微粒子。这些微粒子分散到水或十四碳烷等有机分散剂中,使用喷墨法等,作为液滴配置在栅绝缘膜58上。Next, as shown in FIGS. 5(C) and 6(C),
如图5(D)和6(D)所示,干燥液滴60时,栅电极材料开始从液滴周边部析出,得到沿着液滴外形的环状栅电极62。栅电极62的一部分配置成横过半导体膜56。为了液滴中央部不残留导电性材料,可以积极进行控制使得栅电极材料集中在液滴周边部。关于控制方法,使用与上述半导体膜同样的方法,这里说明从略。As shown in FIGS. 5(D) and 6(D), when the
(元件形成工序)(Element forming process)
接着以栅电极62为掩模,注入成为施主和受主的杂质元素,在半导体膜56上形成源/漏区域。接着形成层间绝缘膜,以覆盖栅绝缘膜58和栅电极62,并贯通栅绝缘膜和层间绝缘膜形成接触孔,通过在该接触孔内埋入导电体而形成源/漏电极。这些工序与上述第一实施方式的工序同样进行,说明从略。Next, using the
根据本实施方式的方法,不仅半导体膜,栅电极也可以通过液滴配置和干燥这样的简单工序在短时间内形成。栅电极可以1微米以下的宽度形成,以其为掩模注入杂质形成源/漏区域,从而可得到栅长为1微米以下的薄膜晶体管。通过缩短栅长,可减小栅电容,从而可形成高性能的薄膜晶体管。According to the method of this embodiment, not only the semiconductor film but also the gate electrode can be formed in a short time through simple steps of droplet arrangement and drying. The gate electrode can be formed with a width of less than 1 micron, and using it as a mask to implant impurities to form source/drain regions, so that a thin film transistor with a gate length of less than 1 micron can be obtained. By shortening the gate length, the gate capacitance can be reduced, thereby forming a high-performance thin film transistor.
<第三实施方式><Third Embodiment>
图7中表示第三方式的半导体膜的制造方法的概要。本实施方式中,从由液滴的配置和干燥得到的1个半导体膜制造2个薄膜晶体管。FIG. 7 shows an outline of a method of manufacturing a semiconductor film according to a third embodiment. In this embodiment, two thin film transistors are produced from one semiconductor film obtained by disposing and drying droplets.
首先,如图7(A)所示,以与第一和第二实施方式相同的方法,在绝缘膜72上形成半导体膜74。接着如该图(B)所示,去除该半导体膜的一部分,得到半导体膜74a和74b。为去除半导体膜74的一部分,举出例如在要去除的场所附加上述液滴的溶剂,溶出半导体材科并按每个溶剂去除的方法,或蚀刻法。去除的区域不需要比较大面积的亚微米数量级的精度,因此可以使用蚀刻法这种并非特别高精度的方法,但却是廉价常用方法。First, as shown in FIG. 7(A), a
接着形成栅绝缘膜(未图示)来覆盖半导体膜74后,形成栅电极76a和76b来横过半导体膜74a和74b的各自的中央部。栅电极将包含栅电极材料的液滴配置在栅绝缘膜上并将其干燥,通过闭环现象成型。用溅射法等形成导电体薄膜、也可以通过图案化来形成,但根据闭环现象,容易形成具有亚微米数量级的宽度的栅电极。栅电极的图案化可通过供给酸性液滴溶出电极来去除的方法和蚀刻法进行。此时,在去除工序中也不需要亚微米数量级的精度,因此使用蚀刻法这种并非特别高精度的方法但却是廉价常用方法的方法。Next, a gate insulating film (not shown) is formed to cover the
接着,以栅电极76a和76b作为掩模注入成为施主和受主的杂质元素,形成源/漏区域78a~78d。接着形成层间绝缘膜(未图示)以覆盖栅电极76a,76b和栅绝缘膜(未图示),贯通栅绝缘膜和层间绝缘膜形成接触孔,通过在该接触孔内埋入导电体而形成源/漏电极80a~80d。这些工序与上述第一实施方式的工序同样进行,说明从略。Next, impurity elements serving as donors and acceptors are implanted using the
根据本实施方式的方法,可用简单工序得到2个用于半导体元件的半导体膜,可高密度高效率地制造半导体装置。此外,栅电极也通过闭环现象制造,制造工序更简单,同时得到栅长为1微米以下的半导体装置。此外,本实施方式中,形成2个半导体膜,但可形成3个以上的半导体膜。According to the method of this embodiment, two semiconductor films used for semiconductor elements can be obtained in a simple process, and semiconductor devices can be manufactured with high density and high efficiency. In addition, the gate electrode is also manufactured through the closed-loop phenomenon, the manufacturing process is simpler, and at the same time, a semiconductor device with a gate length of less than 1 micron is obtained. In addition, in this embodiment, two semiconductor films are formed, but three or more semiconductor films may be formed.
此外上述第一到第三实施方式中,包含半导体材料或栅电极材料的液滴仅配置1滴、进行干燥,来得到了环状薄膜,但又可以配置多个液滴。In addition, in the above-mentioned first to third embodiments, only one droplet containing a semiconductor material or a gate electrode material was placed and dried to obtain a ring-shaped thin film, but a plurality of droplets may be placed.
图8是说明配置2个以上液滴形成薄膜的情况的说明图。如图6(A)所示,隔开一定间隔配置包含半导体材料的液滴时,如该图(B)所示,通过液滴湿润扩展,液滴融合,如该图(C)所示,成为1个线状液滴。通过干燥该线状液滴引起闭环现象,如该图(D)所示,得到沿着线状的液滴外周的环状的薄膜。通过这种方法可以得到直线状的半导体膜88。此外,本实施方式中如果重叠各液滴的一部分而配置各液滴,则通过各液滴湿润扩展融合2个以上液滴。由此,可将液滴形状作种种改变,从而得到的半导体薄膜的形状自由度提高。例如,通过直线状并置并融合多个液滴,可以得到线状液滴。用线状液滴引起闭环,则在其周边部析出半导体材料时,可以得到亚微米数量级的宽度的直线状的半导体膜。此外,除将全部的液滴融合为1个大液滴外,还可以通过反复融合2个以上的液滴并在其周边部析出半导体膜而得到直线状的半导体膜。FIG. 8 is an explanatory diagram illustrating a case where two or more liquid droplets are arranged to form a thin film. As shown in FIG. 6(A), when droplets containing a semiconductor material are arranged at a certain interval, as shown in the figure (B), the droplets are wetted and spread, and the droplets are fused, as shown in the figure (C). Become a linear droplet. The ring-closing phenomenon is caused by drying the linear droplet, and a ring-shaped thin film along the outer periphery of the linear droplet is obtained as shown in the figure (D). In this way, a linear semiconductor film 88 can be obtained. In addition, in the present embodiment, if each droplet is arranged to overlap a part of each droplet, two or more droplets will be fused by wetting and spreading of each droplet. Thereby, the shape of the droplet can be changed in various ways, and the degree of freedom in the shape of the obtained semiconductor thin film can be improved. For example, linear droplets can be obtained by linearly juxtaposing and fusing multiple droplets. When the closed loop is caused by the linear droplet and the semiconductor material is precipitated at the periphery thereof, a linear semiconductor film having a width on the order of submicron can be obtained. In addition to fusing all the droplets into one large droplet, it is also possible to obtain a linear semiconductor film by repeatedly fusing two or more droplets and depositing a semiconductor film on the periphery thereof.
<第四实施方式><Fourth Embodiment>
图9和图10是表示本发明的第一实施方式的薄膜晶体管的制造方法的说明图。以本实施方式制造的薄膜晶体管是图11(B)所示的顶栅型薄膜晶体管T。薄膜晶体管T备有在半导体膜上设置的沟道区域424、对应于沟道区域424的源/漏区域424,和经栅绝缘膜416与沟道区域424对置的栅电极420。9 and 10 are explanatory diagrams showing a method of manufacturing the thin film transistor according to the first embodiment of the present invention. The thin film transistor manufactured in this embodiment mode is a top-gate thin film transistor T shown in FIG. 11(B). The thin film transistor T includes a channel region 424 provided on a semiconductor film, a source/drain region 424 corresponding to the channel region 424 , and a
(半导体膜形成工序)(Semiconductor film formation process)
图9(A)表示在基板410上形成的绝缘膜412上形成半导体膜414的状态。绝缘膜412形成在玻璃等绝缘材料构成的基板410上。本实施方式中,作为绝缘膜412形成氧化硅膜。氧化硅膜可以通过例如等离子体化学气相沉积(PECVD法)、减压化学气相沉积法(LPCVD法)、溅射法等物理气相沉积法等而成膜。此外,可使用液体材料,作为涂布型的绝缘膜(SOG膜)。FIG. 9(A) shows a state where a
本实施方式中,形成硅膜作为半导体膜414。硅膜通过APCVD法、LPCVD法、PECVD法等CVD法或溅射法、蒸镀法等PVD法形成。或者,可与上述本发明的薄膜晶体管的制造方法中使用的栅电极的形成方法同样,使用闭环现象形成硅膜。In this embodiment mode, a silicon film is formed as the
利用闭环现象时,配置包含硅材料的液滴,使得该液滴的周边部位于形成硅膜的区域。又可以根据硅膜的形状配置多个包含硅材料的液滴,在这些液滴融合时得到的液滴形状的周边部析出硅膜。此外,可与本发明的栅绝缘膜的形成方法同样,进行提高液滴周边部的硅膜材料浓度的工序、在硅膜形成后去除一部分的工序、对形成的半导体膜提供热或光能来提高结晶性的工序。When using the closed-loop phenomenon, a droplet containing a silicon material is placed such that the peripheral portion of the droplet is located in a region where the silicon film is formed. Furthermore, a plurality of liquid droplets containing a silicon material may be arranged according to the shape of the silicon film, and the silicon film may be deposited at the peripheral portion of the droplet shape obtained when these droplets fuse. In addition, similar to the method for forming the gate insulating film of the present invention, a step of increasing the concentration of the silicon film material in the peripheral portion of the droplet, a step of removing a part of the silicon film after formation, and applying heat or light energy to the formed semiconductor film can be performed. Process for improving crystallinity.
在用LPCVD法形成硅膜的情况下,使基板温度为约400℃~700℃,以二硅烷(Si2H6)等为原料在基板温度为100℃左右到500℃左右下沉积硅。使用溅射法时,基板温度为从室温到400℃左右。这样,沉积的硅膜初始状态多为非晶质、混晶质、微晶质、或多晶质等种种状态,但可以是任一状态。硅膜的膜厚,在用于半导体膜晶体管的情况下为20nm到100nm左右是适当的。沉积的半导体膜被提供热能来结晶化。本说明书中,所谓“结晶化”不仅是非晶质的半导体膜结晶化,还包含多晶质和微晶质的半导体膜的结晶化。半导体膜的结晶化可以使用激光照射方法和固相生长的方法,但不限定于此。In the case of forming a silicon film by LPCVD, the substrate temperature is about 400°C to 700°C, and silicon is deposited at a substrate temperature of about 100°C to about 500°C using disilane (Si2H6) or the like as a raw material. When using the sputtering method, the substrate temperature is from room temperature to about 400°C. In this way, the initial state of the deposited silicon film is mostly in various states such as amorphous, mixed crystal, microcrystalline, or polycrystalline, but it may be in any state. The film thickness of the silicon film is appropriately about 20 nm to 100 nm when used in a semiconductor film transistor. The deposited semiconductor film is crystallized by supplying thermal energy. In the present specification, the term "crystallization" includes not only the crystallization of amorphous semiconductor films but also the crystallization of polycrystalline and microcrystalline semiconductor films. For crystallization of the semiconductor film, laser irradiation method and solid phase growth method can be used, but not limited thereto.
(绝缘膜形成工序)(Insulating film forming process)
使用图9(B)和(C)说明栅绝缘膜416的形成工序。形成栅绝缘膜416,以覆盖半导体膜414和绝缘膜412,例如为氧化硅膜。氧化硅膜可通过例如电子回旋加速器共振PECVD法(ECR-PECVD法)、PECVD法、常压化学气相沉积法(APCVD法)、或者低压化学气相沉积法(LPCVD法)等成膜法形成。这样形成的栅绝缘膜416如图1(B)所示,在半导体膜414上层叠的区域与在绝缘膜412上层叠的区域部分之间产生阶差,平面不平坦。在其上供给包含到导电性材料的液滴时,不能均匀湿润扩展,不能在希望的位置析出导电性材料并得到栅电极。因此,如图9(C)所示,在配置包含导电性材料的液滴前,平坦化栅绝缘膜416。平坦化可通过化学机械研磨(CMP)、或蚀刻法进行。The process of forming the
栅绝缘膜也可以使用旋涂,通过涂布液体的高K材料和SOG形成。由液体材料涂布的情况下,仅通过涂布工序得到平坦的表面,因此绝缘膜形成后不进行平坦化也可以。可在用PECVD法等形成的栅绝缘膜上层叠旋涂法形成的膜。通过旋涂法层叠膜可平坦化表面。The gate insulating film can also be formed by coating a liquid high-K material and SOG using spin coating. In the case of coating from a liquid material, a flat surface is obtained only through the coating process, so it is not necessary to perform flattening after the insulating film is formed. A film formed by spin coating may be laminated on a gate insulating film formed by PECVD or the like. The surface can be planarized by laminating the film by spin coating.
(液滴配置工序)(droplet disposition process)
接着如图9(D)所示,在绝缘膜416上配置含导电性材料的液滴418。作为导电性材料,可使用例如直径数nm左右的Ag、Au、Cu、Ni等金属微粒子,例如Ag胶质墨等是适当的。这些金属微粒子分散到十四碳烷等有机分散剂中,作为液滴供给。Next, as shown in FIG. 9(D),
作为在绝缘膜416上配置液滴418的方法,可举出使用微滴管、微喷洒、喷墨等的方法,但可进行特别正确的图案化的喷墨方法是适宜的。喷墨法使用后述的喷墨式喷出装置进行。Methods of arranging the
图10(A)表示液滴配置工序的平面图。图10(A)中的沿着IXD-IXD线的截面图为图9(D)。图10(A)中,为明确半导体膜414和液滴418的位置关系省略了栅绝缘膜416。液滴418配置成周边部与沟道区域对置,其外周弧的一部分横过半导体膜414中央附近。FIG. 10(A) is a plan view showing a droplet arrangement step. The cross-sectional view along the line LCD-LCD in FIG. 10(A) is FIG. 9(D). In FIG. 10(A), the
配置液滴时,通过控制栅绝缘膜416表面的湿润性,配置成液滴418周边部与沟道区域相对置,即液滴418的周边部横过半导体膜414中央附近。湿润性的控制使用例如一端具有在栅绝缘膜表面形成SAMs的官能团、另一端具有疏液性官能团的化合物,在栅绝缘膜表面形成单分子膜来进行。除形成栅电极的区域外,通过形成这种SAM膜,包含导电性材料的液滴移动到未形成SAM膜的部分,在那里干燥析出导电性材料。When arranging the droplets, by controlling the wettability of the surface of the
(导电性材料析出工序)(Conductive material precipitation process)
在绝缘膜416上配置的液滴418中,引起上述闭环现象,形成追随液滴外形的环状导电性膜420。In the
图9(E)中表示出液滴完全干燥、导电性材料沿着液滴周边部形状析出、形成环状导电性膜420的状态。图10(B)表示导电性材料析出工序的平面图。沿着图10(B)中的IXE-IXE线的截面图在图9(E)中表示。导电性膜420形成宽度1微米以下的环状,配置成横过半导体膜414的大致中央。FIG. 9(E) shows a state in which the droplet is completely dried, the conductive material is deposited along the shape of the periphery of the droplet, and a ring-shaped
另外,液滴418干燥时,可以控制成提高液滴周边部的导电性材料浓度。例如,调节绝缘基板的温度,或通过在暂时干燥的导电性膜上再次喷出液滴来控制液滴的气化状态或粘度,在液滴中产生对流,可有效地将导电性材料移动到周边部。这样一来,导电性材料不会残留在导电性膜420的中央部,可按宽度细的环状析出导电性材料。导电性材料析出后,可以对得到的导电性膜上进行热处理,凝聚金属微粒子,从而可以提高薄膜的导电性。In addition, when the
(源/漏区域形成工序))(Source/drain region formation process))
接着如图11(A )所示,以栅电极420为掩模注入成为施主和受主的杂质元素,进行所谓的自匹配离子注入,从而在半导体膜414上形成源/漏区域422和活性区域424。例如,作为杂质元素注入磷(P),之后,将XeCl激元激光调整为400mJ/cm2左右的能量密度进行照射来活化杂质元素,从而形成N型薄膜晶体管。此外,替代激光照射,可进行250℃~400℃左右的热处理进行杂质元素的活化。Next, as shown in FIG. 11(A), impurity elements that become donors and acceptors are implanted using the
如上所述,栅电极20其宽度小于1微米,所以通过以其为掩模形成源/漏区域,可以得到栅长为亚微米数量级的半导体元件。As mentioned above, the width of the
这样,本实施方式中,以包含导电性材料的液体的配置和其干燥这样的简单工序就可将具有亚微米数量级宽度的导电性膜形成为希望的形状,不用图案化该导电性膜就可用作栅电极。根据该构成,可简单且廉价地形成栅长非常短且高性能高集成的半导体元件,这是很适当的。Thus, in the present embodiment, a conductive film having a width on the order of submicrometers can be formed into a desired shape by a simple process of disposing a liquid containing a conductive material and drying it, without patterning the conductive film. used as the gate electrode. According to this configuration, it is possible to easily and inexpensively form a high-performance and high-integration semiconductor element with a very short gate length, which is suitable.
(液滴喷出装置)(droplet ejection device)
上述各液滴通过从喷墨式喷出装置喷出来形成。喷墨式喷出装置和喷墨头的结构在第一实施方式中使用图3和图4进行了说明,这里说明从略。Each of the above-mentioned droplets is formed by being ejected from an inkjet type discharge device. The configurations of the inkjet type discharge device and the inkjet head were described in the first embodiment using FIGS. 3 and 4 , and the description is omitted here.
<第五实施方式><Fifth Embodiment>
如12和图13表示本发明的第二实施方式的薄膜晶体管。沿着图12的XIII-XIII线的截面图为图13。FIG. 12 and FIG. 13 show a thin film transistor according to a second embodiment of the present invention. FIG. 13 is a cross-sectional view along line XIII-XIII of FIG. 12 .
如图13所示,本实施方式的薄膜晶体管在源/漏区域464a和464b之间形成2个栅电极463a和463b的所谓“双栅型晶体管”。这种结构的晶体管有所谓泄漏电流低的特征,整体上用作1个晶体管。从图12和图13可知,栅电极463a和463b分别为1个环状导电性薄膜463的一部分。As shown in FIG. 13 , in the thin film transistor of the present embodiment, two gate electrodes 463a and 463b are formed between source/drain regions 464a and 464b, so-called "dual-gate transistors". A transistor having such a structure has a feature of so-called low leakage current, and functions as a single transistor as a whole. As can be seen from FIGS. 12 and 13 , the gate electrodes 463 a and 463 b are part of one ring-shaped conductive
该半导体装置通过在上述本发明的薄膜晶体管的制造方法中,将包含导电性材料的液滴配置成其周边部到达应形成栅电极463的位置上来形成。或者,又可以观察干燥过程中的液滴的收缩,将包含导电性材料的液滴配置在比应形成栅电极463的位置更大的位置上。例如,半导体膜464中配置液滴,使其覆盖从半导体膜两端开始的除应形成源/漏区域464a和464b的区域之外的剩余部分。This semiconductor device is formed by arranging a droplet containing a conductive material so that its peripheral portion reaches the position where the
这样,通过配置1个导电性材料的液滴、使其干燥的容易廉价工序可在希望的位置上形成2个栅电极。得到的栅电极可以是亚微米数量级的宽度,所以在此之后不需要图案化,还可减小半导体装置的栅电容。栅数量增加时,电流也增多,其性能提高。流过相同量电流的情况下,每1个栅的电流非常少,从而可抑制电流损失和发热。In this manner, two gate electrodes can be formed at desired positions by an easy and inexpensive process of arranging one droplet of conductive material and drying it. The resulting gate electrode can be sub-micron in width, so there is no need for patterning thereafter, and the gate capacitance of the semiconductor device can also be reduced. When the number of gates increases, the current also increases and its performance improves. When the same amount of current flows, the current per gate is very small, so that current loss and heat generation can be suppressed.
另外,作为第五实施方式,举例说明了对于1个源/漏区域形成2个栅电极的双栅型,但使用本发明的栅电极的形成方法,可对1个源/漏区域形成3个以上的栅电极,成为多栅型晶体管,该晶体管也包含在本发明中。In addition, as the fifth embodiment, a double gate type in which two gate electrodes are formed for one source/drain region has been described as an example, but using the method for forming gate electrodes of the present invention, three gate electrodes can be formed for one source/drain region. The above gate electrodes constitute a multi-gate transistor, which is also included in the present invention.
<第六实施方式><Sixth Embodiment>
图14和图15表示本发明的第六实施方式的半导体装置。沿着图14的XV-XV线的截面图为图15。14 and 15 show a semiconductor device according to a sixth embodiment of the present invention. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14 .
本实施方式的半导体装置,包括含源/漏区域472a和472b的半导体元件、含源/漏区域472c和472d的半导体元件共2个半导体元件构成的双连接的薄膜晶体管。图15所示的双连接的薄膜晶体管的每一个栅电极474a和474b为图14所示的1个环状导电性薄膜474的一部分。该双连接的晶体管可视为2个晶体管并列连接,整体上用作栅宽度(或沟道宽度)大的1个晶体管。The semiconductor device of this embodiment includes a double-connected thin film transistor composed of two semiconductor elements including a semiconductor element including source/
该半导体装置,通过在上述本发明的薄膜晶体管的制造方法中,将包含导电性材料的液滴配置在应形成导电性薄膜474的位置,即与沟道区域对置的位置上来形成。或者,也可以观察干燥过程中的液滴的收缩,将包含导电性材料的液滴配置在比应形成栅电极474的位置更大的位置上。例如,半导体膜472中配置液滴,使其覆盖从半导体膜两端开始的除应形成漏区域472a和472b的区域之外的剩余部分。This semiconductor device is formed by arranging a droplet containing a conductive material at a position where the conductive
这样,通过配置1个导电性材料的液滴、使其干燥的容易廉价工序可在希望的位置上形成用于双连接的薄膜晶体管的2个栅电极。得到的栅电极可以是亚微米数量级的宽度,所以在此之后不需要图案化,还可减小半导体装置的栅电容。可容易形成双连接的薄膜晶体管,半导体元件的微细加工、高密度化也容易进行。In this way, two gate electrodes for a double-connected thin film transistor can be formed at desired positions by an easy and inexpensive process of disposing a droplet of a conductive material and drying it. The resulting gate electrode can be sub-micron in width, so there is no need for patterning thereafter, and the gate capacitance of the semiconductor device can also be reduced. Double-connected thin film transistors can be easily formed, and microfabrication and high-density semiconductor elements can also be easily performed.
<第七实施方式><Seventh embodiment>
图16和图17中表示本发明的第七实施方式的半导体装置。沿着图16的XVII-XVII线的截面图为图17。A semiconductor device according to a seventh embodiment of the present invention is shown in FIGS. 16 and 17 . FIG. 17 is a cross-sectional view along line XVII-XVII of FIG. 16 .
本实施方式的半导体装置,包括含漏/源区域484a和484b的半导体元件、含源/漏区域484c和484d的半导体元件共2个半导体元件构成的双连接的薄膜晶体管。如图16所示,图17所示的双连接的薄膜晶体管的每一个栅电极486a和486b,通过去除1个环状导电性薄膜的一部分而形成的。该双连接的晶体管被认为是进行不同动作的2个晶体管具有共同的源。The semiconductor device of this embodiment includes a double-connected thin film transistor composed of two semiconductor elements including a semiconductor element including drain/
该半导体装置,通过在上述本发明的薄膜晶体管的制造方法中,配置成包含导电性材料的液滴位于应形成导电性薄膜486a和486b的位置上来形成。或者,观察干燥过程中的液滴的收缩,将包含导电性材料的液滴配置成比应形成导电性薄膜486a和486b的圆具有更大直径。例如,就可以半导体膜484中配置液滴,使其覆盖从半导体膜两端开始的除应形成源/漏区域484a和484b的区域之外的剩余部分。接着通过干燥工序析出导电性材料后,去除作为栅电极不要的部分的薄膜,得到栅电极486a和486b。作为薄膜的去除方法,可以使用供给盐酸、硫酸等的酸性溶液,将该酸性溶液与不要的导电性薄膜一起去除的方法,或用氟酸剥离氧化硅膜的方法、蚀刻法等。去除薄膜的区域并非亚微米数量级,因此蚀刻法是比较廉价的通用方法。This semiconductor device is formed by arranging liquid droplets containing a conductive material at positions where the conductive
根据本实施方式,通过配置1个导电性材料的液滴、使其干燥的容易廉价工序可在希望的位置上形成用于双连接的薄膜晶体管的2个栅电极。得到的栅电极可以是亚微米数量级的宽度,所以在此之后不需要图案化,还可减小半导体装置的栅电容。可容易形成双连接的薄膜晶体管,半导体元件的微细加工、高密度化也容易进行。According to the present embodiment, two gate electrodes for a double-connected thin film transistor can be formed at desired positions by an easy and inexpensive process of arranging and drying one droplet of a conductive material. The resulting gate electrode can be sub-micron in width, so there is no need for patterning thereafter, and the gate capacitance of the semiconductor device can also be reduced. Double-connected thin film transistors can be easily formed, and microfabrication and high-density semiconductor elements can also be easily performed.
<第八实施方式><Eighth Embodiment>
图18和图19中表示本发明的第五实施方式的半导体装置。沿着图18的XIX-XIX线的截面图为图19。A semiconductor device according to a fifth embodiment of the present invention is shown in FIGS. 18 and 19 . FIG. 19 is a cross-sectional view taken along line XIX-XIX of FIG. 18 .
如图19所示,本实施方式的半导体装置是具备N沟道型MOS晶体管TN和P沟道型MOS晶体管TP的互补型MOS半导体装置。漏/源区域(492a和492b)以及源/漏区域(492c和492d)导电型不同,电极496b与P部和N部双方电导通。As shown in FIG. 19 , the semiconductor device of the present embodiment is a complementary MOS semiconductor device including an N-channel MOS transistor TN and a P-channel MOS transistor T P. The drain/source regions (492a and 492b) and the source/drain regions (492c and 492d) have different conductivity types, and the
N沟道型MOS晶体管和P沟道型MOS晶体管的各自栅电极494a和494b,如图18所示,都成一个导电性环状薄膜494的一部分。The respective gate electrodes 494a and 494b of the N-channel type MOS transistor and the P-channel type MOS transistor form part of a conductive
该半导体装置,在互补型MOS半导体装置的制造工序中,在形成栅电极时,在应形成N沟道型MOS晶体管TN和P沟道型MOS晶体管TP的栅电极的位置上配置包含导电性材料的液滴,使其干燥,析出导电性材料来形成。In this semiconductor device, in the manufacturing process of the complementary MOS semiconductor device, when forming the gate electrode, the gate electrode of the N-channel MOS transistor TN and the P-channel MOS transistor T P should be formed. Droplets of conductive materials are dried to precipitate conductive materials.
根据本实施方式,通过配置1个液滴、使其干燥的简单的工序可形成双晶体管的栅电极。得到的栅电极可以是亚微米数量级的宽度,所以在此之后不需要图案化,还可减小半导体装置的栅电容。According to the present embodiment, the gate electrode of the double transistor can be formed by a simple process of disposing one droplet and drying it. The resulting gate electrode can be sub-micron in width, so there is no need for patterning thereafter, and the gate capacitance of the semiconductor device can also be reduced.
<第九实施方式><Ninth Embodiment>
图20和21是表示本发明的第九实施方式的栅电极的制造方法的说明图。本实施方式中表示出使用本发明的薄膜晶体管的制造方法,制造包含2个薄膜晶体管的多沟道型薄膜晶体管的方法。20 and 21 are explanatory diagrams showing a method of manufacturing a gate electrode according to a ninth embodiment of the present invention. This embodiment mode shows a method of manufacturing a multi-channel thin film transistor including two thin film transistors using the thin film transistor manufacturing method of the present invention.
(半导体膜形成工序)(Semiconductor film formation process)
图20(A)表示在基板510上形成的绝缘膜512上形成半导体膜514的状态。绝缘膜512形成在玻璃等绝缘材料构成的基板510上。本实施方式中,作为绝缘膜512形成氧化硅膜。氧化硅膜可以通过例如等离子体化学气相沉积(PECVD法)、减压化学气相沉积法(LPCVD法)、溅射法等物理气相沉积法、SOG(玻璃上旋转)法等成膜。FIG. 20(A) shows a state where a
本实施方式中,形成硅膜作为半导体膜514。硅膜通过APCVD法、LPCVD法、PECVD法等CVD法或溅射法或蒸镀法等PVD法形成。在用LPCVD法形成硅膜的情况下,使基板温度为约400℃~700℃,以硅烷(SiH4)、二硅烷(Si2H6)等为原料沉积硅。PECVD法中以硅烷(SiH4)等为原料在基板温度为100℃到500℃左右下可沉积硅。这样,沉积的硅膜初始状态有非晶质、混晶质、微晶质、或多晶质等种种状态,但可以是任一状态。硅膜的膜厚在用于半导体膜晶体管的情况下为20nm到100nm左右是适当的。沉积的半导体膜被提供热能来结晶化。本说明书中,所谓“结晶化”不仅是非晶质的半导体膜结晶化,还包含多晶质和微晶质的半导体膜的结晶化。半导体膜的结晶化可使用激光照射方法和固相生长的方法,但不限定于此。In this embodiment mode, a silicon film is formed as the
接着,使用光刻法将形成的半导体膜通过蚀刻图案化为需要形状,得到硅膜514。Next, the formed semiconductor film is patterned into a desired shape by etching using photolithography to obtain a
(绝缘膜形成工序)(Insulating film forming process)
使用图20(B)和(C)说明栅绝缘膜516的形成工序。形成栅绝缘膜516以覆盖半导体膜514和绝缘膜512,例如为氧化硅膜。氧化硅膜可通过例如电子回旋加速器共振PECVD法(ECR-PECVD法)、PECVD法、常压化学气相沉积法(APCVD法)、低压化学气相沉积法(LPCVD法)等成膜法形成。这样形成的栅绝缘膜516如图20(B)所示,在半导体膜514上层叠的区域与在绝缘膜512上层叠的部分之间产生阶差,平面不平坦。在其上供给包含到导电性材料的液滴时,不能均匀湿润扩展,不能在希望的位置析出导电性材料并得到栅电极。因此,如图20(C)所示,在配置包含导电性材料的液滴前,平坦化栅绝缘膜516。平坦化可通过化学机械研磨(CMP)、蚀刻法进行。The process of forming the
栅绝缘膜也可使用旋涂通过涂布液体的SOG材料和低K材料形成。液体材料涂布的情况下,即使具有图案或阶差的基底也可以使表面平坦地形成,因此绝缘膜形成后不进行平坦化也可以。The gate insulating film can also be formed by coating a liquid SOG material and a low-K material using spin coating. In the case of liquid material coating, even a base having a pattern or a step can be formed with a flat surface, so it does not need to be planarized after the insulating film is formed.
(液滴配置工序)(droplet disposition process)
接着如图20(D)所示,在绝缘膜516上配置含导电性材料的液滴518。作为导电性材料,可使用例如直径数nm左右的Ag、Au、Cu等金属微粒子,例如Ag胶质墨等是适当的。这些金属微粒子分散到十四碳烷等有机分散剂中,作为液滴供给。Next, as shown in FIG. 20(D), a
作为在绝缘膜516上配置液滴518的方法,可举出使用微滴管、微喷洒、喷墨等的方法,但可进行特别正确的图案化的喷墨方法是适宜的。喷墨法使用后述的喷墨式喷出装置进行。Methods of disposing the
图21(A)表示液滴配置工序的平面图。图21(A)中的沿着XXD-XXD线的截面图为图20(D)。图21(A)中,为明确半导体膜514和液滴518的位置关系省略了栅绝缘膜516。Fig. 21(A) is a plan view showing a droplet arrangement step. The cross-sectional view taken along line XXD-XXD in FIG. 21(A) is FIG. 20(D). In FIG. 21(A), the
本实施方式中,为使用半导体膜514形成2个薄膜晶体管,该2个薄膜晶体管的栅电极连接的构成。配置液滴518,使得液滴518的周边部2次横过半导体膜514。更具体说,液滴518的直径为应形成2个薄膜晶体管的栅电极的位置间的距离。或者观察干燥过程中液滴的收缩,设置具有比该距离稍大直径的液滴。In this embodiment, two thin film transistors are formed using the
(导电性材料析出工序)(Conductive material precipitation process)
在绝缘膜516上配置的液滴518中,引起上述闭环现象,形成追随液滴518外形的环状导电性膜520。In the
图20(E)中表示出液滴完全干燥、导电性材料沿着液滴形状析出、形成环状导电性膜520的状态。图21(B)表示导电性材料析出工序的平面图。沿着图21(B)中的XXE-XXE线的截面图是图20(E)。导电性膜520形成宽度1微米以下的环状,配置成2次横过半导体膜514。FIG. 20(E) shows a state where the droplet is completely dried, the conductive material is deposited along the shape of the droplet, and the ring-shaped
液滴518干燥时,可以控制成以使提高液滴周边部的导电性材料浓度。例如,调节绝缘基板的温度,或通过在一旦干燥的导电性膜上再次喷出液滴来控制液滴的气化状态和粘度,在液滴中产生对流,可有效地将导电性材料移动到周边部。这样一来,半导体材料不会残留在导电性膜520的中央部,可按宽度细的环状析出半导体材料。导电性材料析出后,对得到的导电性薄膜上进行热处理,凝聚金属微粒子,从而提高薄膜的导电性。When the
(源/漏区域形成工序)(Source/drain region formation process)
接着如图22(A)所示,以栅电极520中区域520a和520b为掩模注入成为施主和受主的杂质元素,进行所谓的自匹配离子注入。Next, as shown in FIG. 22(A), so-called self-matching ion implantation is performed by using the
例如,作为杂质元素注入磷(P),之后,将XeCl激元激光调整为400mJ/cm2的能量密度进行照射来活化杂质元素,从而形成N型薄膜晶体管。此外,替代激光照射,可进行250℃~400℃左右的热处理进行杂质元素的活化。For example, phosphorus (P) is implanted as an impurity element, and then the XeCl excimer laser is irradiated with an energy density of 400mJ/cm2 to activate the impurity element, thereby forming an N-type thin film transistor. In addition, instead of laser irradiation, impurity elements may be activated by heat treatment at about 250° C. to 400° C.
通过以区域520a和520b为掩模注入杂质元素,形成区域514a、514b和514c。区域514a作为包含栅电极520a的薄膜晶体管的漏区域、区域514c作为包含栅电极520a的薄膜晶体管的漏区域。区域514b用作包含栅电极520a的薄膜晶体管和包含栅电极520b的薄膜晶体管的源区域。
接着如图22(B)所示,在栅绝缘膜516、栅电极520a和520b上面形成绝缘膜517。例如可用PECVD法形成约500nm的氧化硅膜。接着,在绝缘膜516和517中打开到达源区域514b、漏区域514a和514c的接触孔,在接触孔内和绝缘膜517的接触孔周边部形成源/漏电极528。源/漏电极528可通过例如溅射法沉积铝形成。在绝缘膜517中打开跨栅电极528的接触孔,形成栅电极用端子电极(未示出)。Next, as shown in FIG. 22(B), an insulating
如上所述形成的2个薄膜晶体管,各自的栅电极520a和520b成为1个环状导电性薄膜520的一部分。这种晶体管作为共用源区域和栅电极的2个晶体管而作用。In the two thin film transistors formed as described above, the
本实施方式中,通过配置1个包含导电性材料的液滴和其干燥这样的容易且廉价工序就可制造所述的2个晶体管。本方法得到的栅电极520其宽度小于1微米,所以在此之后不用图案化。通过以该栅电极为掩模形成源/漏区域可得到栅长为亚微米数量级的半导体元件,从而可成为栅电容小的高性能的薄膜晶体管。根据本实施方式的方法,可容易进行半导体元件的微小加工、高密度化。In the present embodiment, the above-mentioned two transistors can be manufactured by an easy and inexpensive process of arranging one droplet containing a conductive material and drying it. The width of the
(液滴喷出装置)(droplet ejection device)
上述各液滴通过从喷墨式喷出装置喷出而形成。喷墨式喷出装置和喷墨头的构成在第一实施方式中使用图3和图4进行了说明,这里说明从略。Each of the above-mentioned droplets is formed by being discharged from an inkjet type discharge device. The configurations of the inkjet discharge device and the inkjet head were described in the first embodiment with reference to FIGS. 3 and 4 , and descriptions thereof are omitted here.
<第十实施方式><Tenth Embodiment>
图23(A)和23(B)中表示本发明的第十实施方式的半导体装置。本实施方式中使用本发明的薄膜晶体管的制造方法,制造双连接的薄膜晶体管。双连接的薄膜晶体管是指2个薄膜晶体管串联连接。沿着图23(A)的XXIIIB-XXIIIB线的截面图为图23(B)。A semiconductor device according to a tenth embodiment of the present invention is shown in FIGS. 23(A) and 23(B). In this embodiment mode, a double-connected thin film transistor is manufactured using the thin film transistor manufacturing method of the present invention. A double-connected thin film transistor means that two thin film transistors are connected in series. A cross-sectional view along line XXIIIB-XXIIIB of FIG. 23(A) is FIG. 23(B).
本实施方式的制造方法中,半导体膜形成工序、绝缘膜形成工序、液滴配置工序、导电性材料析出工序,用上述第一实施方式所述的方法或基于此的方法进行,这里说明从略。In the manufacturing method of this embodiment, the semiconductor film forming step, the insulating film forming step, the droplet arrangement step, and the conductive material deposition step are performed by the method described in the first embodiment above or a method based thereon, and description thereof will be omitted here. .
(栅电极分离工序)(Gate electrode separation process)
本实施方式中,通过闭环现象,在绝缘膜上环状析出导电性薄膜后,去除其一部分,分离与双连接的薄膜晶体管的各自的沟道区域对置的各栅电极。分离的状态平面图为图23(A)。分别对置双连接的薄膜晶体管的沟道区域563a和563b的栅电极566a和566b如图23(A)所示,为彼此分离的岛状。In the present embodiment, after a conductive thin film is deposited in a ring shape on an insulating film by a closed-loop phenomenon, a part thereof is removed to separate each gate electrode facing each channel region of a double-connected thin film transistor. The separated state plan view is Fig. 23(A). The
作为薄膜的去除方法,可使用供给盐酸、硫酸等的酸性溶液,将该酸性溶液与不要的导电性薄膜一起去除的方法,或用氟酸剥离氧化硅膜的方法、蚀刻法等。去除薄膜的区域并非亚微米数量级,因此蚀刻法是比较廉价的通用方法。As the method of removing the thin film, a method of supplying an acidic solution such as hydrochloric acid or sulfuric acid and removing the acidic solution together with the unnecessary conductive thin film, a method of peeling off the silicon oxide film with hydrofluoric acid, or an etching method can be used. The area of the removed film is not on the order of submicron, so etching is a relatively inexpensive general method.
(源/漏区域形成工序)(Source/drain region formation process)
接着如图23(A)所示,以栅电极566a和566b为掩模注入成为施主和受主的杂质元素,进行所谓的自匹配离子注入。Next, as shown in FIG. 23(A), impurity elements serving as donors and acceptors are implanted using the
例如,作为杂质元素注入磷(P),之后,将XeCl激元激光调整为400mJ/cm2左右的能量密度进行照射来活化杂质元素,从而形成N型薄膜晶体管。此外,替代激光照射,可进行250℃~400℃左右的热处理进行杂质元素的活化。For example, phosphorus (P) is implanted as an impurity element, and then XeCl excimer laser is irradiated with an energy density of about 400mJ/cm 2 to activate the impurity element, thereby forming an N-type thin film transistor. In addition, instead of laser irradiation, impurity elements may be activated by heat treatment at about 250° C. to 400° C.
通过以栅电极566a和566b为掩模注入杂质元素,形成区域564a、564b和564c。区域564a作为包含栅电极566a的薄膜晶体管的源区域、区域564b作为包含栅电极566a的薄膜晶体管的漏区域,同时用作包含栅电极566b的薄膜晶体管的源区域。而且,区域564c作为包含栅电极566b的薄膜晶体管的漏区域而作用。
接着如图23(B)所示,在栅绝缘膜516、栅电极566a和566b上面形成绝缘膜517。例如可用PECVD法形成约500nm的氧化硅膜。接着,在绝缘膜516和517中打开到达区域564a、564b和564c的接触孔,在接触孔内和绝缘膜517的接触孔周边部形成源/漏电极568。源/漏电极568可通过例如溅射法沉积铝而形成。在绝缘膜517中打开跨栅电极566a和566b的接触孔,形成栅电极用端子电极(未图示)。Next, as shown in FIG. 23(B), an insulating
本实施方式中,通过配置1个导电性材料的液滴和其干燥这样的容易而廉价工序就可在希望的位置上形成双连接的薄膜晶体管用的2个彼此分离的岛状的栅电极。得到的栅电极为亚微米数量级的宽度,所以在此之后不用图案化,可减小半导体装置的栅电容。由于容易形成双连接的薄膜晶体管,可容易进行半导体元件的微细加工、高密度化。In the present embodiment, two separate island-shaped gate electrodes for a double-connected thin film transistor can be formed at desired positions by an easy and inexpensive process of disposing a droplet of a conductive material and drying it. The resulting gate electrode has a submicron-order width, so there is no need for subsequent patterning, and the gate capacitance of the semiconductor device can be reduced. Since it is easy to form a double-connected thin film transistor, microfabrication and high density of semiconductor elements can be easily performed.
<第十一实施方式><Eleventh Embodiment>
图24表示本发明的第十一实施方式的半导体装置,图25中表示图24所示的半导体装置的XXV-XXV线的截面图。此外,图26表示本实施方式的半导体装置的等效电路图。本实施方式的半导体装置包含4个薄膜晶体管T1~T4,各薄膜晶体管T1~T4的源电极672a、672c、672e以及漏电极672b、672d分别共用(参照图24和图26)。另一方面,形成各薄膜晶体管T1~T4的栅电极674a~674d,如图24所示成为周边部部分重叠地形成的2个环状导电性薄膜(下面叫环状导电性薄膜)674的一部分。这样的晶体管是沟道并联连接的多沟道晶体管,整体上用作沟道宽度大的1个晶体管该构成的半导体装置如下形成。FIG. 24 shows a semiconductor device according to an eleventh embodiment of the present invention, and FIG. 25 shows a cross-sectional view taken along line XXV-XXV of the semiconductor device shown in FIG. 24 . In addition, FIG. 26 shows an equivalent circuit diagram of the semiconductor device of the present embodiment. The semiconductor device of this embodiment includes four thin film transistors T1 to T4, and the
如上所述,首先,在基板670上形成的绝缘膜67上,使用CVD法、PVD法等形成成为半导体层的半导体膜675(参照图25)。该半导体层上随后形成多个沟道区域。通过SOG膜覆盖这样形成的半导体膜675和绝缘膜671来形成表面平坦的栅绝缘膜673。并且,该栅绝缘膜673上使用喷墨式喷出装置(参照图4)顺序滴下包含导电性材料的液滴,形成多个环状导电性薄膜(导电图案)674。具体说,首先,滴下成包含导电性材料的第一液滴周边部那样,对置各沟道区域(源区域和漏区域之间夹持的区域)。该滴下的液滴由于周边部比中央部的干燥速度快,产生从液滴中央部向周边部的流动,导电性材料到达周边部。其结果是形成追随第一液滴外形的环状导电性薄膜674(例如图24所示左侧的环状导电性薄膜)。As described above, first, the semiconductor film 675 to be a semiconductor layer is formed on the insulating film 67 formed on the
对应第一液滴的环状导电性薄膜674形成后,接着滴下第二液,使得其包含环状导电性薄膜674的一部分(换言之,各液滴之间各自的一部分重叠)并且周边部的一部分对置各沟道区域。由此,形成追随第二液滴外形的环状导电性薄膜674(例如图24所示右侧的环状导电性薄膜)。通过形成这2个环状导电性薄膜674,形成成为各导电性薄膜674的一部分的栅电极674a~674d。这样,可通过仅错开规定量的位置滴下多个包含导电性材料的液滴,并使其干燥的容易廉价工序就可在希望位置上以亚微米数量级的宽度形成4连接薄膜晶体管用的4个栅电极674a~674d。4个栅电极形成为2个环状导电性薄膜的一部分,因此为彼此电连接的结构。After the ring-shaped
之后,以形成的上述栅电极674a~674d为掩模适当注入成为施主或受主的自匹配离子,从而在半导体层上形成源区域675a,675c,675e和漏区域675b,675d以及各源区域和各漏区域之间夹持的多个沟道区域(参照图25)。经过以上说明的工序,可得到具有图25所示的亚微米数量级的栅长、包括彼此互相连接的连续形状的栅电极的包含4个薄膜晶体管的多沟道型半导体装置。另外,本实施方式中说明了4个薄膜晶体管,但可以是3个薄膜晶体管或5个薄膜晶体管。此时,通过增加配置的液滴数或调整源区域和漏区域的配置,可以形成这样的薄膜晶体管。Afterwards, self-matched ions that become donors or acceptors are properly implanted using the formed
另外,以上说明中,例示出为形成4个薄膜晶体管而形成2个环状导电性薄膜674的情况,但该环状导电性薄膜674的个数可对应于应形成n(n≥2)连接的薄膜晶体管的数量适当变更(参照图27)。此外,各环状导电性薄膜674的配置间隔和其直径等也可对应于应形成薄膜晶体管的设计等适当变更。In addition, in the above description, the case where two ring-shaped
<第十二实施方式><Twelfth Embodiment>
图28中表示本发明的第十二实施方式的半导体装置,图29中表示本实施方式的半导体装置的等效电路图。本实施方式的半导体装置是具有彼此岛状分离的栅电极的薄膜晶体管T1~T4串联连接的结构的半导体装置(参照图29)。形成该各薄膜晶体管T1~T4的栅电极674a~674d通过去除前面图24所示的2个环状导电性薄膜674的一部分而形成。关于各栅电极674a~674d的形成方法进行说明,首先,如第三实施方式所说明那样,滴下多个包含导电性材料的液滴,形成2个环状导电性薄膜674。FIG. 28 shows a semiconductor device according to a twelfth embodiment of the present invention, and FIG. 29 shows an equivalent circuit diagram of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a semiconductor device having a structure in which thin film transistors T1 to T4 having gate electrodes separated from each other in an island shape are connected in series (see FIG. 29 ). The
接着,从这些环状导电性薄膜674去除作为栅电极而不要的部分的薄膜(即对置沟道区域的部分以外的薄膜),得到栅电极674a~674d。作为薄膜的去除方法,可以使用供给盐酸、硫酸等的酸性溶液,将该酸性溶液与不要的导电性薄膜一起去除的方法,和用氟酸剥离氧化硅膜的方法、蚀刻法等。去除该导电性薄膜的区域并非亚微米数量级,因此蚀刻法是比较廉价的通用方法。去除不要的导电性薄膜后,根据需要可形成栅电极垫(pad)676(参照图28)。Next, from these ring-shaped conductive
此外,本实施方式中,说明了4连接的薄膜晶体管,但可以是3连接的薄膜晶体管或5连接的薄膜晶体管。此时,可增加配置的液滴数、或调整源区域和漏区域的配置形成这种薄膜晶体管。In addition, in this embodiment mode, a 4-connection thin film transistor is described, but a 3-connection thin film transistor or a 5-connection thin film transistor may be used. At this time, such a thin film transistor can be formed by increasing the number of droplets arranged, or adjusting the arrangement of the source region and the drain region.
<第十三实施方式><Thirteenth Embodiment>
图30中表示本发明的第十三实施方式的半导体装置。本实施方式的半导体装置具有与前面图28中所示的半导体装置相同的电路结构,栅电极的形成方法与该半导体装置不同。下面说明本实施方式的栅电极形成方法。FIG. 30 shows a semiconductor device according to a thirteenth embodiment of the present invention. The semiconductor device of this embodiment mode has the same circuit structure as that of the semiconductor device shown in FIG. 28 above, and the method of forming the gate electrode is different from this semiconductor device. Next, the gate electrode forming method of this embodiment will be described.
图31是用以说明本实施方式的栅电极形成方法的图。FIG. 31 is a diagram for explaining a method of forming a gate electrode according to the present embodiment.
首先如图31(A)所示,滴下包含导电性材料的第一液滴,并通过干燥形成追随第一液滴外形的环状导电性薄膜674。接着滴下第二液,使得其包含该环状导电性薄膜674的一部分(参照图31(B))。此时通过控制第二液滴的分散剂、干燥速度、第二液滴包含的导电性材料的粒径、接触角、浓度、第一液滴滴下后到第二液滴滴下的时间间隔,再分散或再溶解第二液滴包含的环状导电性薄膜674(即由第一液滴形成的环状导电性薄膜)的一部分。这样,再分散或再溶解第二液滴包含的环状导电性薄膜674后,通过干燥第二液滴等,形成图31(C)所示的追随第二液滴外形的环状导电性薄膜674。First, as shown in FIG. 31(A), a first droplet containing a conductive material is dropped and dried to form a ring-shaped conductive
对应栅电极数反复执行上述说明的一连串的工序后,从各计算(勘定)导电性薄膜674去除作为栅电极不要的部分的薄膜(参照第十实施方式),得到图30所示的栅电极674a~674d。可通过使其干燥的容易廉价工序就可形成多个具有亚微米数量级宽度的薄膜晶体管的栅电极。本实施方式中,与第十实施方式同样,部分去除导电性薄膜,使各栅电极674a~674d独立,但不去除导电性薄膜,连接各栅电极也可以。After repeating the above-described series of steps in accordance with the number of gate electrodes, the unnecessary parts of the gate electrodes are removed from each calculated (measured) conductive film 674 (refer to the tenth embodiment), and the
<第十四实施方式><Fourteenth embodiment>
图32中表示本发明的第十四实施方式的半导体装置的构成。本实施方式的半导体装置具有与前面图30所示的半导体装置相同的电路构成,仅栅电极的形状不同。具体说,图32所示的栅电极674a~674d大致为直线状。下面说明这种直线状栅电极形成方法。FIG. 32 shows the configuration of a semiconductor device according to a fourteenth embodiment of the present invention. The semiconductor device of this embodiment has the same circuit configuration as the semiconductor device shown in FIG. 30 above, and only the shape of the gate electrode is different. Specifically, the
图33是用以说明本实施方式的栅电极形成方法的图。FIG. 33 is a diagram for explaining a method of forming a gate electrode according to the present embodiment.
本实施方式中,为得到大致直线状的栅电极,以比包含导电性材料的液滴干燥时间快的时间间隔连续滴下该液滴(参照图33(A)。具体说,先滴下的液滴(例如图33(A)中虚线所示最上的液滴)干燥后在该液滴周边部形成环状导电性薄膜之前,与先滴下液滴部分重叠地滴下下一液滴(例如图33(A)中虚线所示的正中央的液滴)。滴下的各液滴通过湿润扩展而融合,最终得到如图33(A)所示的,在各液滴端部连续的2根一对的大致直线状的导电性薄膜(下面叫直线状导电性薄膜)。In this embodiment, in order to obtain a substantially linear gate electrode, the droplets containing the conductive material are continuously dropped at time intervals faster than the drying time of the droplets (see FIG. 33(A). Specifically, the droplets dropped first (For example, the uppermost droplet shown by the dotted line in FIG. The droplet in the center shown by the dotted line in A). Each dropped droplet fuses by wetting and spreading, and finally obtains a pair of two continuous pairs at the end of each droplet as shown in Figure 33(A). A substantially linear conductive film (hereinafter referred to as a linear conductive film).
这样,形成2根一对的直线状导电性薄膜674(对应图33(A)所示的栅电极674a,674b )时,与上述同样滴下多个液滴,以形成新的2根对直线状导电性薄膜674。但是,本实施方式中,各栅电极的配置间隔w1(参照图33(C))比2根一对的直线状导电性薄膜674的间隔w2(参照图33(C))设定得窄,因此可连续滴下液滴以包含已经形成的直线状导电性薄膜674的一部分。In this way, when forming two pairs of linear conductive films 674 (corresponding to the
其结果,如图33(C)所示,得到双层形成的2根一对直线状导电性薄膜674构成的栅电极647a~674d。通过上说明的方法,通过滴下多个包含导电材料的液滴,并使其干燥这样的容易廉价工序可形成多个具有亚微米数量级的宽度的薄膜晶体管的栅电极。另外,本实施方式中,各栅电极的配置间隔w1设定得比2根一对的直线状导电性薄膜674的间隔w2窄,但当然也可以将各栅电极的配置间隔w1设定得比2根一对的直线状导电性薄膜674的间隔w2宽。As a result, as shown in FIG. 33(C), gate electrodes 647a to 674d composed of two pairs of linear conductive
此外,上述实施方式中,半导体区域表示出1个连续的区域,但对应于多个晶体管的每一个可分别形成岛区域。此时,各晶体管的源和漏区域独立,与构成电路的情况相比,具有更多样式。各实施方式中源和漏区域的配置可夹持沟道区域彼此相反。In addition, in the above-mentioned embodiments, the semiconductor region represents one continuous region, but island regions may be formed for each of the plurality of transistors. In this case, the source and drain regions of each transistor are independent, and there are more patterns than the case of forming a circuit. The configuration of the source and drain regions in various embodiments may be opposite to each other sandwiching the channel regions.
<第十五实施方式><Fifteenth embodiment>
本发明的第十五实施方式涉及包括由本发明的薄膜晶体管的制造方法制造的半导体装置等的电光学装置。作为电光学装置的一个例子,举出有机EL(电致发光)显示装置。A fifteenth embodiment of the present invention relates to an electro-optical device including a semiconductor device or the like manufactured by the thin film transistor manufacturing method of the present invention. An example of an electro-optical device is an organic EL (electroluminescence) display device.
图34是说明第四实施方式的电光学装置100的构成的图。本实施方式的电光学装置(显示装置)100,包括:在基板上按矩阵状配置包含薄膜晶体管T1~T4的像素驱动电路而构成的电路基板(有源矩阵基板);由像素驱动电路驱动而发光的发光层;向包含各薄膜晶体管T1~T4而构成的像素驱动电路提供驱动信号的驱动器101和102而构成。驱动器101经扫描线Vsel和发光控制线Vgp而对各像素区域提供驱动信号。驱动器102经数据线Idata和电源线Vdd向各像素区域提供驱动信号。通过控制扫描线Vsel和数据线Idata进行对于各像素区域的电流程序,可控制发光部OELD的发光。构成像素驱动电路的各薄膜晶体管T1~T4和驱动器101,102适用上述第一或第二实施方式的制造方法形成。FIG. 34 is a diagram illustrating the configuration of an electro-
另外,作为电光学装置的一个例子说明了有机EL显示装置,但此外可同样制造液晶显示装置等各种电光学装置。In addition, an organic EL display device was described as an example of an electro-optical device, but various electro-optical devices such as liquid crystal display devices can be similarly manufactured.
接着说明适用本发明的电光学装置100而构成的各种电子仪器。图35是采用电光学装置100的电子仪器例子的图。图35(A )是对移动电话机的适用例子,该移动电话机230备有天线部231、声音输出部232、声音输入部233、操作部234、和本发明的电光学装置100。这样,本发明的电光学装置可用作显示部。图35(B)是对摄像机的适用例子,该摄像机240备有受像部241、操作部242、声音输入部243、和本发明的电光学装置100。这样,本发明的电光学装置可用作取景器或显示部。图35(C)是对便携式个人计算机(所谓PDA)的适用例子,该计算机250备有照相机部251、操作部252、和本发明的电光学装置100。这样本发明的电光学装置可用作显示部。Next, various electronic devices configured by applying the electro-
图35(D)是对头戴式显示器的适用例子,该头戴式显示器260备有带子261、光学系统容纳部262和本发明的电光学装置100。这样本发明的电光学装置可用作图像显示源。此外,本发明的电光学装置100不限于上述例子,可适用于可采用有机EL显示装置、液晶显示装置等的显示装置的所有电子仪器。例如,此外可灵活用于带显示功能的传真装置、数字照相机的取景器、便携型电视、电子记事本、电光揭示板、宣传广告用显示器等。FIG. 35(D) is an example of application to a head-mounted display. This head-mounted
图36(A)是对电视机的适用例子,该电视机300备有本发明的电光学装置100。对于用于个人计算机等的监视器装置,同样可适用本发明的电光学装置。图36(B)是对卷起式(roll up)电视机的适用例子,该卷起式电视机备有本发明的电光学装置100。FIG. 36(A) is an example of application to a television set 300 equipped with the electro-
上述各实施方式的制造方法可用于除电光学装置制造外的各种仪器的制造。例如,可制造FeRAM(铁电RAM)、SRAM、DRAM、NOR型RAM、NAND型RAM、浮动栅型非易失性存储器、磁性RAM(MRAM)等各种存储器。适用微波的非接触型通信系统中,在制造装载了微小电路芯片(IC芯片)的廉价的标记(tag)的情况下也可适用。The manufacturing methods of the above-described embodiments can be used in the manufacture of various devices other than the manufacture of electro-optical devices. For example, various memories such as FeRAM (ferroelectric RAM), SRAM, DRAM, NOR RAM, NAND RAM, floating gate nonvolatile memory, and magnetic RAM (MRAM) can be manufactured. In a non-contact communication system to which microwaves are applied, it is also applicable to manufacture of inexpensive tags on which tiny circuit chips (IC chips) are mounted.
本发明不限定于上述各实施方式的内容,在本发明的主旨范围内可进行种种变形。例如,上述实施方式中,作为半导体膜的一个例子,采用硅膜进行了说明,但半导体膜不限定于此。上述实施方式中,作为使用本发明的半导体膜而形成的半导体元件的一个例子,使用薄膜晶体管进行了说明,但半导体元件不限定于此,可形成其他元件(例如薄膜二极管等)。此外,本发明的薄膜晶体管除用作像素晶体管外,还可用作集成电路的晶体管。The present invention is not limited to the contents of the above-described embodiments, and various modifications can be made within the scope of the present invention. For example, in the above-described embodiments, a silicon film has been used as an example of a semiconductor film for description, but the semiconductor film is not limited thereto. In the above embodiments, a thin film transistor was used as an example of a semiconductor element formed using the semiconductor film of the present invention. However, the semiconductor element is not limited thereto, and other elements (for example, thin film diodes, etc.) may be formed. In addition, the thin film transistor of the present invention can be used as a transistor of an integrated circuit in addition to being used as a pixel transistor.
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