CN100428352C - Decoding system for 8 to 14 modulation or 8 to 16 modulation - Google Patents

Abstract

The present invention proposes a decoding system for 8-14 modulation or 8-16 modulation (EFM/ESM), which includes an analog-to-digital conversion device, an adaptive equalization device and a Viterbi decoding device. The analog-to-digital conversion device receives an analog signal with EFM or ESM modulation characteristics, and converts it into a digital signal with EFM or ESM modulation characteristics; the adaptive equalization device converts the digital signal with EFM or ESM modulation characteristics into a first signal with a minimum phase characteristic; the Viterbi decoding device receives the first signal, and generates a decoded signal according to a Viterbi algorithm and a channel model; wherein, the Viterbi decoding device calculates a path from a branch to a node When the value is , according to the EFM or ESM modulation characteristics, the path that does not exist is discarded.

Description

Decoding system for 8 to 14 modulation or 8 to 16 modulation

technical field

The present invention relates to the technical field of decoding, in particular to a decoding system for 8-14 modulation or 8-16 modulation (EFM/ESM).

Background technique

In an environment with cross data interference (intersymbol interference, ISI), because the read data is affected by the preceding and following data bits, the partial response maximum likelihood (PRML, Partial Response Maximum Likelihood) technology is often used to eliminate reception The phenomenon of cross data interference (ISI) in the data. Viterbi decoding is generally used to resolve signals with cross-data interference.

Viterbi decoding is based on some conditional probabilities to examine possible paths and choose the best one. FIG. 1 is a PRabba channel model, and FIG. 2 is a schematic diagram of Trellis when a is 1 and b is 2 in the PRabba channel model.

In DVD and CD data, due to the use of 8 to 14 modulation or 8 to 16 modulation (eight to fourteen modulation/eight to sixteen modulation, EFM/ESM), there is no run length (run length) of 1 in the data string and 2 data strings. Therefore, when solving EFM/ESM modulated data strings, the Trellis diagram in FIG. 2 can be simplified to the Trellis diagram in FIG. 3 , that is, data strings with a series length of 1 and 2 are excluded. In FIG. 3 , the dotted line represents that a4 is -1, and the solid line represents that a4 is +1. Figure 4 is a schematic diagram of Viterbi decoding using a simplified Trellis graph, where the input sequence is {-1, -1, -1, -1, +1, +1, +1, -1, -1, -1, - 1, -1, +1, +1, +1, +1, +1, +1}. The output sequence is {4, 0, -4, -6, -4, 0, 4, 4, 0, -4, -6, -6, -4, 0, 4, 6, 6, 6}. At the beginning, starting from the node (-1-1-1), the path value from column 0 to column 1 is calculated according to the received data. The node (-1-1-1) has two branches, respectively connected to the node (-1-1-1) and the node (-1-1+1). To calculate the path value from node (-1-1-1) to node (-1-1-1), substitute the output data (4) into the path value formula, that is, substitute s=4 into 9+3s and 4 +2s, you can get 21 and 12 respectively. Label 21 and 12 above node (-1-1-1) and node (-1-1+1) in column 1, respectively. When calculating the path value from column 1 to column 2, at this time, substitute s=0 into 9+3s, 4+2s and 0 to get 9, 4 and 0 respectively, then add 9 and 21, 4 and 21 Add, add 0 and 12, and get the accumulated path value 30, 25, 12, and then mark 30, 25, 12 in the nodes (-1-1-1), (-1-1+1) of column 2 ) and above the node (-1+1+1). And so on. However, the reading speed of DVD and CD drives increases rapidly, and the conventional technology is to increase the timing of the decoding chip. Although this can solve the decoding problem, it will increase the design difficulty of the decoding chip, and at the same time, due to the increase of the operating frequency, the power consumption of the chip will increase and the problem of heat dissipation will also occur. Therefore, the known decoding systems for DVD and CD optical drives still need to be improved.

Contents of the invention

The purpose of the present invention is to provide a decoding system for 8 to 14 modulation or 8 to 16 modulation (EFM/ESM), so as to avoid the difficulty of decoding chip design caused by the known technology, and to reduce the power consumption of the chip Problems of enlargement and heat dissipation.

According to a feature of the present invention, a decoding system for 8 to 14 modulation or 8 to 16 modulation (EFM/ESM) is proposed, the system includes an analog to digital conversion device, an adaptive equalization device and a Viterbi decoding device. The analog-to-digital conversion device receives an analog signal with EFM or ESM modulation characteristics, and converts it into a digital signal with EFM or ESM modulation characteristics; the adaptive equalization device is coupled to the analog-to-digital conversion device to The digital signal with EFM or ESM modulation characteristics is replaced with a first signal with minimum phase characteristics; the Viterbi decoding device is coupled to the adaptive equalization device to receive the first signal, and according to the Viterbi algorithm and a A channel model is used to generate a decoding signal; wherein, when the Viterbi decoding device calculates a path value from a branch to a node, it discards non-existing paths according to the EFM or ESM modulation characteristics.

According to another feature of the present invention, a decoding system for 8-to-14 modulation or 8-to-16 modulation (EFM/ESM) modulation is proposed, the system includes an analog-to-digital conversion device, a dividing circuit , a frequency and phase recovery device, an adaptive equalization device and a Viterbi decoding device. The analog-to-digital conversion device receives an analog signal with EFM or ESM modulation characteristics, and converts it into a digital signal with EFM or ESM modulation characteristics; the division circuit has hysteresis (hysteresis) characteristics, so that the EFM or an analog signal with ESM modulation characteristics is converted into a second signal; the frequency and phase recovery device is coupled to the division circuit and the analog-to-digital conversion device to generate an adjustment signal according to the second signal to adjust the analog-to- The sampling time of the digital conversion device, to restore the frequency and phase of the analog signal of the EFM or ESM modulation characteristic; The digital signal is converted into a first signal with a minimum phase characteristic; the Viterbi decoding device is coupled to the adaptive equalization device to receive the first signal, and generate a decoded signal according to a Viterbi algorithm and a channel model; wherein , when the Viterbi decoding device calculates the value of a path from a branch to a node, according to the EFM or ESM modulation characteristic, the path that does not exist is discarded.

Because the present invention is novel in design, can provide industrial utilization, and has indeed enhanced effect, so apply for the invention patent according to law.

Description of drawings

FIG. 1 is a schematic diagram of a PRabba channel model.

Fig. 2 is a schematic diagram of Trellis when a is 1 and b is 2 in the PRabba channel model.

Figure 3 is a simplified Trellis schematic of the PRabba channel model.

Fig. 4 is a schematic diagram of Viterbi decoding using a simplified Trellis graph.

FIG. 5 is a block diagram of a decoding system for EFM or ESM modulation according to the present invention.

Fig. 6 is a schematic diagram of expanding the Trellis diagram in Fig. 3 from 2 columns to 4 columns.

Figure 7 is a modified Trellis diagram of the present invention.

FIG. 8 is a schematic diagram of Viterbi decoding according to FIG. 7 according to the present invention.

FIG. 9A is a simplified Trellis diagram of a PRaa channel model of the present invention.

FIG. 9B is a modified Trellis diagram according to FIG. 9 according to the present invention.

Figure 10A is a simplified Trellis diagram of a PRaba channel model of the present invention.

FIG. 10B is a modified Trellis diagram according to FIG. 10 according to the present invention.

Symbol Description

Analog to digital conversion device 510 Adaptive equalization device 520

Viterbi decoding device 530 split circuit 540

Frequency and phase recovery device 550

Detailed ways

FIG. 5 is a block diagram of a decoding system used in 8-to-14 modulation or 8-to-16 modulation (EFM/ESM) of the present invention, which includes an analog-to-digital conversion device 510, an adaptive equalization device 520, A Viterbi decoding device 530 , a dividing circuit 540 and a frequency and phase recovery device 550 .

The analog-to-digital conversion device 510 receives an analog signal with EFM or ESM modulation characteristics, and converts it into a digital signal with EFM or ESM modulation characteristics. The slicer 540 has a hysteresis characteristic, and it judges the magnitude of the input signal, and when the input signal is greater than the first hysteresis value, the output is a positive potential. And when the input signal is smaller than the second hysteresis value, the output is zero. The division circuit 540 converts the analog signal with EFM or ESM modulation characteristics into a second signal. The frequency and phase recovery device 550 is coupled to the dividing circuit 540 and the analog-to-digital conversion device 510, so as to generate an adjustment signal according to the second signal to adjust the sampling time of the analog-to-digital conversion device, so the frequency and phase recovery device 550 is to use the signal generated by the division circuit 540 to restore the frequency and phase of the analog signal with EFM or ESM modulation characteristics.

An adaptive equalization device 520 is coupled to the analog-to-digital conversion device 510 to convert the digital signal with EFM or ESM modulation characteristics into a first signal with minimum phase characteristics. The Viterbi decoding device 530 is coupled to the adaptive equalization device 520 to receive the first signal and generate a decoded signal according to the Viterbi algorithm and a channel model. Wherein, the Viterbi decoding device discards non-existing paths according to the EFM or ESM modulation characteristics when calculating the path value from a branch to a node.

Figure 6 expands the Trellis diagram in Figure 3 from 2 columns to 4 columns. It can be seen from FIG. 6 that after the nodes in column 1 and column 3 are determined, the nodes in column 2 can be uniquely determined. That is, when the decoding path passes through the node in column 1 (-1-1-1) and the node in column 3 (-1-1+1), the decoding path must pass through the node in column 2 (-1-1-1 ), as indicated by the darker thick line in Figure 6. Similarly, when the decoding path passes through the node in column 2 (-1-1-1) and the node in column 4 (-1+1+1), the decoding path must pass through the node in column 3 (-1-1+ 1).

表示。列1节点(-1-1-1-1)遇到(-1+1)译码数据时，则至列2节点(-1-1-1+1)，图7中以一点虚线

表示。列1节点(-1-1-1-1)遇到(+1+1)译码数据时，则至列2节点(-1-1+1+1)，图7中以实线(→)表示。由于使用EFM/ESM调变，故数据串中并没有连串长度为1及2的数据串，因此列1节点(-1-1-1-1)不会遇到(+1-1)译码数据。列1节点(+1+1+1+1)遇到(+1+1)译码数据时，则至列2节点(+1+1+1-1)，图7中以两点虚线

表示。Based on the above, the Trellis diagram in Figure 3 can be changed to that shown in Figure 7. Figure 7 is a modified Trellis diagram of the present invention that can decode 2 bits at a time. For example, when column 1 node (-1-1-1-1) encounters (-1-1) decoded data, it goes to column 2 node (-1-1-1-1), shown in dotted line in Figure 7

express. When the column 1 node (-1-1-1-1) encounters (-1+1) decoding data, it goes to the column 2 node (-1-1-1+1), and a dotted line is used in Figure 7

express. When column 1 node (-1-1-1-1) encounters (+1+1) decoding data, then to column 2 node (-1-1+1+1), in Fig. 7 with solid line (→ )express. Due to the use of EFM/ESM modulation, there is no series of data strings with a length of 1 and 2 in the data string, so the column 1 node (-1-1-1-1) will not encounter (+1-1) translation code data. When the column 1 node (+1+1+1+1) encounters (+1+1) decoding data, it will go to the column 2 node (+1+1+1-1), as shown in Figure 7 with two dotted lines

express.

From the modified Trellis diagram in Fig. 7, the Viterbi decoding diagram in Fig. 4 is redrawn as shown in Fig. 8 . FIG. 8 is a schematic diagram of Viterbi decoding according to the technique of the present invention. The input sequence is {-1, -1, -1, -1, +1, +1, +1, -1, -1, -1, -1, -1, +1, +1, +1, + 1, +1, +1}. At the beginning, starting from the node (-1-1-1-1), the path value from column 0 to column 1 is calculated according to the received data. Node (-1-1-1-1) has 3 branches connected to nodes (-1-1-1-1), (-1-1-1+1) and (-1-1+1+ 1). Calculate the path value from node (-1-1-1-1) to node (-1-1-1-1) by substituting the output data (4) into the path value formula, that is, substituting s=4 into 3s +9, 2s+4 and 0 can get 21, 12 and 0 respectively. Label 21, 12 and 0 above the nodes (-1-1-1-1), (-1-1-1+1) and (-1-1+1+1) in column 1, respectively. When calculating the path value from column 1 to column 2, since two bits are decoded at a time, s=-4 is substituted into 3s+9, 2s+4, 0, -2s+4, -2s+4 and -3s+ 9, -3, -4, 0, 12 and 21 can be obtained respectively, and then calculate the accumulated path value to obtain 18, 17, 21, 24, 12 and 21, and then 18, 17, 21, 24, 12 and 21 Nodes marked in column 2 (-1-1-1-1), (-1-1-1+1), (-1-1+1+1), (-1+1+1+1) , (+1+1+1-1) and (+1+1+1+1) above. By analogy, the schematic diagram of Viterbi decoding in Fig. 8 can be obtained.

The Viterbi decoding device 530 performs Viterbi decoding according to the modified Trellis diagram in FIG. 7 . Since the Viterbi decoding device 530 uses 2 bits at a time, its sampling rate can be reduced from 1/T to 1/(2T). The processing time of the adaptive equalization device 520 can be increased from 1T to 2T.

The points (tabs) of the adaptive equalization device 520 are related to the impulse response (impulse response) of the transmission channel, the longer the impulse response of a transmission channel is distributed on the time axis, the points (tabs) required by the adaptive equalization device 520 )more. In the present invention, since the processing time of the adaptive equalization device 520 is increased from 1T to 2T, the required tabs can be reduced. Correspondingly, the decoding depth (depth) of the Trellis graph can also be reduced. This not only reduces the required memory, but also reduces the power consumption of the decoding chip.

FIG. 9A is a simplified Trellis diagram of a PRaa channel model, and FIG. 9B is a modified Trellis diagram of the present invention. FIG. 10A is a simplified Trellis diagram of a PRaba channel model, and FIG. 10B is a modified Trellis diagram of the present invention.

In summary, the operating frequency of the analog-to-digital conversion device 510, an adaptive equalization device 520, a Viterbi decoding device 530, a dividing circuit 540 and a frequency and phase recovery device 550 of the present invention can be reduced compared with known techniques half, and the points (tabs) of the adaptive equalization device 520 and the decoding depth (depth) of the Trellis diagram can also be reduced, which can solve the problem of the difficulty of chip design in the known technology, and avoid the power consumption of the chip in the known technology from becoming larger and heat dissipation issues.

The above-mentioned preferred specific embodiments are only examples for convenience of description, and the scope of protection claimed by the present invention should be based on the claims, rather than limited to the above-mentioned embodiments.

Claims (6)

1. A decoding system for 8 to 14 modulation or 8 to 16 modulation, characterized in that the system comprises: An analog-to-digital conversion device, which receives an analog signal with 8-to-14 modulation or 8-to-16 modulation characteristics, and converts it into a digital signal with the 8-to-14 modulation or 8-to-16 modulation characteristics; an adaptive equalization device, coupled to the analog-to-digital conversion device, to convert the digital signal having the 8-to-14 modulation or 8-to-16 modulation characteristic into a first signal having a minimum phase characteristic; and A Viterbi decoding device is coupled to the adaptive equalization device to receive the first signal and generate a decoded signal according to the Viterbi algorithm and a channel model; Wherein, the Viterbi decoding device discards non-existing paths according to the 8-14 modulation or 8-16 modulation when calculating the path value from a branch to a node. 2. The system of claim 1, further comprising: a division circuit, which has hysteresis characteristics, to convert the analog signal with 8-to-14 modulation or 8-to-16 modulation characteristics into a second signal; and A frequency and phase recovery device, coupled to the dividing circuit and the analog-to-digital conversion device, to generate an adjustment signal according to the second signal to adjust the sampling time of the analog-to-digital conversion device to restore the 8 to 14 modulation Variable or 8 to 16 frequency and phase of analog signal with modulation characteristics. 3. The system according to claim 1, wherein when the analog signal of the 8-14 modulation or 8-16 modulation characteristic is greater than a first hysteresis value, the second signal is a positive potential, and when When the analog signal of the 8-14 modulation or 8-16 modulation characteristic is smaller than a second hysteresis value, the second signal voltage is 0. 4. The system of claim 1, wherein the channel model is a partial corresponding channel with abba parameters. 5. The system of claim 1, wherein the channel model is part of corresponding channels with aa parameters. 6. The system of claim 1, wherein the channel model is a partial corresponding channel with aba parameters.

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