CN100382254C

CN100382254C - memory cell with trench transistor

Info

Publication number: CN100382254C
Application number: CNB028254058A
Authority: CN
Inventors: F·劳; D·塔卡斯; J·威尔勒
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2001-12-18
Filing date: 2002-12-10
Publication date: 2008-04-16
Anticipated expiration: 2022-12-10
Also published as: TW575960B; TW200302571A; CN1605120A; JP2005513778A; WO2003052812A2; EP1456876A2; WO2003052812A3; KR20040065288A; KR100554647B1; JP4081445B2

Abstract

The trench depth is optimized in such a way that the locations for electron and hole injections into the storage layer (11), which is disposed in boundary layers (10, 12) between the trench walls and the gate electrode (4), coincide. The junctions (14) at which the doping of the source zone (2) and the drain zone (3) changes into the opposite sign (i.e. that of the conductivity type of the semiconductor body (1)) and which border the channel region (5) abut a curved region of the trench bottom (7) or a curved lower region of the lateral trench walls (6, 8).

Description

The memory cell of tool trench transistor

Technical field

The invention relates to the memory cell of tool storage transistor, it comprises the top surface of gate electrode in semiconductor body or semiconductor layer, this electrode is located between the source region and drain region of groove, this groove is to manifest the identical section that crosses y direction in section ground at least district by district by the semi-conducting material manufacturing of semiconductor body or layer and its, in this, dielectric layer is preferably the ONO layer and is provided as the storage medium between this gate electrode and semi-conducting material.

Background technology

Deutsche Bundespatent 100 39 441 A1 propose the memory cell of tool trench transistor, it is placed in the groove that is established in the semiconductor body top surface, be arranged between this gate electrode that is installed in groove is side direction adjacent source zone, reaching in the adjacent drain region of opposite side is the oxide-nitride-oxide layer sequence, and it is provided to be captured in the charge carrier of source electrode and drain electrode.This kind transistor is arranged for being appropriate to NVM (non-volatility memorizer) memory cell especially well, and the zone that manifests sequencing and eliminate required electric field strength is located at these transistorized zoness of different at large.The result, in case electric charge at nitride by sequencing, it is difficult will eliminating them fully, it is necessary that electronics is injected to programming operations, electronics must penetrate the oxide adjacent courses and be provided as the nitride layer that stores layer with arrival, based on this reason, and the necessary tool kinetic energy of electronics, this generally is known as hot electron, and this kind electronics exists only in that electric field strength is very strong place in the channel below the gate electrode of semiconductor material surface.

The Fig. 5 that discloses for expression gate electrode 4, gate dielectric 9 (it can be ONO especially and stores layer), and have the figure of adjacent semiconductor material of channel region 5 from left to right.In the vertical direction of representing with arrow, energy is drawn, and it increases in the direction of arrow.The crooked a that draws and b show the upper limit of valency electricity band and the lower limit of conductive strips respectively, have two fermi energy level E _F1And E _F2Arriving these can rank, and the state that only can be occupied singly according to the Pauli principle is for being full of electronics.As fermi energy level Ef1 when being low, only minority electrons is located at the conductive strips that semi-conducting material adjoins, as represented by the hachure zone at Fig. 5.Cognizable at higher fermi energy level E _F2Situation under, polyelectron more, and further the higher-energy electronics is present in conductive strips, so, the higher-energy electronics passed to store the oxide skin(coating) of layer in abutting connection with nitride more easy.

Fig. 6 represents the sectional area of typical transistor structure, and it comprises source region 2, drain region 3, gate electrode 4, gate dielectric 9 and this channel region 5.Dotted line is represented the adjoining of development spacing charge area of this channel.When voltage (it is required for this kind of sequencing transistor) was provided using, electronics was accelerated with the direction of arrow and passes channel region, and the length of arrow (it is not really drawn to scale) shows the mean kinetic energy of electronics.Obviously the mean kinetic energy of electronics is increasing towards these drain region 3 travel directions precipitously, and this increased to and very crosses ratio, because electric field strength is increasing towards these drain region 3 travel directions up to that before this drain region just precipitously.When electronics arrives the end of this channel region 5, their energy is that enough height make them can enter this storage layer.

Under the situation of the storage transistor that is positioned at groove, the zone that the electronics tool is used for the suitable energy of sequencing similarly is positioned at the end of this channel region, and in the case, it ends at directly to be lower than this p-conduction doped substrate and enters this n ⁺One side of the channel bottom of the joint in-conduction doped-drain zone.In this source region of tool in the left side and this drain region in the cross section on right side, this favourable sequencing zone is to be positioned at rough this channel bottom at the bottom right-hand side.

To eliminating operation, being injected to of electric hole (charge carrier of tool contrary sign) needs, and it can only be obtained by this GIDL (gate induced drain leakage stream) effect at n-MOSFET.The position that electronics injects and electric hole is injected thereby it be not necessary for identical.Under any circumstance, the memory cell of this kind form can use high applied voltage and/or very long elimination time to be eliminated.

Summary of the invention

The object of the invention is for building a kind of memory cell of tool trench transistor, and wherein program and elimination time significantly are weak point in the conventional memory cells of this kind form.

Purpose of the present invention can be reached and development by the memory cell that use has a following feature:

A kind of memory cell with storage transistor, it comprises the top surface of gate electrode (4) in semiconductor body (1) or semiconductor layer, this electrode is located between the source region (2) and drain region (3) of groove, this groove is to manifest the identical section that crosses y direction in section ground at least district by district by the semi-conducting material manufacturing of semiconductor body or layer and its, in this, this source region (2) and drain region (3) are to form with semi-conducting material by be doped into indivedual joints (14) from top surface, and this gate electrode passes through dielectric layer (9) to insulate with this semi-conducting material, dielectric layer (9) by construction as storage medium, it is characterized in that this joint (14) in a kind of zone in abutting connection with this trench wall, wherein be arranged in spacing (24) 2/3rds big that is at most this trench wall perpendicular to this trench wall of the section of y direction at the height tool of this joint (14) in the bending radius of every bit.

A kind of memory cell with storage transistor, it comprises the top surface of gate electrode (4) in semiconductor body (1) or semiconductor layer, this electrode is located between the source region (2) and drain region (3) of groove, this groove is to manifest the identical section that crosses y direction in section ground at least district by district by the semi-conducting material manufacturing of semiconductor body or layer and its, in this, this source region (2) and drain region (3) are to form with semi-conducting material by be doped into indivedual joints (14) from top surface, and this gate electrode passes through dielectric layer (9) to insulate with this semi-conducting material, dielectric layer (9) by construction as storage medium, it is characterized in that this gash depth (25), as at this joint (14) and between the groove deepest point of vertical direction with respect to the plane of top surface on plane, measure, at the height of this joint (14) spacing (24) one medium-sized of this trench wall at the most with respect to the top surface of this semiconductor body (1) or layer.

A kind of memory cell with storage transistor, it comprises the top surface of gate electrode (4) in semiconductor body (1) or semiconductor layer, this electrode is located between the source region (2) and drain region (3) of groove, this groove is to manifest the identical section that crosses y direction in section ground at least district by district by the semi-conducting material manufacturing of semiconductor body or layer and its, in this, this source region (2) and drain region (3) are to form with semi-conducting material by be doped into indivedual joints (14) from top surface, and this gate electrode passes through dielectric layer (9) to insulate with this semi-conducting material, dielectric layer (9) by construction as storage medium, it is characterized in that this joint (14) in a kind of zone in abutting connection with this trench wall, wherein be arranged in this trench wall perpendicular to the section of y direction and have bending radius at the most greater than by the minimum value that bending radius embodied 10% at this trench wall.

A kind of memory cell with storage transistor, it comprises the top surface of gate electrode (4) in semiconductor body (1) or semiconductor layer, this electrode is located between the source region (2) and drain region (3) of groove, this groove is to manifest the identical section that crosses y direction in section ground at least district by district by the semi-conducting material manufacturing of semiconductor body or layer and its, in this, this source region (2) and drain region (3) are to form with semi-conducting material by doping, and this gate electrode passes through dielectric layer (9) to insulate with this semi-conducting material, dielectric layer (9) comprises and is positioned at adjacent courses (10,12) the storage layer (11) between, it is characterized in that selecting and this relevant gash depth of a zone, the charge carrier of this storage layer (11) is neutralized in the elimination operation in this zone, and make the electric field composition in programming operations act on this charge carrier, this composition is parallel to wall or is parallel to the tangent line of this channel bottom and is arranged perpendicular to this y direction, and is maximum in same area.According to the present invention, be selected such that the electric field composition that in programming operations, acts on this charge carrier about the gash depth of charge carrier that stores layer in the zone that the elimination operation is neutralized, this composition is parallel to the tangent line of wall or is parallel to this channel bottom and vertically is arranged perpendicular to this groove, is maximum in same area.This mode, this gash depth are harmonious by the position that optimization makes electronics and electric hole inject in this way.Contrary sign is changed into engaging of drain region doping in the source region, also reaches the symbol of the conductive form of this substrate or semiconductor body, in abutting connection with the bending area of this channel bottom or the crooked lower zone of this lateral grooves wall.

Description of drawings

More being described in detail in hereinafter of this memory cell, and with reference to the 1st to 6 figure.

Fig. 1: through the schematic section of two adjacent trenches.

Fig. 2: at the section of represented two grooves of Fig. 1, it is with the assistance emulation of model, the bending of the downward E-field-assembly of its tool.

Fig. 3 and Fig. 4: the corresponding section of memory cell is built in invention.

Fig. 5 and Fig. 6: representative that brief introduction in patent specification is narrated.

Embodiment

Fig. 1 represents the section of two grooves, and it produces on the semiconductor body 1 that is used as substrate or is that the substrate upper semiconductor layer produces.At least district by district section ground, groove longitudinally the ditch grooved profile be identical, therefore, the representative of Fig. 1 looks like identical at the section in projection plane the place ahead and the section at the projection plane rear.In this patent specification and claim, vertically represent the section that perpendicular segment can not change along this section.

Zone on the relevant top surface of this semiconductor body 1 or semiconductor layer, source region 2 and drain region 3 example of this left-hand side trench transistor (herein for) forms by incorporating dopant into.This semiconductor body 1 is through doping p-conduction, for example; This source region 2 and drain region 3 then form this n in view of the above ⁺-conduction.Adjoining between opposite doped region,, after this it be called joint 14 by typically clear expression; They are in (as use SIMS) of position for detecting of this semi-conducting material.Gate electrode 4, for example polysilicon electrode is adorned not in each groove.Channel region 5 develops below source electrode and drain region in that the abutment surface of this semi-conducting material is opposite with this gate electrode.

The

sidewall

6,8 of this groove and bottom 7 presentation surfaces are to the surface of the semi-conducting material of this groove.Between this gate electrode 4 and this semi-conducting material is dielectric layer 9, and it is used as gate electrode and it covers the wall and the bottom of this groove.This dielectric layer 9 is formed as storage medium, and for finishing this, this dielectric layer 9 is preferably multilayer, and it comprises that at least one stores layer 11, and it is between

adjacent courses

10,12 in this Fig. 1 example.This

adjacent courses

10,12 is oxide (particularly herein for silicon dioxide), yet should storage layers 11 can be nitride (Si herein ₃N ₄).

For example, in the operation of this memory cell, be sequencing, the voltage that has 0 volt is in this source region, and 9 volts voltage is in this

gate electrode

4, and 6 volts voltage is in this drain region 3; Be to eliminate, exist-8 volts voltage in the voltage of this gate electrode and 5 volts in this drain region.In this was graphic, the groove of the memory cell on the left of this dielectric layer 9 of channel bottom is comfortable omitted, and this is to be represented by corresponding dotted line.For helping following narration, horizontal arrow 22 and vertical arrows 23 be contained in this graphic in, it shows the lateral to drain electrode from source electrode respectively, and the vertical direction that enters gash depth.Except these, the spacing 24 between the trench wall of the height of this joint 14 and the degree of depth 25 (that is engaging 14 total vertical dimensions certainly) of this groove that is lower than the height of this joint 14 to this groove deepest point also be contained in this graphic in.

This voltage via respectively in the place ahead of projection plane and the contact that connects of rear and be applied to this source region 2 and drain region 3, yet this grid voltage is via horizontal expansion, that is is supplied at this word line 13 of this projection plane.In this programming operations, the known voltage value of the groove of the bottom of tool semicylinder housing shape produces the distribution of electric field strength, and it is being a maximum with this channel bottom tangent or with assembly right-hand side below this engages of the expression section plane of this trench wall tangent.

These connections are shown in Fig. 2, and its section that is illustrated in expression illustrated in Figure 1 is with the Model Calculation of the groove that carries out tool semicylinder bottom.The circuit of crooked this section of expression, in this bending, the composition E γ of electric field, it is represented by arrow, the identical value of difference tool.Some inference about the size of the absolute value of electric field composition can be obtained thus, and electric field extends in the section that is tangential to this trench wall or bottom.

Can obviously find out side memory cell leftward, Fig. 1 its by precharge using corresponding voltage sequencing, rough be when passing the axle A of the semicylinder that forms the bottom when this arrow (being 22 ' now), to take place in the maximum of this electric field composition of this channel longitudinal extension of direction that is rotated down 30 ° arrow 22.At this point, the effective procedure generation of this memory cell, however the zone that electric hole is infused in above the joint 14 that is located immediately at this drain region 3 in eliminating operation takes place.

Fig. 3 represents the suitableeest memory cell of invention of this kind form, and wherein the connection zone of the curved bottom of this groove is placed near the pn between this drain region 3 and this opposite doped semiconductor materials and engages.Under the help of mode computation and emulation and/or sample plot under the help of implementation structure assembly, so most the precise measure of this memory cell of showing can disclose and not have basic difference indivedual example specific embodiments, this emulation is used always by knowing this storage person.But can not obtain corresponding numerical data to all specific embodiments within the scope of the present invention.So, in detail explain now that what person constitutes principle of the present invention, the technology intention can be required in the literary composition by point out with replace manufacturing this type of memory cell know this storage person.

One of them of main importance be for not only only be channel length, but this channel bottom crooked and lower zone form that this lateral grooves is closed basically, and its decision is tangential on the bending of the composition that this trench wall arranges.With this groove necessary means enter this semi-conducting material to make deeply that enough the basic part of this trench wall is positioned at the embodiment of source electrode and drain region below opposite, in memory cell of the present invention, provide lateral thrust between the perpendicular sidewall of actual bottom and this groove, be infused in the zone that this elimination operation takes place in electric hole.Be provided for the direct aligning above this pn-engages of zone generation of sequencing and elimination by the injection of charge carrier.For finishing this, this gash depth is reduced in view of the above.

This is shown in the section of Fig. 3, wherein reference signs tool and the formerly same meaning of each figure.In this source region 2 of 14 of the top surface of this semiconductor body 1 or semiconductor layer and the joints between the opposite doped semiconductor materials in this source region 2 or drain region 3 and the vertical dimension of drain region 3 with this, yet (, this unnecessary formation flat surface on practice, but can be irregular slightly manufactured) in this memory cell only slightly less than total vertical dimension of this groove.When the position that engages by the SIMS decision, the mean value on a certain zone is used.

Total vertical dimension tool of this groove surpasses this and engages 14 downward giving prominence to, and after this it is called as this gash depth 25.This is by measuring in vertical direction in that the joint 14 of this groove is accurate to the position of this channel bottom (about the plane on the main surface, top of this semiconductor body or semiconductor layer) deepest point, that is vertically with respect to the plane of the top surface of this semiconductor body or layer.

In the preferable examples specific embodiment, this degree of depth 25 is at most spacing 24 (this groove width) one medium-sized of this trench wall at the height of this joint 14.This degree of depth 25 is selected such that according to the related geometry of this ditch grooved profile this joint 14 individually contacts this trench wall in a kind of zone, in this zone, wherein be at most spacing 24 2/3rds big of this trench wall in the height tool bending radius of this joint 14 crossing this bending of this trench wall of section longitudinally.

When this channel bottom tool has the shape of the semicylinder housing of radius r, the twice of radius is big for this reason at the most in this spacing 24 that engages this trench wall of height of 14, is referred to as 2r at the most.The bending radius of this channel bottom is r in this example; Therefore, this depth capacity 25 equals r expediently, though be preferably littler slightly.

In the radius r of for example this semicylinder is 55 rice how, and this degree of depth is 55 rice or littler slightly how.Because of channel length should be not too small, 30 how the value of rice can the designated below limit as this degree of depth 25, and this will be kept as far as possible.Known 30 these degree of depth 25 of rice how, the radian of this channel bottom, its section below this joints 14 is a length visible and its rough expression channel, equal 120.88 how rice to the 55 known radius r of rice how, and 134.76 how rice to 70 how meter known radius r; The spacing 24 of this trench wall of the height of this joint 14 equal 97.98 how rice to r=55 rice how, and 114.89 how rice to r=70 rice how; Under any situation, it is little equaling in 2/3rds of the spacing 24 of this trench wall of the height of this joints 14 at this joint 14 in abutting connection with this bending radius of the point of this trench wall.

When for example vertical dimension of this source region 2 and this drain region 3 is 150 rice how, the suitableeest total gash depth of measuring when the top surface of this semiconductor body or layer certainly for 180 how rice to 205 how rice scope to radius r be 55 how rice and 180 how rice to 220 how the scope of rice be 70 rice how to radius r.In this example, this channel bottom does not need the shape of the whole semicylinder housing of tool; This lateral grooves wall directly or to remove slightly above this joint is connected to this curved bottom, bottom feasible only semicylinder housing partly is present in-that is the housing tool central authorities angle of cylinder fan type is less than 180 °.

This gash depth must be applied to other bending radius or thereby other shape of this channel bottom of this channel bottom.The degree of concentration of dopant is also played the part of a kind of role, and it must consider other implantation of this channel region 5.Provide a little for improving this channel conductivity and reducing the meaning that the implantation at the electric field of the point of precipitous channel curvature makes, inject this storages at this regional charge carrier and layer can not take place for precipitous bending is feasible in the zone of this channel bottom.Thereby the implantation that provides tapered slightly channel bottom and dopant to enter at the lower semiconductor material in the zone of bottom deepest point is within the scope of the present invention.In this by select this degree of depth 25 greater than this trench wall spacing 24 of the height of this joint 14 one medium-sized bigger channel length is provided is favourable.Yet, also in this example, longitudinally in the section, engaging 14 in abutting connection with this trench wall place at this perpendicular to this groove, the crooked tool of this wall is 2/3rds big radiuses of this spacing 24 at the most.

In some specific embodiments, when the degree of depth 25 of this groove is favourable less than the half in the spacing 24 of this trench wall of the height of this joint 14 significantly, the side direction of particularly working as the less bending of this groove tool or flat internal and precipitous bending is partly real, and the main part of this wall is rough at least vertically extends, the basic curvature that makes exist only in this bottom than downside.Even so, in these specific embodiments, must consider that this channel length may be not enough to provide the very short degree of depth 25 and the very smooth channel bottom that gets, perhaps the optimization that partly this invention is intended to can be compensated because of little channel length.

This trenched side-wall can be tilted at their upper area to vertical (arrow 23 of Fig. 1).Fig. 4 represents the corresponding section of additional examples specific embodiment, and wherein the sidewall of this groove obviously tilts at their upper area, and some 5 ° of its tools are to vertical angle of inclination.In this example specific embodiment,

sidewall

6,8 only above this channel bottom 7 tool the groove longitudinal direction extend narrow regional 15,17, in this zone, the sidewall direction in section is crooked slightly.Lower zone 16,18 at sidewall, in section to the tangential direction of wall be at the most 10 ° to vertical than wide-angle, for be the ground bending quite a bit, make the zone of remarkable more precipitous curvature of this trench wall in this this channel bottom 7 between the lower zone 16,18 and this channel bottom 7 of this sidewall.

In this example specific embodiment, this gash depth 25 be selected such that between source region and this opposite doped semiconductor materials or the pn between drain region and this opposite doped semiconductor materials engage (engaging 14) and be positioned over the height of this precipitous bending or the position thereon just by rough.Also can embody herein sequencing only betide tool the trench region above the zone of precipitous curvature take place.

For the purpose of illustration, be omitted at the section of the right-hand side groove of comfortable Fig. 4 of dielectric layer 9 of lower zone, this also can be represented by dotted line.Bending radius 19,20 and 20 comprised, its not to scale or accurately drawn, this length only be intended to illustrate this bending radius 19 in the zone that is provided to this actual bottom side direction for very little.Adjacent area 16,18 tools of sidewall are basically than macrobending radius 20, and the bending radius 21 of bottom 7 similarly is sizable.

Note the tangent line to trench wall, it extends on the projection plane transverse to the groove y direction, by the part of formed this wall of sidewall can by at the most 10 ° to the quite little angle of inclination definition of vertical (arrows 23).In groove according to the specific embodiment of Fig. 4, the part of the trench wall of existence between these sidewalls and this bottom deepest point, the bending radius (it perpendicular to y direction) of its tool in the section of Fig. 4, it is at most the medium-sized of spacing 24 between the trench wall at the height of this joint 14 at every bit, this engage 14 in these zones the sidewall in abutting connection with this groove.

Can suppose, eliminate operating period, the zone that the rough at least respectively the most precipitous curvature with this trench wall of tool in the zone that takes place is injected in electric hole is harmonious.So, when this engage 14 bending radius be at the most 10% greater than in these zones of this minimum value of trench wall embodiment in abutting connection with this lateral grooves wall.

This memory cell is preferably tool represented image symmetrical structure in each figure, because in the case, and when institute's applied voltage is inversed, sequencing and eliminate and also betide the storage layer that is positioned at each figure left-hand side.

Claims

1. A memory cell with a storage transistor comprising a gate electrode (4) on the top surface of a semiconductor body (1) or a semiconductor layer, the gate electrode being located in the source region (2) and the drain of the trench Between the regions (3), the trenches are produced from the semiconductor material of the semiconductor body or semiconductor layer and which exhibit at least section by section the same cross-section transverse to the direction of the longitudinal axis, where the source region (2) and the drain The region (3) is formed in semiconductor material by doping from the top surface to the respective junction (14), and the gate electrode is insulated from the semiconductor material by a dielectric layer (9), which is Constructed as a storage medium, characterized in that the joint (14) adjoins a groove wall in a region in which the groove wall has a section perpendicular to the direction of the longitudinal axis and the groove wall has a curvature radius , the height of each point to the junction (14) is at most two-thirds of the groove wall spacing (24).

2. The memory cell according to claim 1, wherein the trench has sidewalls (6, 8) with respect to the direction of the longitudinal axis, which are perpendicular to the plane of the top surface of the semiconductor body (1) or semiconductor layer direction or at most 10° offset from vertical; in the region between the side walls (6, 8) and the deepest point of the trench relative to the plane of the top surface, the section of the trench wall is perpendicular to the The longitudinal axis is oriented and the groove wall has a radius of curvature, the height of each point from the joint (14) is at most half the distance (24) of the groove wall.

3. A memory cell with a storage transistor comprising a gate electrode (4) on the top surface of the semiconductor body (1) or semiconductor layer, the gate electrode being located in the source region (2) and the drain of the trench Between the regions (3), the trench is produced from the semiconductor material of the semiconductor body or the semiconductor layer and which exhibits at least section by section the same cross-section transverse to the direction of the longitudinal axis, where the source region (2) and the drain The region (3) is formed in semiconductor material by doping from the top surface to the respective junction (14), and the gate electrode is insulated from the semiconductor material by a dielectric layer (9), which is Constructed as a storage medium, characterized in that the groove depth (25) is relative to the plane of the top surface of the junction (14) and in a direction perpendicular to the plane of the top surface of the semiconductor body (1) or semiconductor layer The height at this junction (14), measured between the deepest points of the grooves, is at most half the distance (24) between the groove walls.

4. The memory cell according to claim 3, wherein the junction (14) adjoins the groove wall in a region where the groove wall in a section perpendicular to the direction of the longitudinal axis is located at the junction (14) in this region. ) has a radius of curvature at each point that is at most two-thirds of the pitch (24) of the trench walls.

5. The storage unit according to one of claims 1 to 4, wherein the groove bottom has the shape of a semi-cylindrical or cylindrical sector-shaped outer frame, and the joint (14) adjoins the bottom.

6. The memory cell according to one of claims 1 to 4, wherein at the height of the junction (14), the trench wall spacing (24) is between 100 nanometers and 150 nanometers, and the trench a depth (25), as measured between the junction (14) and the deepest point of the trench in a direction perpendicular to the plane of the top surface of the semiconductor body (1) or semiconductor layer, of at least 30 nanometers and at most Half the pitch (24) of the trench walls.

7. A memory cell with a storage transistor comprising a gate electrode (4) on the top surface of the semiconductor body (1) or semiconductor layer, the gate electrode being located in the source region (2) and the drain of the trench Between the regions (3), the trench is produced from the semiconductor material of the semiconductor body or the semiconductor layer and which exhibits at least section by section the same cross-section transverse to the direction of the longitudinal axis, where the source region (2) and the drain The region (3) is formed in semiconductor material by doping from the top surface to the respective junction (14), and the gate electrode is insulated from the semiconductor material by a dielectric layer (9), which is Constructed as a storage medium, characterized in that the junction (14) adjoins a groove wall in a region in which the groove wall has a section perpendicular to the direction of the longitudinal axis and the groove wall has a curvature radius , which is at most 10% greater than the minimum value of the bend radius of the groove wall.

8. A memory cell with a storage transistor comprising a gate electrode (4) on the top surface of the semiconductor body (1) or semiconductor layer, the gate electrode being located in the source region (2) and the drain of the trench Between the regions (3), the trench is produced from the semiconductor material of the semiconductor body or the semiconductor layer and which exhibits at least section by section the same cross-section transverse to the direction of the longitudinal axis, where the source region (2) and the drain The region (3) is formed in a semiconductor material by doping, and the gate electrode is insulated from the semiconductor material by a dielectric layer (9) comprising storage layer (11), characterized in that the trench depth associated with a region in which the charge carriers of the storage layer (11) are neutralized in an erasing operation is selected such that the electric field component in a programming operation acts on The charge carrier, this component is arranged perpendicular to the longitudinal axis direction and parallel to the tangent line of the groove wall or bottom, and has a maximum value in this region.