CN100369207C - A method for preparing a replacement grid - Google Patents

Abstract

The invention belongs to a method for preparing a semiconductor device with a characteristic size of ultra-deep submicron and below, and particularly relates to an alternative gate preparation technology for ultra-deep submicron metal gate CMOS manufacturing. Using metal as the gate electrode can fundamentally eliminate the gate depletion effect and boron penetration phenomenon, and at the same time obtain a very low gate electrode sheet resistance. The invention realizes a novel metal gate CMOS technology by adopting an embedded metal gate CMOS process (that is, a replacement gate preparation process). In this embedded metal gate CMOS process, one of the main key technologies is a set of replacement gate preparation technology, which includes the selection of replacement gate materials, the formation of fine replacement gate patterns, planarization and removal of replacement gates.

Description

A method for preparing a replacement grid

technical field

The invention belongs to the ultra-deep submicron and below feature size semiconductor device technology, and relates to a preparation method of a replacement gate, in particular to a replacement gate used in the manufacture of ultra-deep submicron metal gate CMOS (complementary metal oxide semiconductor) Preparation.

technical background

When the gate length of polysilicon gate CMOS devices is reduced to sub-0.1 μm and the thickness of the gate oxide layer is reduced to less than 2.5nm, the polysilicon gate depletion effect, the increasingly serious boron penetration effect and the excessively high gate resistance have become further improvements in CMOS devices. The performance barrier has made the doped polysilicon gate, which has dominated the field of microelectronics technology for a long time, face great challenges, while the emerging refractory metal gate (metal gate) has become the most promising alternative technology at present. Using metal as the gate electrode can fundamentally eliminate the gate depletion effect and B penetration effect, and at the same time obtain a very low gate electrode sheet resistance.

Contents of the invention

The object of the present invention is to provide an alternative grid preparation method.

In order to achieve the above purpose, the present invention implements a novel metal gate CMOS technology by adopting an embedded metal gate CMOS process (that is, a replacement gate preparation process). The success of the invention is one of the keys and foundations for the sustainable development of ULSI's Si process technology in the future, and has broad application prospects.

The preparation steps of the present invention comprise:

1) After local oxidation isolation or shallow trench isolation and adjustment of gate implantation, replace gate oxidation: enter the boat at 600°C under N ₂ protection, heat up to 750-870°C, and keep N ₂ at constant temperature for 10 minutes; at the same temperature, N ₂ / O ₂ =5:1 atmosphere oxidation, oxidation time 60-120 minutes; then 750-870 ° C, N ₂ annealing 20-60 minutes; finally N ₂ protection, lower the temperature to 600 ° C, out of the boat;

2) Chemical vapor deposition of silicon nitride: temperature 760-820°C, pressure 250-300 millitorr, SiH ₂ Cl ₂ 25-35 sccm, NH ₃ 80-100 sccm, film thickness 220-260 nm;

3) Reactive ion etching to form silicon nitride to replace the gate electrode: power 130-200W, etching gas CHF ₃ 5-10sccm, SF ₆ 20-40sccm, He 100sccm, pressure 300-500 mTorr;

Then tetraethyl orthosilicate thermally decomposes TEOS SiO ₂ -1 film: temperature 720-760°C, thickness 90-150nm;

4) Reactive ion etching TEOS SiO ₂ -1 to form sidewall-1: pressure 200-250mτ, RF (radio frequency) power 250-350W, CHF ₃ /CF ₄ /Ar=40-60sccm/5-16sccm/200- 300sccm, no over etching, soft etching for 5-10 seconds;

5) Low-energy implantation in the source/drain extension region: PMOS: ⁴⁷ BF ₂ , energy 5-8Kev, dose 3-6×10 ¹⁴ cm ^-2 ; NMOS: ⁷⁵ As, energy 5-8Kev, dose 3-6×10 ¹⁴ cm ^-2 ;

6) Thermal decomposition of ethyl orthosilicate to SiO ₂ -2: temperature 710-750°C, thickness 200-260nm;

Then reactive ion etching SiO ₂ -2 to form sidewall-2: pressure 200-250mτ, RF power 250-350W, CHF ₃ /CF ₄ /Ar=40-60sccm/5-16sccm/200-300sccm;

7) Source/drain implantation and rapid thermal annealing: PMOS: ⁴⁷ BF ₂ , energy 25-35Kev, dose 1.5-3×10 ¹⁵ cm ^-2 ; NMOS: ⁷⁵ As, energy 40-55Kev, dose 2-4×10 ¹⁵ cm ^-2 ; the rapid thermal annealing temperature is 1000-1020°C, and the time is 4-8 seconds, forming a source/drain junction;

8) Formation of cobalt silicide in the source/drain region: sputtering of cobalt/titanium composite film, first sputtering titanium film 4-7nm, then sputtering cobalt film 9-15nm; sputtering power is 700-900W, working pressure of titanium sputtering is 4-6×10 ^-3 Torr, sputtered cobalt is 5-7×10 ^-3 Torr;

Then two rapid thermal annealing plus selective corrosion in between: the first rapid thermal annealing temperature 630-670 ℃, time 15-30 seconds; the second rapid thermal annealing temperature 870-910 ℃, time 6-12 seconds after selective etching point;

9) Chemical vapor deposition of low-temperature silicon oxide and borophosphosilicate glass: first chemical vapor deposition of low-temperature silicon oxide: temperature 350-450°C, film thickness 200-250nm; then chemical vapor deposition of borophosphosilicate glass: temperature 350-450 ℃, film thickness 700-800nm;

10) Borophosphosilicate glass reflow: 750-800°C, N ₂ , time 20-30 minutes;

11) The first SOG (spin-on-glass, that is, coating a layer of solvent on the substrate) coating and heat treatment: coating conditions are room temperature, thickness 360-400nm; heat treatment conditions: 350-420 ° C, N ₂ , 30-50 minutes;

12) Back engrave the SOG coated for the first time: RF power 150-250W, pressure 250-350 mTorr, CF ₄ 20-30sccm, CHF ₃ 40-60sccm, O ₂ 2sccm, Ar250-350sccm;

13) The second SOG coating and heat treatment: the conditions are the same as step 11;

14) To engrave back the SOG coated for the second time, first use the following conditions to engrave back, that is, RF power 150-250W, pressure 200-260 mTorr, CF ₄ 20-32sccm, CHF ₃ 18-30sccm, Ar 250-350sccm; When the SOG coated for the second time is etched back, use the following conditions to etch back, that is, CF ₄ 15-25sccm, Ar 200-250sccm, RF power 250-350W, pressure 180-220 mTorr, until the replacement gate is completely exposed ;

15) Etching the gate groove, wet etching net silicon nitride to replace the gate: H ₃ PO ₄ , 160-170°C, the gate groove is formed;

16) Bleed away the replacement gate silicon oxide: HF: H ₂ O = 1:20 rinse the replacement gate silicon oxide;

17) Cleaning: H ₂ SO ₄ :H ₂ O ₂ =5:1, 120°C, wash for 10 minutes, then wash with NH ₄ OH:H ₂ O ₂ :H ₂ O=0.8:1:5, 60°C After 5 minutes, soak in HF/IPA solution (HF: isopropanol (IPA): H ₂ O = 0.5%: 0.02: 1) at room temperature for 1-10 minutes, rinse with water, dry and place in the furnace;

18) Gate oxidation: enter the boat at 600°C under the protection of N ₂ , raise the temperature to 750-850°C, and keep the N ₂ constant temperature for 10 minutes; at the same temperature, oxidize in an atmosphere of N ₂ /O ₂ =5:1, and the oxidation time is 10-50 minutes; N ₂ atmosphere, annealing at 750-850°C for 15-60 minutes; under N ₂ protection, lower the temperature to 600°C, and slowly pull out the boat under N ₂ protection;

19) Sputtering refractory metal, W/TiN=100-150nm/30-45nm, and reactive ion etching to form a metal gate electrode.

Wherein the oxide film thickness of the partial oxidation isolation in step 1 is 350-420nm, and the oxide film thickness of the replacement gate oxidation is 5-7nm.

Wherein the water washing in step 17 is deionized water washing.

The thickness of the gate oxide film in step 18 is 15-35 angstroms.

The order of sputtering the refractory metal in step 19 is to sputter the TiN film first, and then sputter the W film.

Wherein the thickness after heat treatment in step 11 is 300-360nm.

The etching rate of the borophosphosilicate glass in step 12 is twice that of the SOG coated for the first time.

Among them, in step 14, the SOG coated for the second time is engraved back, and the SOG coated with borophosphosilicate glass is etched back at the same etching rate as the SOG coated for the second time. In the second step, borophosphosilicate glass and low-temperature silicon oxide Etch back under the same etch rate conditions.

The features of the present invention are:

1. The source/drain (S/D) is formed first, and the gate is formed later. It avoids the damage to the gate dielectric caused by reactive ion etching (RIE) and source/drain implantation of the metal gate, and avoids the damage to the metal gate caused by high temperature thermal annealing;

2. Developed a planarization technology compatible with conventional CMOS processes, using BPSG thermal reflow plus BPSG/SOG-1 rate difference etch back plus SOG-2/low temperature SiO2 constant speed etch back until the dummy gate is exposed, achieving good planarization change;

3. Removal of replacement gate electrodes and formation of grooves;

4. The etching technology of tungsten/titanium nitride (W/TiN) composite metal gate adopts two-step RIE etching, optimizes the process parameters, and achieves satisfactory results.

Description of drawings

FIG. 1 is a schematic diagram of the structure of the replacement gate of the present invention. Among them: Figure 1a is a cross-sectional view of the structure after silicide formation, symbols 1-replacement gate Si ₃ N ₄ , 2-sidewall, 6-field silicon oxide, 15-CoSi ₂ ; Figure 1b shows that the dummy gate is removed after planarization Schematic diagram, symbol 1-replacement gate Si ₃ N ₄ ; 4-replacement gate silicon oxide, 16-gate groove; Figure 1c shows reactive ion etching W/TiN stacked metal gate to form a T-shaped gate electrode, symbol 11-W, 12-TiN, 13-gate silicon oxide.

Fig. 2 is a schematic flow chart of the preparation method of the replacement gate of the present invention. Among them: symbol 1-replacement gate Si ₃ N ₄ ; 2-sidewall-1; 3-sidewall-2; 4-replacement gate silicon oxide; 5-source/drain extension region; 6-field silicon oxide; 7-SOG -1; 8-BPSG; 9-LTO SiO ₂ ; 10-SOG-2; 11-Wi; 12-TiN; 13-gate silicon oxide; 14-PE SiO ₂ .

Detailed ways

In the embedded metal gate CMOS process of the present invention, one of the main keys is a set of replacement gate preparation technology, which includes the selection of replacement gate material, the formation of fine replacement gate patterns, planarization and removal of dummy gates. In this process, the present invention point is:

1. Silicon nitride is selected as the replacement gate material to replace the usual polysilicon gate material, so that the replacement gate can be removed by wet etching after planarization. Because wet etching of silicon nitride has a relatively high etching selectivity ratio for silicon oxide, it will not cause chemical, especially plasma, damage to the underlying silicon, and reactive ion etching of silicon nitride can obtain a finer profile. Grid graphics.

2. In the research of refractory metal gates, chemical mechanical polishing (CMP) technology is widely used in the world to complete the planarization. We took a unique approach and independently developed a planarization technology that is more compatible with traditional CMOS technology for the first time, using BPSG (borophosphosilicate glass) thermal reflow plus BPSG/SOG (spin-on-coated glass)-1 rate difference etch-back plus SOG- 2/ Low-temperature SiO ₂ etch back at a constant speed until the dummy gate is exposed, achieving good planarization. It saves the expensive cost of configuring CMP large-scale equipment. At the same time cleaner, better compatibility.

Example

Refer to FIG. 1 for the replacement gate structure of the present invention.

Refer to FIG. 2 for the preparation process of the replacement gate of the present invention.

The steps of the present invention to prepare the replacement grid are:

1) LOCOS (local oxidation) isolation or STI (shallow trench) isolation, the field oxidation thickness is 380nm, see "6" in Figure 2(1) and "6" in Figure 1(a);

2) Adjust grid injection;

3) Replace the gate oxidation, see "4" in Figure 2(1): enter the boat at 600°C under the protection of large flow N ₂ , then raise the temperature to 830°C, keep the N ₂ constant temperature for 10 minutes; at the same temperature, N ₂ /O ₂ = Oxidation in 5:1 atmosphere, oxidation time 85 minutes; N ₂ atmosphere, annealing at 830°C, 30 minutes; N ₂ protection, cooling down to 600°C, and then slowly pull out the boat under the protection of large flow N ₂ ;

4) Chemical vapor deposition (LPCVD) silicon nitride: temperature 790°C, pressure 275 mTorr, SiH ₂ Cl ₂ 29 sccm, NH ₃ 90 sccm, film thickness 240 nm;

5) Reactive ion etching forms silicon nitride to replace the gate electrode, see "1" in Figure 2 (1) and Figure 1

(a) "1": power 150W, etching gas CHF ₃ 7sccm, SF ₆ 30sccm, He 100sccm mixed, gas pressure 400 millitorr; then thermally decompose SiO ₂ -1 (TEOS-1) film with tetraethyl orthosilicate: temperature 740 ℃, thickness 120nm;

6) Reactive ion etching of TEOS0-1 to form sidewall-1, see "2" in Figure 2(1) and "2" in Figure 1(a): pressure 200 mTorr, RF power 300W, CHF ₃ /CF ₄ /Ar＝50sccm/10sccm/250sccm, no over-etching, soft etching for 7 seconds;

7) Low-energy implantation in the source/drain extension region, see "5" in Figure 2(1): PMOS: ⁴⁷ BF ₂ , energy 7Kcv, dose 4×10 ¹⁴ cm ^-2 ; NMOS: ⁷⁵ As, energy 5Kev, dose 5× 10 ¹⁴ cm ^-2 ;

8) Thermal decomposition of tetraethyl orthosilicate SiO ₂ -2 (TEOS-2): temperature 740°C, thickness 220nm; then reactive ion etching TEOS-2: pressure 200 mTorr, RF power 300W, CHF ₃ /CF ₄ / Ar=50sccm/10scc/250sccm, no over-etching, soft etching for 7 seconds; form sidewall-2, see "3" in Figure 2(1) and "3" in Figure 1(a);

9) Source/drain implantation and rapid thermal annealing (RTA): PMOS: ⁴⁷ BF ₂ , energy 25Kev, dose 3×10 ¹⁵ cm ^-2 ; NMOS: ⁷⁵ As, energy 50Kev, dose 4×10 ¹⁵ cm ^-2 ; RTA The temperature is 1010°C, the time is 5 seconds, and the source/drain junction is formed;

10) Cobalt silicide formation in the source/drain region, see "15" shown in Figure 1(a): sputtering of cobalt/titanium composite film, first sputter titanium film 5nm, then sputter cobalt film 11nm; sputtering power is 800W , the working pressure of titanium sputtering is 5×10 ^-3 Torr, cobalt sputtering is 6.2×10 ^-3 Torr; two rapid thermal annealing plus selective corrosion in between: the first rapid thermal annealing: temperature 650°C, time 20 seconds ;The second rapid thermal annealing after selective etching: temperature 900°C, time 7 minutes; the device profile after completing the silicide process is shown in Figure 2(1);

11) Chemical vapor deposition of low-temperature silicon oxide (LTO) and borophosphosilicate glass (BPSG) see "9" and "8" in Figure 2 (2): Chemical vapor deposition of LTO: temperature 400°C, film thickness 200-250nm ; Then chemical vapor deposition of borophosphosilicate glass at a temperature of 400°C and a film thickness of 700-800nm;

12) Borophosphosilicate glass reflow: 750°C, N ₂ , time 20 minutes;

13) The first SOG coating and heat treatment, see "7" in Figure 2(2): room temperature, thickness 360-400nm, at this time, due to the fluidity of SOG, the SOG filled at the bottom of the pattern is more than that covered at the top of the step SOG is much thicker, which reduces the step height; heat treatment: 400°C, N ₂ , 40 minutes; after heat treatment, the thickness drops to 300-360nm;

14) Etching back the SOG coated for the first time: RF power 200W, pressure 300 mTorr, CF ₄ 25sccm, CHF ₃ 50sccm, O ₂ 2sccm, Ar 300sccm, the above etching back conditions are small, borophosphosilicate glass etching rate It is twice that of the SOG coated for the first time, so it can effectively reduce the steps of the pattern. At this time, the SOG at the bottom of the valley is etched away, leaving some borophosphosilicate glass and low-temperature silicon oxide, see "8" in Figure 2 (3) " and "9";

15) The second SOG coating and heat treatment, see "10" in Figure 2 (4): the conditions are the same as step 13. further reduced step height;

16) To etch SOG-2 back, first use borophosphosilicate glass to etch back under the same conditions as the second SOG etching rate, that is, RF power 200W, pressure 230 mTorr, CF ₄ 26sccm, CHF ₃ 24sccm, Ar 300sccm; when After the second SOG etch back, use borophosphosilicate glass to etch back under the same conditions as the low temperature silicon oxide etching rate, that is, RF power 300W, pressure 200 mTorr, CF ₄ 19sccm, Ar 250sccm; until the replacement gate is completely exposed , see Figure 2(5);

17) Etch the gate groove, see Figure 2(6), first wet etch clean silicon nitride to replace the gate, see Figure 1(b) "1": H ₃ PO ₄ , 160°C, form the gate groove;

18) Then bleach the replacement gate silicon oxide, see Figure 2(6) and Figure 1(b) "4": HF:H ₂ O = 1:20 rinse the replacement gate silicon oxide, as shown in Figure 2(6) ;

19) Cleaning: 3# (H ₂ SO ₄ : H ₂ O ₂ = 5: 1) - 1 # (NH ₄ OH: H ₂ O ₂ : H ₂ O = 0.8: 1: 5) - then use hydrofluoroester /isopropanol/water=0.5%/0.02%/1 solution soaked at room temperature for 5 minutes, rinsed with deionized water, dried and put into the furnace immediately;

20) Gate oxidation, see "13" in Figure 2(7) and "13" in Figure 1(c): enter the boat at 600°C under the protection of large flow _N2 , push slowly, and protect it with large flow _N2 ; heat up to 830°C, _{N 2} constant temperature for 10 minutes; at the same temperature, N ₂ /O ₂ =5:1 atmosphere oxidation, oxidation time 20 minutes; N ₂ atmosphere, annealing at 830°C, 30 minutes; Slowly pull out the boat under the protection of flow _N2 ; the thickness of the gate oxide film is 25 angstroms;

21) Sputter refractory metal W/TiN, see "11"/"12" in Figure 2 (7): (W/TiN=100nm/35nm), and form a metal gate electrode by reactive ion etching, see Figure 2 ( "11"/"12" in 8) and "11" and "12" in Figure 1(c). Then it is covered with plasma-enhanced chemical vapor deposition silicon oxide (PE SiO ₂ ), see "14" in Fig. 2 (8).

Claims (8)

1. the preparation method of an alternative gate may further comprise the steps:

1) after carrying out local oxide isolation or shallow-trench isolation and tuned grid injection, carries out alternative gate oxidation: N ₂Protect following 600 ℃ to advance boat, be warming up to 750-870 ℃, N ₂Constant temperature 10 minutes; Under the same temperature, N ₂/ O ₂=5: 1 ambient oxidation, oxidization time 60-120 minute; Then 750-870 ℃, N ₂Annealed 20-60 minute; Last N ₂Be cooled to 600 ℃ under the protection, go out boat;

2) cvd silicon nitride: temperature 760-820 ℃, pressure 250-300 milli torr, SiH ₂Cl ₂25-35sccm, NH ₃80-100sccm, film thickness 220-260nm;

3) reactive ion etching forms silicon nitride alternative gate electrode: power 130-200W, etchant gas CHF ₃5-10sccm, SF ₆20-40sccm, He 100sccm mixes, pressure 300-500 milli torr;

Tetraethoxysilane thermal decomposition TEOS SiO then ₂-1 film: temperature 720-760 ℃, thickness 90-150nm;

4) reactive ion etching TEOS SiO ₂-1, form side wall-1: pressure 200-250m τ, radio-frequency power 250-350W, CHF ₃/ CF ₄/ Ar=40-60sccm/5-16sccm/200-300sccm, no over etching, soft etching 5-10 second;

5) source/drain extension region low energy is injected: PMOS: ⁴⁷BF ₂, energy 5-8Kev, dosage 3-6 * 10 ¹⁴Cm ^-2NMOS: ⁷⁵As, energy 5-8Kev, dosage 3-6 * 10 ¹⁴Cm ^-2

6) tetraethoxysilane thermal decomposition SiO ₂-2: temperature 710-750 ℃, thickness 200-260nm;

Reactive ion etching SiO then ₂-2, form side wall-2: pressure 200-250m τ, RF power 250-350W, CHF ₃/ CF ₄/ Ar=40-60sccm/5-16sccm/200-300sccm;

7) source/leakage is injected and rapid thermal annealing: PMOS: ⁴⁷BF ₂, energy 25-35Kev, dosage 1.5-3 * 10 ¹⁵Cm ^-2NMOS: ⁷⁵As, energy 40-55Kev, dosage 2-4 * 10 ¹⁵Cm ^-21000-1020 ℃ of rapid thermal annealing temperature, time 4-8 second, formation source/drain junction;

8) source/drain region cobalt silicide forms: the sputter of cobalt/titanium compound film, spatter titanium film 4-7nm earlier, and spatter cobalt film 9-15nm again; Sputtering power is 700-900W all, and spattering the titanium operating pressure is 4-6 * 10 ^-3Torr, spattering cobalt is 5-7 * 10 ^-3Torr;

Twice rapid thermal annealing adds and carry out selective etching therebetween then: for the first time the rapid thermal annealing temperature is 630-670 ℃, time 15-30 second; 870-910 ℃ of rapid thermal annealing temperature for the second time after the selective etching, time 6-12 second;

9) chemical vapor deposition cryogenic oxidation silicon and boron-phosphorosilicate glass: first chemical vapor deposition cryogenic oxidation silicon: temperature 350-450 ℃, film thickness 200-250nm; Chemical vapor deposition boron-phosphorosilicate glass: temperature 350-450 ℃ then, film thickness 700-800nm;

10) boron-phosphorosilicate glass refluxes: 750-800 ℃, and N ₂, time 20-30 minute;

11) SOG coating for the first time and heat treatment: the coating condition is a room temperature, thickness 360-400nm; Heat-treat condition: 350-420 ℃, N ₂, 30-50 minute;

12) return the SOG:RF power 150-250W that carves the coating first time, pressure 250-350 milli torr, CF ₄20-30sccm, CHF ₃40-60sccm, O ₂2sccm, Ar 250-350sccm;

13) SOG coating for the second time and heat treatment: condition is with 11 steps;

14) return and carve the SOG of coating for the second time, return quarter with following condition earlier, i.e. RF power 150-250W, pressure 200-260 is torr in the least, CF ₄20-32sccm, CHF ₃18-30sccm when the SOG that Ar 250-350sccm applied when the second time returns and carved, returns quarter with following condition, i.e. CF again ₄15-25sccm, Ar 200-250sccm, RF power 250-350W, pressure 180-220 milli torr all exposes until alternative gate;

15) corrosion grid groove, the clean silicon nitride alternative gate of wet etching: H ₃PO ₄, 160-170 ℃, the grid groove forms;

16) float alternative gate silica: HF: H ₂O=1: 20 rinse the alternative gate silica;

17) clean: H ₂SO ₄: H ₂O ₂=5: 1,120 ℃, cleaned 10 fens, use NH then ₄OH: H ₂O ₂: H ₂O=0.8: 1: 5 solution, 60 ℃, cleaned 5 fens, use HF again: isopropyl alcohol: H ₂O=0.5%: 0.02%: 1, to soak 1-10 minute under the room temperature, the water flushing dries stove;

18) gate oxidation: N ₂Protect following 600 ℃ to advance boat, be warming up to 750-850 ℃, N ₂Constant temperature 10 minutes; Under the same temperature, N ₂/ O ₂=5: 1 ambient oxidation, oxidization time 10-50 minute; N ₂Atmosphere, 750-850 ℃ of annealing, 15-60 minute; N ₂Be cooled to 600 ℃, N under the protection ₂Boat is pulled out in protection down slowly;

19) sputtering refractory metals, W/TiN=100-150nm/30-45nm, and reactive ion etching forms metal gate electrode.

2. according to claim 1, it is characterized in that the oxide thickness of the carrying out local oxide isolation in the step 1 is 350-420nm, the oxide thickness of alternative gate oxidation is 5-7nm.

3. according to the preparation method of claim 1, it is characterized in that the water flushing in the step 17 is a washed with de-ionized water.

4. according to the preparation method of claim 1, it is characterized in that step 18 gate oxide film thickness is the 15-35 dust.

5. according to the preparation method of claim 1, it is characterized in that the order of sputtering refractory metals is first sputtered with Ti N film in the step 19, back sputter W film.

6. according to the preparation method of claim 1, it is characterized in that the thickness in the step 11 after Overheating Treatment is 300-360nm.

7. according to the preparation method of claim 1, it is characterized in that in the step 12, the etch rate of boron-phosphorosilicate glass is 2 times of SOG of coating for the first time.

8. according to the preparation method of claim 1, it is characterized in that, in the step 14, return and carve the SOG of coating for the second time, return quarter with the boron-phosphorosilicate glass condition identical with the SOG etch rate of coating for the second time earlier, second step was returned quarter with the boron-phosphorosilicate glass condition identical with the low-temperature oxidation silicon etch rate again.

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