CN1099705C - Manufacturing method of flash memory unit - Google Patents

Abstract

A method for manufacturing a flash memory cell comprises the following steps: providing a semiconductor substrate having at least one multi-layer gate structure, the gate structure comprising a first conductive layer, a dielectric layer, a second conductive layer and a silicon nitride layer; forming a first spacer around the gate structure; forming a polysilicon layer on the gate structure and the substrate; forming a second spacer around the side of the polysilicon layer; performing ion implantation using the second spacer as a mask to form a drain region in the substrate; removing the second spacer; defining a mask and performing ion implantation to form a source region in the substrate; and forming a third conductive layer on the substrate and the gate structure.

Description

Manufacturing method of flash memory unit

The invention relates to a method for manufacturing a flash memory cell (FLash Memory Cell), in particular to a method for manufacturing a flash memory cell with a split gate (Split-Gate).

Read Only Memory (ROM) is a kind of permanent memory (Non-volatile Memory), and the stored information or data will not disappear due to power supply interruption. Erasable Programmable Read-Only Memory (Erasable Programmable ROM, ERPOM) is to extend the application of read-only memory to the deletion and rewriting of data, but the deletion action requires the use of ultraviolet rays, so the packaging cost of EPROM is relatively high. high. In addition, when the EPROM performs data deletion, all the programs or data stored in the EPROM will be completely cleared, which requires reprogramming every time the data is modified, which is quite time-consuming.

Another kind of electrically erasable and programmable read-only memory (Electrically Erasable Programmable ROM, EEPROM) that allows partial modification of data does not have this shortcoming. "(Bit By Bit), the data can be stored, read and cleared multiple times. The flash memory (Flash Memory) has the same structure as the EEPROM, except that when the storage is cleared, it is carried out in a "block by block" (Block By Bolck) manner, and the speed is very fast, about 1 to 2 seconds The work of storage and removal can be completed to save time and manufacturing costs.

Generally, the gate of a flash memory unit includes a two-layer structure, one of which is a floating gate (Floating Gate) made of polysilicon for storing charges, and a control gate (Control Gate) for controlling data access. The floating gate is located below the control gate, which is usually in a "floating" state and is not connected to any lines, while the control gate is usually connected to the word line. There are many documents about flash memory, such as Naruke et al. The paper "A new flash-erase EEPROM cell with a sidewall select-gate on its source side" published in Technical Digest of IEEE Electron Device Meeting in 1988 describes the It is an improved flash memory.

Please refer to FIG. 1A and FIG. 1B , which illustrate a cross-sectional and top view of a flash memory cell structure according to the above paper. Wherein, a floating gate 11 and a control gate 12 are arranged on the semiconductor substrate 10, and a select gate (Select Gate) 13 is arranged on the side, which jointly constitute a split gate 14 (SplitGate) structure with a split structure. In the semiconductor substrate 10 on both sides of the stacked gate 14, there are source regions 15 and drain regions 16 doped with ions respectively, and the selection gate 13 is located on one side of the source region 15 and is formed by an etch-back method (Etch Back). , so it is parallel to the control gate 12 . The feature of this flash memory cell is to use the select gate to prevent the over-erasing phenomenon caused by improper bleed current, so as to maintain the normal operation of the memory. However, because the positions of the selection gate and the control gate are parallel, there will be problems in the design of the components; and because the length of the selection gate must be fixed, the characteristics of the memory cannot be effectively adjusted, and there will be serious interference during data programming (Program). phenomenon occurs.

In order to solve the above problems, in the paper "A novel high density contactless flash memory array using split-gatesource-side injection cell for 5V-only application" published by Y.Ma at the symposium on VLSI technology in 1994, another An improved flash memory.

Please refer to FIG. 2 , which shows a schematic cross-sectional structure of an improved flash memory in the above paper. There are floating gate 21, control gate 22 and selection gate 23 on a semiconductor substrate 20, which are stacked together to form a separated gate 24 with a separated structure. In the semiconductor substrate 20 on both sides of the separated gate 24, ion-doped impurity source region 25 and drain region 26, wherein the select gate 23 covers the top and sides of the control gate 22. Although this structure can improve the interference phenomenon during data programming, the requirement for precise photolithography steps becomes higher when forming the select gate, so a large amount of space will be consumed.

In addition, the way EEPROM stores data is to use the tunneling effect of electrons to store charges in the floating gate. When performing programming operations, a voltage is applied to the control gate and source/drain regions, through the floating gate The underlying gate oxide produces tunneling. The provided gate oxide layer can change the voltage required for programming, and if the gate oxide layer is too thin, it will reduce the stability of the memory due to excessive leakage.

Therefore, the main purpose of the present invention is to provide a method for manufacturing a flash memory unit with a split gate, which performs ion implantation in a self-aligned (Self Aligned) manner to form a split gate structure and saves a photolithography step , to simplify the fabrication process.

Another main object of the present invention is to provide a method of manufacturing a flash memory cell with a split gate. The source region and the drain region are implanted in different steps, so that the parameters of the implanted ions can be based on different properties. and required characteristic changes.

Another main object of the present invention is to provide a method for manufacturing a flash memory cell with a split gate, which can form a gate oxide with a fixed size and high quality, and can accurately control the length of the channel (Channel) to maintain memory stability.

According to the above and other objects of the present invention, a method for manufacturing a flash memory cell with a split gate is proposed. The method is briefly described as follows: a semiconductor substrate is provided on which a floating gate and a control gate structure have been formed, and The sidewalls of the floating gate and the control gate structure form a first spacer, and a layer of first polysilicon layer is covered above the semiconductor base and the structure. Next, cover an oxide layer on the polysilicon layer, etch back to form a second spacer, use the second spacer to provide a function similar to a mask, perform ion implantation of the drain region on the semiconductor substrate through the polysilicon layer, and then remove second spacer. Next, a photoresist layer is formed above the polysilicon layer to form a mask to expose part of the polysilicon layer, and ion implantation is performed on the semiconductor substrate in this region through the polysilicon layer to form a source region; then the photoresist is removed The etchant layer is covered with a conductive layer, and the conductive layer and the polysilicon layer are combined to form a selection gate, so as to complete the structure of the flash memory unit with separated gates.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with accompanying drawings. In the attached picture:

1A and FIG. 1B illustrate a cross-section and a top view of a conventional flash memory cell structure;

FIG. 2 is a schematic cross-sectional view of another existing flash memory cell structure; and

3A to 3H are schematic cross-sectional views illustrating a manufacturing process of a flash memory cell structure according to a preferred embodiment of the present invention.

Please refer to FIG. 3A to FIG. 3H at the same time, which illustrate a schematic cross-sectional view of a manufacturing process of a flash memory cell structure according to a preferred embodiment of the present invention.

Referring to FIG. 3A, a first conductive layer 31, a dielectric layer 32, a second conductive layer 33, and a silicon nitride layer 34 are sequentially formed on a semiconductor substrate 30, and patterned to form a structure as shown in FIG. 3A; wherein , the first conductive layer 31 is used as a floating gate, the second conductive layer 33 is a control gate, and the dielectric layer 32 is a silicon oxide/silicon nitride/silicon oxide (ONO) structure, and a semiconductor substrate 30 has been formed in advance thin gate oxide layer.

Next, referring to FIG. 3B , a first oxide layer is formed on the semiconductor substrate 30 and the silicon nitride layer 34, etch-back is performed to form a first spacer 35 on the sidewall of the above-mentioned structure; a polysilicon layer 36 is formed thereon, As shown in FIG. 3C, the thickness of the polysilicon layer 36 is about 200-500 angstroms.

Afterwards, referring to FIG. 3D , a second oxide layer is formed on the polysilicon layer 36 with a thickness of about 2000-4000 angstroms. The formation method is, for example, plasma-enhanced chemical vapor deposition, or tetraethyl orthosilicate (Tetra-Ethyl- Ortho-Silicate, TEOS) reaction generation; remove part of the second oxide layer, expose the polysilicon layer 36, and form the second spacer 37 on the side of the first polysilicon layer 36; wherein, remove part of the second oxide layer The method is, for example, an etch-back method, preferably an anisotropic etch-back method. Since the second oxide layer is thicker on the side of the polysilicon layer 36 , the second oxide layer on the side of the polysilicon layer 36 will not be completely removed during etching.

Next, referring to FIG. 3E , ion implantation is performed using the second spacer 37 as a mask (Mask), and ions are implanted into the semiconductor substrate 30 through the polysilicon layer 36 to form the drain region 38 . Afterwards, the second spacer 37 is removed by wet etching, for example, to form a structure as shown in FIG. 3F .

Next, referring to FIG. 3G , a layer of photoresist layer 39 is covered on the polysilicon layer 36 , patterned to remove part of the photoresist layer 39 , exposing the region where the source electrode is to be formed, and performing ionization on the region. Implantation: implant ions into the semiconductor substrate 30 through the polysilicon layer 36 to form a common source 40 (Common Source), and then remove the photoresist layer 39.

Afterwards, referring to FIG. 3H , a third conductive layer 41 is formed on the polysilicon layer 36 and patterned to complete a flash memory cell structure with split gates; wherein, the third conductive layer 41 may be composed of a layer of second The polysilicon layer is combined with a layer of tungsten silicide metal, which is combined with the polysilicon layer 36 to form a split gate.

In this embodiment, when the ion implantation forms the drain region, the second spacer is used as a mask to perform self-aligned ion implantation, which saves a step of using a photoresist mask for doping, so that the manufacturing process can be improved. Simplification; and the ion doping of the source region and the drain region is carried out separately, the amount of doping can be controlled separately, and the parameters of the flash memory can be adjusted conveniently. In addition, the second spacer can be used to control the length of the tunneling channel, and the polysilicon layer under the second spacer is used as a protective layer for separating the gate channel, so as to maintain the function and stability of the memory; the polysilicon layer also has conductive properties, Combined with the conductive layer as a select gate.

Therefore, the feature of the present invention is to provide a method for manufacturing a flash memory cell with a split gate, using the second spacer as a mask to perform ion implantation in the drain region of the semiconductor substrate without using a photoresist The step of ion implantation using etchant or other masks.

Another feature of the present invention is to provide a method for manufacturing a flash memory unit with a split gate, using the second spacer as a mask to perform ion implantation in the drain region of the semiconductor substrate, which can control the channel of the split gate length to maintain the performance of the component.

Another feature of the present invention is to provide a method for manufacturing a flash memory cell with a split gate, using the polysilicon layer as a protective layer so that the steps of forming the second spacer and ion implantation will not affect the channel, thereby maintaining component performance.

Another feature of the present invention is to provide a method of manufacturing a flash memory cell with a split gate, the steps of ion implantation into the source region and the drain region are performed separately, so that the parameters of the source region and the drain region can be adjusted separately , so as to obtain memory cell elements of different properties.

Although the present invention has been disclosed in conjunction with a preferred embodiment, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be defined by the appended claims.

Claims (12)

1. manufacture method with flash memory cell of separated grid may further comprise the steps:

The semiconductor substrate is provided, has been provided with at least one stacked gate structure on this semiconductor-based end, wherein this stacked gate structure comprises one first conductive layer, a dielectric layer, one second conductive layer and a silicon nitride layer;

Form one first clearance wall at this stacked gate structure periphery;

On this stacked gate structure and this semiconductor-based end, form one first polysilicon layer;

Around the side of this polysilicon layer, form one second clearance wall;

, carry out ion and inject as a mask with this second clearance wall, in this semiconductor-based end, form a drain region;

Remove this second clearance wall;

Limit mask, carry out ion and inject, in this semiconductor-based end, form the one source pole district; And

On this semiconductor-based end and this stacked gate structure, form one the 3rd conductive layer.

2. the method for claim 1, wherein the generation type of this stacked gate structure may further comprise the steps:

On this semiconductor-based end, form a grid oxic horizon;

On this grid oxic horizon, form this first conductive layer, as a floating grid;

On this first conductive layer, form this dielectric layer;

On this dielectric layer, form this second conductive layer, as a control gate;

On this second conductive layer, form this silicon nitride layer; And

Limit mask, remove this silicon nitride layer of part, this second conductive layer, this dielectric layer, this first conductive layer and this grid oxic horizon, expose this semiconductor-based end of part, form this stacked gate structure.

3. method as claimed in claim 2, wherein, this dielectric layer is one oxide layer/silicon nitride layer/oxide layer structure.

4. the method for claim 1, wherein the generation type of this first clearance wall is as follows:

On this stacked gate structure and this semiconductor-based end, form an oxide layer; And

Carry out etching step, this oxide layer of etching forms this first clearance wall.

5. the method for claim 1, wherein this first polysilicon layer thickness is about 200～500 dusts.

6. the method for claim 1, wherein the generation type of this second clearance wall is as follows:

On this first polysilicon layer, form an oxide layer; And

Carry out etching step, this oxide layer of etching forms this second clearance wall.

7. method as claimed in claim 6, wherein, this etching step is that anisotropy is eat-back method.

8. method as claimed in claim 6, wherein, this oxidated layer thickness scope is about 2000～4000 dusts.

9. method as claimed in claim 6, wherein, this oxide layer forms with the tetraethyl orthosilicate reactant salt.

10. method as claimed in claim 6, wherein, this oxide layer forms with Plasma Enhanced Chemical Vapor Deposition (PECVD).

11. the method for claim 1, wherein this source area formation step also further comprises the following steps:

On this polysilicon layer, form a photoresist layer;

Limit mask, expose the zone that a desire forms source electrode;

Carry out ion and inject, form this source area; And

Remove this photoresist layer.

12. the method for claim 1, wherein forming the step of the 3rd conductor layer comprises:

On this first polysilicon layer, form one second polysilicon layer; And

On this second polysilicon layer, form a tungsten silicide layer.

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