CN109979877A - Tft array substrate and preparation method thereof - Google Patents

Abstract

The present invention provides a TFT array substrate and a manufacturing method thereof. In the method for manufacturing a TFT array substrate of the present invention, a bottom layer semiconductor material film, a doped semiconductor material film and a first metal material film are sequentially formed on the gate insulating layer, and a mask is used for the bottom layer semiconductor material film and the doped semiconductor material film. and the first metal material film is patterned to form a bottom semiconductor layer, a doped semiconductor layer and a metal layer that are sequentially arranged above the gate from bottom to top, and then a second metal material film is formed on the gate insulating layer and the metal layer, The second metal material film, the metal layer and the doped semiconductor layer are patterned to form a source contact block, a drain contact block, a source electrode and a drain electrode, which can reduce the contact interface and drain electrode between the source electrode and the source contact block. The contact resistance of the contact interface with the drain contact block improves product performance.

Description

TFT array substrate and manufacturing method thereof

technical field

The present invention relates to the field of display technology, and in particular, to a TFT array substrate and a manufacturing method thereof.

Background technique

In the field of display technology, flat panel display devices such as Liquid Crystal Display (LCD) and Organic Light Emitting Display (OLED) have gradually replaced Cathode Ray Tube (CRT) display devices. Liquid crystal display devices have many advantages, such as thin body, power saving, and no radiation, and have been widely used.

Most of the liquid crystal display devices on the current market are backlight type liquid crystal display devices, which include a liquid crystal display panel and a backlight module. Usually, a liquid crystal display panel consists of a color filter (CF) substrate, a thin film transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and a sealant. Box (Sealant) composition. The working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates, and there are many vertical and horizontal thin wires between the two glass substrates. refracted to produce a picture.

The TFT array substrates of the existing flat panel display devices including LCD and OLED display devices are mostly manufactured using a 5-mask technology. The process of fabricating the TFT array substrate using the 5mask technology is as follows: please refer to FIG. 1 , provide a substrate 100 , fabricate the gate electrode 200 on the substrate 100 , refer to FIG. 2 , fabricate a gate insulating layer on the gate electrode 200 and the substrate 100 300 , an island-shaped underlying amorphous silicon (a-Si) layer 410 and an island-shaped doped amorphous silicon layer 420 are formed on the gate insulating layer 300 and are sequentially arranged above the gate 200 from bottom to top. A metal material layer is formed on the hetero-amorphous silicon layer 420 and the gate insulating layer 300, and the metal material layer and the doped amorphous silicon layer 420 are patterned, so as to form two layers of the underlying amorphous silicon layer 410 as shown in FIG. 3 . The source contact block 421 and the drain contact block 422 on the ends and the drain contact block 422 and the source electrode 510 and the drain electrode 520 respectively connected to the source contact block 421 and the drain contact block 422 are formed when the 5mask technology is used to fabricate the TFT array substrate. The doped amorphous silicon layer 420 of the electrode contact block 421 and the drain contact block 422 and the metal material layer forming the source electrode 510 and the drain electrode 520 are patterned using two different masks, resulting in the source contact block 421 and the source electrode The contact resistance between the electrodes 510 and the contact resistance between the drain contact block 422 and the drain 520 are relatively large, resulting in a low on-state current of the TFT devices in the prepared TFT array substrate.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a manufacturing method of a TFT array substrate, which can reduce the contact resistance of the contact interface between the source electrode and the source electrode contact block and the contact interface between the drain electrode and the drain contact block, and improve product performance.

Another object of the present invention is to provide a TFT array substrate, which can reduce the contact resistance of the contact interface between the source electrode and the source electrode contact block and the contact interface between the drain electrode and the drain contact block, and improve product performance.

To achieve the above purpose, the present invention first provides a method for manufacturing a TFT array substrate, comprising the following steps:

Step S1, providing a substrate, and sequentially fabricating a gate electrode, a gate insulating layer, an underlying semiconductor material film, a doped semiconductor material film and a first metal material film on the substrate;

Step S2, using a mask to pattern the underlying semiconductor material film, the doped semiconductor material film and the first metal material film to form an island-shaped underlying semiconductor layer, an island-shaped doped semiconductor layer and an island-shaped doped semiconductor layer that are sequentially arranged above the gate from bottom to top. The hetero semiconductor layer and the island-shaped metal layer;

Step S3, forming a second metal material film on the gate insulating layer and the metal layer;

Step S4, patterning the second metal material film, the metal layer and the doped semiconductor layer to form a source contact block and a drain contact block located above and spaced apart from both ends of the underlying semiconductor layer, as well as the source contact block and the drain contact block respectively. a source electrode and a drain electrode in contact with the electrode contact block; the source electrode includes a first sub-source electrode located on the source contact block and a second sub-source electrode in contact with the first sub-source electrode, and the drain electrode includes a first sub-source electrode located on the drain electrode A first sub-drain on the pole contact block and a second sub-drain in contact with the first sub-drain.

The material of the underlying semiconductor material film is amorphous silicon, and the material of the doped semiconductor material film is ion-doped amorphous silicon.

The material of the doped semiconductor material film is amorphous silicon doped with N-type ions.

The thickness of the first sub-source is the same as that of the first sub-drain, the thickness of the second sub-source is the same as that of the second sub-drain, and the thickness of the first sub-source is smaller than that of the second sub-source.

The manufacturing method of the TFT array substrate further includes step S5, forming a passivation layer on the gate insulating layer, the source electrode and the drain electrode; patterning the passivation layer to form a passivation layer located above one of the source electrode and the drain electrode. via;

In step S6, a pixel electrode is formed on the passivation layer, and the pixel electrode is in contact with one of the source and drain through the hole.

The present invention also provides a TFT array substrate, comprising a substrate, a gate disposed on the substrate, a gate insulating layer disposed on the substrate and the gate, and an island disposed on the gate insulating layer and above the gate a bottom semiconductor layer, a source contact block and a drain contact block disposed above and spaced apart from both ends of the bottom semiconductor layer, and a source electrode and a drain electrode respectively in contact with the source contact block and the drain contact block; the source electrode including a first sub-source on the source contact block and a second sub-source in contact with the first sub-source, the drain including a first sub-drain on the drain contact block and a second sub-source in contact with the first sub-source The second sub-drain of the drain contact.

The material of the underlying semiconductor layer is amorphous silicon, and the material of the source contact block and the drain contact block is ion-doped amorphous silicon.

The source contact block and the drain contact block are made of amorphous silicon doped with N-type ions.

The thickness of the first sub-source is the same as that of the first sub-drain, the thickness of the second sub-source is the same as that of the second sub-drain, and the thickness of the first sub-source is smaller than that of the second sub-source.

The TFT array substrate also includes a passivation layer disposed on the gate insulating layer, the source electrode and the drain electrode, and a pixel electrode disposed on the passivation layer; the passivation layer is provided with a passivation layer located in the source electrode and the drain electrode. An upper via through which the pixel electrode contacts one of the source and drain.

Beneficial effects of the present invention: in the method for manufacturing a TFT array substrate of the present invention, a bottom layer semiconductor material film, a doped semiconductor material film and a first metal material film are sequentially fabricated on the gate insulating layer, and a mask is used for the bottom layer semiconductor material film. , The doped semiconductor material film and the first metal material film are patterned to form a bottom semiconductor layer, a doped semiconductor layer and a metal layer that are sequentially arranged above the gate from bottom to top, and then formed on the gate insulating layer and the metal layer. The second metal material film is patterned on the second metal material film, the metal layer and the doped semiconductor layer to form a source contact block, a drain contact block, a source electrode and a drain electrode, which can reduce the source and source contact blocks The contact interface and the contact resistance of the contact interface between the drain and the drain contact block are improved, and the product performance is improved. The TFT array substrate of the present invention can reduce the contact resistance of the contact interface between the source electrode and the source electrode contact block and the contact interface between the drain electrode and the drain contact block, and improve product performance.

Description of drawings

In order to further understand the features and technical content of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings, however, the accompanying drawings are only for reference and illustration, and are not intended to limit the present invention.

In the attached drawing,

1 to 3 are schematic diagrams of manufacturing a TFT array substrate using the 5mask technology in the prior art;

FIG. 4 is a flow chart of the manufacturing method of the TFT array substrate of the present invention;

FIG. 5 is a schematic diagram of step S1 of the manufacturing method of the TFT array substrate of the present invention;

FIG. 6 is a schematic diagram of step S2 of the manufacturing method of the TFT array substrate of the present invention;

7 is a schematic diagram of step S3 of the manufacturing method of the TFT array substrate of the present invention;

FIG. 8 is a schematic diagram of step S4 of the manufacturing method of the TFT array substrate of the present invention;

9 is a schematic diagram of step S5 of the manufacturing method of the TFT array substrate of the present invention;

FIG. 10 is a schematic diagram of step S6 of the manufacturing method of the TFT array substrate of the present invention.

Detailed ways

In order to further illustrate the technical means adopted by the present invention and its effects, a detailed description is given below in conjunction with the preferred embodiments of the present invention and the accompanying drawings.

Referring to FIG. 4 , the present invention provides a method for fabricating a TFT array substrate, including the following steps:

Step S1 , referring to FIG. 5 , a substrate 10 is provided, and the gate electrode 20 , the gate insulating layer 30 , the underlying semiconductor material film 49 , the doped semiconductor material film 59 and the first metal material film 67 are sequentially formed on the substrate 10 .

Specifically, the material of the underlying semiconductor material film 49 is undoped amorphous silicon, and the material of the doped semiconductor material film 59 is ion-doped amorphous silicon.

Preferably, the material of the doped semiconductor material film 59 is amorphous silicon doped with N-type ions.

Step S2 , referring to FIG. 6 , use a mask to pattern the underlying semiconductor material film 49 , the doped semiconductor material film 59 and the first metal material film 67 to form an island-like sequence arranged above the gate 20 from bottom to top The underlying semiconductor layer 40 , the island-shaped doped semiconductor layer 58 and the island-shaped metal layer 68 are formed.

Specifically, in the step S2, the underlying semiconductor material film 49 and the doped semiconductor material film 59 are patterned by dry etching, and at the same time, the first metal material film 67 can be designed to be thinner so that the first metal material The film 67 can be patterned by dry etching together with the underlying semiconductor material film 49 and the doped semiconductor material film 59 .

Step S3 , referring to FIG. 7 , a second metal material film 69 is formed on the gate insulating layer 30 and the metal layer 68 .

Step S4 , referring to FIG. 8 , pattern the second metal material film 69 , the metal layer 68 and the doped semiconductor layer 58 to form source contact blocks 51 and drain contacts located above and spaced apart from both ends of the underlying semiconductor layer 40 Block 52 and source 61 and drain 62 in contact with source contact block 51 and drain contact block 52, respectively. The source electrode 61 includes a first sub-source electrode 611 located on the source contact block 51 and a second sub-source electrode 612 in contact with the first sub-source electrode 611 , and the drain electrode 62 includes a second sub-source electrode 612 located on the drain contact block 52 . The first sub-drain 621 and the second sub-drain 622 in contact with the first sub-drain 621 . The source contact block 51 and the drain contact block 52 are formed by patterning the doped semiconductor layer 58 , the first sub-source 611 and the first sub-drain 621 are formed by patterning the metal layer 68 , and the second sub-source 612 And the second sub-drain 622 is formed by patterning the second metal material film 69 .

Specifically, in the step S4, the second metal material film 69 may be patterned first to form the second sub-source 612 and the second sub-drain 622, and then the second sub-source 612 and the second sub-drain The metal layer 68 and the doped semiconductor layer 58 are dry-etched to form the source contact block 51 , the drain contact block 52 , the first sub-source electrode 611 and the first sub-drain electrode 621 for shielding 622 .

Preferably, the thickness of the first sub-source electrode 611 is the same as that of the first sub-drain electrode 621 , the thickness of the second sub-source electrode 612 is the same as that of the second sub-drain electrode 622 , and the thickness of the first sub-source electrode 611 is less than The thickness of the second sub-source 612 .

Step S5 , referring to FIG. 9 , a passivation layer 70 is formed on the gate insulating layer 30 , the source electrode 61 and the drain electrode 62 . The passivation layer 70 is patterned to form a via hole 71 over one of the source electrode 61 and the drain electrode 62 .

Step S5 , referring to FIG. 10 , a pixel electrode 80 is formed on the passivation layer 70 , and the pixel electrode 80 is in contact with one of the source electrode 61 and the drain electrode 62 through the hole 71 .

It should be noted that, in the manufacturing method of the TFT array substrate of the present invention, the bottom layer semiconductor material film 49, the doped semiconductor material film 59 and the first metal material film 67 are sequentially formed on the gate insulating layer 30, and a mask is used for the bottom layer. The semiconductor material film 49 , the doped semiconductor material film 59 and the first metal material film 67 are patterned to form the underlying semiconductor layer 40 , the doped semiconductor layer 58 and the metal layer 68 , and then the gate insulating layer 30 and the metal layer 68 are formed. A second metal material film 69 is formed, the second metal material film 69, the metal layer 68 and the doped semiconductor layer 58 are patterned to form a source contact block 51, a drain contact block 52, a source electrode 61 and a drain electrode 62, The source contact block 51 and the drain contact block 52 are formed by patterning the doped semiconductor layer 58 , and the first sub-source 611 in the source 61 and the first sub-drain 621 in the drain 62 are patterned by the metal layer 68 The second sub-source 612 in the source 61 and the second sub-drain 622 in the drain 62 are formed by patterning the second metal material film 69, so that the contact interface between the source 61 and the source contact block 51 and The characteristics of the contact interface between the drain electrode 62 and the drain electrode contact layer 52 are not affected by the patterning process, and have smaller contact resistance, so that the on-state current of the TFT device in the TFT array substrate prepared by the present invention is higher, and the product Better performance.

Please refer to FIG. 10 , based on the same inventive concept, the present invention also provides a TFT array substrate, which is produced by the above-mentioned manufacturing method of a TFT array substrate. The TFT array substrate includes a substrate 10 and a gate electrode disposed on the substrate 10 . The electrode 20 , the gate insulating layer 30 disposed on the substrate 10 and the gate 20 , the island-shaped underlying semiconductor layer 40 disposed on the gate insulating layer 30 and above the gate 20 , and the two ends of the underlying semiconductor layer 40 Above and spaced apart source contact block 51 and drain contact block 52 and source and drain electrodes 61 and 62 in contact with source contact block 51 and drain contact block 52, respectively. The source electrode 61 includes a first sub-source electrode 611 located on the source contact block 51 and a second sub-source electrode 612 in contact with the first sub-source electrode 611 , and the drain electrode 62 includes a second sub-source electrode 612 located on the drain contact block 52 . The first sub-drain 621 and the second sub-drain 622 in contact with the first sub-drain 621 .

Specifically, the material of the underlying semiconductor layer 40 is amorphous silicon, and the material of the source contact block 51 and the drain contact block 52 is ion-doped amorphous silicon.

Preferably, the source contact block 51 and the drain contact block 52 are made of amorphous silicon doped with N-type ions.

Preferably, the thickness of the first sub-source electrode 611 is the same as that of the first sub-drain electrode 621 , the thickness of the second sub-source electrode 612 is the same as that of the second sub-drain electrode 622 , and the thickness of the first sub-source electrode 611 is less than The thickness of the second sub-source 612 .

Specifically, the TFT array substrate further includes a passivation layer 70 disposed on the gate insulating layer 30 , the source electrode 61 and the drain electrode 62 , and a pixel electrode 80 disposed on the passivation layer 70 . The passivation layer 70 is provided with a via hole 71 over one of the source electrode 61 and the drain electrode 62 , and the pixel electrode 80 is in contact with one of the source electrode 61 and the drain electrode 62 through the hole 71 .

It should be noted that the TFT array substrate of the present invention is produced by the above-mentioned manufacturing method of the TFT array substrate, and the source electrode 61 includes the first sub-source electrode 611 disposed on the source contact block 51 and the first sub-source electrode 611 and the first sub-source electrode. The second sub-source 612 in contact with 611, the drain 62 includes a first sub-drain 621 disposed on the drain contact block 52 and a second sub-drain 622 in contact with the first sub-drain 621, the source 61 and The characteristics of the contact interface of the source contact block 51 and the contact interface of the drain 62 and the drain contact layer 52 are not affected by the patterning process, and have smaller contact resistance, so that the TFT device in the TFT array substrate of the present invention has a lower contact resistance. The on-state current is higher, and the product performance is better.

To sum up, the manufacturing method of the TFT array substrate of the present invention sequentially manufactures the underlying semiconductor material film, the doped semiconductor material film and the first metal material film on the gate insulating layer, and utilizes a mask for the underlying semiconductor material film, the doped semiconductor material film and the first metal material film. The doped semiconductor material film and the first metal material film are patterned to form a bottom semiconductor layer, a doped semiconductor layer and a metal layer that are arranged in sequence from bottom to top above the gate, and then a first layer is formed on the gate insulating layer and the metal layer. Two metal material films, pattern the second metal material film, the metal layer and the doped semiconductor layer to form source contact blocks, drain contact blocks, source electrodes and drain electrodes, which can reduce the difference between the source electrode and the source electrode contact block. The contact resistance of the contact interface and the contact interface between the drain and the drain contact block improves product performance. The TFT array substrate of the present invention can reduce the contact resistance of the contact interface between the source electrode and the source electrode contact block and the contact interface between the drain electrode and the drain contact block, and improve product performance.

As mentioned above, for those of ordinary skill in the art, various other corresponding changes and deformations can be made according to the technical solutions and technical concepts of the present invention, and all these changes and deformations should belong to the protection scope of the claims of the present invention .

Claims (10)

1. a preparation method of a TFT array substrate, is characterized in that, comprises the following steps: In step S1, a substrate (10) is provided, and a gate electrode (20), a gate insulating layer (30), an underlying semiconductor material film (49), a doped semiconductor material film (59) and a first metal material film (67); Step S2, using a mask to pattern the underlying semiconductor material film (49), the doped semiconductor material film (59) and the first metal material film (67), which are formed on the gate (20) and are arranged in sequence from bottom to top an island-shaped underlying semiconductor layer (40), an island-shaped doped semiconductor layer (58) and an island-shaped metal layer (68); Step S3, forming a second metal material film (69) on the gate insulating layer (30) and the metal layer (68); Step S4, patterning the second metal material film (69), the metal layer (68) and the doped semiconductor layer (58) to form source contact blocks (51) located above and spaced apart from both ends of the underlying semiconductor layer (40). ) and a drain contact block (52) and a source electrode (61) and a drain electrode (62) in contact with the source contact block (51) and the drain contact block (52), respectively; the source electrode (61) comprises a a first sub-source (611) on the source contact block (51) and a second sub-source (612) in contact with the first sub-source (611), the drain (62) including a drain contact A first sub-drain (621) on the block (52) and a second sub-drain (622) in contact with the first sub-drain (621). 2. The method for manufacturing a TFT array substrate according to claim 1, wherein the material of the underlying semiconductor material film (49) is amorphous silicon, and the material of the doped semiconductor material film (59) is Ion-doped amorphous silicon. 3. The method for manufacturing a TFT array substrate according to claim 2, wherein the material of the doped semiconductor material film (59) is amorphous silicon doped with N-type ions. 4. The method for fabricating a TFT array substrate according to claim 1, wherein the thickness of the first sub-source (611) is the same as the thickness of the first sub-drain (621), and the thickness of the second sub-source (612) ) is the same as the thickness of the second sub-drain (622), and the thickness of the first sub-source (611) is smaller than that of the second sub-source (612). 5. The method for manufacturing a TFT array substrate according to claim 1, further comprising step S5, forming a passivation layer on the gate insulating layer (30), the source electrode (61) and the drain electrode (62) (70); patterning the passivation layer (70) to form a via hole (71) located above one of the source electrode (61) and the drain electrode (62); Step S6, a pixel electrode (80) is formed on the passivation layer (70), and the pixel electrode (80) is in contact with one of the source electrode (61) and the drain electrode (62) through the hole (71). 6. A TFT array substrate, characterized in that it comprises a substrate (10), a gate electrode (20) arranged on the substrate (10), a gate electrode arranged on the substrate (10) and the gate electrode (20) A pole insulating layer (30), an island-shaped underlying semiconductor layer (40) arranged on the gate insulating layer (30) and located above the gate (20), and a source arranged over and spaced apart from both ends of the underlying semiconductor layer (40) a pole contact block (51) and a drain contact block (52) and a source electrode (61) and a drain electrode (62) in contact with the source contact block (51) and the drain contact block (52), respectively; the source electrode (61) comprising a first sub-source (611) on the source contact block (51) and a second sub-source (612) in contact with the first sub-source (611), the drain (62) A first sub-drain (621) located on the drain contact block (52) and a second sub-drain (622) in contact with the first sub-drain (621) are included. 7. The TFT array substrate according to claim 6, wherein the material of the underlying semiconductor layer (40) is amorphous silicon, and the source contact block (51) and the drain contact block (52) are made of amorphous silicon. The material is ion-doped amorphous silicon. 8. The TFT array substrate according to claim 7, wherein the source contact block (51) and the drain contact block (52) are made of amorphous silicon doped with N-type ions. 9. The TFT array substrate according to claim 6, wherein the thickness of the first sub-source (611) is the same as the thickness of the first sub-drain (621), and the thickness of the second sub-source (612) The thickness of the first sub-source (611) is smaller than that of the second sub-source (612), which is the same as the thickness of the second sub-drain (622). 10. The TFT array substrate according to claim 6, further comprising a passivation layer (70) provided on the gate insulating layer (30), the source electrode (61) and the drain electrode (62), and a set a pixel electrode (80) on the passivation layer (70); the passivation layer (70) is provided with a via hole (71) located above one of the source electrode (61) and the drain electrode (62), the The pixel electrode (80) is in contact with one of the source electrode (61) and the drain electrode (62) through the hole (71).